Memory device

Abstract

To provide a memory device with a large storage capacity.SOLUTION: In a NAND type memory device connected multiple storage cells including a writing transistor, and a reading transistor, a holding capacitor can be eliminated or can be made compact, by using an oxide semiconductor in the semiconductor layer of the writing transistor. The reading transistor includes a back gate. Information held in the storage cells is read out by applying a reading voltage to the back gate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in the present specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Thus, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, communication devices, electronic devices, and the like may include semiconductor elements and semiconductor circuits. Thus, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] 2. Description of the Related Art In recent years, transistors using an oxide semiconductor or a metal oxide for a channel formation region (oxide semiconductor transistors, hereinafter also referred to as "OS transistors" or "OS-FETs") have attracted attention (Patent Document 1).

[0005] OS transistors have an extremely small off-state current. Nonvolatile memories utilizing this characteristic are disclosed in Patent Documents 2 and 3. Nonvolatile memories using OS transistors have no limit to the number of times data can be rewritten, and further consume little power when rewriting data.

[0006] In this specification, nonvolatile memory using OS transistors may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor RAM" and refers to RAM having gain cell type (2T type, 3T type) memory cells. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] JP 2016-115387 A Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a highly reliable memory device.An object of one embodiment of the present invention is to provide a memory device having a large storage capacity.An object of one embodiment of the present invention is to provide a memory device having a small occupation area.An object of one embodiment of the present invention is to provide a memory device having low manufacturing costs.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device having low manufacturing costs.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a NAND memory device in which a plurality of memory elements (also referred to as "memory cells") including a writing transistor and a reading transistor are connected. By using an oxide semiconductor for the semiconductor layer of the writing transistor, a storage capacitor is not required or the storage capacitor can be reduced in size. The reading transistor has a back gate. By applying a reading voltage to the back gate, data stored in the storage element can be read.

[0011] Another aspect of the present invention includes a first memory cell, a second memory cell, a first wiring, a second wiring, a third wiring, a first transistor, and a second transistor, and each of the first memory cell and the second memory cell includes a third transistor and a fourth transistor, a source of the third transistor included in the first memory cell is electrically connected to the third wiring, a drain of the third transistor included in the first memory cell is electrically connected to a source of the third transistor included in the second memory cell, a gate of the third transistor included in the first memory cell is electrically connected to the first wiring, a gate of the third transistor included in the second memory cell is electrically connected to the second wiring, and a source of the fourth transistor included in the first memory cell is electrically connected to the third wiring. a drain of the fourth transistor included in the first memory cell electrically connected to a source of the fourth transistor included in the second memory cell, a gate of the fourth transistor included in the first memory cell electrically connected to a drain of the third transistor included in the first memory cell, a gate of the fourth transistor included in the second memory cell electrically connected to a drain of the third transistor included in the second memory cell, and a drain of the fourth transistor included in the second memory cell electrically connected to the second transistor, and the fourth transistor included in the first memory cell and the fourth transistor included in the second memory cell are transistors having back gates.

[0012] Another aspect of the present invention includes n (n is an integer of 3 or more) memory cells, n word lines, a bit line, a first transistor, and a second transistor, each of the n memory cells includes a third transistor and a fourth transistor, a source of the third transistor included in a first memory cell is electrically connected to the bit line, a drain of the third transistor included in the first memory cell is electrically connected to a source of the third transistor included in a second memory cell, a gate of the third transistor included in the first memory cell is electrically connected to a first word line, a source of the fourth transistor included in the first memory cell is electrically connected to the first transistor, a drain of the fourth transistor included in the first memory cell is electrically connected to a source of the fourth transistor included in the second memory cell, a gate of the fourth transistor included in the first memory cell is electrically connected to a drain of the third transistor included in the first memory cell, and a source of the third transistor included in an i-th (i is an integer of 2 or more and less than n) memory cell is an i-1th the drain of the third transistor included in the i-th memory cell is electrically connected to the source of the third transistor included in the i+1-th memory cell, the gate of the third transistor included in the i-th memory cell is electrically connected to the i-th word line, the source of the fourth transistor included in the i-th memory cell is electrically connected to the drain of the fourth transistor included in the i-1-th memory cell, the drain of the fourth transistor included in the i-th memory cell is electrically connected to the source of the fourth transistor included in the i+1-th memory cell, the gate of the fourth transistor included in the i-th memory cell is electrically connected to the drain of the third transistor included in the i-th memory cell, the source of the third transistor included in the n-th memory cell is electrically connected to the drain of the third transistor included in the n-1-th memory cell, the gate of the third transistor included in the n-th memory cell is electrically connected to the n-th word line, and the source of the fourth transistor included in the n-th memory cell isa drain of a fourth transistor included in an n-1th memory cell is electrically connected to the drain of the fourth transistor included in the nth memory cell, a gate of the fourth transistor included in the nth memory cell is electrically connected to the second transistor, and a gate of the fourth transistor included in the nth memory cell is electrically connected to the drain of the third transistor included in the nth memory cell, and each of the fourth transistors included in the n memory cells is a transistor having a back gate.

[0013] Another aspect of the present invention includes n (n is an integer of 3 or more) memory cells, n word lines, a first wiring, a first bit line, a second bit line, a first transistor, a second transistor, and a fifth transistor, each of the n memory cells includes a third transistor and a fourth transistor, a source of the third transistor included in a first memory cell is electrically connected to the first bit line, a drain of the third transistor included in the first memory cell is electrically connected to a source of the third transistor included in a second memory cell, a gate of the third transistor included in the first memory cell is electrically connected to the first word line, a source of the fourth transistor included in the first memory cell is electrically connected to the first transistor, a drain of the fourth transistor included in the first memory cell is electrically connected to a source of the fourth transistor included in the second memory cell, a gate of the fourth transistor included in the first memory cell is electrically connected to a drain of the third transistor included in the first memory cell, and an i-th (i is an integer of 2 or more and less than n) memory cell includes a third transistor and a fourth transistor, a source of the third transistor included in the i-1th memory cell is electrically connected to a drain of the third transistor included in the i-th memory cell, a drain of the third transistor included in the i-th memory cell is electrically connected to a source of the third transistor included in the i+1th memory cell, a gate of the third transistor included in the i-th memory cell is electrically connected to the i-th word line, a source of the fourth transistor included in the i-1th memory cell is electrically connected to a drain of the fourth transistor included in the i-th memory cell, a drain of the fourth transistor included in the i-th memory cell is electrically connected to a source of the fourth transistor included in the i+1th memory cell, a gate of the fourth transistor included in the i-th memory cell is electrically connected to a drain of the third transistor included in the i-th memory cell, a source of the third transistor included in the n-th memory cell is electrically connected to a drain of the third transistor included in the n-1th memory cell, and a gate of the third transistor included in the n-th memory cell is electrically connected to the n-th word line;A storage device in which the source of a fourth transistor included in an nth memory cell is electrically connected to the drain of a fourth transistor included in an n-1th memory cell, the drain of the fourth transistor included in the nth memory cell is electrically connected to the second transistor, the gate of the fourth transistor included in the nth memory cell is electrically connected to the drain of a third transistor included in the nth memory cell, the drain of the third transistor included in the nth memory cell is electrically connected to the source of a fifth transistor, the drain of the fifth transistor is electrically connected to a second bit line, and the gate of the fifth transistor is electrically connected to a first wiring, and each of the fourth transistors included in the n memory cells is a transistor having a back gate.

[0014] In all the memory cells, a capacitance may be provided at the drain of the third transistor included in each memory cell. The third transistor is preferably a transistor including an oxide semiconductor in a semiconductor layer. The fourth transistor is preferably a transistor including an oxide semiconductor in a semiconductor layer. Effect of the Invention

[0015] According to one embodiment of the present invention, a highly reliable storage device can be provided. According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a storage device with a small occupation area can be provided. According to one embodiment of the present invention, a storage device with low manufacturing costs can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low manufacturing costs can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0017] [Figure 1] Fig. 1A is a circuit diagram showing a configuration example of a memory device, Figs. 1B to 1D are circuit diagrams showing configuration examples of a memory element, and Fig. 1E is a circuit diagram showing a configuration example of a transistor. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration example of the storage device. [Diagram 3] FIG. 3 is a circuit diagram showing a configuration example of the storage device. [Figure 4] FIG. 4 is a perspective circuit diagram showing a configuration example of a storage device. [Diagram 5] FIG. 5 is a perspective circuit diagram showing a configuration example of a storage device. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of a storage device. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a storage device. [Figure 8] 8A is a timing chart illustrating a write operation of the memory device, and FIG 8B is a timing chart illustrating a read operation of the memory device. [Figure 9] 9(A) and (B) are circuit diagrams illustrating the write operation of the memory device. [Figure 10] 10(A) and (B) are circuit diagrams illustrating the write operation of the memory device. [Figure 11] FIG. 11 is a circuit diagram illustrating the write operation of the memory device. [Figure 12] 12(A) and (B) are circuit diagrams illustrating the read operation of the memory device. [Figure 13]13(A) and (B) are circuit diagrams illustrating the read operation of the memory device. [Figure 14] FIG. 14 is a circuit diagram showing a configuration example of a storage device. [Figure 15] FIG. 15 is a circuit diagram showing a configuration example of a storage device. [Figure 16] FIG. 16 is a timing chart illustrating the write operation of the memory device. [Figure 17] 17(A) and (B) are circuit diagrams illustrating the write operation of the memory device. [Figure 18] FIG. 18 is a circuit diagram illustrating the write operation of the memory device. [Figure 19] FIG. 19 is a circuit diagram showing a configuration example of a storage device. [Figure 20] FIG. 20 is a circuit diagram showing a configuration example of a storage device. [Figure 21] FIG. 21 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 22] 22A to 22C are perspective views illustrating configuration examples of a semiconductor device. [Figure 23] Fig. 23A is a top view illustrating a configuration example of a memory device, and Fig. 23B is a cross-sectional view illustrating the configuration example of the memory device. [Figure 24] 24(A) and (B) are cross-sectional views for explaining a configuration example of a memory device. [Diagram 25] FIG. 25 is a cross-sectional view illustrating a configuration example of a transistor. [Figure 26] 26(A) and (B) are cross-sectional views for explaining a configuration example of a memory device. [Figure 27] Fig. 27(A) is a diagram explaining the classification of IGZO crystal structures, Fig. 27(B) is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Fig. 27(C) is a diagram explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. [Figure 28]28A is a top view illustrating an example of a method for manufacturing a memory device, and FIGS. 28B to 28D are cross-sectional views illustrating an example of a method for manufacturing a memory device. [Figure 29] 29A is a top view illustrating an example of a method for manufacturing a memory device, and FIGS. 29B to 29D are cross-sectional views illustrating an example of a method for manufacturing a memory device. [Diagram 30] 30A is a top view illustrating an example of a method for manufacturing a memory device, and FIGS. 30B to 30D are cross-sectional views illustrating an example of a method for manufacturing a memory device. [Diagram 31] 31A is a top view illustrating an example of a method for manufacturing a memory device, and FIGS. 31B to 31D are cross-sectional views illustrating an example of a method for manufacturing a memory device. [Diagram 32] 32A is a top view illustrating an example of a method for manufacturing a memory device, and FIGS. 32B to 32D are cross-sectional views illustrating an example of a method for manufacturing a memory device. [Diagram 33] 33A is a top view illustrating an example of a method for manufacturing a memory device, and FIGS. 33B to 33D are cross-sectional views illustrating an example of a method for manufacturing a memory device. [Diagram 34] 34A is a top view illustrating an example of a method for manufacturing a memory device, and FIGS. 34B to 34D are cross-sectional views illustrating an example of a method for manufacturing a memory device. [Diagram 35] Fig. 35(A) is a schematic diagram of the semiconductor device, and Fig. 35(B) is a perspective view of the semiconductor device. [Diagram 36] 36A to 36E are diagrams illustrating an example of a storage device. [Figure 37] 37A to 37G are diagrams illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated description will be omitted.

[0019] In addition, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in the actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0020] In addition, in top views (also called "plan views"), perspective views, and the like, illustration of some components may be omitted in order to make the drawings easier to understand.

[0021] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0022] In addition, in this specification and the like, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0023] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0024] In addition, in this specification, "electrically connected" includes a direct connection and a connection via "something having some electrical action." Here, the "something having some electrical action" is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects. Therefore, even when it is expressed as "electrically connected," in the actual circuit, there may be no physical connection and only wiring extending therethrough.

[0025] In this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. This therefore includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This therefore includes cases in which the angle is 85° or more and 95° or less.

[0026] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "same," "equal," "uniform," etc. are used, they are intended to include an error of plus or minus 20% unless otherwise expressly stated.

[0027] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, a ground potential or a source potential). Therefore, voltage and potential can often be interchanged. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0028] Even when written as "semiconductor", for example, if the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to use "semiconductor" instead of "insulator". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read as interchangeable.

[0029] Furthermore, even when written as "semiconductor", if the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to use "semiconductor" in place of "conductor". In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be interchangeable.

[0030] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components, and do not indicate any order or ranking, such as the order of processes or stacking. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0031] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as a "non-conductive state").

[0032] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0033] In this specification and the like, high power supply potential VDD (hereinafter also simply referred to as "VDD", "H potential", or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS", "L potential", or "L"). Also, VSS refers to a power supply potential that is lower than VDD. Also, ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0034] In addition, unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field effect transistors. Therefore, the threshold voltage (also referred to as "Vth") is assumed to be higher than 0 V. In addition, unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." In addition, unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0035] In this specification and the like, a gate refers to a gate electrode and a part or the whole of a gate wiring. A gate wiring refers to a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0036] In this specification and the like, the source refers to a source region, a source electrode, and a part or all of a source wiring. The source region refers to a region of a semiconductor layer having a resistivity equal to or lower than a certain value. The source electrode refers to a conductive layer connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0037] In this specification and the like, the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is equal to or lower than a certain value. The drain electrode refers to a conductive layer that is connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0038] In addition, the functions of the source and the drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, so it is difficult to determine which is the source or the drain. For this reason, the terms source and drain can be used interchangeably in this specification. Therefore, in order to make the description of one embodiment of the present invention easier to understand, in this specification and the like, one of the source or the drain may be called the "source" and the other of the source or the drain may be called the "drain."

[0039] In addition, in drawings, etc., to make the potential of wiring and electrodes easier to understand, "H" indicating H potential or "L" indicating L potential may be written next to the wiring and electrode. Wiring and electrodes where a potential change has occurred may be written with "H" or "L" enclosed in a box. When a transistor is in the off state, an "x" symbol may be written over the transistor.

[0040] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance", "load", and "region having a resistance value", and conversely, the terms "resistance", "load", and "region having a resistance value" can be replaced with terms such as "resistance element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0041] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term "capacitive element" refers not only to a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also to a parasitic capacitance appearing between wirings, a gate capacitance appearing between one of the source or drain of a transistor and the gate, and the like. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like can be rephrased as "capacitance", and conversely, the term "capacitance" can be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the electrostatic capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0042] (Embodiment 1) Fig. 1A shows a circuit diagram of a memory device 100 according to one embodiment of the present invention. The memory device 100 includes a plurality of memory elements 110 between a transistor 131 and a transistor 132. Fig. 1B shows a circuit diagram of the memory element 110. The memory element 110 includes a transistor 111 and a transistor 112. The transistor 112 has a backgate.

[0043] In this embodiment and the like, the first memory element 110 is denoted as memory element 110[1], and the nth (n is an integer equal to or greater than 3) memory element 110 is denoted as memory element 110[n]. The ith (i is an integer equal to or greater than 2 and less than n) memory element 110 is denoted as memory element 110[i]. Note that when describing matters common to the memory elements 110[1] to 110[n], the memory element may simply be referred to as "memory element 110."

[0044] In this embodiment and the like, the transistor 111 included in the memory element 110[1] is referred to as the transistor 111[1], the transistor 111 included in the memory element 110[i] is referred to as the transistor 111[i], and the transistor 111 included in the memory element 110[n] is referred to as the transistor 111[n]. Note that when matters common to the transistors 111[1] to 111[n] are described, the transistor 111 may simply be referred to as the "transistor 111." The transistor 112 and a node 113 described later will also be referred to in the same manner as the transistor 111.

[0045] <Storage device configuration example> An example of a circuit configuration of the memory device 100 illustrated in FIG. 1A will be described in detail. One of a source or a drain of a transistor 111[1] included in a memory element 110[1] is electrically connected to a wiring WBL, and the other is electrically connected to a node 113[1]. A gate of the transistor 111[1] is electrically connected to a terminal 121[1]. One of a source or a drain of a transistor 112[1] is electrically connected to a transistor 131, and the other is electrically connected to one of a source or a drain of a transistor 112[2]. A gate of the transistor 112[1] is electrically connected to a node 113[1]. A backgate of the transistor 112[1] is electrically connected to a terminal 122[1].

[0046] One of the source and the drain of the transistor 131 is electrically connected to the wiring RBL, and the other is electrically connected to one of the source and the drain of the transistor 112[1]. A gate of the transistor 131 is electrically connected to a terminal 133.

[0047] One of the source and the drain of the transistor 111[2] included in the memory element 110[2] is electrically connected to the node 113[1], and the other is electrically connected to the node 113[2]. The gate of the transistor 111[2] is electrically connected to the terminal 121[2]. One of the source and the drain of the transistor 112[2] is electrically connected to the other of the source and the drain of the transistor 112[1], and the gate is electrically connected to the node 113[2]. The backgate of the transistor 112[2] is electrically connected to the terminal 122[2].

[0048] One of the source and the drain of the transistor 111[i] included in the memory element 110[i] is electrically connected to a node 113[i-1] (not shown), and the other is electrically connected to a node 113[i] (not shown). The gate of the transistor 111[i] is electrically connected to a terminal 121[i]. One of the source and the drain of the transistor 112[i] is electrically connected to one or the other of the source and the drain of the transistor 112[i-1] (not shown). The gate of the transistor 112[i] is electrically connected to the node 113[i], and the backgate of the transistor 112[i] is electrically connected to a terminal 122[i].

[0049] One of the source and the drain of the transistor 111[n] included in the memory element 110[n] is electrically connected to a node 113[n-1] (not shown). The other of the source and the drain of the transistor 111[n] is electrically connected to a node 113[n]. The gate of the transistor 111[n] is electrically connected to a terminal 121[n].

[0050] In addition, one of the source and the drain of the transistor 112[n] is electrically connected to one of the source and the drain of the transistor 112[n-1] (not shown). The other of the source and the drain of the transistor 112[n] is electrically connected to one of the source and the drain of the transistor 132. The gate of the transistor 112[n] is electrically connected to the node 113[n], and the backgate of the transistor 112[n] is electrically connected to the terminal 122[n].

[0051] The other of the source and the drain of the transistor 132 is electrically connected to the wiring SL. The gate of the transistor 132 is electrically connected to a terminal .

[0052] 1A includes n memory elements 110 between transistors 131 and 132, and adjacent transistors 111[1] to 111[n] are connected in series with a source of one transistor and a drain of the other transistor shared (electrically connected) in common. Similarly, adjacent transistors 112[1] to 112[n] are connected in series with a source of one transistor and a drain of the other transistor shared (electrically connected).

[0053] More specifically, the source of transistor 111[i] is electrically connected to the drain of transistor 111[i-1], the drain of transistor 111[i] is electrically connected to the source of transistor 111[i+1], the source of transistor 112[i] is electrically connected to the drain of transistor 112[i-1], and the drain of transistor 112[i] is electrically connected to the source of transistor 112[i+1].

[0054] In this specification and the like, the gate of a transistor may be referred to as the first terminal, one of the source or drain as the second terminal, the other of the source or drain as the third terminal, and the backgate as the fourth terminal. For example, it can be said that the second terminal of transistor 111[i] is electrically connected to the third terminal of transistor 111[i-1], the third terminal of transistor 111[i] is electrically connected to the second terminal of transistor 111[i+1], and the third terminal of transistor 111[i] is electrically connected to the first terminal of transistor 112[i].

[0055] In this way, a structure in which a plurality of memory elements 110 are connected in series with a transistor included in one memory element 110 connected in series with a transistor included in an adjacent memory element 110 may be called a "string," a "cell string," or a "memory cell string." For example, one memory device 100 may be called "one string" or simply a "string." Note that the "string," "cell string," and "memory cell string" may also be referred to as a unit.

[0056] [Memory element] The memory element 110 (see FIG. 1B) has a function of holding a potential (charge) written to the node 113. Specifically, a voltage that turns on the transistor 111 is supplied to the gate of the transistor 111, and charge for setting the node 113 to a predetermined voltage is supplied to the node 113 via the source and drain of the transistor 111. Then, a voltage that turns off the transistor 111 is supplied to the gate of the transistor 111. By turning off the transistor 111, the charge written to the node 113 can be held.

[0057] The semiconductor layers of the transistor 111 and the transistor 112 can be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either alone or in combination. Examples of the semiconductor material that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. The semiconductor layers of the transistor 131 and the transistor 132 can also be formed using similar semiconductor materials.

[0058] Note that the semiconductor layers used in the transistor may be stacked. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for each of the semiconductor layers.

[0059] In particular, the transistor 111 is preferably an OS transistor. An oxide semiconductor has a band gap of 2 eV or more, and therefore has an extremely low off-state current. When an OS transistor is used as the transistor 111, charge written to the node 113 can be held for a long period of time. When an OS transistor is used as the transistor 111, the memory element 110 can be called an "OS memory."

[0060] The OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered as a non-volatile memory.

[0061] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0062] In addition, since OS memory writes charge to a node via an OS transistor, it does not require the high voltage required for conventional flash memory, and can achieve high-speed write operations. In addition, OS memory does not require the erase operation before rewriting data, which is performed in flash memory. In addition, since no charge is injected into or extracted from the floating gate or charge trapping layer, OS memory can write and read data an unlimited number of times. OS memory is less susceptible to deterioration and is highly reliable compared to conventional flash memory.

[0063] In addition, the OS memory does not involve structural changes at the atomic level, as in magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), etc. Therefore, the OS memory has better rewrite endurance than the magnetoresistive random access memory and the resistive random access memory.

[0064] Moreover, the off-current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. Moreover, the on-current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory is stable in operation even in a high-temperature environment, and is highly reliable. Moreover, the OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that is stable in operation even in a high-temperature environment and has good reliability can be realized.

[0065] 1C, a transistor having a back gate may be used as the transistor 111 included in the memory element 110. In FIG 1C, the gate and the back gate of the transistor 111 are electrically connected to each other.

[0066] 1D, a capacitor 125 may be provided between the node 113 and the terminal 123. When the capacitor 125 is provided, a fixed potential is preferably supplied to the terminal 123. By providing the capacitor 125, a potential fluctuation of the node 113 can be suppressed and the reliability of the memory device 100 can be improved. In particular, when multi-level data is stored in the memory element 110, it is preferable to provide the capacitor 125 in the memory element 110.

[0067] 1E, a transistor having a back gate may be used as the transistor 131 and / or the transistor 132. In FIG 1E, the gate and the back gate of the transistor are electrically connected to each other.

[0068] Note that the memory device 100 may include two memory elements 110, a transistor 131, and a transistor 132. That is, n may be 2. FIG 2 shows an example of a circuit configuration of the memory device 100 when n is 2.

[0069] The gate of the transistor 111 may be electrically connected to the wiring WL. Alternatively, the gate of the transistor 111 may be electrically connected to the wiring WL through a terminal 121. The backgate of the transistor 112 may be electrically connected to the wiring CL. Alternatively, the backgate of the transistor 112 may be electrically connected to the wiring CL through a terminal 122. A signal for controlling a write operation described later is supplied to the wiring WL. A signal for controlling a read operation described later is supplied to the wiring CL.

[0070] FIG. 3 shows an example in which the gate of transistor 111[1] is electrically connected to wiring WL[1], the gate of transistor 111[2] is electrically connected to wiring WL[2], the gate of transistor 111[i] is electrically connected to wiring WL[i], and the gate of transistor 111[n] is electrically connected to wiring WL[n].

[0071] FIG. 3 also shows an example in which the backgate of transistor 112[1] is electrically connected to wiring CL[1], the backgate of transistor 112[2] is electrically connected to wiring CL[2], the backgate of transistor 112[i] is electrically connected to wiring CL[i], and the backgate of transistor 112[n] is electrically connected to wiring CL[n].

[0072] Furthermore, by using a plurality of memory devices 100, it is possible to increase the storage capacity of a semiconductor device including the memory devices 100. In other words, by increasing the number of strings, it is possible to increase the storage capacity of the semiconductor device.

[0073] As an example, a perspective circuit diagram of three memory devices 100 (three strings) connected in parallel is shown in Fig. 4. In Fig. 4, the first memory device 100 is shown as memory device 100_1, the second memory device 100 is shown as memory device 100_2, and the third memory device 100 is shown as memory device 100_3.

[0074] When one memory device 100 has n memory elements 110, the wiring RBL, the wiring SL, each of the n wirings WL, and each of the n wirings CL can be used as common wirings among the multiple memory devices 100.

[0075] 4, one of the source or drain of the transistor 131 included in the memory device 100_1, one of the source or drain of the transistor 131 included in the memory device 100_2, and one of the source or drain of the transistor 131 included in the memory device 100_3 are electrically connected to a wiring RBL. The other of the source or drain of the transistor 132 included in the memory device 100_1, the other of the source or drain of the transistor 132 included in the memory device 100_2, and the other of the source or drain of the transistor 132 included in the memory device 100_3 are electrically connected to a wiring SL.

[0076] The gate of the transistor 111[1] included in the memory device 100_1, the gate of the transistor 111[1] included in the memory device 100_2, and the gate of the transistor 111[1] included in the memory device 100_3 are electrically connected to the wiring WL[1]. The backgate of the transistor 112[n] included in the memory device 100_1, the backgate of the transistor 112[n] included in the memory device 100_2, and the backgate of the transistor 112[n] included in the memory device 100_3 are electrically connected to the wiring CL[n].

[0077] The memory devices 100_1 to 100_3 may be electrically connected to individual wirings RBL. Fig. 5 is a modification of the perspective circuit diagram shown in Fig. 4. In the perspective circuit diagram shown in Fig. 5, one of a source or a drain of the transistor 131 included in the memory device 100_1 is electrically connected to the wiring RBL[1], one of a source or a drain of the transistor 131 included in the memory device 100_2 is electrically connected to the wiring RBL[2], and one of a source or a drain of the transistor 131 included in the memory device 100_3 is electrically connected to the wiring RBL[3].

[0078] In this case, the gate of the transistor 131 included in each of the memory devices 100_1 to 100_3 is electrically connected to the wiring RSL. Note that the gate of the transistor 131 may be electrically connected to the wiring RSL through a terminal 133.

[0079] 5, the gates of the transistors 132 included in each of the memory devices 100_1 to 100_3 may be electrically connected to the wiring SSL. Note that the gates of the transistors 132 may be electrically connected to the wiring SSL through the terminals 134.

[0080] By providing the wiring RBL for each memory device 100, it is possible to simultaneously read out information held in each memory device 100. Therefore, in a semiconductor device having a plurality of memory devices 100, the speed at which information is read out can be increased.

[0081] In many cases, one string is provided extending in one direction, and wiring for controlling writing or reading of information (for example, wiring WL and wiring CL) often extends in a direction perpendicular to the extension direction of the string.

[0082] <Variation 1> 6 shows a memory device 100A, which is a modification of the memory device 100. The memory device 100A differs from the memory device 100 in that one of the source or the drain of the transistor 111[1] is electrically connected to the other of the source or the drain of the transistor 131 and in that the wiring WBL is omitted. By omitting the wiring WBL, the structure of the memory device 100 is simplified and the area occupied by the memory device 100 can be reduced.

[0083] <Variation 2> 7 shows a memory device 100B which is a modification of the memory device 100. The memory device 100B differs from the memory device 100 in that transistors having back gates are used as the transistors 131 and 132. In FIG. 7, the gate and back gate of the transistor 131 and / or the transistor 132 are electrically connected to each other.

[0084] <Example of storage device operation> An example of the operation of the memory device 100 will be described with reference to the drawings. In this embodiment, a memory device 100 including four memory elements 110 will be described as an example.

[0085] [Write operation] In this embodiment, an example of an operation in which an H potential is written to the memory element 110[1], the memory element 110[2], and the memory element 110[4] and an L potential is written to the memory element 110[3] will be described. Fig. 8(A) is a timing chart illustrating the write operation of the memory device 100. Figs. 9(A), 9(B), 10(A), 10(B), and 11 are circuit diagrams illustrating the write operation of the memory device 100.

[0086] In an initial state, an L potential is written to the memory elements 110[1] to 110[4]. That is, the potentials of the nodes 113[1] to 113[4] are set to an L potential. Also, an L potential is supplied to the wirings WL[1] to WL[4], the wirings CL[1] to CL[4], the terminals 133 and 134, the wirings SL, WBL, and RBL.

[0087] [Period T1] In a period T1, an H potential is supplied to the wirings WL[1] to WL[4] and the wiring WBL (see FIG. 9A). Then, the potentials of the nodes 113[1] to 113[4] become H potentials. Therefore, the transistors 112[1] to 112[4] are turned on.

[0088] In the case where the potential of the wiring WBL is changed in the period T1, the potential of the wiring WBL is preferably changed after the transistors 112[1] to 112[4] are turned on.

[0089] [Period T2] In the period T2, an L potential is supplied to the wiring WL[4] (see FIG. 9B). Then, the transistor 111[4] is turned off, and the charge written to the node 113[4] is held. Here, a charge equivalent to an H potential is held. In addition, an L potential is supplied to the wiring WBL.

[0090] When the potential of the wiring WBL is changed in the period T2, the transistor 111[4] is turned off and then the potential of the wiring WBL is changed. When an L potential is supplied to the wiring WBL, the potentials of the nodes 113[1] to 113[3] become L potentials. Therefore, the transistors 112[1] to 112[3] are turned off.

[0091] [Period T3] In the period T3, an L potential is supplied to the wiring WL[3] (see FIG. 10A). Then, the transistor 111[3] is turned off, and the charge written to the node 113[3] is held. Here, a charge equivalent to the L potential is held. In addition, an H potential is supplied to the wiring WBL.

[0092] When the potential of the wiring WBL is changed in the period T3, the potential of the wiring WBL is changed after the transistor 111[3] is turned off. When an H potential is supplied to the wiring WBL, the potentials of the node 113[1] and the node 113[2] become H potentials. Therefore, the transistor 112[1] and the transistor 112[2] are turned on.

[0093] [Period T4] In the period T4, an L potential is supplied to the wiring WL[2] (see FIG. 10B). Then, the transistor 111[2] is turned off, and the charge written to the node 113[2] is held. Here, a charge equivalent to an H potential is held.

[0094] In this embodiment, since an H potential is written to the node 113[1] in the period T5, the potential of the wiring WBL remains at an H potential. When the potential of the wiring WBL is changed in the period T4, the potential of the wiring WBL is changed after the transistor 111[2] is turned off.

[0095] [Period T5] In the period T5, an L potential is supplied to the wiring WL[1] (see FIG. 11). Then, the transistor 111[1] is turned off, and the charge written to the node 113[1] is held. Here, a charge equivalent to an H potential is held. In this manner, data can be written to the memory elements 110[1] to 110[4].

[0096] In the case where the potential of the wiring WBL is changed in the period T5, the potential of the wiring WBL is changed after the transistor 111[1] is turned off.

[0097] As described above, the memory device 100 according to one embodiment of the present invention does not require the erase operation before data is rewritten, which is performed in a flash memory. Therefore, data can be rewritten in the same manner as the write operation described above.

[0098] Furthermore, when writing information to a memory element 110 close to the wiring WBL, the operation of writing information to a memory element 110 located farther away than the memory element 110 can be omitted. For example, when writing information to the memory element 110[1], the operation of writing information to the memory elements 110[2] to 110[4] can be omitted. When writing information to the memory element 110[2], the operation of writing information to the memory elements 110[3] and 110[4] can be omitted. Therefore, by storing information that is frequently rewritten in the memory element 110 close to the wiring WBL, the time required for writing (rewriting) information can be shortened. In other words, the speed of writing (rewriting) information can be increased.

[0099] [Read operation] In this embodiment, an example of a read operation of information stored in the memory element 110[2] among information stored in the memory elements 110[1] to 110[4] will be described. It is assumed that an H potential is stored in the memory element 110[2]. FIG. 8B is a timing chart for explaining the read operation. FIG. 12A, FIG. 12B, FIG. 13A, and FIG. 13B are circuit diagrams for explaining the read operation.

[0100] [Period T6] In a period T6, an H potential is supplied to the wirings CL[1] to CL[4] and the terminal 133 to turn on the transistors 112[1] to 112[4] and the transistor 131. The wiring RBL is precharged with an H potential (see FIG. 12A). Specifically, after the H potential is supplied to the wiring RBL, the wiring RBL is put into a floating state.

[0101] [Period T7] In the period T7, an L potential is supplied to the wiring CL[2] (see FIG. 12B). Because the H potential is held at the node 113[2], the transistor 112[2] remains on.

[0102] [Period T8] In a period T8, an H potential is supplied to the terminal 134 to turn on the transistor 132 (see FIG. 13A). Since the transistors 112[1] to 112[4] are all on, the wiring RBL and the wiring SL are brought into electrical continuity, and the potential of the wiring RBL changes to an L potential.

[0103] Note that when the potential of the node 113[2] is an L potential, the transistor 112[2] is turned off when an L potential is supplied to the wiring CL[2]. In this case, even when the transistor 132 is turned on, the potential of the wiring RBL remains an H potential. By knowing the change in the potential of the wiring RBL, the data stored in the memory element 110 can be known.

[0104] That is, in the period T8, the potential of the wiring CL corresponding to the memory element 110 from which data is to be read is set to an L potential, so that data held in the memory element 110 can be read.

[0105] [Period T9] In a period T9, an L potential is supplied to the wirings CL[1] to CL[4], the terminal 133, and the terminal 134 (see FIG. 13B). As a result, the transistors 112[1], 112[2], 112[4], 131, and 132 are turned off.

[0106] The memory device 100 described in this embodiment and the like functions as a NAND type memory device.

[0107] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0108] (Embodiment 2) In this embodiment, another configuration example and operation example of the storage device 100 shown in the above embodiment will be described.

[0109] <Storage device configuration example> FIG 14 shows a circuit diagram of memory device 100C. FIG 15 shows a circuit diagram of memory device 100D. Memory device 100C and memory device 100D are modified versions of memory device 100 shown in the above embodiment. To reduce repetition of explanation, this embodiment will mainly explain the differences between memory device 100C and memory device 100D and memory device 100.

[0110] The memory device 100C and the memory device 100D have a configuration in which a transistor 116 is added to the memory device 100.

[0111] 14, one of the source and drain of the transistor 111[1] is electrically connected to the wiring WBL1. One of the source and drain of the transistor 116 is electrically connected to the node 113[n], and the other is electrically connected to the wiring WBL2. The gate of the transistor 116 is electrically connected to the terminal 136.

[0112] 15 is a modification of the memory device 100C. In the memory device 100D, one of the source and the drain of the transistor 111[1] is electrically connected to the other of the source and the drain of the transistor 131. In addition, the other of the source and the drain of the transistor 116 is electrically connected to the one of the source and the drain of the transistor 132.

[0113] In the memory devices 100C and 100D, similarly to the memory device 100, the gate of the transistor 111 may be electrically connected to the wiring WL. Alternatively, the gate of the transistor 111 may be electrically connected to the wiring WL through a terminal 121. The backgate of the transistor 112 may be electrically connected to the wiring CL. Alternatively, the backgate of the transistor 112 may be electrically connected to the wiring CL through a terminal 122. The gate of the transistor 116 may be electrically connected to a wiring WSL described later. Alternatively, the gate of the transistor 116 may be electrically connected to the wiring WSL through a terminal 136.

[0114] The transistor 116 can be the same as the transistor 111. An OS transistor is preferably used as the transistor 116. Alternatively, the transistor 116 may have a backgate.

[0115] <Example of storage device operation> An operation example of the memory device 100C will be described with reference to Figures 16, 17(A), 17(B), and 18. Here, a memory device 100C including four memory elements 110 will be described as an example. In addition, in the memory device 100C, the gate of the transistor 111[1] is electrically connected to the wiring WL[1], the gate of the transistor 111[2] is electrically connected to the wiring WL[2], the gate of the transistor 111[3] is electrically connected to the wiring WL[3], the gate of the transistor 111[4] is electrically connected to the wiring WL[4], and the gate of the transistor 116 is electrically connected to the wiring WSL.

[0116] In addition, in the memory device 100C, the backgate of the transistor 112[1] is electrically connected to the wiring CL[1], the backgate of the transistor 112[2] is electrically connected to the wiring CL[2], the backgate of the transistor 112[3] is electrically connected to the wiring CL[3], and the backgate of the transistor 112[4] is electrically connected to the wiring CL[4].

[0117] [Write operation] In this embodiment, an example of an operation in which an H potential is written to the memory elements 110[1] to 110[3] and an L potential is written to the memory element 110[4] is described. Fig. 16 is a timing chart illustrating the write operation of the memory device 100C. Figs. 17A, 17B, and 18 are circuit diagrams illustrating the write operation of the memory device 100C.

[0118] In an initial state, an L potential is written to the memory elements 110[1] to 110[4]. That is, the potentials of the nodes 113[1] to 113[4] are set to an L potential. Also, an L potential is supplied to the wirings WL[1] to WL[4], the wirings CL[1] to CL[4], the terminals 133, 134, the wiring SL, the wiring RBL, the wiring WSL, the wiring WBL1, and the wiring WBL2.

[0119] [Period T11] In period T11, an H potential is supplied to wiring WL[1], wiring WL[2], wiring WL[4], wiring WSL, wiring WBL1, and wiring WBL2 (see Figure 17A). The wiring WL[3] is kept at an L potential. Then, transistors 111[1], 111[2], 111[4], and 116 are turned on, and the potentials of nodes 113[1] to 113[4] become H potentials. Therefore, transistors 112[1] to 112[4] are turned on.

[0120] When the potential of the wiring WBL1 is changed in the period T11, it is preferable to change the potential of the wiring WBL after the transistors 112[1] and 112[2] are turned on. When the potential of the wiring WBL2 is changed in the period T11, it is preferable to change the potential of the wiring WBL2 after the transistors 112[4] and 116 are turned on.

[0121] [Period T12] In the period T12, an L potential is supplied to the wiring WL[2] and the wiring WL[4] (see FIG. 17B). Then, the transistors 111[2] and 111[4] are turned off, and the charges written to the nodes 113[2] and 113[3] are held. In this embodiment, charges equivalent to an H potential are held. In addition, an L potential is supplied to the wiring WBL2.

[0122] When the potential of the wiring WBL1 is changed in the period T12, the transistor 111[2] is turned off and then the potential of the wiring WBL1 is changed. When the potential of the wiring WBL2 is changed in the period T12, the transistor 111[3] is turned off and then the potential of the wiring WBL2 is changed. When an L potential is supplied to the wiring WBL2, the potential of the node 113[4] becomes an L potential. Therefore, the transistor 112[4] is turned off.

[0123] [Period T13] In a period T13, an L potential is supplied to the wiring WL[1] and the wiring WSL (see FIG. 18). Then, the transistor 111[1] and the transistor 116 are turned off, and the charges written to the node 113[1] and the node 113[4] are held. In this embodiment, a charge corresponding to an H potential is held in the node 113[1], and a charge corresponding to an L potential is held in the node 113[4].

[0124] The potential of the wiring WBL1 is changed after the transistor 111[1] is turned off, and the potential of the wiring WBL2 is changed after the transistor 116 is turned off.

[0125] In the memory device 100C, the time required for a write operation can be made shorter than that of the memory device 100 since information can be written from both the wiring WBL1 and the wiring WBL2.

[0126] The memory device 100D can operate in the same manner as the memory device 100C. However, in the memory device 100D, the wiring RBL functions as the wiring WBL1 and the wiring SL functions as the wiring WBL2 during a write operation. In the memory device 100D, the transistors 131 and 132 are turned on during a write operation. At this time, a short circuit between the wiring RBL and the wiring SL can be prevented by supplying an L potential to at least one of the multiple wirings CL.

[0127] In the memory device 100C and the memory device 100D, n is preferably an even number. When n is an even number, the transistor 111 that is turned off in the period T11 is the (n / 2+1)th transistor 111.

[0128] [Read operation] The read operation of the memory device 100C and the memory device 100D can be performed in the same manner as the memory device 100. Therefore, the description thereof will be omitted in this embodiment.

[0129] <Modification> A modified example of the memory device 100C is shown as memory device 100E in Fig. 19. A modified example of the memory device 100D is shown as memory device 100F in Fig. 20. The memory device 100E and the memory device 100F do not include the transistor 116 included in the memory device 100C and the memory device 100D, and have a configuration in which the transistor 111[k] and the transistor 111[k+1] are electrically separated from each other.

[0130] In the storage device 100E and the storage device 100F, it is preferable that n is an even number. When n is an even number, k may be set to n / 2.

[0131] In the memory element 110[k+1], one of the source or the drain of the transistor 111[k+1] is electrically connected to the gate of the transistor 112[k+1], and the other one is electrically connected to one of the source or the drain of the transistor 111[k+2].

[0132] In the memory element 110[n], one of the source and the drain of the transistor 111[n] is electrically connected to the gate of the transistor 112[n] and the other of the source and the drain of the transistor 111[n-1] (not shown).

[0133] In the memory elements 110[k+1] to 110[n], a node where one of the source and the drain of the transistor 111 and the gate of the transistor 112 are electrically connected functions as a node 113.

[0134] The write operation of the memory device 100E and the memory device 100F can be performed in the same manner as the memory device 100C and the memory device 100D, except that there is no transistor 111 (for example, the transistor 111[3] in the above description of the write operation) that is turned off during the period T11. The read operation can also be performed in the same manner as the memory device 100C and the memory device 100D.

[0135] In addition, in the memory device 100E and the memory device 100F, the write operation of the memory elements 110[1] to 110[k] and the write operation of the memory elements 110[k+1] to 110[n] can be performed separately. Therefore, the power consumption required for the write operation can be reduced.

[0136] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0137] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device 200 including a memory device 100 will be described.

[0138] 21 is a block diagram illustrating a configuration example of a semiconductor device 200 according to one embodiment of the present invention. The semiconductor device 200 illustrated in FIG. 21 includes a driver circuit 210 and a memory array 220. The memory array 220 includes one or more memory devices 100. FIG. 21 illustrates an example in which the memory array 220 includes a plurality of memory devices 100 (a plurality of strings) arranged in a matrix.

[0139] The drive circuit 210 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 includes a peripheral circuit 211, a control circuit 212, and a voltage generating circuit 228.

[0140] In the semiconductor device 200, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0141] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 212.

[0142] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine an operation mode (e.g., a write operation, a read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0143] The voltage generating circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 228. For example, when an H-level signal is provided to the signal WAKE, the signal CLK is input to the voltage generating circuit 228, and the voltage generating circuit 228 generates a negative voltage.

[0144] The peripheral circuit 211 is a circuit for writing and reading data to and from the memory device 100. The peripheral circuit 211 has a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0145] The row decoder 221 and the column decoder 222 have a function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying a row to be accessed, and the column decoder 222 is a circuit for specifying a column to be accessed. The row driver 223 has a function of selecting the wiring WL specified by the row decoder 221. The column driver 224 has a function of writing data to the memory device 100, a function of reading data from the memory device 100, a function of holding the read data, and the like.

[0146] The input circuit 225 has a function of holding a signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is data (Din) to be written to the memory device 100. The data (Dout) read from the memory device 100 by the column driver 224 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. In addition, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is a signal RDA.

[0147] The PSW241 has a function of controlling the supply of VDD to the peripheral circuit 215. The PSW242 has a function of controlling the supply of VHM to the row driver 223. Here, the high power supply voltage of the semiconductor device 200 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD. The on / off of the PSW241 is controlled by a signal PON1, and the on / off of the PSW242 is controlled by a signal PON2. In FIG. 21, the number of power supply domains to which VDD is supplied in the peripheral circuit 215 is one, but it may be multiple. In this case, a power switch may be provided for each power supply domain.

[0148] The driving circuit 210 and the memory array 220 may be provided on the same plane. Also, as shown in Fig. 22(A), the driving circuit 210 and the memory array 220 may be provided so as to overlap each other. By providing the driving circuit 210 and the memory array 220 so as to overlap each other, the signal propagation distance can be shortened. Also, as shown in Fig. 22(B), the memory array 220 may be provided so as to overlap in multiple layers on the driving circuit 210.

[0149] Also, as shown in FIG. 22C, memory arrays 220 may be provided above and below the driving circuit 210. FIG. 22C shows an example in which one memory array 220 is provided above and below the driving circuit 210. By arranging the driving circuit 210 between a plurality of memory arrays 220, the signal propagation distance can be further shortened. Note that the number of layers of the memory array 220 stacked above the driving circuit 210 and the memory array 220 stacked below the driving circuit 210 may each be one or more. It is preferable that the number of memory arrays 220 stacked above the driving circuit 210 and the number of memory arrays 220 stacked below the driving circuit 210 are equal.

[0150] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0151] (Embodiment 4) In this embodiment, a specific configuration example and a manufacturing method of the memory device 100 will be described with reference to the drawings.

[0152] <Storage device configuration example> A configuration example of the memory device 100 will be described with reference to FIG. 23(A), FIG. 23(B), FIG. 24(A), FIG. 24(B), FIG. 25, FIG. 26(A), and FIG. 26(B). FIG. 23(A) is a top view of the memory device 100. FIG. 23(B) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 23(A). FIG. 24(A) is a cross-sectional view of a portion indicated by a dashed line B1-B2 in FIG. 23(A). FIG. 24(B) is a cross-sectional view of a portion indicated by a dashed line C1-C2 in FIG. 23(A). FIG. 25 is an enlarged view of the transistor 112[1] shown in FIG. 23(B). FIG. 26(A) is a cross-sectional view of a portion indicated by a dashed line D1-D2 in FIG. 23(A). FIG. 26(B) is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in FIG. 23(A), and is a modified example of FIG. 23(B).

[0153] Fig. 23(B), Fig. 25, Fig. 26(A), and Fig. 26(B) show cross sections of the transistor in the channel length direction. Fig. 24(A) and Fig. 24(B) show cross sections of the transistor in the channel width direction. Note that in the top view of Fig. 23(A), some elements are omitted for clarity.

[0154] The memory device 100 has an insulator 312 on a substrate (not shown), an insulator 314 on the insulator 312, an insulator 316 on the insulator 314, and conductors 305 (conductors 305a, 305b, and 305c) arranged so as to be embedded in the insulator 316. The memory device 100 also has an insulator 322 on the insulator 316 and on the conductor 305, an insulator 324 on the insulator 322, an oxide 330a_1 on the insulator 324, and an oxide 330b_1 on the oxide 330a_1. Note that in this specification and the like, the oxide 330a_1 and the oxide 330b_1 may be collectively referred to as the oxide 330_1.

[0155] The memory device 100 also has an oxide 343a, an oxide 343b, and an insulator 350 on the oxide 330b_1, a conductor 342a on the oxide 343a, and a conductor 342b on the oxide 343b. In this specification and the like, the oxide 343a and the oxide 343b may be collectively referred to as the oxide 343. The conductor 342a and the conductor 342b may be collectively referred to as the conductor 342.

[0156] The memory device 100 also has a conductor 360 (conductor 360a and conductor 360b) that overlaps a part of the oxide 330b_1 via the insulator 350, an insulator 375 that is arranged to cover the conductor 342, and an insulator 380 on the insulator 375. An opening that reaches the oxide 330b_1 is provided in the insulator 380 and the insulator 375. The insulator 350 and the conductor 360 are arranged in the opening. The opening is also provided between the conductor 342a and the oxide 343a and the conductor 342b and the oxide 343b. Thus, the conductor 360 is provided between the conductor 342a and the oxide 343a and the conductor 342b and the oxide 343b. Here, the insulator 350 is preferably provided in contact with an upper surface of the oxide 330b_1 overlapping with the opening, a side surface of the oxide 343, a side surface of the conductor 342, a side surface of the insulator 375, and a side surface of the insulator 380. The conductor 360 is preferably provided in contact with the insulator 350. As shown in Fig. 23(B) and Fig. 25, an upper surface of the conductor 360, an upper surface of the insulator 350, and an upper surface of the insulator 380 are in contact with the insulator 335 described later.

[0157] The memory device 100 also has an oxide 330a_2 on the insulator 380 and an oxide 330b_2 on the oxide 330a_2. Note that in this specification and the like, the oxide 330a_2 and the oxide 330b_2 may be collectively referred to as the oxide 330_2.

[0158] In addition, in order to reduce repetition of explanation, in this specification and the like, when matters common to oxide 330_1 and oxide 330_2 are described, they may be simply referred to as "oxide 330". Similarly, when matters common to oxide 330a_1 and oxide 330a_2 are described, they may be simply referred to as "oxide 330a". Similarly, when matters common to oxide 330b_1 and oxide 330b_2 are described, they may be simply referred to as "oxide 330b".

[0159] The oxide 330 preferably has an oxide 330a and an oxide 330b. By having the oxide 330a below the oxide 330b, it is possible to suppress the diffusion of impurities from a structure formed below the oxide 330a to the oxide 330b.

[0160] The memory device 100 also has an oxide 345 and an insulator 351 on the oxide 330b_2, and a conductor 344 on the oxide 345. The memory device 100 also has a conductor 361 (conductor 361a and conductor 361b) overlapping a part of the oxide 330b_2 via the insulator 351, an insulator 335 arranged to cover the conductor 344, and an insulator 384 on the insulator 335.

[0161] The insulator 384, the insulator 335, the conductor 344, and the oxide 345 have openings that reach the oxide 330b_2. The insulator 351 and the conductor 361 are disposed in the openings. Here, the insulator 351 is preferably provided in contact with an upper surface of the oxide 330b_2 that overlaps with the openings, a side surface of the oxide 345, a side surface of the conductor 344, a side surface of the insulator 335, and a side surface of the insulator 384. The conductor 361 is preferably provided in contact with the insulator 351. As shown in FIG. 23B, an upper surface of the conductor 361, an upper surface of the insulator 351, and an upper surface of the insulator 384 are in contact with the insulator 385 described later.

[0162] The memory device 100 also has an insulator 385 over the conductor 361, the insulator 351, and the insulator 384, and an insulator 378 over the insulator 385. The memory device 100 also has a region at the end of the string or in a region outside the string where parts of the insulator 385, the insulator 384, the insulator 335, the insulator 380, the insulator 375, the conductor 342, the oxide 343, the oxide 330_1, the insulator 324, the insulator 322, the insulator 316, the insulator 314, and the like have been removed. In FIG. 23B, part of the insulator 378 is in contact with part of the insulator 312 in this region.

[0163] The memory device 100 also has a conductor 338 and a conductor 339 on an insulator 378. The conductor 338 is electrically connected to one of a source electrode or a drain electrode of the transistor 131 through a contact plug 340 embedded in the insulator 378, the insulator 385, the insulator 384, the insulator 335, the insulator 380, and the insulator 375. An insulator 337 is provided on a side surface of the contact plug 340. The conductor 339 is electrically connected to one of a source electrode or a drain electrode of the transistor 111[1] through a contact plug 341 embedded in the insulator 378, the insulator 385, the insulator 384, and the insulator 335. The memory device 100 also has an insulator 379 on the insulator 378, the conductor 338, and the conductor 339.

[0164] The oxide 330a and the oxide 330b function as semiconductor layers. Note that in this embodiment, the oxide 330 has a structure in which two layers of the oxide 330a and the oxide 330b are stacked; however, the present invention is not limited to this. For example, the oxide 330b may have a single layer or a stacked structure of three or more layers, or each of the oxide 330a and the oxide 330b may have a stacked structure. In addition, when an oxide similar to the oxide 330a or the oxide 330b is stacked on the oxide 330b, the oxide may be provided in a shape that follows the bottom and side surfaces of the opening, as in the insulator 350.

[0165] In this embodiment and the like, the conductor 338 functions as a wiring RBL, and the conductor 339 functions as a wiring WBL. The conductor 360 functions as a gate electrode (also referred to as a "first gate" or a "first gate electrode") of the transistor 112, and the conductor 305 functions as a backgate electrode (also referred to as a "second gate" or a "second gate electrode") of the transistor 112. The conductor 361 functions as a gate electrode of the transistor 111.

[0166] The conductor 305 included in the transistor 112[1] functions as a wiring CL[1]. The conductor 361 included in the transistor 111[1] functions as a wiring WL[1].

[0167] Similarly, the conductor 305 of the transistor 112[i] functions as a wiring CL[i]. The conductor 361 of the transistor 111[i] functions as a wiring WL[i] (see FIG. 26A).

[0168] The insulator 350 and the insulator 351 function as a gate insulator (also referred to as a "first gate insulator"). The insulator 324 and the insulator 322 function as a back gate insulator (also referred to as a "second gate insulator"). The conductor 342 and the conductor 344 function as a source electrode or a drain electrode.

[0169] At least a part of a region of the oxide 330_1 that overlaps with the conductor 360 functions as a channel formation region. Similarly, at least a part of a region of the oxide 330_2 that overlaps with the conductor 361 functions as a channel formation region.

[0170] 25, the oxide 330_1 has a region 333c which functions as a channel formation region of the transistor and a region 333sd which functions as a source region or drain region. The region 333c at least partially overlaps with the conductor 360. In other words, the region 333c is provided in a region between the conductor 342a and the conductor 342b. The region 333sd is provided so as to overlap with the conductor 342. Note that although FIG. 25 is an enlarged view of the transistor 112, the oxide 330_2 included in the transistor 111 is similar to the oxide 330_1.

[0171] The region 333c functioning as a channel formation region has fewer oxygen vacancies or a lower impurity concentration than the region 333sd, and is therefore a high-resistance region with a low carrier concentration. The region 333sd functioning as a source region or drain region has many oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, and metal elements, and thus has an increased carrier concentration and low resistance. In other words, the region 333sd has a higher carrier concentration and a lower resistance than the region 333c.

[0172] Here, the carrier concentration of the region 333c functioning as a channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 333c functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0173] A region may be formed between the region 333c and the region 333sd, the carrier concentration of which is equal to or lower than that of the region 333sd and equal to or higher than that of the region 333c. That is, the region functions as a junction region between the region 333c and the region 333sd. The junction region may have a hydrogen concentration equal to or lower than that of the region 333sd and equal to or higher than that of the region 333c. The junction region may have an oxygen vacancy equal to or less than that of the region 333sd and equal to or more than that of the region 333c.

[0174] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide 330. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may change continuously in each region, not just stepwise. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0175] Here, the region 333c is formed in each transistor 112, but the region 333sd overlapping with the conductor 342a and the conductor 342a are shared by two adjacent transistors 112. For example, the conductor 342a functions as one of the source electrode or drain electrode of the transistor 112[i] and at the same time functions as the other of the source electrode or drain electrode of the transistor 112[i-1]. Also, for example, the conductor 342b functions as the other of the source electrode and drain electrode of the transistor 112[i] and at the same time functions as one of the source electrode and drain electrode of the transistor 112[i+1].

[0176] In addition, the region 333sd overlapping with the conductor 342a functions as one of the source and drain of the transistor 112[i] and also functions as the other of the source and drain of the transistor 112[i+1]. In this manner, the sources and drains of the multiple transistors 112 are connected in series. Note that the source and drain of the transistor 111 are also connected in series, similar to the transistor 112.

[0177] By sharing the source and drain between adjacent transistors, it is possible to reduce the area occupied by the memory device 100. Therefore, it is possible to increase the memory capacity per unit area.

[0178] It is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 330 including the channel formation region. In addition, it is preferable to use a metal oxide that functions as a semiconductor having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap in this manner, the off-state current of the transistor can be reduced.

[0179] By reducing the off-state current of the transistor 111, leakage current between the wiring RBL and the wiring SL can be significantly reduced. As a result, power consumption of the memory device can be significantly reduced. Furthermore, by reducing the off-state current of the transistor 112, the data retention time of the memory element 110 can be significantly extended.

[0180] As the oxide 330_1 and the oxide 330_2, for example, a metal oxide such as an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, or magnesium) may be used. For example, an In-Ga-Zn oxide may be used as the oxide 330, or an oxide obtained by adding tin to an In-Ga-Zn oxide (In-Ga-Zn-Sn oxide) may be used. Also, as the oxide 330_1 and the oxide 330_2, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0181] The metal oxide can be formed on a substrate by using a sputtering method or the like. Thus, a memory cell array can be provided on a peripheral circuit such as a driving circuit formed on a silicon substrate. This reduces the area occupied by the peripheral circuit provided on one chip and increases the area occupied by the memory cell array, thereby increasing the memory capacity of the semiconductor device. Furthermore, by forming a plurality of layers of the metal oxide film, the memory cell array can be provided in a stacked manner. This allows cells to be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D cell array can be configured. Thus, a semiconductor device with a large memory capacity can be provided by achieving high integration of memory cells.

[0182] Here, it is preferable that the atomic ratio of In to the element M in the metal oxide used for oxide 330b is greater than the atomic ratio of In to the element M in the metal oxide used for oxide 330a.

[0183] In this manner, by disposing the oxide 330a below the oxide 330b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 330a into the oxide 330b.

[0184] In addition, since the oxide 330a and the oxide 330b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 330a and the oxide 330b can be reduced. Since the defect state density at the interface between the oxide 330a and the oxide 330b can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0185] It is preferable that the oxide 330a and the oxide 330b each have crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 330b_1 (the oxide 330b_2).

[0186] CAAC-OS has a highly crystalline and dense structure and is free of impurities and defects (e.g., oxygen vacancies (V O In particular, by subjecting the metal oxide to heat treatment at a temperature at which the metal oxide does not polycrystallize (for example, 400° C. or higher and 600° C. or lower) after formation of the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0187] On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is said that the decrease in electron mobility caused by grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0188] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region in which a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies is called a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V OH.) and may generate electrons that serve as carriers even when no voltage is applied to the gate electrode of the transistor. For this reason, if oxygen vacancies are present in the region in the oxide semiconductor in which a channel is formed, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and current flows through the transistor). Therefore, in the region in the oxide semiconductor in which a channel is formed, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, in a state in which no voltage is applied to the gate electrode of the transistor, a region in the oxide semiconductor where a channel is formed preferably has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0189] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor and heat treatment is performed. In this way, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or drain region, this may cause a decrease in the on-current of the transistor or a decrease in the field effect mobility. Furthermore, if the oxygen supplied to the source region or drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0190] Therefore, in the oxide semiconductor, the region 333c functioning as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the region 333sd functioning as a source region or drain region preferably has a high carrier concentration and is n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the region 333sd.

[0191] For example, in the manufacture of the transistor 112, an opening is formed in a part of the insulator 380 and the insulator 375 to expose a part of the oxide 330b_1, and a microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 333c and V O The microwave treatment is intended to reduce H. Here, the microwave treatment refers to a treatment using an apparatus having a power source that generates high density plasma using microwaves, for example. Note that the microwave treatment may be performed after the insulator 350 is formed.

[0192] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be made to work. At this time, microwaves or high frequency waves such as RF can also be irradiated onto region 333c. The V O H is split off, hydrogen H is removed from the region 333c, and oxygen vacancy V O can be supplemented with oxygen. That is, in the region 333c, O H→H+V O " occurs, and the hydrogen concentration in the region 333c can be reduced. Therefore, the oxygen vacancies in the region 333c and the V O H can be reduced, lowering the carrier concentration.

[0193] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like are shielded by the conductors 342a and 342b and do not reach the region 333sd. Furthermore, the effects of oxygen plasma can be reduced by the insulators 375 and 380. As a result, during microwave processing, the V O A reduction in H and an excessive supply of oxygen do not occur, and a reduction in the carrier concentration in the region 333sd can be prevented.

[0194] In this manner, oxygen vacancies and V OBy removing H, the region 333c can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region 333sd that functions as a source region or a drain region can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 112, and suppresses variations in the electrical characteristics of the transistor 112 within the substrate surface.

[0195] When the transistor 111 is formed, microwave treatment can be performed in the same manner as the transistor 112 .

[0196] By configuring the transistor 111 and the transistor 112 as described above, a semiconductor device with less variation in transistor characteristics can be provided. In addition, a semiconductor device with good electrical characteristics can be provided. In addition, a semiconductor device with good reliability can be provided.

[0197] In FIG. 23B and other figures, the side of the opening into which the conductor 360 and the like are embedded and / or the side of the opening into which the conductor 361 and the like are embedded are approximately perpendicular to the surface on which the oxide 330b is to be formed, but this embodiment is not limited to this. For example, the bottom of the opening may be in a U-shape with a gentle curve. Also, for example, the side of the opening may be inclined with respect to the surface on which the oxide 330b is to be formed.

[0198] 24A, in a cross-sectional view of the transistor 112 in the channel width direction, a curved surface may be formed between a side surface of the oxide 330b_1 and a top surface of the oxide 330b_1. In other words, ends of the side surface and the top surface may be curved (also referred to as rounded). Similarly, as shown in FIG. 24B, in a cross-sectional view of the transistor 111 in the channel width direction, a curved surface may be formed between a side surface of the oxide 330b_2 and a top surface of the oxide 330b_2.

[0199] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 330b_1 (or oxide 330b_2) in the region overlapping with the conductor 342 (or conductor 344), or smaller than half the length of the region of the upper surface of the oxide 330b_1 (or oxide 330b_2) that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. Such a shape can improve the coverage of the insulator 350 (or insulator 351) and the conductor 360 (or conductor 361) with the oxide 330b_1 (or oxide 330b_2).

[0200] The oxide 330 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 330a, the atomic ratio of element M to the metal element that is the main component is preferably greater than the atomic ratio of element M to the metal element that is the main component in the metal oxide used for the oxide 330b. In addition, in the metal oxide used for the oxide 330a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 330b. In addition, in the metal oxide used for the oxide 330b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 330a.

[0201] Moreover, the oxide 330b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies) and have a highly crystalline and dense structure. This makes it possible to suppress the extraction of oxygen from the oxide 330b by the source or drain electrode. This makes it possible to reduce the extraction of oxygen from the oxide 330b even when heat treatment is performed, so that the OS transistor is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0202] Here, the conduction band minimum changes gradually at the junction between the oxide 330a and the oxide 330b. In other words, the conduction band minimum at the junction between the oxide 330a and the oxide 330b changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 330a and the oxide 330b.

[0203] Specifically, when the oxide 330a and the oxide 330b have a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 330b is an In-M-Zn oxide, the oxide 330a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0204] For example, the oxide 330a may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 330b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use gallium as the element M.

[0205] In addition, when a metal oxide film is formed by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0206] By configuring the oxide 330a and the oxide 330b as described above, the defect state density at the interface between the oxide 330a and the oxide 330b can be reduced. As a result, the effect of interface scattering on carrier conduction is reduced, and the OS transistor can have high field-effect mobility, high on-state current, and high frequency characteristics. By using such a transistor as the transistor 111, the writing speed can be improved. In addition, by using such a transistor as the transistor 112, the reading speed can be improved.

[0207] At least one of the insulators 312, 314, 385, and 378 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 111 to the transistor 111 and the transistor 112. Therefore, at least one of the insulators 312, 314, 385, and 378 is preferably made of an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (through which the above impurities are unlikely to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (through which the above oxygen is unlikely to permeate). The insulator 375 and / or the insulator 335 may be made of an insulating material having a function of suppressing the diffusion of impurities. The insulator 375 and / or the insulator 335 may be made of an insulating material having a function of suppressing the diffusion of oxygen.

[0208] In this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property means a function of suppressing the diffusion of a corresponding substance (also called low permeability) or a function of capturing and fixing a corresponding substance (also called gettering).

[0209] For example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used as the insulator 312, the insulator 314, the insulator 385, the insulator 378, the insulator 375, and the insulator 335. For example, it is preferable to use silicon nitride or the like, which has a higher hydrogen barrier property, as the insulator 312 and the insulator 378. For example, it is preferable to use aluminum oxide or the like, which has a higher function of capturing and fixing hydrogen, as the insulator 314, the insulator 375, the insulator 335, and the insulator 385. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 111 and the transistor 112 side through the insulator 312 and the insulator 314. Alternatively, it can suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like arranged outside the insulator 378 to the transistor 111 and the transistor 112 side. Alternatively, oxygen contained in the insulator 324 and the like can be suppressed from diffusing toward the substrate side through the insulator 312 and the insulator 314. Alternatively, oxygen contained in the insulator 380, the insulator 384, and the like can be suppressed from diffusing upward from the transistor 111 through the insulator 378 and the like. In this manner, it is preferable to have a structure in which the transistor 111, the transistor 112, and the like are surrounded by the insulators 312, 314, 385, and 378, which have the function of suppressing diffusion of impurities such as water and hydrogen, and oxygen.

[0210] The insulators 312, 314, 385, 378, 375, and 335 may be formed by, for example, a sputtering method. The sputtering method does not require the use of hydrogen as a film formation gas, and therefore can reduce the hydrogen concentration in the insulators 312, 314, 385, 378, 375, and 335. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may be used as appropriate.

[0211] It may also be preferable to reduce the resistivity of the insulator 312 and the insulator 378. For example, the resistivity of the insulator 312 and the insulator 378 may be reduced to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 312 and the insulator 378 may be able to reduce charge-up of the conductor 305, the conductor 342, the conductor 360, the conductor 344, or the conductor 361 in a process using plasma or the like in a semiconductor device manufacturing process. 10 Ωcm or more 1×10 15 Ωcm or less.

[0212] The insulator 316, the insulator 380, and the insulator 384 preferably have a lower dielectric constant than the insulator 314. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as the insulator 316, the insulator 380, and the insulator 384 as appropriate. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0213] In this specification, the term "oxynitride" in the name of a material refers to a material having a composition in which the oxygen content is greater than the nitrogen content, and the term "oxynitride" in the name of a material refers to a material having a composition in which the nitrogen content is greater than the oxygen content.

[0214] The conductor 305 includes conductor 305a, conductor 305b, and conductor 305c. The conductor 305a is provided in contact with the bottom surface and side wall of the opening. The conductor 305b is provided so as to be embedded in a recess formed in the conductor 305a. Here, the upper surface of the conductor 305b is lower than the upper surface of the conductor 305a and the upper surface of the insulator 316. The conductor 305c is provided in contact with the upper surface of the conductor 305b and the side surface of the conductor 305a. Here, the height of the upper surface of the conductor 305c is approximately equal to the height of the upper surface of the conductor 305a and the height of the upper surface of the insulator 316. In other words, the conductor 305b is configured to be enclosed by the conductor 305a and the conductor 305c.

[0215] Here, the conductor 305a and the conductor 305c are preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0216] By using a conductive material having a function of reducing hydrogen diffusion for the conductor 305a and the conductor 305c, it is possible to prevent impurities such as hydrogen contained in the conductor 305b from diffusing into the oxide 330 via the insulator 324 and the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion for the conductor 305a and the conductor 305c, it is possible to suppress the conductor 305b from being oxidized and its conductivity from decreasing. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, the conductor 305a may be a single layer or a multilayer of the above conductive material. For example, the conductor 305a may be made of titanium nitride.

[0217] The conductor 305b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0218] The conductor 305 may function as a backgate electrode. In this case, the threshold voltage (Vth) of the transistor 112 can be controlled by changing the potential applied to the conductor 305 independently of the potential applied to the conductor 360. Furthermore, by applying a negative potential to the conductor 305, the Vth of the transistor 112 can be increased and the off-state current can be reduced. Therefore, applying a negative potential to the conductor 305 can reduce the drain current when the potential applied to the conductor 360 is 0 V, compared to not applying a negative potential.

[0219] The electrical resistivity of the conductor 305 is designed taking into consideration the potential applied to the conductor 305, and the film thickness of the conductor 305 is set according to the electrical resistivity. The film thickness of the insulator 316 is approximately the same as that of the conductor 305. Here, it is preferable to make the film thicknesses of the conductor 305 and the insulator 316 thin within the range permitted by the design of the conductor 305. By making the film thickness of the insulator 316 thin, the absolute amount of impurities such as hydrogen contained in the insulator 316 can be reduced, and therefore the diffusion of the impurities into the oxide 330 can be reduced.

[0220] The conductor 305 is provided so as to overlap a region of the oxide 330_1 that does not overlap with the conductor 342a and the conductor 342b. The conductor 305 is preferably provided larger than the region. In other words, the conductor 305 is preferably provided so as to overlap with a region 333c described later and to be larger than the region 333c. In particular, as shown in FIG. 24A, the conductor 305 preferably extends also in a region outside the end of the oxide 330_1 that intersects with the channel width direction. In other words, the conductor 305 and the conductor 360 preferably overlap with each other through an insulator on the outside of the side surface of the oxide 330_1 in the channel width direction. With this structure, the channel formation region of the oxide 330_1 can be electrically surrounded by the electric field of the conductor 360 that functions as a gate electrode (also referred to as a "first gate electrode") and the electric field of the conductor 305 that functions as a backgate electrode (also referred to as a "second gate electrode"). In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric fields of a first gate electrode and a second gate electrode is called a surrounded channel (S-channel) structure.

[0221] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is unlikely to occur.

[0222] 24A, the conductor 305 is extended in the channel width direction to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 305.

[0223] Note that, although the transistor 112 illustrates a case where the conductor 305 has a stacked structure of the conductor 305a, the conductor 305b, and the conductor 305c, the present invention is not limited to this. For example, the conductor 305 may have a single-layer structure, a two-layer structure, or a four or more layer structure.

[0224] The insulator 322 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 322 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 322 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 324.

[0225] The insulator 322 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 322 is formed using such a material, the insulator 322 functions as a layer that suppresses release of oxygen from the oxide 330 to the substrate side and diffusion of impurities such as hydrogen from the periphery of the transistor 112 to the oxide 330. Thus, by providing the insulator 322, it is possible to suppress diffusion of impurities such as hydrogen into the inside of the transistor 112 and suppress generation of oxygen vacancies in the oxide 330. In addition, it is possible to suppress reaction of the conductor 305 with oxygen contained in the insulator 324 or the oxide 330.

[0226] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. The insulator 322 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0227] The insulator 322 may be a single layer or a multilayer of insulators including so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0228] The insulator 324 in contact with the oxide 330_1 preferably contains excess oxygen (oxygen is released by heating). For example, the insulator 324 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 330_1, oxygen vacancies in the oxide 330_1 can be reduced and the reliability of the transistor can be improved.

[0229] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating, in other words, an insulating material having an excess oxygen region, as the insulator 324. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 or more than 3.0×10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0230] In addition, in a manufacturing process of a transistor, it is preferable to perform heat treatment while the surface of the oxide 330 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 330 to reduce oxygen deficiencies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0231] In addition, by subjecting the oxide 330 to an oxygen supply treatment, the oxygen vacancies in the oxide 330 are repaired by the supplied oxygen. In other words, O In addition, the reaction of the hydrogen remaining in the oxide 330 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 330 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0232] The insulator 322 and the insulator 324 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 324 may be formed in an island shape by overlapping with the oxide 330a. In this case, the insulator 375 is configured to contact the side surface of the insulator 324 and the top surface of the insulator 322.

[0233] The oxide 343 is provided over the oxide 330b_1. Note that the oxide 343 is preferably provided so as to overlap with the conductor 342 and may be arranged in a line on the oxide 330_1. Similarly, the oxide 345 is provided over the oxide 330b_2. Note that the oxide 345 is preferably provided so as to overlap with the conductor 344 and may be arranged in a line on the oxide 330_2.

[0234] The oxide 343 and the oxide 345 preferably have a function of suppressing oxygen permeation. By disposing the oxide 343 having the function of suppressing oxygen permeation between the conductor 342 and the oxide 330b_1, the electrical resistance between the conductor 342 and the oxide 330b_1 is reduced, which is preferable. Similarly, by disposing the oxide 345 having the function of suppressing oxygen permeation between the conductor 344 and the oxide 330b_2, the electrical resistance between the conductor 344 and the oxide 330b_2 is reduced, which is preferable.

[0235] Such a structure can improve the electrical characteristics and reliability of the transistor 111 and the transistor 112. Note that if the electrical resistance between the conductor 342 and the oxide 330b_1 can be sufficiently reduced, the oxide 343 may not be provided. If the electrical resistance between the conductor 344 and the oxide 330b_2 can be sufficiently reduced, the oxide 345 may not be provided.

[0236] Metal oxides having element M may be used as the oxide 343 and the oxide 345. In particular, the element M may be aluminum, gallium, yttrium, or tin. The oxide 343 and the oxide 345 preferably have a higher concentration of element M than the oxide 330b. Gallium oxide may be used as the oxide 343 and the oxide 345. Metal oxides such as In-M-Zn oxide may be used as the oxide 343 and the oxide 345. Specifically, in the metal oxide used for the oxide 343 and the oxide 345, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 330b. The film thickness of the oxide 343 and the oxide 345 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. The oxide 343 and the oxide 345 preferably have crystallinity. When the oxide 343 and the oxide 345 have crystallinity, it is possible to suitably suppress the release of oxygen from the oxide 330. For example, when the oxide 343 and the oxide 345 have a crystal structure such as a hexagonal crystal structure, it may be possible to suppress the release of oxygen from the oxide 330.

[0237] As the conductor 342 and the conductor 344, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. In addition, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when they absorb oxygen.

[0238] Note that hydrogen contained in the oxide 330b etc. may diffuse into the conductor 342 or the conductor 344. In particular, by using a nitride containing tantalum for the conductor 342 and the conductor 344, hydrogen contained in the oxide 330b etc. is likely to diffuse into the conductor 342 or the conductor 344, and the diffused hydrogen may bond with nitrogen contained in the conductor 342 or the conductor 344. In other words, hydrogen contained in the oxide 330b etc. may be absorbed by the conductor 342 or the conductor 344.

[0239] It is preferable that no curved surface is formed between the side surface and the top surface of the conductor 342 and between the side surface and the top surface of the conductor 344. By using a conductor that does not have such a curved surface, the cross-sectional area of ​​the conductor 344 in the cross section in the channel width direction can be increased as shown in FIG. 24A. This reduces the resistance of the conductor 344 and increases the on-current of the transistor 111. Similarly, the cross-sectional area of ​​the conductor 342 in the cross section in the channel width direction can be increased as shown in FIG. 24B. This reduces the resistance of the conductor 342 and increases the on-current of the transistor 112.

[0240] The insulator 375 is provided to cover the insulator 324, the oxide 330_1, the oxide 343, and the conductor 342, and has an opening in a region where the insulator 350, the conductor 360, and the like are provided. The insulator 375 is preferably provided in contact with a top surface of the insulator 324, a side surface of the oxide 330_1, a side surface of the oxide 343, a side surface of the conductor 342, and a top surface of the conductor 342 (see FIG. 24B). The insulator 375 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 375 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the oxide 330_1 or the insulator 324, and preferably has a function of capturing impurities such as hydrogen.

[0241] The insulator 335 is provided to cover the insulator 380, the oxide 330_2, the oxide 345, and the conductor 344, and has openings in regions where the insulator 351, the conductor 361, and the like are provided. The insulator 335 is preferably provided in contact with a top surface of the insulator 380, a side surface of the oxide 330_2, a side surface of the oxide 345, a side surface of the conductor 344, and a top surface of the conductor 344 (see FIG. 24A). The insulator 335 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 335 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above to the oxide 330_2 or the insulator 380, and preferably has a function of capturing impurities such as hydrogen.

[0242] As the insulator 375 and the insulator 335, for example, an insulator such as aluminum oxide or silicon nitride may be used.

[0243] By providing the insulator 375 and the insulator 335 as described above, the conductor 342 and the conductor 344 can be wrapped in an insulator having a barrier property against oxygen. In other words, oxygen contained in the insulator 380 can be prevented from diffusing into the conductor 342 and the conductor 344. This can prevent the conductor 342 from being directly oxidized by oxygen contained in the insulator 380, which increases the resistivity and reduces the field-effect mobility and the on-current. In addition, it can prevent the conductor 344 from being directly oxidized by oxygen contained in the insulator 384, which increases the resistivity and reduces the field-effect mobility and the on-current. In this way, the write speed of the memory device 100 can be improved by increasing the field-effect mobility and the on-current of the transistor 111. In addition, the read speed of the memory device 100 can be improved by increasing the field-effect mobility and the on-current of the transistor 112.

[0244] By providing insulator 375 having a function of capturing impurities such as hydrogen in contact with insulator 380 in the region sandwiched between insulator 312 and insulator 378, impurities such as hydrogen contained in insulator 380 and the like can be captured, and the amount of hydrogen in the region can be kept constant. Furthermore, by providing insulator 335 having a function of capturing impurities such as hydrogen in contact with insulator 384, impurities such as hydrogen contained in insulator 384 and the like can be captured, and the amount of hydrogen in the region can be kept constant. In this case, it is preferable to use aluminum oxide or the like as insulator 375 and insulator 335.

[0245] The insulators 350 and 351, which function as gate insulators, are preferably disposed in contact with the upper surface of the oxide 330b. The insulators 350 and 351 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. In particular, oxides containing silicon, such as silicon oxide and silicon oxynitride, are preferred because they are stable against heat.

[0246] Similar to the insulator 324, the concentrations of impurities such as water and hydrogen are preferably reduced in the insulators 350 and 351. The thicknesses of the insulators 350 and 351 are preferably 1 nm or more and 20 nm or less.

[0247] A metal oxide may be provided between the insulator 350 and the conductor 360. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 350 to the conductor 360. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 350 to the conductor 360 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 330 can be suppressed. Also, oxidation of the conductor 360 due to oxygen from the insulator 350 can be suppressed. Similarly, a metal oxide may be provided between the insulator 351 and the conductor 361. For example, hafnium oxide or the like can be used as the metal oxide.

[0248] The metal oxide may be configured to function as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 330 may be used as the metal oxide. In this case, the electric resistance value of the metal oxide can be reduced to make it a conductor by forming the conductor 360a and / or the conductor 361a by a sputtering method. This can be called an OC (Oxide Conductor) electrode.

[0249] The inclusion of the metal oxide can improve the on-state current of the transistor 112 without weakening the influence of the electric field from the conductor 360. Furthermore, the physical thickness of the insulator 350 and the metal oxide can maintain a distance between the conductor 360 and the oxide 330, thereby suppressing leakage current between the conductor 360 and the oxide 330. Furthermore, the provision of a stacked structure of the insulator 350 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 360 and the oxide 330 and the electric field strength applied from the conductor 360 to the oxide 330. The same applies to the insulator 351 and the conductor 361.

[0250] The conductor 360 preferably has a conductor 360a and a conductor 360b arranged on the conductor 360a. The conductor 361 preferably has a conductor 361a and a conductor 361b arranged on the conductor 361a. For example, the conductor 360a is preferably arranged so as to overlap the bottom and side surfaces of the conductor 360b. The conductor 361a is preferably arranged so as to overlap the bottom and side surfaces of the conductor 361b.

[0251] In this embodiment and the like, conductor 360 is shown as having a two-layer structure of conductor 360a and conductor 360b, and conductor 361 is shown as having a two-layer structure of conductor 361a and conductor 361b, but conductor 360 and conductor 361 may have a single-layer structure or a laminated structure of three or more layers.

[0252] The conductor 360a and the conductor 361a are preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0253] Furthermore, since the conductor 360a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity caused by oxidation of the conductor 360b due to oxygen contained in the insulator 350. Since the conductor 361a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity caused by oxidation of the conductor 361b due to oxygen contained in the insulator 351. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0254] Moreover, since the conductor 360 and the conductor 361 also function as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 360b and the conductor 361b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 360b and the conductor 361b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0255] In the transistor 112, the conductor 360 is formed in a self-aligned manner so as to fill an opening formed in the insulator 380 or the like. In the transistor 111, the conductor 361 is formed in a self-aligned manner so as to fill an opening formed in the insulator 384 or the like. By forming the conductor 360 in this manner, it is possible to place the conductor 360 in the region between the conductor 342a and the conductor 342b without aligning them. The same is true for the conductor 361.

[0256] 24A, when the bottom surface of the insulator 322 is taken as a reference surface in the channel width direction of the transistor 112, the height from the reference surface to the bottom surface of the conductor 360 in a region where the conductor 360 and the oxide 330b do not overlap is preferably lower than the height from the reference surface to the bottom surface of the oxide 330b. When the conductor 360, which functions as a gate electrode, is configured to cover the side and top surfaces of the channel formation region of the oxide 330b_1 via the insulator 350 or the like, the electric field of the conductor 360 can be easily applied to the entire channel formation region of the oxide 330b_1. Thus, the on-current of the transistor 112 can be increased, and the frequency characteristics can be improved. When the bottom surface of insulator 322 is taken as a reference plane, the difference between the height from the reference plane to the bottom surface of conductor 360 in the region where oxide 330_1 and conductor 360 do not overlap, and the height from the reference plane to the bottom surface of oxide 330b_1 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0257] The insulator 380 is provided on the insulator 375, and has openings formed in regions where the insulator 350 and the conductor 360 are provided. The insulator 384 is provided on the insulator 335, and has openings formed in regions where the insulator 351 and the conductor 361 are provided. The top surfaces of the insulator 380 and the insulator 384 may be flattened.

[0258] Like the insulator 324, the insulator 380 and the insulator 384 preferably have an excess oxygen region or excess oxygen. The concentrations of impurities such as water and hydrogen in the insulator 380 and the insulator 384 are preferably reduced. For example, the insulator 380 and the insulator 384 may be made of an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate. By providing an insulator having excess oxygen near the oxide 330, oxygen vacancies in the oxide 330 can be reduced and the reliability of the transistor can be improved.

[0259] The insulator 385 is disposed in contact with the top surfaces of the conductor 361, the insulator 351, and the insulator 384. The insulator 385 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 384, and preferably has a function of capturing impurities such as hydrogen. The insulator 385 preferably functions as a barrier insulating film that suppresses oxygen transmission. For example, an insulator such as aluminum oxide may be used as the insulator 385. By providing the insulator 385 in contact with the insulator 384 in a region sandwiched between the insulator 312 and the insulator 378 and having a function of capturing impurities such as hydrogen, the impurities such as hydrogen contained in the insulator 384 can be captured, and the amount of hydrogen in the region can be kept constant.

[0260] The insulator 378 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 384. The insulator 378 is disposed on the insulator 384. As the insulator 378, it is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 378 may be a silicon nitride film formed by a sputtering method. By forming the insulator 378 by a sputtering method, a silicon nitride film that has high density and is less likely to form voids can be formed. Alternatively, as the insulator 378, a silicon nitride film formed by a CVD method may be stacked on the silicon nitride film formed by the sputtering method.

[0261] The transistor 131 and the transistor 132 can have a structure similar to that of the transistor 111 or the transistor 112. For example, when the transistor 131 has a back gate, a conductor 305 is provided in the transistor 131 (see FIG. 26B).

[0262] [Materials Constituting Semiconductor Devices] The following describes materials that can be used to construct the storage device 100.

[0263] [substrate] The substrate on which the memory device 100 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include the above-mentioned semiconductor substrate having an insulating region inside, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0264] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0265] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0266] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0267] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0268] In addition, the transistor using metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0269] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 330, oxygen vacancies in the oxide 330 can be compensated for.

[0270] [conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0271] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0272] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0273] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0274] [Metal oxides] It is preferable to use a metal oxide that functions as a semiconductor (oxide semiconductor) as the oxide 330. Hereinafter, metal oxides that can be applied to the oxide 330 according to the present invention will be described.

[0275] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to the above, one or more elements selected from the above-mentioned element M may be contained. Here, the case where the metal oxide is an In-M-Zn oxide having indium, the above-mentioned element M, and zinc is considered.

[0276] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0277] [Classification of crystal structures] First, classification of crystal structures of oxide semiconductors will be described with reference to Fig. 27A, which illustrates classification of the crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0278] As shown in FIG. 27(A), oxide semiconductors are roughly classified into "amorphous", "crystalline", and "crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystalline" includes single crystal and poly crystal.

[0279] The structure in the bold frame shown in Fig. 27(A) is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0280] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 27(B). The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 27(B) will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 27(B) is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 27(B) is 500 nm.

[0281] As shown in Figure 27(B), a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 27(B), the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0282] The crystal structure of the film or substrate can be evaluated from a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 27(C). FIG. 27(C) is a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 27(C) is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0283] As shown in FIG. 27(C), multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0284] [Structure of oxide semiconductor] Note that oxide semiconductors may be classified differently from that shown in FIG. 27A when focusing on their crystal structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0285] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0286] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0287] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0288] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0289] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0290] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0291] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0292] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0293] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0294] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0295] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0296] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0297] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0298] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0299] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0300] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0301] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0302] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0303] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0304] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0305] [Transistor Having Oxide Semiconductor] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0306] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0307] It is preferable to use an oxide semiconductor having a low carrier concentration for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 It is more preferable that the carrier concentration in the oxide semiconductor film is less than 100%. In order to reduce the carrier concentration in the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0308] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0309] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0310] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0311] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0312] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the vicinity of the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0313] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0314] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0315] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0316] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0317] [Other semiconductor materials] The semiconductor material that can be used for the oxide 330 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide 330. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material, a two-dimensional material, or the like) that functions as a semiconductor is preferably used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0318] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0319] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0320] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 330. Specific examples of transition metal chalcogenides that can be used as the oxide 330 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0321] <Method of manufacturing the storage device 100> Next, as an example of a method for manufacturing the memory device 100, a method for manufacturing the transistor 112 will be described with reference to Figures 28(A) to 34(A), Figures 28(B) to 34(B), Figures 28(C) to 34(C), and Figures 28(D) to 34(D).

[0322] Each of Fig. 28(A) to Fig. 34(A) shows a top view. Each of Fig. 28(B) to Fig. 34(B) is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in Fig. 28(A) to Fig. 34(A), and is also a cross-sectional view in the channel length direction of the transistor 112. Each of Fig. 28(C) to Fig. 34(C) is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in Fig. 28(A) to Fig. 34(A), and is also a cross-sectional view in the channel width direction of the transistor 112. Each of Fig. 28(D) to Fig. 34(D) is a cross-sectional view of a portion indicated by a dashed line A5-A6 in Fig. 28(A) to Fig. 34(A). Note that some elements are omitted in each of the top views in Fig. 28(A) to Fig. 34(A) for clarity.

[0323] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0324] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0325] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0326] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0327] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0328] In addition, the ALD method utilizes the self-regulating nature of atoms and can deposit atoms one layer at a time, which has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In the PEALD (Plasma Enhanced ALD) method, the use of plasma can enable film formation at lower temperatures, which may be preferable. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0329] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0330] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0331] First, a substrate (not shown) is prepared, and an insulator 312 is formed over the substrate (see FIGS. 28A to 28D). The insulator 312 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 312 can be reduced. However, the method for forming the insulator 312 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0332] In this embodiment, a silicon nitride film is formed as the insulator 312 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, making the film thickness distribution more uniform. In addition, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows power to be supplied to the electrodes more efficiently, improving the sputtering rate and film quality.

[0333] By using an insulator such as silicon nitride through which impurities such as water and hydrogen do not easily permeate, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 312. Furthermore, by using an insulator such as silicon nitride through which copper does not easily permeate as the insulator 312, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 312, it is possible to suppress the diffusion of the metal upward through the insulator 312.

[0334] Next, the insulator 314 is formed over the insulator 312. The insulator 314 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 314 can be reduced. However, the method for forming the insulator 314 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.

[0335] In this embodiment, an aluminum oxide film is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas as the insulator 314. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0336] By using aluminum oxide, which has high hydrogen capturing and fixing ability, as the insulator 314, hydrogen contained in the insulator 316 formed on the insulator 314 can be captured or fixed, and the hydrogen can be prevented from diffusing into the oxide 330.

[0337] Next, the insulator 316 is formed over the insulator 314. The insulator 316 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 316 can be reduced. However, the method for forming the insulator 316 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0338] In this embodiment, a silicon oxide film is formed by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen gas as the insulator 316. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0339] It is preferable that the insulators 312, 314, and 316 are successively formed without exposure to air. For example, a multi-chamber film formation apparatus can be used. This can reduce hydrogen in the insulators 312, 314, and 316 and can also reduce hydrogen from entering the films between film formation steps.

[0340] Next, an opening is formed in the insulator 316, extending in the A3-A4 direction to reach the insulator 314. The opening may be appropriately provided in accordance with the arrangement of the transistors 112. The opening may be, for example, a groove or a slit. The opening may refer to a region in which an opening is formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 314, it is preferable to select an insulator that functions as an etching stopper film when the insulator 316 is etched to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 316 that forms the groove, the insulator 314 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0341] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0342] After the opening is formed, a conductive film that becomes the conductor 305a is formed. The conductive film that becomes the conductor 305a preferably contains a conductor that has a function of suppressing oxygen transmission. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, it can be a stacked film of a conductor that has a function of suppressing oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 305a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0343] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 305a. By using such a metal nitride as the lower layer of the conductor 305b described later, it is possible to prevent the conductor 305b from being oxidized by the insulator 316 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 305b, it is possible to prevent the metal from diffusing out of the conductor 305a.

[0344] Next, a conductive film to be the conductor 305b is formed. As the conductive film to be the conductor 305b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film to be the conductor 305b.

[0345] Next, a CMP process is performed to remove a portion of the conductive film that becomes the conductor 305a and a portion of the conductive film that becomes the conductor 305b, thereby exposing the insulator 316. As a result, the conductor 305a and the conductor 305b remain only in the openings. Note that the CMP process may remove a portion of the insulator 316.

[0346] Next, the upper portion of the conductor 305b is removed by etching, so that the upper surface of the conductor 305b is lower than the upper surfaces of the conductor 305a and the insulator 316. The conductor 305b can be etched by dry etching or wet etching, but dry etching is preferable for fine processing.

[0347] Next, a conductive film to be the conductor 305c is formed over the insulator 316, the conductor 305a, and the conductor 305b. The conductive film to be the conductor 305c preferably contains a conductor having a function of suppressing oxygen permeation, similar to the conductive film to be the conductor 305a.

[0348] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 305c. By using such a metal nitride as the upper layer of the conductor 305b, it is possible to prevent the conductor 305b from being oxidized by the insulator 322 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 305b, it is possible to prevent the metal from diffusing out of the conductor 305c.

[0349] Next, a part of the conductive film that will become the conductor 305c is removed by performing CMP processing, and the insulator 316 is exposed. As a result, the conductor 305a, the conductor 305b, and the conductor 305c remain only in the opening. This allows the conductor 305 with a flat upper surface to be formed. Furthermore, the conductor 305b is configured to be surrounded by the conductor 305a and the conductor 305c. This prevents impurities such as hydrogen from the conductor 305b from diffusing out of the conductor 305a and the conductor 305c, and prevents oxygen from entering from outside the conductor 305a and the conductor 305c and oxidizing the conductor 305b. Note that the CMP processing may remove a part of the insulator 316.

[0350] Next, the insulator 322 is formed over the insulator 316 and the conductor 305. As the insulator 322, an insulator containing one or both of an oxide of aluminum and hafnium may be formed. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. An insulator containing one or both of an oxide of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 322 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 112 are prevented from diffusing into the inside of the transistor 112 through the insulator 322, and the generation of oxygen vacancies in the oxide 330 can be suppressed.

[0351] The insulator 322 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide is formed by a sputtering method as the insulator 322. By using a sputtering method in which hydrogen is not required as a deposition gas, the hydrogen concentration in the insulator 322 can be reduced.

[0352] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0353] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulator 322 as much as possible.

[0354] In this embodiment, after the insulator 322 is formed, heat treatment is performed at a flow rate ratio of nitrogen gas and oxygen gas of 4 slm:1 slm at a temperature of 400° C. for one hour. The heat treatment can remove impurities such as water and hydrogen contained in the insulator 322. When an oxide containing hafnium is used as the insulator 322, the heat treatment can improve the crystallinity of the insulator 322. The heat treatment can also be performed at a timing such as after the insulator 324 is formed.

[0355] Next, the insulator 324 is formed over the insulator 322. The insulator 324 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 324 by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 324 can be reduced. Because the insulator 324 comes into contact with the oxide 330a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0356] Here, in order to form an excess oxygen region in the insulator 324, a plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high density plasma using, for example, microwaves. Alternatively, the apparatus may have a power source that applies RF (Radio Frequency) to the substrate side. By using high density plasma, high density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high density plasma can be efficiently guided into the insulator 324. Alternatively, after performing a plasma treatment including an inert gas using this apparatus, a plasma treatment including oxygen may be performed to compensate for the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 324 can be removed by appropriately selecting the conditions of the plasma treatment. In that case, heat treatment does not need to be performed.

[0357] Here, after forming an aluminum oxide film on the insulator 324 by, for example, a sputtering method, the aluminum oxide may be removed by a CMP process until the insulator 324 is reached. The CMP process can planarize and smooth the surface of the insulator 324. By disposing the aluminum oxide on the insulator 324 and performing the CMP process, it becomes easy to detect the end point of the CMP process. In addition, the CMP process may polish a part of the insulator 324, and the thickness of the insulator 324 may become thin, but the thickness may be adjusted when the insulator 324 is formed. By planarizing and smoothing the surface of the insulator 324, it may be possible to prevent a deterioration in the coverage of the oxide to be formed later and to prevent a decrease in the yield of the semiconductor device. In addition, it is preferable to form an aluminum oxide film on the insulator 324 by a sputtering method, since oxygen can be added to the insulator 324.

[0358] Next, oxide film 330A and oxide film 330B are sequentially formed on insulator 324. Note that oxide film 330A and oxide film 330B are preferably formed successively without exposure to the air environment. By forming the films without exposure to the air, it is possible to prevent impurities or moisture from the air environment from adhering to oxide film 330A and oxide film 330B, and it is possible to keep the vicinity of the interface between oxide film 330A and oxide film 330B clean.

[0359] The oxide film 330A and the oxide film 330B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0360] For example, when the oxide film 330A and the oxide film 330B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. When the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0361] In particular, during the formation of the oxide film 330A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 324. Therefore, the ratio of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0362] When the oxide film 330B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably from 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 330B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than or equal to 1% and less than or equal to 30%, preferably from 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. When the oxide film is formed while the substrate is heated, the crystallinity of the oxide film can be improved.

[0363] In this embodiment, the oxide film 330A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide film 330B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film may be formed according to the desired characteristics of the oxide 330a and oxide 330b obtained by processing in a later step by appropriately selecting the film formation conditions and atomic ratio.

[0364] Next, the oxide film 343A is formed on the oxide film 330B. The oxide film 343A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 343A is preferably greater than the atomic ratio of Ga to In in the oxide film 330B. In this embodiment, the oxide film 343A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0365] It is preferable to form the insulator 322, the insulator 324, the oxide film 330A, the oxide film 330B, and the oxide film 343A by a sputtering method without exposing them to the atmosphere. For example, a multi-chamber film forming apparatus may be used. This allows the insulator 322, the insulator 324, the oxide film 330A, the oxide film 330B, and the oxide film 343A to be formed with reduced hydrogen in the films, and further reduces the inclusion of hydrogen in the films between each film forming process.

[0366] Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range in which the oxide film 330A, the oxide film 330B, and the oxide film 343A are not polycrystallized, and may be performed at 250° C. to 650° C., preferably 400° C. to 600° C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere.

[0367] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the oxide film 330A, the oxide film 330B, and the oxide film 343A as much as possible.

[0368] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550° C. for 1 hour, followed by another heat treatment in an oxygen atmosphere at 550° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 330A, the oxide film 330B, and the oxide film 343A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 330B, resulting in a denser and more compact structure. This can reduce the diffusion of oxygen or impurities in the oxide film 330B.

[0369] Next, the conductive film 342A is formed on the oxide film 343A. The conductive film 342A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, tantalum nitride may be formed as the conductive film 342A by a sputtering method. Note that a heat treatment may be performed before the conductive film 342A is formed. The heat treatment may be performed under reduced pressure, and the conductive film 342A may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 343A and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide film 330A, the oxide film 330B, and the oxide film 343A can be further reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is set to 200° C.

[0370] Next, for example, the oxide film 330A, the oxide film 330B, the oxide film 343A, and the conductive film 342A are processed into an island shape extending in the A1-A2 direction by using a lithography method to form the oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B (see FIG. 29(A) to FIG. 29(D)). The oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B may be appropriately provided according to the arrangement of the transistors 112. This processing may be performed by a dry etching method or a wet etching method. Processing by the dry etching method is suitable for microfabrication. The oxide film 330A, the oxide film 330B, the oxide film 343A, and the conductive film 342A may be processed under different conditions. Note that in this process, the thickness of the region of the insulator 324 that does not overlap with the oxide 330a may be thin. In this step, the insulator 324 may be processed into an island shape by overlapping with the oxide 330a.

[0371] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a desired area of ​​the resist can be selected and irradiated with the beam, so that a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after the dry etching process, or a dry etching process after the wet etching process.

[0372] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film that will be a hard mask material is formed on the conductive film 342A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 342A and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching of the conductive film 342A and the like, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect a later process or can be used in a later process, it is not necessarily necessary to remove the hard mask. For example, when the hard mask is formed of an insulating film, the hard mask may be left and used as a barrier insulating film.

[0373] The oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B are formed so as to at least partially overlap with the conductor 305. The side surfaces of the oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B are preferably approximately perpendicular to the top surface of the insulator 322. When the side surfaces of the oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B are approximately perpendicular to the top surface of the insulator 322, a reduction in area and a high density can be achieved when providing a plurality of transistors 112. Alternatively, the angles formed by the side surfaces of the oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B and the top surface of the insulator 322 may be low. In this case, the angles formed by the side surfaces of the oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B and the upper surface of the insulator 322 are preferably 60 degrees or more and less than 70 degrees. By forming the insulator 322 in such a shape, the coverage of the insulator 375 and the like can be improved in the subsequent steps, and defects such as voids can be reduced.

[0374] In addition, by-products generated in the above etching process may be formed in layers on the side surfaces of the oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B. In this case, the layered by-products remain between the oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B and the insulator 375 to be formed later. Similarly, layered by-products may remain on the insulator 324. Even if the insulator 375 is formed in a state in which the layered by-products remain on the insulator 324, the layered by-products will prevent oxygen from being added to the insulator 324. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 324.

[0375] Next, the insulator 375 is formed over the insulator 324, the oxide 330a, the oxide 330b, the oxide layer 343B, and the conductive layer 342B. (See Figures 30(A) to 30(D)). The insulator 375 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 375 is preferably an insulating film having a function of suppressing oxygen permeation. For example, aluminum oxide may be formed by a sputtering method as the insulator 375. By forming the insulator 375 by a sputtering method, oxygen can be added to the insulator 324.

[0376] Next, an insulating film to be the insulator 380 is formed on the insulator 375. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be formed by a sputtering method as the insulating film. The insulating film to be the insulator 380 can be formed by a sputtering method in an atmosphere containing oxygen, thereby forming the insulator 380 containing excess oxygen. In addition, the hydrogen concentration in the insulator 380 can be reduced by using a sputtering method that does not require hydrogen as a deposition gas. Note that a heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 375 and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 330a, the oxide 330b, the oxide layer 343B, and the insulator 324 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0377] Next, the insulating film that becomes the insulator 380 is subjected to CMP processing to form the insulator 380 with a flat upper surface. Note that a silicon nitride film may be formed on the insulator 380 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP processing until it reaches the insulator 380.

[0378] Next, a part of the insulator 380, a part of the insulator 375, a part of the conductive layer 342B, a part of the oxide layer 343B, the oxide 330a, the oxide 330b, and a part of the insulator 324 are processed to form an opening that reaches the oxide 330b (see Figures 31(A) to 31(D)). The opening is preferably formed so as to overlap with the conductor 305. By forming the opening, the conductor 342a, the conductor 342b, the oxide 343a, and the oxide 343b are formed. In other words, the multiple conductors 342 and the multiple oxides 343 are divided by the opening and arranged in a straight line. Here, the top surface of the oxide 330b is exposed from the opening.

[0379] When the opening is formed, the upper part of the oxide 330b is removed. By removing a part of the oxide 330b, a groove is formed in the oxide 330b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0380] Furthermore, a part of the insulator 380, a part of the insulator 375, a part of the conductive layer 342B, a part of the oxide layer 343B, and a part of the oxide 330b can be processed by dry etching or wet etching. Processing by the dry etching method is suitable for fine processing. Moreover, the processing may be performed under different conditions. For example, a part of the insulator 380 may be processed by dry etching, a part of the insulator 375 may be processed by wet etching, and a part of the oxide layer 343B, a part of the conductive layer 342B, and a part of the oxide 330b may be processed by dry etching. Moreover, processing of a part of the oxide layer 343B and a part of the conductive layer 342B and processing of a part of the oxide 330b may be performed under different conditions.

[0381] Here, it is preferable to remove impurities attached to the surfaces of the oxide 330a, the oxide 330b, etc. or diffused therein. It is also preferable to remove damaged areas formed on the surface of the oxide 330b by the dry etching. The impurities include those originating from components contained in the insulator 380, the insulator 375, and the conductive layer 342B, components contained in the members used in the device used to form the opening, and components contained in the gas or liquid used in the etching. The impurities include, for example, aluminum, silicon, tantalum, fluorine, and chlorine.

[0382] In particular, impurities such as aluminum or silicon inhibit the oxide 330b from becoming a CAAC-OS. Therefore, it is preferable to reduce or remove impurity elements such as aluminum or silicon that inhibit the CAAC-OS. For example, the concentration of aluminum atoms in the oxide 330b and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0383] In addition, the region of the metal oxide in which the CAAC-OS formation is inhibited by impurities such as aluminum or silicon and which becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so the V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC region of the oxide 330b is reduced or removed.

[0384] In contrast, it is preferable that the oxide 330b has a layered CAAC structure. In particular, it is preferable that the oxide 330b has the CAAC structure up to the lower end of the drain. Here, in the transistor 112, the conductor 342a or the conductor 342b and its vicinity function as the drain. In other words, it is preferable that the oxide 330b near the lower end of the conductor 342a (conductor 342b) has the CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 330b is removed, and by having the CAAC structure, the fluctuation in the electrical characteristics of the transistor 112 can be further suppressed. In addition, the reliability of the transistor 112 can be improved.

[0385] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning methods may be combined appropriately. Note that the above-mentioned grooves may become deeper due to the cleaning process.

[0386] For wet cleaning, a cleaning process may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0387] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be called diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution may be appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0388] In addition, it is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning. By using such a frequency, damage to the oxide 330b and the like can be reduced.

[0389] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0390] In the present embodiment, as the cleaning process, wet cleaning is performed using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of the oxides 330a and 330b or diffused inside can be removed. Furthermore, the crystallinity of the oxide 330b can be improved.

[0391] In the past, processing such as dry etching or the above-mentioned cleaning process may result in the thickness of insulator 324 in the area that overlaps with the opening but does not overlap with oxide 330b being thinner than the thickness of insulator 324 in the area that overlaps with oxide 330b.

[0392] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 330a and the oxide 330b, thereby reducing the oxygen vacancy V. O In addition, by performing such heat treatment, the crystallinity of the oxide 330b can be improved. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0393] Next, the insulating film 350A is formed (see FIGS. 32A to 32D). Heat treatment may be performed before the formation of the insulating film 350A, or the heat treatment may be performed under reduced pressure, and the insulating film 350A may be formed continuously without exposure to air. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 330b can be removed, and the moisture and hydrogen concentrations in the oxide 330a and the oxide 330b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0394] The insulating film 350A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 350A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration in the insulating film 350A to be reduced. Since the insulating film 350A becomes the insulator 350 that contacts the oxide 330b in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0395] In addition, it is preferable to form the insulating film 350A by using the ALD method. The thickness of the insulator 350 functioning as the gate insulating film of the miniaturized transistor 112 must be extremely thin (for example, about 5 nm to 30 nm) and have small variations. In contrast, the ALD method is a film formation method in which a precursor and a reactant (oxidizer) are alternately introduced, and the thickness can be adjusted by the number of times this cycle is repeated, so that precise thickness adjustment is possible. Therefore, the precision of the gate insulating film required by the miniaturized transistor 112 can be achieved. In addition, the insulating film 350A must be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 380, etc. Since layers of atoms can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 350A can be formed with good coverage on the opening.

[0396] In addition, for example, when the insulating film 350A is formed by using the PECVD method, the film forming gas containing hydrogen is decomposed in the plasma, and a large amount of hydrogen radicals is generated. The oxygen in the oxide 330b is extracted by the reduction reaction of the hydrogen radicals, and V O When H is formed, the hydrogen concentration in the oxide 330b increases. However, when the insulating film 350A is formed using the ALD method, the generation of hydrogen radicals can be suppressed both when the precursor and the reactant are introduced. Therefore, by forming the insulating film 350A using the ALD method, the hydrogen concentration in the oxide 330b can be prevented from increasing. For example, a silicon oxide film may be formed as the insulating film 350A using the ALD method.

[0397] Next, microwave processing is performed in an atmosphere containing oxygen. Here, the wavy dashed arrows shown in Fig. 32(B), Fig. 32(C), and Fig. 32(D) indicate microwaves, high frequency such as RF, oxygen plasma, or oxygen radicals. For the microwave processing, it is preferable to use a microwave processing apparatus having a power source that generates high density plasma using microwaves. The microwave processing apparatus may also have a power source that applies RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated. By applying RF to the substrate side, oxygen ions generated by high density plasma can be efficiently introduced into the oxide 330b. The microwave processing is preferably performed under reduced pressure, with the pressure being 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. The oxygen flow rate ratio (O2 / O2+Ar) is preferably 50% or less, preferably 10% or more and 30% or less. The processing temperature may be 750°C or less, preferably 500°C or less, for example, about 400°C. Furthermore, after the microwave treatment, a heat treatment may be carried out successively without exposure to the outside air.

[0398] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between conductors 342a and 342b of oxide 330b. At this time, microwaves or high frequency waves such as RF can also be irradiated to region 333c. In other words, microwaves, high frequency waves such as RF, oxygen plasma, etc. can be applied to region 333c shown in FIG. 25. The action of plasma, microwaves, etc. increases the V O H can be split off and hydrogen H can be removed from the region 333c. O H→H+V O " occurs, and the hydrogen concentration in the region 333c can be reduced. Therefore, the oxygen vacancies in the region 333c and the V OBy supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 350 to the oxygen vacancies formed in the region 333c, the oxygen vacancies in the region 333c can be further reduced, and the carrier concentration can be reduced.

[0399] On the other hand, conductors 342a and 342b are provided on region 333sd shown in Fig. 25. As shown in Fig. 32(B), Fig. 32(C), and Fig. 32(D), conductors 342a and 342b block the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like, so that these effects do not reach region 333sd. As a result, V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0400] In this manner, oxygen vacancies and V O By removing H, the region 333c can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region 333sd functioning as a source region or a drain region can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 112, and suppresses variations in the electrical characteristics of the transistor 112 within the substrate surface.

[0401] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0402] Moreover, a heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment. By performing such a treatment, hydrogen in the insulating film 350A, the oxide 330b, and the oxide 330a can be efficiently removed. A part of the hydrogen may be gettered to the conductor 342 (the conductor 342a and the conductor 342b). Alternatively, a step of performing a heat treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film 350A, the oxide 330b, and the oxide 330a can be more efficiently removed. Note that the heat treatment temperature is preferably 300° C. or more and 500° C. or less.

[0403] Furthermore, by modifying the film quality of the insulating film 350A through microwave processing, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. through the insulator 350 into the oxide 330b, the oxide 330a, etc., by a post-process such as film formation of the conductive film that becomes the conductor 360, or a post-treatment such as heat treatment.

[0404] In this embodiment, the microwave treatment is performed after the insulating film 350A is formed, but the present invention is not limited to this. For example, the microwave treatment may be performed before the insulating film 350A is formed, or before or after the barrier insulating film is formed. In addition, these microwave treatments may be performed not only once but also multiple times. In addition, when the insulating film 350A and the barrier insulating film are formed by the PEALD method, the microwave treatment may be replaced by a treatment with a plasma-excited reactant (oxidant) in a PEALD apparatus. Here, oxygen gas may be used as the reactant (oxidant).

[0405] Next, a conductive film 360A to become the conductor 360a and a conductive film 360B to become the conductor 360b are formed in this order (see FIGS. 33(A) to 33(D)). The conductive films 360A and 360B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive films 360A and 360B are formed by a CVD method.

[0406] Next, the insulating film 350A, the conductive film 360A, and the conductive film 360B are polished by CMP until the insulator 380 is exposed. This polishing process forms the insulator 350, the conductor 360a, and the conductor 360b (see FIGS. 34(A) to 34(D)). As a result, the insulator 350 is formed so as to cover the opening that reaches the oxide 330b and the inner walls (side walls and bottom surface) of the groove of the oxide 330b. The conductor 360 is formed so as to fill the opening and the groove through the insulator 350.

[0407] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 350 and 380. Note that after the heat treatment, the insulator 385 may be formed without exposure to air.

[0408] In this manner, the transistor 112 can be manufactured. Figure 34B shows cross sections of three transistors 112. After that, the transistor 111 is provided over the transistor 112. The transistor 111 can be manufactured through approximately the same process as the transistor 112. In this manner, the memory device 100 can be manufactured.

[0409] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0410] (Embodiment 5) In this embodiment, an example of a chip 1200, which is a type of semiconductor device on which a memory device of the present invention is mounted, is shown with reference to Figures 35(A) and 35(B). A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0411] As shown in FIG. 35(A), a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0412] Chip 1200 is provided with bumps (not shown) and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in Fig. 35(B). In addition, a plurality of bumps 1202 are provided on the back side of the first surface of PCB 1201 and are connected to a motherboard 1203.

[0413] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. The semiconductor device described in the above embodiment is preferably used as the flash memory 1222. By using the semiconductor device described in the above embodiment for the flash memory 1222, the storage capacity of the flash memory 1222 can be increased.

[0414] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and multiplication and accumulation. By providing the GPU 1212 with an image processing circuit and a multiplication and accumulation circuit, it becomes possible to execute image processing and multiplication and accumulation with low power consumption.

[0415] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0416] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0417] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0418] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0419] The network circuit 1216 includes a network circuit for connecting to a LAN (Local Area Network), etc. It may also include a circuit for network security.

[0420] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0421] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be referred to as a GPU module 1204.

[0422] The GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0423] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes.

[0424] (Embodiment 6) In this embodiment, an application example of a semiconductor device using the storage device described in the previous embodiment will be described. The storage device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 36(A) to 36(E) are schematic diagrams showing some configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0425] 36A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The memory chip 1105 or the like can be incorporated with the storage device or the semiconductor device described in the above embodiment.

[0426] FIG. 36B is a schematic diagram of the appearance of an SD card, and FIG. 36C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 on the back side of the substrate 1113 as well, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This makes it possible to read and write data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The memory chip 1114 or the like can be incorporated with the memory device or the semiconductor device described in the above embodiment.

[0427] FIG. 36(D) is a schematic diagram of the appearance of the SSD, and FIG. 36(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. The capacity of the SSD 1150 can be increased by providing a memory chip 1154 on the back side of the board 1153. The memory chip 1154 or the like can be incorporated with the storage device or semiconductor device shown in the above embodiment.

[0428] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

[0429] (Embodiment 7) 37A to 37G illustrate specific examples of electronic devices equipped with a memory device or a semiconductor device according to one embodiment of the present invention.

[0430] <Electronic equipment and systems> The memory device or semiconductor device according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic devices include information terminals, computers, smartphones, e-book terminals, television devices, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, and audio playback devices. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0431] The electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0432] An electronic device according to one embodiment of the present invention may have a sensor (including a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0433] The electronic device of one embodiment of the present invention can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded in a recording medium, etc.

[0434] [Information terminal] A memory device for storing programs of a microcontroller can be formed using a memory device or a semiconductor device according to one embodiment of the present invention, and therefore, according to one embodiment of the present invention, a microcontroller chip can be made smaller.

[0435] 37A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display portion 5102. As input interfaces, a touch panel is provided on the display portion 5102 and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one embodiment of the present invention, a limited space inside the mobile phone can be effectively used. In addition, a storage device according to one embodiment of the present invention may be used for storage of the mobile phone. This allows the storage capacity per unit area of ​​the storage to be increased.

[0436] 37B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space inside the notebook information terminal can be effectively utilized. In addition, a storage device according to one embodiment of the present invention may be used for the storage of the notebook information terminal. This allows the storage capacity per unit area of ​​the storage to be increased.

[0437] In the above description, a smartphone and a notebook type information terminal are shown as examples of electronic devices in Fig. 37(A) and Fig. 37(B), respectively, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0438] [Game consoles] FIG. 37C illustrates a portable game machine 5300, which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection portion 5305 of the housing 5301 to another housing (not shown), a video output to the display portion 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation portion. This allows a plurality of players to play a game at the same time. A memory device or a semiconductor device according to one embodiment of the present invention can be incorporated into chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

[0439] 37(D) shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

[0440] A miniaturized microcontroller according to one embodiment of the present invention can be used effectively in a game machine such as a portable game machine 5300 or a stationary game machine 5400. A storage device or a semiconductor device according to one embodiment of the present invention can be used for storage of the portable game machine. This can increase the storage capacity per unit area of ​​the storage.

[0441] 37(C) and 37(D) show a portable game machine and a stationary game machine as examples of game machines, but game machines to which the microcontroller of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the microcontroller of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0442] [Mainframe computers] A memory device or a semiconductor device according to one embodiment of the present invention can be applied to a large-scale computer.

[0443] 37(E) is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 37(F) is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0444] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and a microcontroller according to one embodiment of the present invention can be mounted on the board. By using the miniaturized microcontroller according to one embodiment of the present invention, the limited space of a large computer can be effectively utilized. In addition, a storage device or a semiconductor device according to one embodiment of the present invention may be used for the storage of the large computer. This allows the storage capacity per unit area of ​​the storage to be increased.

[0445] 37(E) and 37(F) show a supercomputer as an example of a large computer, but the large computer to which the microcontroller according to an embodiment of the present invention is applied is not limited to this. Examples of large computers to which the microcontroller according to an embodiment of the present invention is applied include computers that provide services (servers) and large general-purpose computers (mainframes).

[0446] [electric appliances] 37G illustrates an electric refrigerator-freezer 5800, which is an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a door for a refrigerator compartment 5802, a door for a freezer compartment 5803, and the like.

[0447] A memory device or a semiconductor device according to one embodiment of the present invention can also be applied to an electric refrigerator-freezer 5800. For example, by applying a miniaturized microcontroller according to one embodiment of the present invention to the electric refrigerator-freezer 5800, the limited space of the electric refrigerator-freezer can be effectively utilized.

[0448] Although an electric refrigerator-freezer has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0449] The electronic devices, functions, effects, and the like described in this embodiment mode can be appropriately combined with descriptions of other electronic devices.

[0450] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes. [Explanation of symbols]

[0451] 100 storage device 110 Memory element 111 Transistor 112 Transistor 113 nodes 121 Terminal 122 Terminal 123 Terminal 125 capacity 131 Transistor 132 Transistor 133 Terminal 134 Terminals 200 Semiconductor device 210 Drive circuit 211 Peripheral circuits 212 Control Circuit 215 Peripheral Circuits 220 Memory Array 221 Line Decoder 222 Column Decoder 223 line driver 224 Column Driver 225 Input Circuit 226 Output circuit 227 Sense Amplifier 228 Voltage Generation Circuit 241 PSW 242 PSW

Claims

1. a first memory cell, a second memory cell, a first wiring, a second wiring, a third wiring, a first transistor, and a second transistor; each of the first memory cell and the second memory cell includes a third transistor and a fourth transistor; a source of the third transistor included in the first memory cell is electrically connected to the third wiring; a drain of the third transistor included in the first memory cell is electrically connected to a source of the third transistor included in the second memory cell; a gate of the third transistor included in the first memory cell is electrically connected to the first wiring; a gate of the third transistor included in the second memory cell is electrically connected to the second wiring; a source of the fourth transistor included in the first memory cell is electrically connected to the first transistor; a drain of the fourth transistor included in the first memory cell is electrically connected to a source of the fourth transistor included in the second memory cell; a gate of the fourth transistor included in the first memory cell is electrically connected to a drain of the third transistor included in the first memory cell; a gate of the fourth transistor included in the second memory cell is electrically connected to a drain of the third transistor included in the second memory cell; a drain of the fourth transistor included in the second memory cell is electrically connected to the second transistor; the fourth transistor included in the first memory cell and the fourth transistor included in the second memory cell each have a back gate; each of the first memory cell and the second memory cell has a function of holding a charge written via a source and a drain of the third transistor between a gate of the fourth transistor and a drain of the third transistor; a first oxide semiconductor having a region functioning as a channel formation region of the first transistor, a region functioning as a channel formation region of the fourth transistor included in the first memory cell, and a region functioning as a channel formation region of the fourth transistor included in the second memory cell; a first conductor having a region located above the first oxide semiconductor and functioning as a gate electrode of the fourth transistor included in the first memory cell; a second conductor having a region located above the first oxide semiconductor and functioning as a gate electrode of the fourth transistor included in the second memory cell; a second oxide semiconductor having a region in contact with an upper surface of the first conductor and a region in contact with an upper surface of the second conductor and functioning as a channel formation region of the third transistor included in the first memory cell, and a region functioning as a channel formation region of the third transistor included in the second memory cell; a third conductor having a region located above the second oxide semiconductor and functioning as a source electrode of the third transistor included in the first memory cell; an insulator having a region located above the third conductor; The lower surface of the insulator has a region in contact with a fourth conductor having a region that functions as a gate electrode of the first transistor.

2. The memory cell includes n memory cells (n is an integer of 3 or more), n word lines, a bit line, a first transistor, and a second transistor; Each of the n memory cells includes a third transistor and a fourth transistor; a source of the third transistor included in a first memory cell is electrically connected to the bit line; a drain of the third transistor included in the first memory cell is electrically connected to a source of the third transistor included in a second memory cell; a gate of the third transistor included in the first memory cell is electrically connected to a first word line; a source of the fourth transistor included in the first memory cell is electrically connected to the first transistor; a drain of the fourth transistor included in the first memory cell is electrically connected to a source of the fourth transistor included in the second memory cell; a gate of the fourth transistor included in the first memory cell is electrically connected to a drain of the third transistor included in the first memory cell; a source of the third transistor included in an i-th memory cell (i is an integer equal to or greater than 2 and less than n) is electrically connected to a drain of the third transistor included in an (i-1)-th memory cell; a drain of the third transistor included in the i-th memory cell is electrically connected to a source of the third transistor included in the (i+1)-th memory cell; a gate of the third transistor included in the i-th memory cell is electrically connected to an i-th word line; a source of the fourth transistor included in the i-th memory cell is electrically connected to a drain of the fourth transistor included in the (i-1)-th memory cell; a drain of the fourth transistor included in the i-th memory cell is electrically connected to a source of the fourth transistor included in the (i+1)-th memory cell; a gate of the fourth transistor included in the i-th memory cell is electrically connected to a drain of the third transistor included in the i-th memory cell; a source of the third transistor included in the n-th memory cell is electrically connected to a drain of the third transistor included in the (n-1)-th memory cell; a gate of the third transistor included in the n-th memory cell is electrically connected to an n-th word line; a source of the fourth transistor included in the n-th memory cell is electrically connected to a drain of the fourth transistor included in the (n-1)-th memory cell; a drain of the fourth transistor included in the n-th memory cell is electrically connected to the second transistor; a gate of the fourth transistor included in the n-th memory cell is electrically connected to a drain of the third transistor included in the n-th memory cell; Each of the fourth transistors included in the n memory cells has a back gate, each of the n memory cells has a function of holding a charge written via a source and a drain of the third transistor between a gate of the fourth transistor and a drain of the third transistor; a first oxide semiconductor having a region functioning as a channel formation region of the first transistor, a region functioning as a channel formation region of the fourth transistor included in the first memory cell, and a region functioning as a channel formation region of the fourth transistor included in the second memory cell; a first conductor having a region located above the first oxide semiconductor and functioning as a gate electrode of the fourth transistor included in the first memory cell; a second conductor having a region located above the first oxide semiconductor and functioning as a gate electrode of the fourth transistor included in the second memory cell; a second oxide semiconductor having a region in contact with an upper surface of the first conductor and a region in contact with an upper surface of the second conductor and functioning as a channel formation region of the third transistor included in the first memory cell, and a region functioning as a channel formation region of the third transistor included in the second memory cell; a third conductor having a region located above the second oxide semiconductor and functioning as a source electrode of the third transistor included in the first memory cell; an insulator having a region located above the third conductor; The lower surface of the insulator has a region in contact with a fourth conductor having a region that functions as a gate electrode of the first transistor.

3. The memory cell includes n memory cells (n is an integer of 3 or more), n word lines, a first wiring, a first bit line, a second bit line, a first transistor, a second transistor, and a fifth transistor; Each of the n memory cells includes a third transistor and a fourth transistor; a source of the third transistor included in a first memory cell is electrically connected to the first bit line; a drain of the third transistor included in the first memory cell is electrically connected to a source of the third transistor included in a second memory cell; a gate of the third transistor included in the first memory cell is electrically connected to a first word line; a source of the fourth transistor included in the first memory cell is electrically connected to the first transistor; a drain of the fourth transistor included in the first memory cell is electrically connected to a source of the fourth transistor included in the second memory cell; a gate of the fourth transistor included in the first memory cell is electrically connected to a drain of the third transistor included in the first memory cell; a source of the third transistor included in an i-th (i is an integer equal to or greater than 2 and less than n) memory cell is electrically connected to a drain of the third transistor included in an (i-1)-th memory cell; a drain of the third transistor included in the i-th memory cell is electrically connected to a source of the third transistor included in the (i+1)-th memory cell; a gate of the third transistor included in the i-th memory cell is electrically connected to an i-th word line; a source of the fourth transistor included in the i-th memory cell is electrically connected to a drain of the fourth transistor included in the (i-1)-th memory cell; a drain of the fourth transistor included in the i-th memory cell is electrically connected to a source of the fourth transistor included in the (i+1)-th memory cell; a gate of the fourth transistor included in the i-th memory cell is electrically connected to a drain of the third transistor included in the i-th memory cell; a source of the third transistor included in the n-th memory cell is electrically connected to a drain of the third transistor included in the (n-1)-th memory cell; a gate of the third transistor included in the n-th memory cell is electrically connected to an n-th word line; a source of the fourth transistor included in the n-th memory cell is electrically connected to a drain of the fourth transistor included in the (n-1)-th memory cell; a drain of the fourth transistor included in the n-th memory cell is electrically connected to the second transistor; a gate of the fourth transistor included in the n-th memory cell is electrically connected to a drain of the third transistor included in the n-th memory cell; a drain of the third transistor included in the n-th memory cell is electrically connected to a source of the fifth transistor; a drain of the fifth transistor electrically connected to the second bit line; a gate of the fifth transistor is electrically connected to the first wiring; Each of the fourth transistors included in the n memory cells has a back gate, each of the n memory cells has a function of holding a charge written via a source and a drain of the third transistor between a gate of the fourth transistor and a drain of the third transistor; a first oxide semiconductor having a region functioning as a channel formation region of the first transistor, a region functioning as a channel formation region of the fourth transistor included in the first memory cell, and a region functioning as a channel formation region of the fourth transistor included in the second memory cell; a first conductor having a region located above the first oxide semiconductor and functioning as a gate electrode of the fourth transistor included in the first memory cell; a second conductor having a region located above the first oxide semiconductor and functioning as a gate electrode of the fourth transistor included in the second memory cell; a second oxide semiconductor having a region in contact with an upper surface of the first conductor and a region in contact with an upper surface of the second conductor and functioning as a channel formation region of the third transistor included in the first memory cell, and a region functioning as a channel formation region of the third transistor included in the second memory cell; a third conductor having a region located above the second oxide semiconductor and functioning as a source electrode of the third transistor included in the first memory cell; an insulator having a region located above the third conductor; The lower surface of the insulator has a region in contact with a fourth conductor having a region that functions as a gate electrode of the first transistor.

4. In claim 2 or 3, The third transistor of the memory cell has a capacitance at its drain.

5. In any one of claims 1 to 4, the first oxide semiconductor contains at least one of indium and zinc; The second oxide semiconductor includes at least one of indium and zinc.

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