Substrate and display panel

Abstract

In the substrate and display panel according to the embodiments of the present application, the thin film transistor includes a gate, an active layer, and a source / drain metal layer. The active layer is stacked with the gate so as to be a different layer from the gate. A blocking layer covers at least the active layer and the gate and blocks water and oxygen. A planarization layer covers the blocking layer, and the source / drain metal layer is disposed on the planarization layer. The source / drain metal layer includes a source and a drain connected to the active layer, respectively.

Description

[Technical field]

[0001] The present application relates to the technical field of displays, and in particular to substrates and display panels. [Background technology]

[0002] Compared with traditional liquid crystal panels, active matrix organic light emitting diode panels have the characteristics of faster response speed, higher contrast, wider viewing angle, and lower energy consumption, and are therefore widely popular. They are gradually replacing liquid crystal display panels as the next-generation mainstream display panel.

[0003] In the course of studying and practicing the conventional technologies, the inventors of the present application discovered that in both liquid crystal panels and organic light emitting diode panels, the active layers are susceptible to factors such as hydrogen, water, and oxygen that enter from the outside, which causes electrical offset in the thin film transistors and ultimately reduces the reliability of the panel. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present application provide a substrate and a display panel for reducing the risk of hydrogen, water and oxygen ingress into the active layer. [Means for solving the problem]

[0005] The substrate according to the embodiment of the present application is With the base, a plurality of thin film transistors disposed on the base; The thin film transistor is A gate provided on the base; an active layer provided on the base and stacked with the gate so as to be a different layer from the gate; a barrier layer that covers at least the active layer and the gate and blocks water and oxygen; a planarizing layer covering the barrier layer; a source / drain metal layer disposed on the planar layer to include a source and a drain each connected to the active layer.

[0006] Preferably, in some embodiments of the present application, the substrate further comprises a first insulating layer provided on the active layer such that the gate is provided thereon; The active layer, the first insulating layer and the gate are stacked to form a protruding structure, and the blocking layer covers an outer surface of the protruding structure.

[0007] Preferably, in some embodiments of the present application, the active layer includes a first top surface and a first side surface connected to a periphery of the first top surface; the first insulating layer is provided in an intermediate region of the first top surface to include a second top surface and a second side surface connected to a periphery of the second top surface; the gate is provided on the second top surface to include a third top surface and a third side surface connected to a periphery of the third top surface; The blocking layer covers a lateral region of the first top surface, the first side surface, the second side surface, the third top surface, and the third side surface.

[0008] Preferably, in some embodiments of the present application, the substrate comprises: a light-shielding layer provided on the base and laminated with the active layer; a buffer layer provided between the light-shielding layer and the active layer; A second insulating layer provided on the source / drain metal layer, The source / drain metal layer further includes a source extension line connected to the source and the light-shielding layer, respectively.

[0009] Preferably, in some embodiments of the present application, the substrate further comprises a first insulating layer provided on the gate such that the active layer is provided thereon; The barrier layer covers the outer surface of the active layer.

[0010] Preferably, in some embodiments of the present application, the first insulating layer is provided with a groove disposed around the outer periphery of the gate and covered with the blocking layer.

[0011] Preferably, in some embodiments of the present application, the density of the barrier layer is less than 2.5 g / cm 3 That's all.

[0012] Preferably, in some embodiments of the present application, the barrier layer is a single layer structure, the material of which includes a metal oxide.

[0013] Preferably, in some embodiments of the present application, the barrier layer comprises: a first barrier layer comprising a material including a metal oxide; and a second barrier layer disposed on the first barrier layer such that the material comprises silicon oxide.

[0014] Preferably, in some embodiments of the present application, the active layer comprises one of polycrystalline silicon, monocrystalline silicon, and a metal oxide.

[0015] A display panel according to an embodiment of the present application includes the substrate described in the above embodiment, and a first electrode, a light-emitting layer, and a second electrode that are laminated together, The substrate is With the base, a plurality of thin film transistors disposed on the base; The thin film transistor is A gate provided on the base; an active layer provided on the base and stacked with the gate so as to be a different layer from the gate; a barrier layer that covers at least the active layer and the gate and blocks water and oxygen; a planarizing layer covering the barrier layer; a source-drain metal layer provided on the planar layer to include a source and a drain each connected to the active layer; The first electrode is connected to the drain.

[0016] Preferably, in some embodiments of the present application, the substrate further comprises a first insulating layer provided on the active layer such that the gate is provided thereon; The active layer, the first insulating layer and the gate are stacked to form a protruding structure, and the blocking layer covers an outer surface of the protruding structure.

[0017] Preferably, in some embodiments of the present application, the active layer includes a first top surface and a first side surface connected to a periphery of the first top surface; the first insulating layer is provided in an intermediate region of the first top surface to include a second top surface and a second side surface connected to a periphery of the second top surface; the gate is provided on the second top surface to include a third top surface and a third side surface connected to a periphery of the third top surface; The blocking layer covers a lateral region of the first top surface, the first side surface, the second side surface, the third top surface, and the third side surface.

[0018] Preferably, in some embodiments of the present application, the substrate comprises: a light-shielding layer provided on the base and laminated with the active layer; a buffer layer provided between the light-shielding layer and the active layer; A second insulating layer provided on the source / drain metal layer, The source / drain metal layer further includes a source extension line connected to the source and the light-shielding layer, respectively.

[0019] Preferably, in some embodiments of the present application, the substrate further comprises a first insulating layer provided on the gate such that the active layer is provided thereon; The barrier layer covers the outer surface of the active layer.

[0020] Preferably, in some embodiments of the present application, the first insulating layer is provided with a groove disposed around the outer periphery of the gate and covered with the blocking layer.

[0021] Preferably, in some embodiments of the present application, the density of the barrier layer is less than 2.5 g / cm3 That's all.

[0022] Preferably, in some embodiments of the present application, the barrier layer is a single layer structure, the material of which includes a metal oxide.

[0023] Preferably, in some embodiments of the present application, the barrier layer comprises: a first barrier layer comprising a material including a metal oxide; and a second barrier layer disposed on the first barrier layer such that the material comprises silicon oxide.

[0024] Preferably, in some embodiments of the present application, the active layer comprises one of polycrystalline silicon, monocrystalline silicon, and a metal oxide.

[0025] Another display panel according to an embodiment of the present application includes an array substrate, a counter substrate, and a liquid crystal provided between the array substrate and the counter substrate; The array substrate includes the substrate described in the above embodiment, The substrate is With the base, a plurality of thin film transistors disposed on the base; The thin film transistor is A gate provided on the base; an active layer provided on the base and stacked with the gate so as to be a different layer from the gate; a barrier layer that covers at least the active layer and the gate and blocks water and oxygen; a planarizing layer covering the barrier layer; a source / drain metal layer disposed on the planar layer to include a source and a drain each connected to the active layer.

[0026] Preferably, in some embodiments of the present application, the substrate further comprises a first insulating layer provided on the active layer such that the gate is provided thereon; The active layer, the first insulating layer and the gate are stacked to form a protruding structure, and the blocking layer covers an outer surface of the protruding structure.

[0027] Preferably, in some embodiments of the present application, the active layer includes a first top surface and a first side surface connected to a periphery of the first top surface; the first insulating layer is provided in an intermediate region of the first top surface to include a second top surface and a second side surface connected to a periphery of the second top surface; the gate is provided on the second top surface to include a third top surface and a third side surface connected to a periphery of the third top surface; The blocking layer covers a lateral region of the first top surface, the first side surface, the second side surface, the third top surface, and the third side surface.

[0028] Preferably, in some embodiments of the present application, the substrate comprises: a light-shielding layer provided on the base and laminated with the active layer; a buffer layer provided between the light-shielding layer and the active layer; A second insulating layer provided on the source / drain metal layer, The source / drain metal layer further includes a source extension line connected to the source and the light-shielding layer, respectively.

[0029] Preferably, in some embodiments of the present application, the substrate further comprises a first insulating layer provided on the gate such that the active layer is provided thereon; The barrier layer covers the outer surface of the active layer.

[0030] Preferably, in some embodiments of the present application, the first insulating layer is provided with a groove disposed around the outer periphery of the gate and covered with the blocking layer.

[0031] Preferably, in some embodiments of the present application, the density of the barrier layer is less than 2.5 g / cm 3 That's all.

[0032] Preferably, in some embodiments of the present application, the barrier layer is a single layer structure, the material of which includes a metal oxide.

[0033] Preferably, in some embodiments of the present application, the barrier layer comprises: a first barrier layer comprising a material including a metal oxide; and a second barrier layer disposed on the first barrier layer such that the material comprises silicon oxide.

[0034] Preferably, in some embodiments of the present application, the active layer comprises one of polycrystalline silicon, monocrystalline silicon, and a metal oxide. Effect of the Invention

[0035] In the substrate and display panel according to the embodiment of the present application, the thin film transistor includes a gate, an active layer, and a source / drain metal layer, the active layer is laminated with the gate so as to be a layer different from the gate, the blocking layer covers at least the active layer and the gate and blocks water and oxygen, the planarizing layer covers the blocking layer, and the source / drain metal layer is provided on the planarizing layer so as to include a source and a drain connected to the active layer, respectively. In the embodiment of the present application, by covering at least the gate and active layer of the thin film transistor with the blocking layer, external hydrogen, oxygen, water vapor, etc. are blocked from entering the gate and active layer, and by planarizing the laminated structure of the active layer and the gate with the planarizing layer, the risk that the source / drain metal layer and the film layer thereon are affected by complex topography is reduced. [Brief description of the drawings]

[0036] In order to more clearly describe the technical means of the embodiments of the present application, the drawings necessary for describing the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without any creative work.

[0037] [Figure 1] 1 is a schematic diagram of a first embodiment of a substrate according to the present application; [Diagram 2] 1 is a schematic diagram showing a protruding structure of a first embodiment of a substrate according to the present application; [Diagram 3] FIG. 2 is another schematic diagram of the blocking layer of the first embodiment of the substrate according to the present application. [Figure 4] FIG. 11 is a schematic diagram of a second embodiment of a substrate according to the present application. [Diagram 5] FIG. 11 is a schematic diagram of a third embodiment of a substrate according to the present application. [Figure 6] 1 is a schematic diagram illustrating a configuration of a first embodiment of a display panel according to the present application. [Figure 7] FIG. 11 is a schematic diagram illustrating a configuration of a second embodiment of a display panel according to the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Hereinafter, the technical means in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, and are not all of them. All other embodiments obtained based on the embodiments of the present application without the creative labor of a person skilled in the art are within the scope of protection of the present application. It should be understood that the specific embodiments described herein are only for explaining and interpreting the present application, and do not limit the present application. In this application, unless otherwise stated, the directional terms such as "up" and "down" generally mean the up and down of the device in the actual use or operation state, specifically the direction of the drawing in the drawing, and "inside" and "outside" refer to the contour of the device.

[0039] The embodiment of the present application provides a substrate and a display panel, and the source and drain of the thin film transistor are interchangeable. In the embodiment of the present application, in order to distinguish the two poles of the thin film transistor other than the gate, one pole is called the source and the other pole is called the drain. Hereinafter, the detailed description will be given. For the sake of explanation, the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0040] 1 is a schematic diagram of a first embodiment of a substrate according to the present application. A substrate 100 according to the present application includes a base 11 and a plurality of thin film transistors TFT. The plurality of thin film transistors TFT are provided on the base 11.

[0041] The thin film transistor TFT includes a gate 12 , an active layer 13 , a blocking layer 14 , a planarization layer 15 , and a source / drain metal layer 16 .

[0042] The gate 12 is provided on the base 11. The active layer 13 is provided on the base 11 so as to be a layer different from the gate 12. The active layer 13 is provided by stacking it with the gate 12.

[0043] The barrier layer 14 covers at least the active layer 13 and the gate 12. The barrier layer 14 blocks water and oxygen. The planar layer 15 covers the barrier layer 14. The source-drain metal layer 16 is provided on the planar layer 15 to include a source 161 and a drain 162. The source 161 and the drain 162 are each connected to the active layer 13.

[0044] In the substrate 100 according to the embodiment of the present application, by covering at least the gate 12 and active layer 13 of the thin film transistor TFT with a blocking layer 14, external hydrogen, oxygen, water vapor, etc. are prevented from entering the gate 12 and active layer 13, and by planarizing the stacked structure of the active layer 13 and gate 12 with a planarizing layer 15, the risk that the source / drain metal layer 16 and the film layers thereon will be affected by complex topography is reduced, thereby improving the luminous efficiency of the panel.

[0045] Preferably, the base 11 may be a rigid substrate or a flexible base, and the material of the base 11 includes one of glass, sapphire, silicon, silica, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide, and polyurethane.

[0046] Preferably, the material of the active layer 13 includes one of polycrystalline silicon, monocrystalline silicon, and metal oxide, and may be, for example, indium gallium zinc oxide (IGZO), zinc oxide, indium tin oxide, indium tin zinc oxide, etc.

[0047] Preferably, the material of the planarization layer 15 may be an organic transparent film layer, such as transparent photoresist, epoxy resin, polyimide, polyvinyl alcohol, polymethyl methacrylate, polystyrene, and so on.

[0048] Preferably, in this first embodiment, the substrate 100 further includes a first insulating layer 17. The first insulating layer 17 is provided on the active layer 13. The gate 12 is provided on the first insulating layer 17.

[0049] The protruding structure TC is formed by stacking the active layer 13, the first insulating layer 17 and the gate 12. The blocking layer 14 covers the outer surface of the protruding structure TC.

[0050] In this first embodiment, the blocking layer 14 covers the entire outer surface of the protruding structure TC, thereby further improving the water and oxygen barrier properties of the thin film transistor TFT.

[0051] Preferably, as shown in FIGS. 1 and 2, the active layer 13 includes a first top surface 13a and a first side surface 13b connected to the periphery of the first top surface 13a.

[0052] The first insulating layer 17 is provided in a central region of the first top surface 13a. The first insulating layer 17 includes a second top surface 17a and a second side surface 17b connected to the periphery of the second top surface 17a.

[0053] The gate 12 is provided on the second top surface 17a. The gate 12 includes a third top surface 12a and a third side surface 12b connected to the periphery of the third top surface 12a.

[0054] The blocking layer 14 covers the side area of ​​the first top surface 13a, the first side surface 13b, the second side surface 17b, the third top surface 12a and the third side surface 12b.

[0055] Preferably, the material of the first insulating layer 17 may be silicon oxide, silicon nitride or silicon oxynitride.

[0056] Preferably, the substrate 100 further includes a light-shielding layer 18, a buffer layer 19, and a second insulating layer 110. The light-shielding layer 18 is provided on the base 11. The light-shielding layer 18 is provided by stacking with the active layer 13. The buffer layer 19 is provided between the light-shielding layer 18 and the active layer 13. The second insulating layer 110 is provided on the source-drain metal layer 16.

[0057] The source-drain metal layer 16 further includes a source extension line 163. The source extension line 163 is connected to the source 161 and the light-shielding layer 18, respectively.

[0058] Here, since the blocking layer 14 and the flat layer 15 are provided between the source extension line 163 and the light-shielding layer 18, the distance between them is increased, and the stray capacitance between them is reduced. That is, by providing the blocking layer 14 and the flat layer 15 in a stacked manner, the water and oxygen-proof performance of the thin film transistor TFT is improved, and the complex topography formed in the front-end process is flattened, and the stray capacitance between the light-shielding layer 18 and the source extension line 163 is reduced.

[0059] Preferably, the light-shielding layer 18 may be a molybdenum titanium laminate structure or a molybdenum copper laminate structure. The material of the buffer layer 19 may be silicon nitride or silicon oxide, or may be a laminate structure of a silicon nitride film layer and a silicon oxide film layer.

[0060] Preferably, the second insulating layer 110 may be a passivation layer, such as silicon oxide.

[0061] Preferably, the density of the barrier layer 14 is 2.5 g / cm 3 This is all. With this setting, water and oxygen can be effectively blocked. The density of the blocking layer 14 is 2.5 g / cm 3 , 3g / cm 3 , 3.5g / cm3 , 5 g / cm3, etc.

[0062] Preferably, the thickness of the blocking layer 14 is between 300 angstroms and 500 angstroms, and may be, for example, 300 angstroms, 400 angstroms, and 500 angstroms. By making the thickness of the blocking layer 14 300 angstroms or more, the blocking layer 14 can effectively block water and oxygen, and by making the thickness of the blocking layer 14 500 angstroms or less, the blocking layer 14 is prevented from being too thick, and the geopotential height of the thin film transistor region is increased.

[0063] Preferably, the barrier layer 14 is a single layer structure. The material of the barrier layer 14 includes a metal oxide. For example, the material of the barrier layer 14 may be a metal oxide such as magnesium oxide, zinc oxide, aluminum oxide, nickel oxide, or tin oxide.

[0064] The blocking layer 14 is a dense oxide film formed from a metal oxide. For example, a dense oxide film can be formed on the base 11 by sputtering using a metal oxide as a target material.

[0065] Preferably, when the material of the barrier layer 14 is aluminum oxide (Al2O3), the compounding ratio of oxygen to aluminum is 1.5:1. When the material of the barrier layer 14 is aluminum oxide (ZnO), the compounding ratio of oxygen to zinc is 1:1. When the material of the barrier layer 14 is aluminum oxide (MgO), the compounding ratio of oxygen to magnesium is 1:1.

[0066] 3, the barrier layer 14 preferably includes a first barrier layer 141 and a second barrier layer 142 disposed on the first barrier layer 141. The material of the first barrier layer 141 includes a metal oxide. The material of the second barrier layer 142 includes a silicon oxide.

[0067] By laminating the first blocking layer 141 and the second blocking layer 142, the waterproof performance of the thin film transistor TFT can be further improved.

[0068] Preferably, the first barrier layer 141 and the second barrier layer 142 may be provided alternately.

[0069] The first blocking layer 141 is a dense oxide film formed from a metal oxide. For example, a dense oxide film can be formed on the base 11 by sputtering using a metal oxide as a target material. The metal oxide may be a metal oxide such as magnesium oxide, zinc oxide, aluminum oxide, nickel oxide, or tin oxide.

[0070] 4, the substrate 200 according to the present embodiment includes a base 11 and a plurality of thin film transistors TFT. The plurality of thin film transistors TFT are disposed on the base 11.

[0071] The thin film transistor TFT includes a gate 12, an active layer 13, a blocking layer 14, a planar layer 15, and a source-drain metal layer 16. The gate 12 is provided on a base 11. The active layer 13 is provided on the base 11 so as to be a layer different from the gate 12. The active layer 13 is provided in a laminated state with the gate 12. The blocking layer 14 covers at least the active layer 13 and the gate 12. The blocking layer 14 blocks water and oxygen. The planar layer 15 covers the blocking layer 14. The source-drain metal layer 16 is provided on the planar layer 15 so as to include a source 161 and a drain 162. The source 161 and the drain 162 are each connected to the active layer 13.

[0072] The substrate 200 of this embodiment differs from the substrate 100 of the above embodiment in the following points. The substrate 200 further includes a first insulating layer 17. The first insulating layer 17 is provided on the gate 12. The active layer 13 is provided on the first insulating layer 17. The second insulating layer 110 covers the source-drain metal layer 16 and the planar layer 15.

[0073] A barrier layer 14 covers the outer surface of active layer 13 .

[0074] Specifically, the blocking layer 14 covers the top surface of the active layer 13 and the side surface connected to the top surface.

[0075] In the substrate 200 of this embodiment, the active layer 13 is covered with the blocking layer 14, and the stacked structure of the gate 12, the first insulating layer 17 and the active layer 13 is planarized with the planarization layer 15, thereby improving the light emitting efficiency of the panel.

[0076] 5, the substrate 300 of this embodiment differs from the substrate 200 of the above embodiment in the following respects: A groove 171 is provided in the first insulating layer 17. The groove 171 is provided around the outer periphery of the gate 12, and the blocking layer 14 covers the groove 171.

[0077] The planarization layer 15 covers the stacked structure of the gate 12, the first insulating layer 17 and the active layer 13, thereby planarizing the protruding portions of the stacked structure, and covers the grooves 171, thereby planarizing the recessed portions of the grooves 171, thereby providing a flat base surface for subsequent film layers and further improving the luminous efficiency of the panel.

[0078] The substrate 300 of this embodiment is based on the substrate 200 of the above embodiment, but has a groove 171 around the outer periphery of the gate 12, and the blocking layer 14 extends into the groove 171, so that the blocking layer 14 covers the active layer 13 and the gate 12, thereby improving the water and oxygen resistance of the thin film transistor TFT.

[0079] 6, a display panel 1000 according to an embodiment of the present application includes the substrate (100 / 200 / 300) described in the above embodiment. The display panel 1000 further includes a first electrode P1, a light-emitting layer EL, and a second electrode P2, which are stacked. The first electrode P1 is connected to the drain 162.

[0080] The display panel 1000 of this embodiment is illustrated diagrammatically by taking the substrate 100 of this embodiment as an example, but is not limited thereto.

[0081] The first electrode P1 is an anode and the second electrode P2 is a cathode. In some embodiments, the first electrode P1 may be a cathode and the second electrode P2 may be an anode.

[0082] Preferably, the material of the light-emitting layer EL may be an organic material, such as Alq3, bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq), DPVBi, Almq3, 3-tert-butyl-9,10-di(2-naphthyl)anthracene (TBADN).

[0083] The material of the light-emitting layer EL may be one or more selected from inorganic materials such as group IV semiconductor nanocrystals, group II-V semiconductor nanocrystals, group II-VI semiconductor nanocrystals, group IV-VI semiconductor nanocrystals, group III-V semiconductor nanocrystals, and group III-VI semiconductor nanocrystals, etc. For example, the material may be one or more of silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, and gallium nitride quantum dots, etc.

[0084] In the display panel 1000 according to the embodiment of the present application, the thin film transistor TFT includes a gate 12, an active layer 13, and a source / drain metal layer 16. The active layer 13 and the gate 12 are provided in different layers and are laminated, and a barrier layer 14 covers at least the active layer 13 and the gate 12 to block water and oxygen. A planar layer 15 covers the barrier layer 14, and a source / drain metal layer 16 is provided on the planar layer 15. The source / drain metal layer 16 includes a source 161 and a drain 162 connected to the active layer 13, respectively.

[0085] In the display panel 1000 according to the embodiment of the present application, the blocking layer 14 covers at least the gate 12 and active layer 13 of the thin film transistor TFT, thereby blocking external hydrogen, oxygen, water vapor, etc. from entering the gate 12 and active layer 13, and the planarization layer 15 flattens the laminated structure of the active layer 13 and the gate 12, thereby reducing the risk that the source / drain metal layer 16 and the film layers above it will be affected by complex topography, and further improving the luminous efficiency of the display panel 1000.

[0086] 7, another display panel 2000 according to an embodiment of the present application includes an array substrate AR, a counter substrate CF, and a liquid crystal LC provided between the array substrate AR and the counter substrate CF. The array substrate AR includes the substrate (100 / 200 / 300) described in the above embodiment.

[0087] The display panel 2000 of this embodiment is shown diagrammatically as an example in which the substrate 100 of the above embodiment is a part of the array substrate AR, but is not limited thereto.

[0088] In the display panel 2000 according to the embodiment of the present application, the thin film transistor TFT includes a gate 12, an active layer 13, and a source / drain metal layer 16. The active layer 13 and the gate 12 are provided in different layers and are laminated, and a barrier layer 14 covers at least the active layer 13 and the gate 12 to block water and oxygen. A planar layer 15 covers the barrier layer 14, and a source / drain metal layer 16 is provided on the planar layer 15. The source / drain metal layer 16 includes a source 161 and a drain 162 connected to the active layer 13, respectively.

[0089] In the display panel 1000 according to the embodiment of the present application, the blocking layer 14 covers at least the gate 12 and active layer 13 of the thin film transistor TFT, thereby blocking external hydrogen, oxygen, water vapor, etc. from entering the gate 12 and active layer 13, and the planarization layer 15 flattens the laminated structure of the active layer 13 and the gate 12, thereby reducing the risk that the source / drain metal layer 16 and the film layers above it will be affected by complex topography, and further improving the luminous efficiency of the display panel 1000.

[0090] The above provides a detailed description of the substrate and display panel according to the embodiments of the present application, and the present specification uses specific examples to explain the principles and embodiments of the present application. However, the above description of the embodiments is merely intended to facilitate an understanding of the method and core ideas of the present application, and a person skilled in the art may modify the specific embodiments and scope of application in light of the ideas of the present application. In short, the contents of this specification should not be construed as limiting the present application.

Claims

1. With the base, a plurality of thin film transistors disposed on the base; The thin film transistor is A gate provided on the base; an active layer provided on the base and stacked with the gate so as to be a different layer from the gate; a barrier layer that covers at least the active layer and the gate and blocks water and oxygen; a planarizing layer covering the barrier layer; a source-drain metal layer provided on the planar layer to include a source and a drain each connected to the active layer; the substrate further includes a first insulating layer disposed on the active layer such that the gate is disposed thereon; The active layer, the first insulating layer and the gate are stacked to form a protruding structure, and the blocking layer covers an outer surface of the protruding structure; the active layer includes a first top surface and a first side surface connected to a periphery of the first top surface; the first insulating layer is provided in an intermediate region of the first top surface to include a second top surface and a second side surface connected to a periphery of the second top surface; the gate is provided on the second top surface to include a third top surface and a third side surface connected to a periphery of the third top surface; the blocking layer covers a side area of ​​the first top surface, the first side surface, the second side surface, the third top surface, and the third side surface; substrate.

2. a light-shielding layer provided on the base and laminated with the active layer; a buffer layer provided between the light-shielding layer and the active layer; A second insulating layer provided on the source / drain metal layer, The source / drain metal layer further includes a source extension line connected to the source and the light-shielding layer, respectively. The substrate of claim 1 .

3. a first insulating layer provided on the gate so that the active layer is provided thereon; The barrier layer covers an outer surface of the active layer. The substrate of claim 1 .

4. The first insulating layer has a groove formed around the outer periphery of the gate and covered with the blocking layer. The substrate according to claim 3 .

5. The density of the barrier layer is 2.5 g / cm or more and 5 g / cm or less. The substrate of claim 1 .

6. The blocking layer has a single layer structure, and the material thereof includes a metal oxide. The substrate of claim 1 .

7. The blocking layer is a first barrier layer comprising a material including a metal oxide; a second barrier layer disposed on the first barrier layer such that the material comprises silicon oxide; The substrate of claim 1 .

8. The light-emitting device includes a substrate, a first electrode, a light-emitting layer, and a second electrode that are laminated together, The substrate is a substrate according to any one of claims 1 to 7. Display panel.

9. The liquid crystal display device includes an array substrate, an opposing substrate, and a liquid crystal provided between the array substrate and the opposing substrate; The array substrate includes a substrate, The substrate is a substrate according to any one of claims 1 to 7. Display panel.

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