Method, device, quantum chip, and electronic device for generating quantum state preparation circuit

Abstract

The present application relates to a method, an apparatus, a quantum chip, and an electronic device for generating a quantum state preparation circuit, and the quantum chip can be applied to various smart terminals and in-vehicle devices. The method includes a step of determining a first unitary operator corresponding to n quantum bits (S702), a step of obtaining at least two second unitary operators used for performing a phase shift on the n quantum bits (S704), and a step of calculating the quantum bits of the control register and the quantum bits of the target register by r c qubits, and r t determining a third unitary operator to be used for replacing the quantum bits (S706); t The fourth unitary operator used to restore qubits, and r c The method includes generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to quantum bits (S708), combining each diagonal unitary matrix quantum circuit with a 1-bit gate to obtain at least two uniformity control gates (S710), and combining the at least two uniformity control gates as a quantum state preparation circuit (S712).

Description

[Technical field]

[0001] The present application relates to the field of quantum technology, and in particular to a method, an apparatus, an electronic device, a storage medium, and a computer program product for generating a quantum state preparation circuit.

[0002] This application claims priority to a Chinese patent application filed with the China Patent Office on April 29, 2022, bearing application number 2022104659281 and entitled "METHING, APPARATUS, QUANTUM STATE PREPARATION CIRCUIT GENERATION METHOD, APPARATUS, QUANTUM CHIP, AND ELECTRONIC DEVICE," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] In the field of quantum technology, it is usually necessary to load classical data into a quantum state, and this process is called quantum state preparation. The quantum state preparation process is an important process in the field of quantum technology, and often occupies most of the operation time of a quantum algorithm, therefore optimizing the quantum state preparation contributes to improving the operation efficiency of the quantum algorithm.

[0004] The current quantum state preparation circuit has a circuit depth of O(2 n ), n is the number of quantum bits. Theoretically, the lower limit of the depth of the quantum state preparation circuit is Ω(2 n / n). That is, the conventional quantum state preparation circuit is not an optimal circuit in terms of depth in an incremental sense, and still has a relatively large room for improvement. Summary of the Invention [Problem to be solved by the invention]

[0005] According to various embodiments of the present application, a method, an apparatus, an electronic device, a computer-readable storage medium, and a computer program product for generating a quantum state preparation circuit are provided. [Means for solving the problem]

[0006] In a first aspect, the present application provides a method of generating a quantum state preparation circuit, the method being performed by an electronic device, the method comprising: Determining a first unitary operator corresponding to n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t encoding quantum bits into a control register and a target register, respectively, where n is an integer greater than or equal to 2; obtaining at least two second unitary operators for use in performing a phase shift on the n quantum bits; The qubits of the control register and the qubits of the target register are c qubits, and the r t determining a third unitary operator used to replace the qubits; the first unitary operator, the second unitary operator, the third unitary operator, and the r t A fourth unitary operator used to restore the r qubits, c generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; combining each of the diagonal unitary matrix quantum circuits with a one-bit gate to obtain at least two uniformity control gates; combining the at least two uniform control gates as a quantum state preparation circuit.

[0007] In a second aspect, the present application further provides an apparatus for generating a quantum state preparation circuit, the apparatus comprising: A first determination module for determining a first unitary operator corresponding to n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t a first decision module for encoding the quantum bits into a control register and a target register, respectively, where n is an integer greater than or equal to 2; A first acquisition module for acquiring at least two second unitary operators for performing a phase shift on the n quantum bits; The qubits of the control register and the qubits of the target register are c qubits, and the r t a second determination module adapted to determine a third unitary operator adapted to replace the qubits; the first unitary operator, the second unitary operator, the third unitary operator, and the r t A fourth unitary operator used to restore the r qubits, c A generation module used for generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; A first combination module is used for combining each of the diagonal unitary matrix quantum circuits with a one-bit gate to obtain at least two uniformity control gates; and a second combination module adapted to combine the at least two uniformity control gates as a quantum state preparation circuit.

[0008] In a third aspect, there is provided a quantum chip including a quantum state preparation circuit, the quantum state preparation circuit being realized by a method for generating a quantum state preparation circuit, the method for generating the quantum state preparation circuit comprising the steps of: Determining a first unitary operator corresponding to n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t encoding quantum bits into a control register and a target register, respectively, where n is an integer greater than or equal to 2; obtaining at least two second unitary operators for use in performing a phase shift on the n quantum bits; The qubits of the control register and the qubits of the target register are cqubits, and the r t determining a third unitary operator used to replace the qubits; the first unitary operator, the second unitary operator, the third unitary operator, and the r t A fourth unitary operator used to restore the r qubits, c generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; combining each of the diagonal unitary matrix quantum circuits with a one-bit gate to obtain at least two uniformity control gates; and combining the at least two uniformity control gates as a quantum state preparation circuit.

[0009] In a fourth aspect, the present application further provides an electronic device, the electronic device including a memory and a processor, a computer program stored in the memory, the processor executing the computer program, Determining a first unitary operator corresponding to n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t encoding quantum bits into a control register and a target register, respectively, where n is an integer greater than or equal to 2; obtaining at least two second unitary operators for use in performing a phase shift on the n quantum bits; The qubits of the control register and the qubits of the target register are c qubits, and the r t determining a third unitary operator used to replace the qubits; the first unitary operator, the second unitary operator, the third unitary operator, and the r t A fourth unitary operator used to restore the r qubits,c generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; combining each of the diagonal unitary matrix quantum circuits with a one-bit gate to obtain at least two uniformity control gates; combining the at least two uniformity control gates as a quantum state preparation circuit.

[0010] In a fifth aspect, the present application further provides a computer-readable storage medium having stored thereon a computer program, the computer program being capable of, when executed by a processor, Determining a first unitary operator corresponding to n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t encoding quantum bits into a control register and a target register, respectively, where n is an integer greater than or equal to 2; obtaining at least two second unitary operators for use in performing a phase shift on the n quantum bits; The qubits of the control register and the qubits of the target register are c qubits, and the r t determining a third unitary operator used to replace the qubits; the first unitary operator, the second unitary operator, the third unitary operator, and the r t A fourth unitary operator used to restore the r qubits, c generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; combining each of the diagonal unitary matrix quantum circuits with a one-bit gate to obtain at least two uniformity control gates; combining the at least two uniformity control gates as a quantum state preparation circuit.

[0011] In a sixth aspect, the present application further provides a computer program product, the computer program product including a computer program that, when executed by a processor, Determining a first unitary operator corresponding to n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t encoding quantum bits into a control register and a target register, respectively, where n is an integer greater than or equal to 2; obtaining at least two second unitary operators for use in performing a phase shift on the n quantum bits; The qubits of the control register and the qubits of the target register are c qubits, and the r t determining a third unitary operator used to replace the qubits; the first unitary operator, the second unitary operator, the third unitary operator, and the r t A fourth unitary operator used to restore the r qubits, c generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; combining each of the diagonal unitary matrix quantum circuits with a one-bit gate to obtain at least two uniformity control gates; combining the at least two uniformity control gates as a quantum state preparation circuit.

[0012] The details of one or more embodiments of the application are set forth in the drawings and the description below. Other features and advantages of the application will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is an application environment diagram of a method for generating a quantum state preparation circuit in one embodiment. [Diagram 2] FIG. 2 is a schematic diagram of an n-path restriction of a quantum circuit in one embodiment. [Diagram 3] FIG. 2 is a schematic diagram of the framework of an n-qubit quantum state preparation circuit in one embodiment. [Figure 4] FIG. 2 is a structural schematic diagram of an n-qubit uniform control gate in one embodiment. [Diagram 5] FIG. 2 is a schematic diagram of decomposing a diagonal unitary matrix to obtain a first unitary operator, a second unitary operator, a third unitary operator, a fourth unitary operator, and a diagonal unitary matrix operator in one embodiment. [Figure 6] 1 is a quantum circuit framework for diagonal unitary matrices under path restrictions in one embodiment. [Figure 7] 1 is a flowchart of a method for generating a quantum state preparation circuit in one embodiment. [Figure 8] FIG. 1 is a schematic diagram of an implementation of the CNOT gate [Equation 1] under path constraints in one embodiment. [Figure 9] 1 is a flowchart of quantum state preparation in one embodiment. [Figure 10] FIG. 2 is a structural block diagram of a generating device for a quantum state preparation circuit in one embodiment. [Figure 11] FIG. 13 is a structural block diagram of a generating device for a quantum state preparation circuit in another embodiment. [Figure 12] FIG. 1 is a diagram showing the internal structure of an electronic device according to an embodiment.

[0014]

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[0015] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be described in more detail below in conjunction with drawings and examples. It should be understood that the specific examples described herein are merely for the purpose of interpreting the present application, and are not used to limit the present application.

[0016] It should be noted that in the following description, the terms "first, second, third, fourth, and fifth" are merely used to distinguish between similar objects and do not represent a particular order to the objects. It will be understood that "first, second, third, fourth, and fifth" may be interchanged with the specific order or priority under permitted circumstances, such that the embodiments of the present application described herein may be implemented in other than the order illustrated or described herein.

[0017] The method for generating a quantum state preparation circuit provided by the embodiment of the present application can be applied in the application environment shown in Fig. 1. Here, the electronic device 102 interacts with the quantum chip 104 through a sensor or a network. The data storage system can store data that the electronic device 102 needs to process. The data storage system can be integrated in the electronic device 102, or can be located in a cloud or other network server. The electronic device 102 can be used to generate a quantum state preparation circuit 1042, and the quantum chip 104 can be finally manufactured according to the quantum state preparation circuit 1042.

[0018] Here, the electronic device 102 may be an industrialized smart device used to manufacture the quantum state preparation circuit 1042, such as a photoetching device, a robot arm, and other devices required for industrial production. After using the quantum state preparation circuit 1042 to manufacture the quantum chip 104, the quantum chip 104 can be integrated into various smart terminals, including smartphones, tablet computers, laptops, desktop computers, smart speakers, smart watches, Internet of Things devices, and portable wearable devices, and the Internet of Things devices may be smart speakers, smart TVs, smart air conditioners, and smart car-mounted devices, etc. The portable wearable devices may be smart watches, smart bracelets, and head-mounted devices, etc.

[0019] Before providing a more detailed description of the embodiments of the present invention, the nouns, terms, symbols, relevant parameters, and basic quantum gates according to the embodiments of the present invention will be explained. The nouns and terms according to the embodiments of the present invention are applied to the following interpretation.

[0020] (1) Quantum Computation: A type of computing method that utilizes properties such as superposition of quantum states and entanglement to quickly complete computational tasks.

[0021] (2) Quantum bit (Qubit): A format for carrying quantum information.

[0022] (3) Quantum Circuit: A type of quantum computing model that consists of a series of quantum gate sequences and completes a calculation using quantum gates.

[0023] (4) Quantum chip: The central processor of a quantum computer. A quantum computer is a type of machine that uses the superposition principle of quantum mechanics and quantum entanglement to perform calculations. It has relatively high parallel processing capabilities and can solve some problems that are difficult for classical computers to calculate.

[0024] (5) i-Gray code cycle: {0,1} n A sequence of all n-bit strings in (abbreviated as n-bit string sequences) such that two adjacent bit strings differ in exactly one bit, and the first and last bit strings differ in exactly one bit. For any i ∈ [n], let [Number 2] denote an n-bit string sequence, and for any i ∈ [n], let [Number 3] denote an n-bit string sequence. For any j ∈ {2,3,…,2 n}, h ij where [number 4] and [number 5] represent subscripts of different bits, and h i1 If [Equation 6] and [Equation 7] are used to represent subscripts of different bits, then the following equation [Equation 8] is obtained.

[0025]

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number

number

number

number

number

[0026]

number

[0027] The bit string sequence [Number 9] of the above structure is called an (i,n)-Gray code cycle, and is abbreviated to i-Gray code cycle in this application. It should be noted that in the following embodiments, unless otherwise specified, the Gray code cycle can also refer to the i-Gray code cycle.

[0028]

number

[0029] (6) n-path restriction (abbreviated as path restriction): If in an n-quantum circuit, a two-bit gate (CNOT) is allowed to act only on two adjacent quantum bits, the n-quantum circuit is said to be under the n-path restriction. As shown in FIG. 2(a), FIG. 2(a) shows the n-path restriction of an n-qubit circuit, and vertex R 1 , R 2 , … , R n represent n quantum bits, respectively. If two quantum bits are connected by an edge, then a two-bit gate can act on both quantum bits.

[0030] (7) d-dimensional grid restriction (i.e., multidimensional grid restriction): In an n-quantum circuit arranged in a d-dimensional grid, a 2-bit gate is only allowed to act on two adjacent quantum bits, in which case the quantum circuit arranged in a d-dimensional grid is said to be under the d-dimensional grid restriction. As shown in FIG. 2(b), in a quantum circuit arranged in a 2-dimensional grid, a point in the 2-dimensional grid represents a quantum bit, resulting in a total of m1×m2=n quantum bits. If two quantum bits are connected by one edge, a 2-bit gate can act on the two quantum bits. Also, as shown in FIG. 2(c), in a quantum circuit arranged in a 3-dimensional grid, a point in the 3-dimensional grid represents a quantum bit, resulting in a total of m1×m2×m3=n quantum bits, and if two quantum bits are connected by one edge, a 2-bit gate can act on the two quantum bits.

[0031] (8) The basic symbol in this application: [n] represents the set {1, 2, ..., n}. 2 represents a binary field (belonging to a finite field). For any x=(x 1 ,…,x n ) T , y=(y 1 ,…,y n ) T ∈{0,1} n For , the inner product is [Equation 10] and the inner product is [Equation 11], where addition and multiplication are both defined in the binary field. n , and 1 n represent vectors of length n whose elements are all 0 and all 1, respectively. i denotes a vector whose i-th element is 1 and the other elements are 0. For any set S of positive integers, Equation 12 denotes the quantum state Equation 13 consisting of the qubits in set S.

[0032]

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[0033] (9) The basic quantum gates according to the present application are specifically shown in [Table 1].

[0034] [Table 1]

[0035] (10) The basic quantum gate parameters according to the present invention are specifically as follows [Equation 14].

[0036]

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[0037] Here, [Number 15] represents rounding up.

[0038]

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[0039] (11) The problem of quantum state preparation under the path restriction is defined as follows [Equation 18]: ||v|| 2 Given an arbitrary complex vector [Equation 16] that satisfies =1, and an initial state [Equation 17], prepare an n-bit quantum state.

[0040]

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number

[0041]

number

[0042] where {|k>:k=0,1,…,2 n −1} is a computational basis for a group of quantum systems. In the design of quantum state preparation circuits, we only allow the use of arbitrary 1-bit quantum gates and 2-bit gates, and 2-bit gates are only allowed to operate on two adjacent bits.

[0043] In order to make the present application clearer and more intuitively understandable, the design process of the quantum state preparation circuit under the n-path restriction will be described here first in conjunction with an embodiment, as shown in FIG. 6, the specific content is as follows:

[0044] S602: Decompose the quantum state preparation circuit into uniform control gates according to the target quantum state.

[0045] Here, the number of uniformity control gates obtained by decomposition is n, and V 1 , V 2 , …, V n and is as shown in Figure 3.

[0046] S604: Further decompose each uniformity control gate to obtain a diagonal unitary matrix and a 1-bit gate.

[0047] Now, after decomposing each uniformity control gate, we can obtain three diagonal unitary matrices and four 1-qubit gates, as shown in FIG.

[0048] Through the two steps S3602 and S604, the quantum state preparation circuit is transformed into a set of diagonal unitary matrices Λ j (j∈[n]), and a 1-bit gate (i.e., a 1-qubit gate). Therefore, if we realize any diagonal unitary matrix quantum circuit under the path restriction, we can directly obtain a quantum state preparation circuit under the path restriction.

[0049] S606: Construct a diagonal unitary matrix quantum circuit under path restrictions.

[0050] Combinatorial techniques and recursive methods are used to realize quantum circuits for diagonal unitary matrices under path restrictions, and the quantum circuits are optimal depth circuits in the incremental sense.

[0051] As can be seen from Table 1, the diagonal unitary matrix Λ n The effect of is to realize the following transformation for each vector |x> in the computational base:

[0052] |x>→e iθ(x) |x>,∀x∈{0,1} n -{0 n},θ(x)∈R,θ(0 n )=1

[0053] {α s :s∈{0,1} n -{0 n}} exists and satisfies the following formula:

[0054] Σ s <s,x> α s =θ(x),∀x∈{0,1} n -{0 n} (2)

[0055] In the structure of a diagonal unitary matrix quantum circuit under the path restriction, the set of real numbers {α s :s∈{0,1} n -{0 n}} will be used.

[0056] Therefore, the realization of S606 is divided into five sub-steps, specifically as follows:

[0057] S6062: Construct an n-qubit unitary operator [mathematical formula 19].

[0058]

number

[0059] S6064: n-qubit unitary operator G 1 ,G 2 ,…,G l Configure.

[0060] S6066: Construct an n-qubit unitary operator [mathematical formula 20].

[0061]

number

[0062] S6068:r t -Construct a unitary operator R for qubits.

[0063] S6070:r c -Construct the diagonal unitary operator [Eq. 21] of qubits.

[0064]

number

[0065] Then, the above unitary operator

[22] , G 1 ,G 2 ,…,G l , [Equation 23], R, and [Equation 24] are used to obtain the diagonal unitary matrix Λ n As shown in FIG. 5, a diagonal unitary matrix quantum circuit is constructed, and the diagonal unitary matrix quantum circuit and a 1-bit gate are combined as a uniformity control gate, and finally a quantum state preparation circuit is combined using the uniformity control gate.

[0066]

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[0067] In one embodiment, as shown in FIG. 7, a method for generating a quantum state preparation circuit is provided. Taking the method as an example for application to electronic devices, the method includes the following steps S702 to S712.

[0068] S702: A first unitary operator corresponding to the n quantum bits is determined.

[0069] Here, the first unitary operator ([Numerical formula 25]) is the r c qubits, and r t n is an integer equal to or greater than 2. The first unitary operator

[26] is used to encode r quantum bits into a control register and a target register, respectively, where n is an integer equal to or greater than 2. c qubits into the control register, and finally r t The qubits can be transposed into the target register, i.e., as follows:

[0070]

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[0071]

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[0072] Since the first unitary operator [Equation 28] is a reversible linear transformation in the computational base, the reversible linear transformation can be realized in a circuit under the path restriction or multidimensional grid restriction to obtain the circuit depth of the first unitary operator [Equation 29]. Therefore, under the path restriction or multidimensional grid restriction, the first unitary operator has a circuit depth of O(n 2 ), where the path restriction indicates that the 2-bit gate acts on two adjacent qubits in the n qubit set.

[0073]

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[0074] For a 2-bit gate [Equation 30], [Equation 30] represents that the control bit of the 2-bit gate is on the ith qubit of the control register, and the target bit is on the jth qubit of the target register. Under the path constraint, the 2-bit gate [Equation 30] can be realized by a 2-bit circuit whose circuit depth and size are both O(|ij|), as shown in Figure 8.

[0075]

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[0076] S704: Obtain at least two second unitary operators used to perform a phase shift on the n quantum bits.

[0077] Here, the second unitary operator (G 1 ,…,G l ) is a unitary operator used to perform a phase shift on n qubits.

[0078] In one embodiment, the electronic device can first construct and then store at least two second unitary operators used to perform phase shifts on the n quantum bits, and retrieve the at least two second unitary operators when needed to generate the quantum state preparation circuit.

[0079] Before constructing the second unitary operator, we will explain the contents related to the second unitary operator. First, let us consider a set T (1) , T (2) , …, T (l)is defined, and its specific properties are as follows:

[0080]

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[0081] (1) For each k ∈ [l], the set

[32] is a finite field F 2 are linearly independent in

[0082]

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[0083] (2) Set T (1) , T (2) , …, T (l) can cover the set [Equation 33], i.e., [Equation 34].

[0084]

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[0085] For each k∈[l]∪{0}, r t The quantum state of a bit is defined as follows [Equation 35].

[0086]

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[0087] That is, y (0) and x target is the same as [Equation 36], and [Equation 37] is a linear function related to [Equation 37]. In the following [Equation 38], we consider the mutually disjoint sets F 1 , F 2 , … , F l Define.

[0088]

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[0089]

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[0090] For any i ≠ j ∈ [l], the set F 1 , F 2 , … , F l satisfies [equation 39] and is also as follows [equation 40].

[0091]

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[0092]

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[0093] Below, the second unitary operator G k Given the definition of , for any k ∈ [l], we have the following [Equation 41].

[0094]

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[0095] As can be seen from the above formula, the second unitary operator G k has two actions: first, it introduces a phase, and second, it goes from k-1 steps to k steps.

[0096] In one embodiment, after determining the second unitary operator, the electronic device can further construct a unitary matrix quantum circuit under path restriction based on the second unitary operator, thereby constructing a diagonal unitary matrix quantum circuit using the unitary matrix quantum circuit and unitary matrix quantum circuits corresponding to other unitary operators.

[0097] The construction of the unitary matrix quantum circuit corresponding to the second unitary operator may include two steps: a generation step and a Gray code cycle step, where the generation step mainly realizes the circuit structure of the generated unitary operator, and the generated unitary operator is r t In the quantum bit, the calculation base is converted into a reversible linear transformation in a finite field, and the Gray code cycle stage mainly realizes the circuit structure of the Gray code cycle operator. The Gray code cycle operator is c It is used to perform a phase shift of the quantum state for n quantum bits by a Gray code cycle corresponding to n quantum bits.

[0098] (1) Generation stage

[0099] At the generation stage, we realize that the generating unitary operator [Equation 42] satisfies the following [Equation 43].

[0100]

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[0101]

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[0102] where y (k-1) , and y (k) are set T (k-1) , and T (k)For k∈[l]∪{0}, we have [Equation 44]. Fixing the order of elements in the set, we define the matrix [Equation 45] for any k∈[l], and for k=0, we have [Equation 46]. Therefore, the vector y (k) can be written as the following [Number 47].

[0103]

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[0104]

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[0105] [Number 48] is a finite field F 2 Since it is linearly independent in

[49] , the finite field F 2 It is invertible in and the generating unitary operator is defined as follows

[50] .

[0106]

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[0107]

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[0108] Here, the matrix-vector multiplication on the right hand side of the above equation is 2 This can be combined with equation (9) to obtain the following equation (51):

[0109]

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[0110] As can be seen from the above, we can convert the computational base into a finite field F 2 Therefore, under the path restriction, the generating unitary operator

[52] has depth O(n 2 ), where the path restriction indicates that the 2-bit gate operates on two adjacent qubits in the n qubit set.

[0111]

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[0112] (2) Gray Code Cycle Phase

[0113] Gray code cycle operator U GrayCycle It is possible to realize the above, which satisfies the following [Equation 53].

[0114]

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[0115] where k∈[l] and F k is defined in equation (4). For any i∈[r t ], [Equation 54] shows that the number of bits is r c Let denote an i-Gray code cycle where i∈[r t For any [number 56], [number 57] and [number 58] represent subscripts of different bits, and h i1 Let [number 59] and [number 60] represent subscripts of different bits. c For an i-bit Gray code cycle, h ij The definition of is as follows [Number 61].

[0116]

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[0117]

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[0118] h ij As can be seen from the definition of h 1j =k appears at most [number 62] times.

[0119]

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[0120] It should be noted that the Gray code stage includes

[63] stages, where: 1) Stage 1: The first of the stages is realized by a first rotating gate circuit that operates on the i-th quantum bit of the target register. For example, for any i ∈ [r t ], if the bit string is [number 64], then the circuit C 1 The rotation

[65] of operates on the i-th bit of the target register.

[0121]

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[0122] 2) Stage

[66] consists of two steps.

[0123]

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[0124] In step p.1, the p-th stage of the

[67] stages is realized by a first 2-bit gate circuit, and the control bit of the 2-bit gate in the first 2-bit gate circuit is h of the control register. ip The i-th qubit of the target register is the i-th qubit, and the target bit is the i-th qubit of the target register. For example, for each i∈[r t ], the control bit of the 2-bit gate in the first 2-bit gate circuit is h ip The i-th qubit is located at the i-th bit of the target register T, and the target bit is located at the i-th bit of the target register T. That is, for each i ∈ [r t ], if h ip ≦r t If so, apply the 2-bit gate [Equation 68] and if h ip >r t If so, a two-bit gate

[69] is applied.

[0125]

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[0126] In step p.2, the p-th stage in the

[70] stages is realized by a second rotary gate circuit, which operates on the i-th quantum bit of the target register. For example, for each i∈[r t For i = 1 i , if i = 1 i , then the rotation gate i = 1 i , whose sign is 2 i , operates on the i th qubit (whose sign is 2 i ) of the target register.

number

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[0127] 3) Step

[70] : The

[70] th step in the

[70] steps is realized by a second 2-bit gate circuit, and the control bit of the 2-bit gate in the second 2-bit gate circuit is h i1 The i-th qubit of the target register is the i-th qubit, and the target bit is the i-th qubit of the target register. For example, for each i∈[r t ], the control bit of the 2-bit gate in the second 2-bit gate circuit is h i1 The i-th qubit of the target register is the i-th qubit, and the target bit is the i-th qubit of the target register. That is, for each i∈[r t ], if h i1 < rt If so, apply the 2-bit gate [Equation 73] and if h i1 >r t If so, a two-bit gate

[74] is applied.

[0128]

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[0129] Therefore, at the Gray code cycle stage, the Gray code cycle operator can be realized by a circuit whose circuit depth is

[75] .

[0130]

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[0131] Here we prove the correctness of the above circuit, and for each

[76] , define the set

[77] as follows

[78] .

[0132]

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[0133]

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[0134] F in equation (6) k As can be understood based on the definition of , the set

[79] satisfies the following

[80] .

[0135]

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[0136]

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[0137] Next, we use the Grey cycle operator U GrayCycle The Gray cycle operator U GrayCycle can be seen from equation (12).

[0138]

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[0139]

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[0140] The circuit depth of each stage of the gray cycle is analyzed below, where: 1) Stage 1 consists of a first rotating gate circuit that operates on different qubits in the target register; therefore, it can be realized in a single layer circuit, i.e., the circuit depth is 1.

[0141] 2) In step

[83] , consider the following different situations:

[0142]

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[0143] If at step p h 1p If p.=1, then step p.1 can be realized by the first 2-bit gate circuit of the following equation (84).

[0144]

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[0145] Because the path constraints of each 2-bit gate in the first 2-bit gate circuit do not intersect, the circuit depth of the first 2-bit gate circuit is 1. Step p.2 may be composed of rotate gates operating on different quantum bits in the target register. It can therefore be realised in a single layer rotate gate circuit, and therefore the circuit depth of the first rotate gate circuit is 1.

[0146] If 2≦h at stage p 1pIf ≦τ, step p.1 can be realized by a first 2-bit gate circuit of the following equation (85).

[0147]

number

[0148] The path constraints of each 2-bit gate in the 2-bit gate circuit [Equation 86] do not cross each other, that is, all the 2-bit gates in the 2-bit gate circuit can be realized simultaneously. The reason is that C k The distance between the control bit and the target bit of each 2-bit gate in is at most O(h 1p ) Since step p.1 consists of the circuit [Equation 87], the total circuit depth of step p.1 is [Equation 88]. Step p.2 can consist of rotation gates operating on different qubits in the target register. It can therefore be realized in a single layer rotation gate circuit. Here, [Equation 89] above represents truncation.

[0149]

number

number

number

number

[0150] At step p, h 1p If >τ, step p.1 can be realized by a first 2-bit gate circuit, so that under the path restriction, the depth of step p.1 can be O(n 2). Step p.2 can be composed of rotate gates operating on different bits in the target register. It can therefore be realized in a single layer of rotate gate circuitry.

[0151] 3) Step

[90] is implemented by a second 2-bit gate circuit. As can be seen from the fact that reversible linear transformations are implemented by circuits under the path restriction or multidimensional grid restriction, the circuit depth of this step under the path restriction is O(n 2 )

[0152]

number

[0153] In one embodiment, the electronic device determines a circuit depth of a gate circuit that realizes a Gray code cycle operator based on circuit depths corresponding to a first rotate gate circuit, a second rotate gate circuit, a first 2-bit gate circuit, and a second 2-bit gate circuit, respectively.

[0154] For example, as can be seen from the properties of the Gray code cycle, the stages

[91] So, h 1p appears at most [Equation 92] times, so the total circuit depth of all [Equation 93] stages is [Equation 94]. Therefore, under the path constraint, the Gray code cycle operator can be realized by a gate circuit whose circuit depth is [Equation 95].

[0155]

number

number

number

number

number

[0156] It should be pointed out that the above circuit depth is the circuit depth under the path constraint, but the circuit depth also matches under the multi-dimensional grid constraint.

[0157] Therefore, the generation stage circuit and the Gray cycle stage circuit can be constructed and combined to obtain the operator G k We can obtain the circuit structure under the path restriction of k can be realized by a quantum circuit with depth

[96] , where the quantum circuit can consist of 1-bit gates (e.g., rotation gates) and 2-bit gates.

[0158]

number

[0159] S706: The quantum bit of the control register and the quantum bit of the target register are c qubits, and r t Determine the third unitary operator used to replace the qubits.

[0160] Here, the action of the third unitary [Eq. 97] is to move the qubits in the control register by the previous c qubits, and the qubits in the target register are replaced by the last r t This is to replace it onto quantum bits, that is, as shown below in [Number 98].

[0161]

number

[0162]

number

[0163] Therefore, under the path restriction, or under the multidimensional grid restriction, the third unitary operator has depth O(n 2 ) can be realized by a quantum circuit.

[0164] S708: First unitary operator, second unitary operator, third unitary operator, r t The fourth unitary operator used to restore qubits, and r c A diagonal unitary matrix quantum circuit is generated based on a diagonal unitary matrix operator corresponding to the quantum bits.

[0165] In one embodiment, the electronic device includes: t derive a fourth unitary operator used to restore the qubits, the fourth unitary operator being the last r t qubits, which eventually t The quantum states corresponding to the qubits are restored to the input state, i.e., as follows:

[0166]

number

[0167] Since the fourth unitary operator R is a reversible linear transformation in the computational base, the reversible linear transformation can be realized by a circuit under the path restriction, and therefore a 2-bit gate circuit of the fourth unitary operator R can be obtained.

[0168] After the first unitary operator, the second unitary operator, the third unitary operator, and the fourth unitary operator are all realized by the target circuit, the n-qubit diagonal unitary matrix can be divided into two parts, including a diagonal unitary matrix with a circuit designed and a diagonal unitary matrix with no circuit designed. The diagonal unitary matrix with no circuit designed [number 100] can be continued to be designed in a recursive manner, specifically as follows:

[0169]

number

[0170] In one embodiment, the electronic device obtains a diagonal unitary matrix operator, the diagonal unitary matrix operator being r c is a diagonal unitary matrix of quantum bits, satisfying the following [mathematical formula 101].

[0171]

number

[0172] Under the path restriction or multi-dimensional grid restriction, the diagonal unitary matrix operator can be realized by a recursive method, that is, the diagonal unitary matrix operator is taken as a new diagonal unitary matrix, the new diagonal unitary matrix is ​​further analyzed by a recursive method to obtain a new first unitary operator, a second unitary operator, a third unitary operator, a fourth unitary operator, and a diagonal unitary matrix operator, and then a circuit is designed for the new first unitary operator, a second unitary operator, a third unitary operator, and a fourth unitary operator. This analogy continues until there is no matrix for which a circuit has not been designed.

[0173] Specifically, the electronic device includes a two-bit gate circuit that realizes a first unitary operator, a quantum circuit that realizes a second unitary operator, a quantum circuit that realizes a third unitary operator, a two-bit gate circuit that realizes a fourth unitary operator, and r c A diagonal unitary matrix quantum circuit is generated based on a diagonal unitary matrix operator corresponding to qubits, where the diagonal unitary matrix operator is realized by a recursive scheme. n can be realized by the n-qubit quantum circuit of FIG. 5. The circuit depth is O(2 n / n).

[0174] Proof: We first prove the correctness of the circuit framework. First, by applying [Numerical formula 102], the first and second halves of the previous input quantum state |x> can be replaced into the control register and the target register, respectively.

[0175]

number

[0176]

number

[0177] Next, a set of unitary operators G 1 , … , G l By applying the above formula, the following transformation [Number 104] can be realized.

[0178]

number

[0179] Then, [Number 105] is applied to restore the first and second halves of the input quantum state to their initial positions.

[0180]

number

[0181]

number

[0182] Next, apply the operator R and finally r t Restore qubits to their initial states.

[0183]

number

[0184] Finally, we recursively realize the diagonal unitary matrix

[108] .

[0185]

number

[0186]

number

[0187] From the above discussion, the circuit framework in Fig. 5 is n It is explained that this makes it possible to realize quantum circuits.

[0188] In one embodiment, the electronic device determines a circuit depth of the quantum state preparation circuit based on a circuit depth of a 2-bit gate circuit corresponding to the first unitary operator, a circuit depth of a quantum circuit corresponding to the second unitary operator, a circuit depth of a quantum circuit corresponding to the third unitary operator, and a circuit depth of a 2-bit gate circuit corresponding to the fourth unitary operator, where the circuit depth is O(2 n / n).

[0189] In the following, the circuit depth is D(n) = O(2 n / n), there exists one real number α>0 such that the operator G k The circuit depth of is at most

[110] . There exists one real number β>0 such that the circuit depth of operator R is at most βn 2 Therefore, D(n) satisfies the recurrence formula given below in [Math. 111].

[0190]

number

[0191]

number

[0192] According to the above recurrence formula, D(n) = O(2 n / n) can be obtained.

[0193] S710: Combine each diagonal unitary matrix quantum circuit with a 1-bit gate to obtain at least two uniformity control gates.

[0194] S712: Combine at least two uniformity control gates as a quantum state preparation circuit.

[0195] In one embodiment, the electronic device can further detect the circuit depth of the quantum state preparation circuit, and the specific steps include: the electronic device obtains a diagonal unitary matrix, and detects the circuit depth of the quantum state preparation circuit by the diagonal unitary matrix. When it is determined that the quantum state preparation circuit can realize the diagonal unitary matrix based on the detection result, a target data vector is obtained, and a quantum state is prepared for the target data vector based on the quantum state preparation circuit.

[0196] For example, when preparing a quantum state, one can first determine the algorithms that need to be prepared for the quantum state, such as linear simultaneous equation solving, recommendation systems, support vector machines, clustering algorithms, and Hamiltonian simulation algorithms, and then vectorize the parameters of the algorithms, and then encode the resulting data vector into the quantum state as a target data vector. For example, a data vector x=(x 1 ,…,x n ) T ∈R n Encode into a quantum state [Numerical formula 112]. This step is quantum state preparation, as shown in Fig. 9, which can obtain quantum algorithms such as quantum linear simultaneous equation solving, quantum recommendation system, quantum support vector machine, quantum clustering algorithm, and Hamiltonian simulation.

[0197]

number

[0198] In the above embodiment, a first unitary operator corresponding to n quantum bits is determined, and the first unitary operator is c qubits, and r t qubits into a control register and a target register, respectively, n being an integer equal to or greater than 2, and obtaining at least two second unitary operators for performing a phase shift on the n qubits; and encoding the qubits of the control register and the qubits of the target register into r c qubits, and r t Determine the third unitary operator to be used to replace the qubits, and determine the first unitary operator, the second unitary operator, the third unitary operator, r t The fourth unitary operator used to restore qubits, and r c Based on the diagonal unitary matrix operators corresponding to quantum bits, a diagonal unitary matrix quantum circuit is generated, so that the circuit depth of the diagonal unitary matrix quantum circuit can be effectively reduced. Then, each diagonal unitary matrix quantum circuit is combined with a 1-bit gate to obtain at least two uniformity control gates, and the at least two uniformity control gates are combined as a quantum state preparation circuit, so that the circuit depth of the quantum state preparation circuit can be effectively reduced, and the time of quantum state preparation can be effectively reduced, and the operation efficiency of quantum computing can be improved.

[0199] As should be understood, although each step in the flowcharts according to the above embodiments is displayed in order according to the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly described in this specification, the execution of these steps is not limited to a strict order, and these steps may be executed in other orders. And, at least some of the steps in the flowcharts according to the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily performed sequentially, but may be executed in order or alternately with other steps or at least some of steps or stages in other steps.

[0200] Based on the same inventive idea, the embodiments of the present application further provide a quantum state preparation circuit generating device, which is used to realize the above-mentioned quantum state preparation circuit generating method. The means for solving the problem provided by the device are similar to the means described in the above-mentioned method, so that the specific limitations of one or more embodiments of the quantum state preparation circuit generating device provided below can refer to the limitations of the above-mentioned quantum state preparation circuit generating method, and will not be repeated here.

[0201] In one embodiment, as shown in FIG. 10, a generating device for a quantum state preparation circuit is provided, which includes a first determination module 1002, a first acquisition module 1004, a second determination module 1006, a generating module 1008, a first combination module 1010, and a second combination module 1012, where: The first determination module 1002 is used to determine a first unitary operator corresponding to n quantum bits, and the first unitary operator is r of the n quantum bits. c qubits, and r t n is an integer greater than or equal to 2, and The first acquisition module 1004 is used to acquire at least two second unitary operators used to perform a phase shift on the n quantum bits; The second determination module 1006 determines the qubits of the control register and the qubits of the target register as r c qubits, and r t is used to determine the third unitary operator used to replace the qubits, The generation module 1008 generates a first unitary operator, a second unitary operator, a third unitary operator, r t The fourth unitary operator used to restore qubits, and r c generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; The first combination module 1010 is used for combining each diagonal unitary matrix quantum circuit with a one-bit gate to obtain at least two uniformity control gates; The second combining module 1012 is used to combine at least two uniform control gates as a quantum state preparation circuit.

[0202] In one embodiment, under the path constraint or multidimensional grid constraint, the first unitary operator has a circuit depth of O(n 2 ) where the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linear array of n quantum bits. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid array of n quantum bits.

[0203] In one embodiment thereof, the second unitary operator includes a Gray code cycle operator and a generating unitary operator, and the Gray code cycle operator is r cIt is used to perform a phase shift of the quantum state for n qubits by a Gray code cycle corresponding to qubits, and the generating unitary operator is r t In this quantum bit, the computational basis is used to convert it into a reversible linear transformation in a finite field.

[0204] In one embodiment, under path constraints or multidimensional grid constraints, the generating unitary operator has a circuit depth of O(n 2 ) Under the path restriction, or multidimensional grid restriction, the Gray code cycle operator is realized by a gate circuit with a circuit depth of [mathematical formula - see original document], where the path restriction indicates that the 2-bit gate circuit operates on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linearly arranged n-qubit system. The multidimensional grid restriction indicates that the 2-bit gate circuit operates on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid arranged n-qubit system.

[0205]

number

[0206] In one embodiment thereof, the Gray code cycle operator includes [Equation 114] stages, a first stage of [Equation 114] being implemented by a first twiddle gate circuit operating on an i-th qubit of a target register, and a p-th stage of [Equation 114] being implemented by a first 2-bit gate circuit, the control bit of the 2-bit gate in the first 2-bit gate circuit being h of the control register. ipthe pth step of the [number 114] steps is realized by a second rotary gate circuit, the second rotary gate circuit operates on the ith quantum bit of the target register, the [number 114]th step of the [number 114] steps is realized by a second 2-bit gate circuit, the control bit of the 2-bit gate in the second 2-bit gate circuit is the hth quantum bit of the control register. i1 The i-th qubit of the target register is located at the i-th qubit, where i∈[r t , n], and h ip and i1 represents the subscript of different bits between adjacent bit strings in an n-bit string sequence, or the subscript of different bits between the first and last bit strings in an n-bit string sequence.

[0207]

number

[0208] In one embodiment, the first rotary gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of 1, the second rotary gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of 1, and the first 2-bit gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of O(n 2 ) and the circuit depth of the second 2-bit gate circuit under the path restriction, or the multidimensional grid restriction, is [Mathematical formula 115].

[0209]

number

[0210] In one embodiment thereof, as shown in FIG. 11, the apparatus includes: The circuit further includes a third determination module 1014 used for determining a circuit depth of a gate circuit for realizing a Gray code cycle operator based on the circuit depths corresponding to the first rotary gate circuit, the second rotary gate circuit, the first 2-bit gate circuit, and the second 2-bit gate circuit, respectively.

[0211] In one embodiment, under path constraints or multidimensional grid constraints, the third unitary operator has a circuit depth of O(n 2 ), and the fourth unitary operator is realized by a quantum circuit with a circuit depth of O(n 2 ) where the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linear array of n quantum bits. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid array of n quantum bits.

[0212] In one embodiment thereof, as shown in FIG. 11, the apparatus includes: The quantum state preparation circuit further includes a fourth determination module 1016, which is used to determine a circuit depth of the quantum state preparation circuit based on a circuit depth of the 2-bit gate circuit corresponding to the first unitary operator, a circuit depth of the quantum circuit corresponding to the second unitary operator, a circuit depth of the quantum circuit corresponding to the third unitary operator, and a circuit depth of the 2-bit gate circuit corresponding to the fourth unitary operator, where the circuit depth is O(2 n / n).

[0213] In one embodiment thereof, as shown in FIG. 11 , the apparatus further includes a second acquisition module 1018, a detection module 1020, and a preparation module 1022; The second obtaining module 1018 is used for obtaining a diagonal unitary matrix; The detection module 1020 is used for detecting the circuit depth of the quantum state preparation circuit by a diagonal unitary matrix; The second acquisition module 1018 is further used for acquiring a target data vector when it is determined according to the detection result that the quantum state preparation circuit can realize a diagonal unitary matrix; The preparation module 1022 is used for preparing a quantum state for the target data vector based on the quantum state preparation circuit.

[0214] In the above embodiment, a first unitary operator corresponding to n quantum bits is determined, and the first unitary operator is c qubits, and r t qubits into a control register and a target register, respectively, n being an integer equal to or greater than 2, and obtaining at least two second unitary operators for performing a phase shift on the n qubits; and encoding the qubits of the control register and the qubits of the target register into r c qubits, and r t Determine the third unitary operator to be used to replace the qubits, and determine the first unitary operator, the second unitary operator, the third unitary operator, r t The fourth unitary operator used to restore qubits, and r c Based on the diagonal unitary matrix operators corresponding to quantum bits, a diagonal unitary matrix quantum circuit is generated, so that the circuit depth of the diagonal unitary matrix quantum circuit can be effectively reduced. Then, each diagonal unitary matrix quantum circuit is combined with a 1-bit gate to obtain at least two uniformity control gates, and the at least two uniformity control gates are combined as a quantum state preparation circuit, so that the circuit depth of the quantum state preparation circuit can be effectively reduced, and the time of quantum state preparation can be effectively reduced, and the operation efficiency of quantum computing can be improved.

[0215] Each module in the quantum state preparation circuit generating device may be realized in whole or in part by software, hardware, or a combination thereof. Each module may be integrated into or independent of a processor in an electronic device in the form of hardware, or may be stored in a memory in an electronic device in the form of software, so that the processor calls and executes the operations corresponding to each module.

[0216] In one embodiment, an electronic device is provided, which may be an industrialized smart device, and its internal structure diagram may be shown in FIG. 12. The electronic device includes a processor, a memory, an input / output interface (abbreviated as Input / Output, I / O), and a communication interface. Here, the processor, the memory, and the input / output interface are connected by a system bus, and the communication interface is connected to the system bus by the input / output interface. Here, the processor of the electronic device is used to provide calculation and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the electronic device is used to store a target data vector. The input / output interface of the electronic device is used for information exchange between the processor and an external device. The communication interface of the electronic device is used for connecting and communicating with an external terminal through a network. When the computer program is executed by the processor, it realizes a method for generating a quantum state preparation circuit.

[0217] As will be understood by those skilled in the art, the structure shown in FIG. 12 is merely a block diagram of some structures related to the present invention, and does not constitute a limitation on electronic devices to which the present invention is applied; a specific electronic device may include more or fewer components than those shown in the drawing, or may combine certain components or have a different component arrangement.

[0218] In one embodiment, a quantum chip is provided that includes a quantum state preparation circuit, the quantum state preparation circuit being realized by the method for generating a quantum state preparation circuit of the present application.

[0219] In one embodiment, an electronic device is provided, comprising: a memory; and a processor, the memory storing a computer program, the processor, when executing the computer program, performing: Determining a first unitary operator corresponding to the n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t the step of encoding n qubits into a control register and a target register, respectively, n being an integer equal to or greater than 2; obtaining at least two second unitary operators used to perform a phase shift on the n qubits; and encoding the qubits of the control register and the qubits of the target register into r c qubits, and r t determining a third unitary operator to be used to replace the qubits; determining the first unitary operator, the second unitary operator, the third unitary operator, r t The fourth unitary operator used to restore qubits, and r c The method includes the steps of generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to quantum bits, combining each diagonal unitary matrix quantum circuit with a 1-bit gate to obtain at least two uniformity control gates, and combining the at least two uniformity control gates as a quantum state preparation circuit.

[0220] In one embodiment, under the path constraint or multidimensional grid constraint, the first unitary operator has a circuit depth of O(n 2 ) where the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linear array of n quantum bits. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid array of n quantum bits.

[0221] In one embodiment, the second unitary operator includes a Gray code cycle operator and a generating unitary operator, and the Gray code cycle operator is r c It is used to perform a phase shift of the quantum state for n qubits by a Gray code cycle corresponding to qubits, and the generating unitary operator is r t In this quantum bit, the computational basis is used to convert it into a reversible linear transformation in a finite field.

[0222] In one embodiment, under path constraints or multidimensional grid constraints, the generating unitary operator has a circuit depth of O(n 2 ), and under the path restriction or multidimensional grid restriction, the Gray code cycle operator is realized by a gate circuit with a circuit depth of [mathematical formula - see original document]. Here, the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linearly arranged n-qubit system. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid arranged n-qubit system.

[0223]

number

[0224] In one embodiment, the Gray code cycle operator includes [Equation 117] stages, a first stage of [Equation 117] being implemented by a first twiddle gate circuit operating on an i-th qubit of a target register, and a p-th stage of [Equation 117] being implemented by a first 2-bit gate circuit, a control bit of a 2-bit gate in the first 2-bit gate circuit being h of the control register. ip the pth step of the [Number 117] steps is realized by a second 2-bit gate circuit, the second 2-bit gate circuit operates on the ith quantum bit of the target register, and the [Number 117]th step of the [Number 117] steps is realized by a second 2-bit gate circuit, the control bit of the 2-bit gate in the second 2-bit gate circuit is the hth quantum bit of the control register. i1 The i-th qubit of the target register is located at the i-th qubit, where i∈[r t , n], and h ip and i1 represents the subscript of different bits between adjacent bit strings in an n-bit string sequence, or the subscript of different bits between the first and last bit strings in an n-bit string sequence.

[0225]

number

[0226] In one embodiment, the first rotary gate circuit has a circuit depth under the path constraint or multi-dimensional grid constraint of 1, the second rotary gate circuit has a circuit depth under the path constraint or multi-dimensional grid constraint of 1, and the first 2-bit gate circuit has a circuit depth under the path constraint or multi-dimensional grid constraint of O(n 2 ) and the circuit depth of the second 2-bit gate circuit under the path restriction, or the multidimensional grid restriction, is [Mathematical formula 118].

[0227]

number

[0228] In one embodiment, the processor, when executing a computer program, The step of determining a circuit depth of a gate circuit realizing a Gray code cycle operator based on the circuit depths corresponding to the first rotary gate circuit, the second rotary gate circuit, the first 2-bit gate circuit, and the second 2-bit gate circuit, respectively, is further implemented.

[0229] In one embodiment, under path constraints or multidimensional grid constraints, the third unitary operator has a circuit depth of O(n 2 ), and the fourth unitary operator is realized by a quantum circuit with a circuit depth of O(n 2 ) where the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linear array of n quantum bits. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid array of n quantum bits.

[0230] In one embodiment, the processor, when executing a computer program, Further implementing a step of determining a circuit depth of the quantum state preparation circuit based on a circuit depth of the 2-bit gate circuit corresponding to the first unitary operator, a circuit depth of the quantum circuit corresponding to the second unitary operator, a circuit depth of the quantum circuit corresponding to the third unitary operator, and a circuit depth of the 2-bit gate circuit corresponding to the fourth unitary operator, wherein the circuit depth is O(2 n / n).

[0231] In one embodiment, the processor, when executing a computer program, The method further includes the steps of obtaining a diagonal unitary matrix, detecting a circuit depth of the quantum state preparation circuit by the diagonal unitary matrix, and, when it is determined based on the detection result that the quantum state preparation circuit can realize the diagonal unitary matrix, obtaining a target data vector, and preparing a quantum state for the target data vector based on the quantum state preparation circuit.

[0232] In one embodiment, a computer readable storage medium is provided having stored thereon a computer program, the computer program, when executed by a processor, Determining a first unitary operator corresponding to the n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t the step of encoding n qubits into a control register and a target register, respectively, n being an integer equal to or greater than 2; obtaining at least two second unitary operators used to perform a phase shift on the n qubits; and encoding the qubits of the control register and the qubits of the target register into r c qubits, and r t determining a third unitary operator to be used to replace the qubits; determining the first unitary operator, the second unitary operator, the third unitary operator, r t The fourth unitary operator used to restore qubits, and r c The method includes the steps of generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to quantum bits, combining each diagonal unitary matrix quantum circuit with a 1-bit gate to obtain at least two uniformity control gates, and combining the at least two uniformity control gates as a quantum state preparation circuit.

[0233] In one embodiment, under the path constraint or multidimensional grid constraint, the first unitary operator has a circuit depth of O(n 2) where the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linear array of n quantum bits. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid array of n quantum bits.

[0234] In one embodiment, the second unitary operator includes a Gray code cycle operator and a generating unitary operator, and the Gray code cycle operator is r c It is used to perform a phase shift of the quantum state for n qubits by a Gray code cycle corresponding to qubits, and the generating unitary operator is r t In this quantum bit, the computational basis is used to convert it into a reversible linear transformation in a finite field.

[0235] In one embodiment, under path constraints or multidimensional grid constraints, the generating unitary operator has a circuit depth of O(n 2 ), and under the path restriction or multidimensional grid restriction, the Gray code cycle operator is realized by a gate circuit with a circuit depth of [Mathematical formula -119]. Here, the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linearly arranged n-qubit system. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid arranged n-qubit system.

[0236]

number

[0237] In one embodiment, the Gray code cycle operator includes

[120] stages, a first stage of the

[120] stages being implemented by a first twiddle gate circuit operating on an i-th qubit of a target register, and a p-th stage of the

[120] stages being implemented by a first 2-bit gate circuit, a control bit of a 2-bit gate in the first 2-bit gate circuit being h of the control register. ip the pth step of the [number 120] steps is realized by a second 2-bit gate circuit, the second 2-bit gate circuit operates on the ith quantum bit of the target register, and the [number 120]th step of the [number 120] steps is realized by a second 2-bit gate circuit, the control bit of the 2-bit gate in the second 2-bit gate circuit is the hth quantum bit of the control register. i1 The i-th qubit of the target register is located at the i-th qubit, where i∈[r t , n], and h ip and i1 represents the subscript of different bits between adjacent bit strings in an n-bit string sequence, or the subscript of different bits between the first and last bit strings in an n-bit string sequence.

[0238]

number

[0239] In one embodiment, the first rotary gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of 1, the second rotary gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of 1, and the first 2-bit gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of O(n 2 ) and the circuit depth of the second 2-bit gate circuit under the path restriction, or the multidimensional grid restriction, is [Mathematical formula 121].

[0240]

number

[0241] In one embodiment, the computer program, when executed by a processor, The step of determining a circuit depth of a gate circuit realizing a Gray code cycle operator based on the circuit depths corresponding to the first rotary gate circuit, the second rotary gate circuit, the first 2-bit gate circuit, and the second 2-bit gate circuit, respectively, is further implemented.

[0242] In one embodiment, under path constraints or multidimensional grid constraints, the third unitary operator has a circuit depth of O(n 2 ), and the fourth unitary operator is realized by a quantum circuit with a circuit depth of O(n 2 ) where the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linear array of n quantum bits. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid array of n quantum bits.

[0243] In one embodiment, the computer program, when executed by a processor, Further implementing a step of determining a circuit depth of the quantum state preparation circuit based on a circuit depth of the 2-bit gate circuit corresponding to the first unitary operator, a circuit depth of the quantum circuit corresponding to the second unitary operator, a circuit depth of the quantum circuit corresponding to the third unitary operator, and a circuit depth of the 2-bit gate circuit corresponding to the fourth unitary operator, wherein the circuit depth is O(2 n / n).

[0244] In one embodiment, the computer program, when executed by a processor, The method further includes the steps of obtaining a diagonal unitary matrix, detecting a circuit depth of the quantum state preparation circuit by the diagonal unitary matrix, and, when it is determined based on the detection result that the quantum state preparation circuit can realize the diagonal unitary matrix, obtaining a target data vector, and preparing a quantum state for the target data vector based on the quantum state preparation circuit.

[0245] In one embodiment, a computer program product is provided that includes a computer program that, when executed by a processor, Determining a first unitary operator corresponding to the n quantum bits, the first unitary operator being r of the n quantum bits. c qubits, and r t the step of encoding n qubits into a control register and a target register, respectively, n being an integer equal to or greater than 2; obtaining at least two second unitary operators used to perform a phase shift on the n qubits; and encoding the qubits of the control register and the qubits of the target register into r c qubits, and r t determining a third unitary operator to be used to replace the qubits; determining the first unitary operator, the second unitary operator, the third unitary operator, r t The fourth unitary operator used to restore qubits, and r c The method includes the steps of generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to quantum bits, combining each diagonal unitary matrix quantum circuit with a 1-bit gate to obtain at least two uniformity control gates, and combining the at least two uniformity control gates as a quantum state preparation circuit.

[0246] In one embodiment, under the path constraint or multidimensional grid constraint, the first unitary operator has a circuit depth of O(n 2) where the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linear array of n quantum bits. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid array of n quantum bits.

[0247] In one embodiment, the second unitary operator includes a Gray code cycle operator and a generating unitary operator, and the Gray code cycle operator is r c It is used to perform a phase shift of the quantum state for n qubits by a Gray code cycle corresponding to qubits, and the generating unitary operator is r t In this quantum bit, the computational basis is used to convert it into a reversible linear transformation in a finite field.

[0248] In one embodiment, under path constraints or multidimensional grid constraints, the generating unitary operator has a circuit depth of O(n 2 ), and under the path restriction or multidimensional grid restriction, the Gray code cycle operator is realized by a gate circuit with a circuit depth of [mathematical formula - see original document]. Here, the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linearly arranged n-qubit system. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid arranged n-qubit system.

[0249]

number

[0250] In one embodiment, the Gray code cycle operator includes [Equation 123] stages, a first stage of the [Equation 123] stages being implemented by a first twiddle gate circuit operating on an i-th qubit of a target register, and a p-th stage of the [Equation 123] stages being implemented by a first 2-bit gate circuit, a control bit of a 2-bit gate in the first 2-bit gate circuit being h of the control register. ip the pth step of the [number 123] steps is realized by a second 2-bit gate circuit, the second 2-bit gate circuit operates on the ith quantum bit of the target register, and the [number 123]th step of the [number 123] steps is realized by a second 2-bit gate circuit, the control bit of the 2-bit gate in the second 2-bit gate circuit is the hth quantum bit of the control register. i1 The i-th qubit of the target register is located at the i-th qubit, where i∈[r t , n], and h ip and i1 represents the subscript of different bits between adjacent bit strings in an n-bit string sequence, or the subscript of different bits between the first and last bit strings in an n-bit string sequence.

[0251]

number

[0252] In one embodiment, the first rotary gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of 1, the second rotary gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of 1, and the first 2-bit gate circuit has a circuit depth under the path restriction or multi-dimensional grid restriction of O(n 2 ) and the circuit depth of the second 2-bit gate circuit under the path restriction, or the multidimensional grid restriction, is [Number 124].

[0253]

number

[0254] In one embodiment, the computer program, when executed by a processor, The step of determining a circuit depth of a gate circuit realizing a Gray code cycle operator based on the circuit depths corresponding to the first rotary gate circuit, the second rotary gate circuit, the first 2-bit gate circuit, and the second 2-bit gate circuit, respectively, is further implemented.

[0255] In one embodiment, under path constraints or multidimensional grid constraints, the third unitary operator has a circuit depth of O(n 2 ), and the fourth unitary operator is realized by a quantum circuit with a circuit depth of O(n 2 ) where the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a linear array of n quantum bits. The multidimensional grid restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in a multidimensional grid array of n quantum bits.

[0256] In one embodiment, the computer program, when executed by a processor, Further implementing a step of determining a circuit depth of the quantum state preparation circuit based on a circuit depth of the 2-bit gate circuit corresponding to the first unitary operator, a circuit depth of the quantum circuit corresponding to the second unitary operator, a circuit depth of the quantum circuit corresponding to the third unitary operator, and a circuit depth of the 2-bit gate circuit corresponding to the fourth unitary operator, wherein the circuit depth is O(2 n / n).

[0257] In one embodiment, the computer program, when executed by a processor, The method further includes the steps of obtaining a diagonal unitary matrix, detecting a circuit depth of the quantum state preparation circuit by the diagonal unitary matrix, and, when it is determined based on the detection result that the quantum state preparation circuit can realize the diagonal unitary matrix, obtaining a target data vector, and preparing a quantum state for the target data vector based on the quantum state preparation circuit.

[0258] It is necessary to explain that the user information (including but not limited to user device information and user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) related to this application are all information and data authorized by the user or fully authorized by each party, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0259] As can be understood by those skilled in the art, the implementation of all or part of the processes in the methods of the above embodiments may be completed by issuing instructions to relevant hardware by a computer program, and the computer program may be stored in a non-volatile computer-readable storage medium, and may include the processes of the above embodiments of the methods when the computer program is executed. Here, any examples of memory, database, or other medium used in the embodiments provided in the present application may include at least one of non-volatile memory and volatile memory. The non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM (registered trademark)), phase change memory (PCM), graphene memory, etc. The volatile memory may include random access memory (RAM), external cache memory, etc. As a non-limiting example, the RAM may be of multiple types, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). In the embodiments provided herein, the database may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a distributed database based on a blockchain. In the embodiments provided herein, the processor may be, but is not limited to, a general-purpose processor, a central processor, a graphic processor, a digital signal processor, a programmable logic device, and a data processing logic device based on quantum computing.

[0260] The technical features of the above embodiments can be combined in any combination, and for the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there are no contradictions between the combinations of these technical features, they should be considered within the scope of the present specification.

[0261] The above examples only represent a number of embodiments of the present application, and the description is relatively specific and detailed, but this should not be understood as a limitation on the patent scope of the present application. It should be noted that those skilled in the art can make some modifications and improvements without departing from the concept of the present application, all of which belong to the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of the attached claims. [Explanation of symbols]

[0262] 102 Electronic equipment 104 Quantum Chip 1002 First Decision Module 1004 First Acquisition Module 1006 Second Decision Module 1008 Generation Module 1010 First combination module 1012 2nd Combination Module 1014 Third Decision Module 1016 4th Decision Module 1018 2nd Acquisition Module 1020 Detection Module 1022 Preparation Module 1042 Quantum state preparation circuit

Claims

1. 1. A method for generating a quantum state preparation circuit, the method comprising the steps of: Determining a first unitary operator corresponding to n quantum bits, the first unitary operator being a unitary operator corresponding to r of the n quantum bits. ｃ qubits, and r ｔ encoding quantum bits into a control register and a target register, respectively, where n is an integer greater than or equal to 2; obtaining at least two second unitary operators used to perform a phase shift on the n quantum bits; The qubits of the control register and the qubits of the target register are ｃ qubits, and the r ｔ determining a third unitary operator to be used to replace each of the qubits; the first unitary operator, the second unitary operator, the third unitary operator, and the r ｔ a fourth unitary operator used to restore the r qubits, and ｃ generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; combining each of the diagonal unitary matrix quantum circuits with a one-bit gate to obtain at least two uniformity control gates; combining the at least two uniformity control gates as a quantum state preparation circuit.

2. Under the path restriction or multidimensional grid restriction, the first unitary operator has a circuit depth of O(n ２ ) is realized by a 2-bit gate circuit, the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a line; 2. The method of claim 1 , wherein the multidimensional grid constraint indicates that the two-bit gate circuit operates on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a multidimensional grid.

3. the second unitary operator includes a Gray code cycle operator and a generating unitary operator; The Gray code cycle operator is ｃ for performing a phase shift of a quantum state for the n quantum bits by a Gray code cycle corresponding to the n quantum bits; The generating unitary operator is the r ｔ 13. The method of claim 1, wherein the method is used to convert a computational basis to a reversible linear transformation in a finite field in a quantum bit.

4. Under the path restriction, or under the multidimensional grid restriction, the generating unitary operator has a circuit depth of O(n ２ ) is realized by a 2-bit gate circuit, Under the path restriction or multidimensional grid restriction, the Gray code cycle operator is realized by a gate circuit whose circuit depth is the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a line; 4. The method of claim 3, wherein the multidimensional grid constraint indicates that the two-bit gate circuit operates on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a multidimensional grid. [0010]

5. The Gray code cycle operator includes the following steps: a first step of the steps is realized by a first rotary gate circuit, the first rotary gate circuit operating on an i-th quantum bit of the target register; The p-th step of the steps of [Equation 2] is realized by a first 2-bit gate circuit, and the control bit of the 2-bit gate in the first 2-bit gate circuit is h of the control register. ｉｐ the pth step is implemented by a second rotary gate circuit, the second rotary gate circuit operating on the ith quantum bit of the target register; and the target bit is in the i-th quantum bit of the target register; or The [number 2]th step of the [number 2] steps is realized by a second 2-bit gate circuit, and a control bit of a 2-bit gate in the second 2-bit gate circuit is h of the control register. ｉ１ the i-th qubit of the target register, and the target bit is the i-th qubit of the target register; i ∈ [r ｔ , n], and h ｉｐ and ｉ１ 4. The method of claim 3, wherein r denotes a subscript of different bits between adjacent bit strings in an n-bit string sequence or a subscript of different bits between a first bit string and a last bit string in the n-bit string sequence. [0025]

6. The first rotary gate circuit has a circuit depth under a path restriction or a multi-dimensional grid restriction of 1; The second rotary gate circuit has a circuit depth under a path restriction or a multi-dimensional grid restriction of 1; The circuit depth of the first 2-bit gate circuit under the path constraint or the multidimensional grid constraint is O(n ２ ) and 6. The method of claim 5, wherein the path restriction or circuit depth under the multidimensional grid restriction of the second 2-bit gate circuit is: [0030]

7. The method comprises:

7. The method of claim 6, further comprising determining a circuit depth of a gate circuit that realizes the Gray code cycle operator based on circuit depths corresponding to the first rotate gate circuit, the second rotate gate circuit, the first 2-bit gate circuit, and the second 2-bit gate circuit, respectively.

8. Under the path restriction or multidimensional grid restriction, the third unitary operator has a circuit depth of O(n ２ ), and the fourth unitary operator is realized by a quantum circuit having a circuit depth of O(n ２ ) is realized by a 2-bit gate circuit, the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a line; 2. The method of claim 1 , wherein the multidimensional grid constraint indicates that the two-bit gate circuit operates on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a multidimensional grid.

9. The method comprises: The method further includes determining a circuit depth of the quantum state preparation circuit based on a circuit depth of a 2-bit gate circuit corresponding to the first unitary operator, a circuit depth of a quantum circuit corresponding to the second unitary operator, a circuit depth of a quantum circuit corresponding to the third unitary operator, and a circuit depth of a 2-bit gate circuit corresponding to the fourth unitary operator, and the circuit depth is O(2 ｎ / n).

10. The method comprises: obtaining a diagonal unitary matrix; Detecting a circuit depth of the quantum state preparation circuit by the diagonal unitary matrix; When the quantum state preparation circuit determines that the diagonal unitary matrix can be realized based on the detected result, obtaining a target data vector; 10. The method of claim 9, further comprising: performing quantum state preparation for the target data vector based on the quantum state preparation circuit.

11. A quantum state preparation circuit generating device, A first determination module adapted to determine a first unitary operator corresponding to n quantum bits, the first unitary operator being r of the n quantum bits. ｃ qubits, and r ｔ a first decision module for encoding the quantum bits into a control register and a target register, respectively, where n is an integer greater than or equal to 2; a first acquisition module for acquiring at least two second unitary operators for performing a phase shift on the n quantum bits; The qubits of the control register and the qubits of the target register are ｃ qubits, and the r ｔ a second determination module adapted to determine a third unitary operator used to replace the qubits; the first unitary operator, the second unitary operator, the third unitary operator, and the r ｔ a fourth unitary operator used to restore the r qubits, and ｃ A generation module used for generating a diagonal unitary matrix quantum circuit based on a diagonal unitary matrix operator corresponding to the qubits; a first combination module for combining each of the diagonal unitary matrix quantum circuits with a one-bit gate to obtain at least two uniformity control gates; a second combination module used to combine the at least two uniformity control gates into a quantum state preparation circuit.

12. Under the path restriction or multidimensional grid restriction, the first unitary operator has a circuit depth of O(n ２ ) is realized by a 2-bit gate circuit, 12. The apparatus of claim 11, wherein the path restriction indicates that the two-bit gate circuit operates on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a linear fashion.

13. the second unitary operator includes a Gray code cycle operator and a generating unitary operator; The Gray code cycle operator is ｃ for performing a phase shift of a quantum state for the n quantum bits by a Gray code cycle corresponding to the n quantum bits; The generating unitary operator is the r ｔ 12. The apparatus of claim 11, wherein the apparatus is used to invert a computational basis in quantum bits to a reversible linear transformation in a finite field.

14. Under the path restriction, or under the multidimensional grid restriction, the generating unitary operator has a circuit depth of O(n ２ ) is realized by a 2-bit gate circuit, Under the path restriction or multidimensional grid restriction, the Gray code cycle operator is realized by a gate circuit whose circuit depth is the path restriction indicates that the 2-bit gate circuit acts on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a line; 14. The apparatus of claim 13, wherein the multidimensional grid constraint indicates that the two-bit gate circuit operates on two adjacent quantum bits, and the two adjacent quantum bits are quantum bits in the n quantum bits arranged in a multidimensional grid. [0045]

15. The Gray code cycle operator includes the following stages: a first step of the steps is realized by a first rotary gate circuit, the first rotary gate circuit operating on an i-th quantum bit of the target register; The p-th step of the steps of [Equation 5] is realized by a first 2-bit gate circuit, and the control bit of the 2-bit gate in the first 2-bit gate circuit is h of the control register. ｉｐ the pth step of the [mathematical formula 5] is realized by a second rotary gate circuit, the second rotary gate circuit operates on the ith quantum bit of the target register; The [Numerical value 5]-th step of the [Numerical value 5] steps is realized by a second 2-bit gate circuit, and a control bit of a 2-bit gate in the second 2-bit gate circuit is h of the control register. ｉ１ the i-th qubit of the target register, and the target bit is the i-th qubit of the target register; i ∈ [r ｔ , n], and h ｉｐ and ｉ１ 14. The apparatus of claim 13, wherein ^ represents a subscript of different bits between adjacent bit strings in an n-bit string sequence or a subscript of different bits between a first bit string and a last bit string in the n-bit string sequence. [0050]

16. The first rotary gate circuit has a circuit depth under a path restriction or a multi-dimensional grid restriction of 1; The second rotary gate circuit has a circuit depth under a path restriction or a multi-dimensional grid restriction of 1; The circuit depth of the first 2-bit gate circuit under the path constraint or the multidimensional grid constraint is O(n ２ ) and 16. The apparatus of claim 15, wherein the path restriction or circuit depth under the multidimensional grid restriction of the second 2-bit gate circuit is: [006]

17. A quantum chip comprising a quantum state preparation circuit, the quantum state preparation circuit being realized by a method according to any one of claims 1 to 8.

18. An electronic device comprising a memory and a processor, a computer program stored in the memory, and the processor, when executing the computer program, realizing the method according to any one of claims 1 to 8.

19. A computer program which, when executed by a processor, implements the method according to any one of claims 1 to 8.

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