Semiconductor structure and method for manufacturing same - Patents.com

Abstract

To provide a semiconductor structure with which electronic devices, such as DRAM, can be manufactured in a cost saving manner.SOLUTION: A semiconductor structure (DRAM structure 100) has a device defining region D. The device defining region includes a first portion P1 and a second portion P2 separated from each other. The semiconductor structure includes a stack 104. The stack includes first conductive layers 106 and first dielectric layers disposed alternately. The stack has an opening O through the stack in the device defining region. The semiconductor structure further includes a second conductive layer 112, a first conductive pillar 114, a third conductive layer 118, a second conductive pillar 120, and a third conductive pillar 122. The second conductive layer is disposed along a sidewall of the opening. The first conductive pillar is disposed in the opening in the first portion. The third conductive layer is disposed in the opening along an edge of the second portion. The second conductive pillar and the third conductive pillar are disposed in the second portion and separated from each other.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates to semiconductor structures and methods for fabricating same, and more particularly, to semiconductor structures comprising 3D DRAM structures and methods for fabricating same. [Background technology]

[0002] With the development of the semiconductor industry, three-dimensional (3D) structures for various electronic devices have been proposed for the purpose of increasing density and reducing volume. In some kinds of electronic devices, such as dynamic random access memory (DRAM), the means of realizing 3D structures is to stack two-dimensional (2D) structures layer by layer. Although such 3D structures enable more space-saving electronic devices, they are not beneficial for cost reduction. Summary of the Invention

[0003] This disclosure focuses on improving 3D structures to enable the low-cost manufacturing of electronic devices such as DRAMs.

[0004] In one aspect of the disclosure, a semiconductor structure is provided. The semiconductor structure has a device definition region. The device definition region includes a first portion and a second portion separated from each other. The semiconductor structure comprises a stack. The stack includes a plurality of alternating first conductive layers and a plurality of first dielectric layers. The stack has an opening through the stack in the device definition region. The semiconductor structure further comprises a second conductive layer, a first conductive pillar, a third conductive layer, a second conductive pillar, and a third conductive pillar. The second conductive layer is disposed along a sidewall of the opening. The first conductive pillar is disposed in the opening in the first portion of the device definition region. The third conductive layer is disposed in the opening along an edge of the second portion of the device definition region. The second conductive pillar and the third conductive pillar are disposed in the second portion and are separated from each other.

[0005] In another aspect of the disclosure, a method for fabricating a semiconductor structure is provided. The semiconductor structure has a device definition region. The device definition region includes a first portion and a second portion separated from each other. The method includes the following steps: First, a stack is formed, the stack including a plurality of alternating first conductive layers and a plurality of first dielectric layers, the stack having an opening through the stack in the device definition region. Then, a second conductive layer is formed along a sidewall of the opening. A first conductive pillar is formed in the opening in the first portion of the device definition region. A third conductive layer is formed in the opening along an edge of the second portion of the device definition region. A second conductive pillar and a third conductive pillar are formed in the second portion, the second conductive pillar and the third conductive pillar being separated from each other. [Brief description of the drawings]

[0006] [Figure 1A] 1 illustrates an exemplary semiconductor structure and its DRAM structure. [Figure 1B] 1 illustrates an exemplary semiconductor structure and its DRAM structure. [Figure 1C] 1 illustrates an exemplary semiconductor structure and its DRAM structure.

[0007] [Diagram 2] 2 illustrates another exemplary semiconductor structure and its DRAM structure.

[0008] [Diagram 3] 2 illustrates yet another exemplary semiconductor structure, and its DRAM structure.

[0009] [Figure 4] Further exemplary semiconductor structures and their DRAM structures are shown.

[0010] [Figure 5A] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5B]1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5C] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5D] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5E] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5F] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5G] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5H] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5I] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5J] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5K] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5L] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure. [Figure 5M] 1 illustrates various stages of an exemplary method for fabricating a semiconductor structure.

[0011] In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form to simplify the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Various embodiments will now be described in more detail with reference to the accompanying drawings. The description and drawings are merely for illustrative purposes and are not intended to be limiting. For clarity, elements may not be drawn to scale. Furthermore, some elements and / or reference numbers may be omitted from some drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated in another embodiment without further recitation.

[0013] One aspect of the disclosure is directed to a semiconductor structure. The semiconductor structure has a device definition region. The definition region includes a first portion and a second portion separated from one another. The semiconductor structure comprises a stack. The stack includes a plurality of alternating first conductive layers and a plurality of first dielectric layers. The stack has an opening through the stack in the device definition region. The semiconductor structure further comprises a second conductive layer, a first conductive pillar, a third conductive layer, a second conductive pillar, and a third conductive pillar. The second conductive layer is disposed along a sidewall of the opening. The first conductive pillar is disposed in the opening in the first portion of the device definition region. The third conductive layer is disposed in the opening along an edge of the second portion of the device definition region. The second conductive pillar and the third conductive pillar are disposed in the second portion and are separated from one another.

[0014] 1A-1C show an exemplary semiconductor structure 10 and its DRAM structure 100. FIG. 1A is a top view of the semiconductor structure 10 with the top first dielectric layer 108 removed for clarity. FIG. 1B is a perspective view of the semiconductor structure 10 with some portions of some elements enlarged and some portions of some other elements omitted for clarity. FIG. 1C is an exemplary circuit diagram of a DRAM cell of the DRAM structure 100.

[0015] The semiconductor structure 10 has a device definition region D. Herein, the device definition region D may be realized as a region of the semiconductor structure 10 in which an electronic device having a 3D structure (such as a DRAM) is formed, and thus may be defined to encompass areas and portions of elements forming the DRAM structure 100. The device definition region D includes a first portion P1 and a second portion P2 that are separated from one another.

[0016] The semiconductor structure 10 may include a substrate 102. Any suitable substrate may be used having any suitable layers disposed thereon, including, but not limited to, circuit layers, interlevel dielectric layers, and the like, without limitation.

[0017] The semiconductor structure 10 comprises a stack 104, which may be disposed on a substrate 102. The stack 104 includes a plurality of first conductive layers 106 and a plurality of first dielectric layers 108 that are alternately arranged. A stacking direction of the stack 104 is substantially perpendicular to the substrate 102 (e.g., Z direction in the drawing). In other words, the first conductive layers 106 and the first dielectric layers 108 are stacked in a stacking direction that is substantially perpendicular to the substrate 102. The stack 104 has an opening O in a device definition region D that passes through the stack 104.

[0018] The semiconductor structure 10 may further include a second dielectric layer 110 disposed on a sidewall of the opening O. The semiconductor structure 10 includes a second conductive layer 112. The second conductive layer 112 is disposed on the second dielectric layer 110. As a result, the second conductive layer 112 may be disposed along the sidewall of the opening O. In the semiconductor structure 10, as shown in FIG. 1B, the second conductive layer 112 extends discontinuously in the stacking direction of the stack 104. More specifically, the second conductive layer 112 may include a plurality of discontinuous portions each corresponding to the first conductive layer 106.

[0019] The semiconductor structure 10 comprises a first conductive pillar 114. The first conductive pillar 114 is disposed in an opening O in a first portion P1 of the device definition region D. In some embodiments, the extent of the first portion P1 is determined substantially according to the first conductive pillar 114, and the first conductive pillar 114 forms an edge of the first portion P1. The first conductive pillar 114 may extend continuously in the stacking direction throughout the stack 104.

[0020] The semiconductor structure 10 may further include a third dielectric layer 116 disposed as the outermost layer of the second portion P2. In such a state, the extent of the second portion P2 is substantially determined according to the third dielectric layer 116, and the third dielectric layer 116 forms the edge of the second portion P2. The semiconductor structure 10 includes a third conductive layer 118. The third conductive layer 118 is disposed on the third dielectric layer 116. As a result, the third conductive layer 118 may be disposed in the opening O along the edge of the second portion P2 of the device definition region D. The third dielectric layer 116 and the third conductive layer 118 may extend continuously in the stacking direction throughout the stack 104.

[0021] The semiconductor structure 10 includes a second conductive pillar 120 and a third conductive pillar 122. The second conductive pillar 120 and the third conductive pillar 122 are disposed in the second portion P2 and are separated from each other. Similar to the first conductive pillar 114, the second conductive pillar 120 and the third conductive pillar 122 may extend continuously in the stacking direction throughout the stack 104.

[0022] The semiconductor structure 10 may further include a first dielectric material 124 that fills the remaining space of the opening O except for the first portion P1 and the second portion P2. The semiconductor structure 10 may further include a second dielectric material 126 that fills the remaining space of the second portion P2.

[0023] According to some embodiments, the semiconductor structure 10 may further comprise a placeholder 128 disposed in a central portion of the device definition region D. The first portion P1 and the second portion P2 are located on two opposite sides of the placeholder 128.

[0024] The DRAM structure 100 is disposed on a substrate 102 and may be composed of the elements described above. For example, the first conductive layer 106, the second conductive layer 112, and the first conductive pillar 114 form a first transistor T1 of the DRAM structure 100, and the second conductive layer 112, the third conductive layer 118, the second conductive pillar 120, and the third conductive pillar 122 form a second transistor T2 of the DRAM structure 100. Specifically, the DRAM structure 100 includes a plurality of DRAM cells. The DRAM cells may be 2T0C cells. In other words, each DRAM cell may be composed of a first transistor T1 and a second transistor T2 without using a capacitor. The corresponding first conductive layer 106, a portion of the second conductive layer 112 corresponding to the corresponding first conductive layer 106, and the first conductive pillar 114 form the first transistor T1. A portion of the second conductive layer 112 corresponding to the corresponding first conductive layer 106, the third conductive layer 118, the second conductive pillar 120, and the third conductive pillar 122 form a second transistor T2. More specifically, the corresponding first conductive layer 106 can form a first terminal t11 of the first transistor T1, the first conductive pillar 114 can form a second terminal t12 of the first transistor T1, and a portion of the second conductive layer 112 corresponding to the corresponding first conductive layer 106 can form a channel and a third terminal t13 of the first transistor T1. A portion of the second conductive layer 112 corresponding to the corresponding first conductive layer 106 can form a first terminal t21 of the second transistor T2, the second conductive pillar 120 can form a second terminal t22 of the second transistor T2, the third conductive pillar 122 can form a third terminal t23 of the second transistor T2, and the third conductive layer 118 can form a channel of the second transistor T2.

[0025] As shown in FIG. 1C, the first transistor T1 may be a write transistor and the second transistor T2 may be a read transistor. The first terminal t11 of the first transistor T1 may be a gate terminal of the first transistor T1 and may be further connected to a write word line WWL in some embodiments. The second terminal t12 of the first transistor T1 may be a drain terminal of the first transistor T1 and may be further connected to a write bit line WBL in some embodiments. The third terminal t13 of the first transistor T1 may be a source terminal of the first transistor T1 and may be connected to a first terminal t21 of the second transistor T2. The first terminal t21 of the second transistor T2 may be a gate terminal of the second transistor T2. A storage node SN may be formed between the third terminal t13 of the first transistor T1 and the first terminal t21 of the second transistor T2. The second terminal t22 of the second transistor T2 may be a drain terminal of the second transistor T2 and may be further connected to a read word line RWL in some embodiments. The third terminal t23 of the second transistor T2 may be the source terminal of the second transistor T2, and in some embodiments may be further connected to a read bit line RBL.

[0026] A specific example of the operation of the nth DRAM cell is provided here and listed in Table 1 for further understanding, but the present disclosure is not limited thereto. To program a logic state "1", a voltage V WWLn can be applied from the corresponding n-th write word line WWL, turning on the outer channel of the write transistor. WBL Since the potential of the read bit line RBL and the read word line RWL can be set to −2V to 0V, the storage node SN is discharged to −2V to 0V. -11 Read current I smaller than A (1E-11A) read The read current I readcan enter the DRAM cell from the read bit line RBL, and the read word line RWL can be grounded. To hold a logic "1" state, a voltage V WWLn The read bit line RBL and the read word line RWL are still at 10 V. The write transistor is turned off. The storage node SN is still at -2 V to 0 V. -11 Read current I smaller than A (1E-11A) read To program the logic state "0", a voltage V between -1V and 5V is required. WWLn Then, to charge the storage node SN to 1V to 3V, a voltage V WBL In such a state, the read bit line RBL and the read word line RWL may be set to 10 -9 Read current I greater than A (1E-9A) read To hold the logic state "0", the voltage V WWLn The read bit line RBL and the read word line RWL are still at 10 V to 3 V, and the write transistor is turned off. The storage node SN is still at 1 V to 3 V. -9 Read current I greater than A (1E-9A) read Read out. [Table 1]

[0027] The first transistor T1 and the second transistor T2 can be IGZO transistors. The cut-off current of IGZO transistors is low, which is beneficial for enhancing the data retention capability of the memory cell. Moreover, compared to other types of transistors, the corresponding BEOL electronic components of IGZO transistors require less space. The stacked DRAM structure of the present disclosure can be used to provide a high density 3D DRAM device.

[0028] According to some embodiments, the corresponding first conductive layer 106 can further function as a write word line WWL. According to some embodiments, the first conductive pillar 114 can further function as a write bit line WBL. According to some embodiments, the second conductive pillar 120 can further function as a read word line RWL. According to some embodiments, the third conductive pillar 122 can further function as a read bit line RBL.

[0029] As described above, the first conductive layer 106, the second conductive layer 112, the first conductive pillar 114, the third conductive layer 118, the second conductive pillar 120, and the third conductive pillar 122 form the first transistor T1 and the second transistor T2 of the DRAM structure 100. As a result, a device definition region D may be defined to encompass at least a portion of the first conductive layer 106 proximate the second conductive layer 112, the second conductive layer 112, the first conductive pillar 114, the third conductive layer 118, the second conductive pillar 120, and the third conductive pillar 122. It should be understood that in addition to the above-mentioned elements, the DRAM cell may be realized to include other elements, such as the second dielectric layer 110, the third dielectric layer 116, the first dielectric material 124, the second dielectric material 126, the placeholder 128, and / or any other suitable elements. For example, the second dielectric layer 110 and the third dielectric layer 116 may function as gate dielectric layers for the first transistor T1 and the second transistor T2, respectively.

[0030] FIG. 2 shows another exemplary semiconductor structure 10A and its DRAM structure 100A. FIG. 2 is a perspective view of the semiconductor structure 10A, in which some parts of some elements are enlarged and some parts of some other elements are omitted for clarity. The DRAM structure 100A differs from the DRAM structure 100 in that the second dielectric layer 110A and the second conductive layer 112A extend continuously in the stacking direction of the stack 104. They may further extend over the entire first dielectric layer 108. Other details of the semiconductor structure 10A are similar to those of the semiconductor structure 10 and will not be repeated here.

[0031] 3 shows yet another exemplary semiconductor structure 10B and its DRAM structure 100B. FIG. 3 shows a top view of the semiconductor structure 10B, in which the top first dielectric layer 108 has been removed for clarity. The DRAM structure 100B differs from the DRAM structure 100 in that the DRAM structure 100B does not include a placeholder 128. Other details of the semiconductor structure 10B are similar to those of the semiconductor structure 10 and will not be repeated here.

[0032] FIG. 4 shows a further exemplary semiconductor structure 10C and its DRAM structure 100. FIG. 4 shows a top view of the semiconductor structure 10C, in which the top first dielectric layer 108 has been removed for clarity. The semiconductor structure 10C differs from the semiconductor structure 10 in that the semiconductor structure 10C includes a plurality of DRAM structures 100 arranged on a substrate 102. The DRAM structures 100 share a common stack 104. The DRAM structures 100 may be arranged in a staggered manner, although the disclosure is not limited thereto. Other details of the semiconductor structure 10C are similar to those of the semiconductor structure 10 and will not be repeated here.

[0033] Another aspect of the disclosure is directed to a method for fabricating a semiconductor structure. The semiconductor structure has a device definition region. The device definition region includes a first portion and a second portion that are separated from one another. The method includes the following steps: First, a stack is formed, the stack including a plurality of alternating first conductive layers and a plurality of first dielectric layers, the stack having an opening through the stack in the device definition region. Then, a second conductive layer is formed along a sidewall of the opening. A first conductive pillar is formed in the opening in the first portion of the device definition region. A third conductive layer is formed in the opening along an edge of the second portion of the device definition region. A second conductive pillar and a third conductive pillar are formed in the second portion, the second conductive pillar and the third conductive pillar being separated from one another.

[0034] 5A-5M, an exemplary method of the present disclosure is shown for use in fabricating a semiconductor structure 10. For clarity, FIGS. 5A-5E show the structure in cross-sectional view and FIGS. 5F-5M show the structure in top view, where the hardmask layer 210 has been removed. FIGS. 5F and 5E show the same stage of the method. In this exemplary method, a sacrificial material replacement process is used to form the stack 104 of the first conductive layer 106 and the first dielectric layer 108, although it should be understood that the present disclosure is not limited in this respect.

[0035] First, as shown in FIG. 5A, a substrate 102 is provided. Any suitable substrate can be used without any particular limitation. Optionally, an interlevel dielectric layer 202 or any other suitable layer can be formed on the substrate 102. The interlevel dielectric layer 202 can be formed of an oxide. An initial stack 204 is formed on the substrate 102 and on the interlevel dielectric layer 202 (if present). The initial stack 204 includes a plurality of layers 206 of a sacrificial material and a plurality of layers 208 of a dielectric material, which are arranged in alternating order. The sacrificial material can be silicon nitride. The dielectric material can be an oxide. According to some embodiments, a hard mask layer 210 can be formed on the initial stack 204. The hard mask layer 210 can be formed of an oxide.

[0036] As shown in Fig. 5B, openings O are formed through the initial stack 204. Optionally, before forming the second dielectric layer 110, the layer of sacrificial material 206 can be recessed from the openings O, as shown in Fig. 5C. As a result, a number of recesses P of the layer of sacrificial material 206 are formed. The recession process may be performed by wet etching using H3PO4 as an etchant or by reactive ion etching.

[0037] As shown in FIG. 5D, a second dielectric layer 110 may be formed on the sidewalls of the opening O, and in particular in the recessed portion P. The second dielectric layer 110 may be formed of an oxide. A second conductive layer 112 may be formed on the second dielectric layer 110. As a result, the second conductive layer 112 may be formed along the sidewalls of the opening O. The second conductive layer 112 may be formed of a conductive material. It is noted that in some other embodiments of the manufacture of the semiconductor structure 10A, the second dielectric layer 110A and the second conductive layer 112A may be formed continuously in the stacking direction throughout the initial stack 204 without forming the recessed portion P.

[0038] As shown in Figures 5E and 5F, a first dielectric material 124 is filled into the opening O. The first dielectric material 124 may be an oxide. Optionally, before filling the opening O with the first dielectric material 124, a placeholder 128 may be formed in the center of the device definition region D (shown in Figure 1A). In some embodiments, the formation of the placeholder 128 is useful for positioning components to be formed in subsequent steps, in particular those to be formed in the first and second portions P1 and P2 of the device definition region D. The placeholder 128 may be formed of silicon nitride.

[0039] As shown in FIG. 5G, a first conductive pillar 114 is formed in the opening O of the first portion P1 of the device definition region D. More specifically, the first conductive pillar 114 is formed in the first portion P1 through the first dielectric material 124. In some embodiments, the extent of the first portion P1 is determined substantially according to the first conductive pillar 114, and the first conductive pillar 114 forms an edge of the first portion P1. The first conductive pillar 114 may extend continuously in the stacking direction throughout the initial stack 204. The first conductive pillar 114 may be formed of N+ polysilicon.

[0040] 5H, a hole H is formed through the first dielectric material 124 of the second portion P2 of the device definition region D. In some embodiments, the extent of the second portion P2 is determined substantially according to the third dielectric layer 116 to be formed in a subsequent step, and the hole H is formed by removing all of the first dielectric material 124 of the second portion P2. The hole H may be formed by reactive ion etching that is highly selective to the conductive material of the second conductive layer 112.

[0041] As shown in FIG. 5I, a third dielectric layer 116 may be formed on the sidewall of the hole H. The third dielectric layer 116 may form an edge of the second portion P2 of the device definition region D. The third dielectric layer 116 may be formed of an oxide. As shown in FIG. 5J, a third conductive layer 118 may be formed on the third dielectric layer 116. As a result, the third conductive layer 118 may be formed in the opening O along the edge of the second portion P2 of the device definition region D. The third conductive layer 118 may be formed of a conductive material.

[0042] Then, as shown in Figure 5K, the hole H is filled with a second dielectric material 126. The second dielectric material 126 can be an oxide. The second dielectric material 126 and the first dielectric material 124 can be the same.

[0043] As shown in FIG. 5L, a second conductive pillar 120 and a third conductive pillar 122 are formed in the second portion P2. The second conductive pillar 120 and the third conductive pillar 122 are separated from each other. The second conductive pillar 120 and the third conductive pillar 122 may be formed through the second dielectric material 126. More specifically, the second conductive pillar 120 and the third conductive pillar 122 may extend continuously in the stacking direction throughout the initial stack 204. The second conductive pillar 120 and the third conductive pillar 122 may be formed of N+ polysilicon.

[0044] 5M, the sacrificial material of the initial stack 204 may be replaced with a conductive material to form the stack 104. Thus, the stack 104 is formed, which includes a plurality of first conductive layers 106 and a plurality of first dielectric layers 108 arranged in an alternating manner.

[0045] As a result, the semiconductor structure 10 is thus formed. According to some embodiments, the first conductive layer 106, the second conductive layer 112, and the first conductive pillar 114 form a first transistor T1 of the DRAM structure 100, and the second conductive layer 112, the third conductive layer 118, the second conductive pillar 120, and the third conductive pillar 122 form a second transistor of the DRAM structure 100. More specifically, the DRAM structure 100 may include a plurality of DRAM cells, each DRAM cell being composed of a first transistor T1 and a second transistor T2. The corresponding first conductive layer 106, a portion of the second conductive layer 112 corresponding to the corresponding first conductive layer 106, and the first conductive pillar 114 form the first transistor T1. The portion of the second conductive layer 112 corresponding to the corresponding first conductive layer 106, the third conductive layer 118, the second conductive pillar 120, and the third conductive pillar 122 form the second transistor T2. In some embodiments, the corresponding first conductive layer 106 forms the first terminal t11 of the first transistor T1, the first conductive pillar 114 forms the second terminal t12 of the first transistor T1, a portion of the second conductive layer 112 corresponding to the corresponding first conductive layer 106 forms the channel and third terminal t13 of the first transistor T1, a portion of the second conductive layer 112 corresponding to the corresponding first conductive layer 106 forms the first terminal t21 of the second transistor T2, the second conductive pillar 120 forms the second terminal t22 of the second transistor T2, the third conductive pillar 122 forms the third terminal t23 of the second transistor T2, and the third conductive layer 118 forms the channel of the second transistor T2. In some embodiments, the corresponding first conductive layer 106 further functions as a write word line WWL, the first conductive pillar 114 further functions as a write bit line WBL, the second conductive pillar 120 further functions as a read word line RWL, and the third conductive pillar 122 further functions as a read bit line RBL. Other details of the semiconductor structure 10 have been described above and will not be repeated here.

[0046] As such, the semiconductor structure according to the present disclosure may be formed in a manufacturing process in which the DRAM cells of the 3D DRAM structure are all formed in the same process, rather than fabricated layer by layer, and such a manufacturing process is also known as a bit cost scalable process, and its cost is reduced compared to conventional 3D semiconductor processes.

[0047] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.

Claims

1. 1. A semiconductor structure having a device definition region, the device definition region including a first portion and a second portion separated from one another, the semiconductor structure comprising: a stack including a plurality of alternating first conductive layers and a plurality of first dielectric layers, said stack having an opening therethrough in said device defining region; a second conductive layer disposed along a sidewall of the opening; a first conductive pillar disposed in the opening in the first portion of the device definition region; a third conductive layer disposed in the opening along an edge of the second portion of the device definition region; a second conductive pillar and a third conductive pillar disposed in the second portion and separated from each other; a second dielectric layer disposed on the sidewalls of the opening, wherein the second conductive layer is disposed on the second dielectric layer; a third dielectric layer disposed as an outermost layer of the second portion, wherein the third conductive layer is disposed on the third dielectric layer; and DRAM structure Equipped with the first portion of the device definition area is on a first side of the device definition area, the first portion being adjacent to the second conductive layer; the plurality of first conductive layers, the second conductive layer, and the first conductive pillar form a first transistor of the DRAM structure, and the second conductive layer, the third conductive layer, the second conductive pillar, and the third conductive pillar form a second transistor of the DRAM structure; the DRAM structure includes a plurality of DRAM cells, each DRAM cell being comprised of a first transistor and a second transistor, a corresponding first conductive layer, a portion of the second conductive layer corresponding to the corresponding first conductive layer, and the first conductive pillar forming the first transistor, and the portion of the second conductive layer corresponding to the corresponding first conductive layer, the third conductive layer, the second conductive pillar, and the third conductive pillar forming the second transistor; the corresponding first conductive layer forms a first terminal of the first transistor, the first conductive pillar forms a second terminal of the first transistor, the portion of the second conductive layer corresponding to the corresponding first conductive layer forms a channel and a third terminal of the first transistor, the portion of the second conductive layer corresponding to the corresponding first conductive layer forms a first terminal of the second transistor, the second conductive pillar forms a second terminal of the second transistor, the third conductive pillar forms a third terminal of the second transistor, and the third conductive layer forms a channel of the second transistor; the first terminal of the first transistor is a gate terminal of the first transistor, the second terminal of the first transistor is a drain terminal of the first transistor, the third terminal of the first transistor is a source terminal of the first transistor, the first terminal of the second transistor is a gate terminal of the second transistor, the second terminal of the second transistor is a drain terminal of the second transistor, and the third terminal of the second transistor is a source terminal of the second transistor; the first transistor is a write transistor and the second transistor is a read transistor; The second portion of the device definition area is on a second side of the device definition area opposite the first side, the second portion being adjacent to the second conductive layer. Semiconductor structure.

2. a first dielectric material filling a remaining volume of the opening except for the first portion and the second portion; and a second dielectric material filling the remaining space in the second portion; 10. The semiconductor structure of claim 1 further comprising:

3. a placeholder disposed in a central portion of the device definition area, wherein the first portion and the second portion are located on two opposite sides of the placeholder.

10. The semiconductor structure of claim 1 further comprising:

4. 2. The semiconductor structure of claim 1 wherein said second conductive layer extends discontinuously in a stacking direction of said stack.

5. 2. The semiconductor structure of claim 1 wherein said second conductive layer extends continuously in a stacking direction of said stack.

6. The semiconductor structure comprising a substrate, The DRAM structure is disposed on the substrate.

10. The semiconductor structure of claim 1.

7. 2. The semiconductor structure of claim 1 , wherein the corresponding first conductive layer further functions as a write word line, the first conductive pillar further functions as a write bit line, the second conductive pillar further functions as a read word line, and the third conductive pillar further functions as a read bit line.

8. a plurality of said DRAM structures disposed on said substrate, wherein said plurality of DRAM structures share a common stack; 7. The semiconductor structure of claim 6 comprising:

9. 1. A method for fabricating a semiconductor structure, the semiconductor structure having a device definition region, the device definition region including a first portion and a second portion separated from one another, the method comprising: forming a stack including a plurality of alternating first conductive layers and a plurality of first dielectric layers, said stack having an opening therethrough in said device definition region; forming a second conductive layer along a sidewall of the opening; forming a first conductive pillar in the opening in the first portion of the device definition region; forming a third conductive layer in the opening along an edge of the second portion of the device definition region; forming a second conductive pillar and a third conductive pillar in the second portion, wherein the second conductive pillar and the third conductive pillar are separated from one another; forming an initial stack on a substrate, the initial stack including multiple layers of alternating sacrificial material and multiple layers of dielectric material; forming the opening through the initial stack; forming a second dielectric layer on the sidewalls of the opening; forming the second conductive layer on the second dielectric layer; filling the opening with a first dielectric material; forming a hole through the first dielectric material in the second portion of the device definition area; forming a third dielectric layer on a sidewall of the hole; forming the third conductive layer on the third dielectric layer; filling the hole with a second dielectric material; forming the second conductive pillar and the third conductive pillar through the second dielectric material; and replacing the sacrificial material of the initial stack with a conductive material to form the stack. Equipped with the first portion of the device definition area is on a first side of the device definition area, the first portion being adjacent to the second conductive layer; the plurality of first conductive layers, the second conductive layer, and the first conductive pillar form a first transistor of a DRAM structure, and the second conductive layer, the third conductive layer, the second conductive pillar, and the third conductive pillar form a second transistor of the DRAM structure; the DRAM structure includes a plurality of DRAM cells, each DRAM cell being comprised of a first transistor and a second transistor, a corresponding first conductive layer, a portion of the second conductive layer corresponding to the corresponding first conductive layer, and the first conductive pillar forming the first transistor, and the portion of the second conductive layer corresponding to the corresponding first conductive layer, the third conductive layer, the second conductive pillar, and the third conductive pillar forming the second transistor; the corresponding first conductive layer forms a first terminal of the first transistor, the first conductive pillar forms a second terminal of the first transistor, the portion of the second conductive layer corresponding to the corresponding first conductive layer forms a channel and a third terminal of the first transistor, the portion of the second conductive layer corresponding to the corresponding first conductive layer forms a first terminal of the second transistor, the second conductive pillar forms a second terminal of the second transistor, the third conductive pillar forms a third terminal of the second transistor, and the third conductive layer forms a channel of the second transistor; the corresponding first conductive layer further functions as a write word line, the first conductive pillar further functions as a write bit line, the second conductive pillar further functions as a read word line, and the third conductive pillar further functions as a read bit line; the first terminal of the first transistor is a gate terminal of the first transistor, the second terminal of the first transistor is a drain terminal of the first transistor, the third terminal of the first transistor is a source terminal of the first transistor, the first terminal of the second transistor is a gate terminal of the second transistor, the second terminal of the second transistor is a drain terminal of the second transistor, and the third terminal of the second transistor is a source terminal of the second transistor; the first transistor is a write transistor and the second transistor is a read transistor; The second portion of the device definition area is on a second side of the device definition area opposite the first side, the second portion being adjacent to the second conductive layer. method.

10. recessing the layers of the sacrificial material from the openings prior to forming the second dielectric layer. The method of claim 9 further comprising:

11. forming a placeholder in a central portion of the device definition area prior to filling the opening with the first dielectric material. The method of claim 9 further comprising:

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