Circuit device and oscillator

Abstract

To provide a circuit device that can improve the accuracy of temperature compensation and reduce the size of a circuit.SOLUTION: A circuit device 100 includes: an oscillation circuit 160 that generates an oscillation signal by using a vibrator 10; a frequency adjustment circuit 150 that adjusts the oscillatory frequency of the oscillation circuit 160 based on pieces of frequency adjustment data CLa, CLb; a temperature sensor circuit 110 that outputs temperature data TD[11:0]; a storage circuit 130; and a frequency adjustment data operation circuit 140. The storage circuit 130 stores the n-th order differential value of the frequency adjustment data and an initial value of the 0 to n-1-th order differential, and outputs the n-th order differential value and the initial value based on the temperature data TD[11:0]. n is an integer of 1 or more. The frequency adjustment data operation circuit 140 performs addition processing of the n-th order differential value and the initial value output from the storage circuit 130 to output frequency adjustment data CLa, CLb corresponding to the temperature data TD[11:0].SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a circuit device, an oscillator, and the like. [Background technology]

[0002] Patent Document 1 discloses a temperature-compensated oscillator circuit that includes a temperature measurement unit that outputs the temperature measurement result as a digital signal, a counter that outputs the upper bits of the digital signal as an address value, a memory unit that outputs a correction value corresponding to the address value, and a capacitance array that adjusts the oscillation frequency by being set to a capacitance value corresponding to the correction value. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-67675 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the invention described in Patent Document 1, the data capacity of the correction value is determined by the number of bits of the correction value and the number of addresses that store the correction value. Therefore, if the number of bits or addresses of the correction value is increased to perform high-precision temperature compensation, the memory capacity of the memory unit must be increased, and the circuit area increases. On the other hand, if the memory capacity of the memory unit is reduced to reduce the size, the number of bits or addresses of the correction value must be reduced, and the accuracy of the temperature compensation decreases. Thus, Patent Document 1 has an issue in that it is difficult to achieve both high precision temperature compensation and small circuit size. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including an oscillation circuit that generates an oscillation signal using a vibrator, a frequency adjustment circuit that adjusts an oscillation frequency of the oscillation circuit based on frequency adjustment data, a temperature sensor circuit that outputs temperature data, a memory circuit that stores an n-th order differential value (n is an integer equal to or greater than 1) of the frequency adjustment data and an initial value of a 0th to n-1th order differential, and outputs the n-th order differential value and the initial value based on the temperature data, and a frequency adjustment data calculation circuit that outputs the frequency adjustment data corresponding to the temperature data by performing an addition process of the n-th order differential value output by the memory circuit and the initial value.

[0006] Another aspect of the present disclosure relates to an oscillator including the circuit device described above and the resonator. [Brief description of the drawings]

[0007] [Figure 1] An example of the characteristics of frequency adjustment data against temperature data. [Diagram 2] 1 shows an example of an oscillator configuration and a first example of a circuit device. [Diagram 3] An example of the characteristics of the 0th order differential value, 1st order differential value, and 2nd order differential value of frequency adjustment data against temperature data. [Figure 4] FIG. 1 is a diagram illustrating a data set stored in a lookup table. [Diagram 5] Data set for n=2. [Figure 6] 1 shows an example of the configuration of a frequency adjustment data calculation circuit. [Figure 7] Data set for n=3. [Figure 8] 2 shows a second configuration example of a circuit device. [Figure 9] An example of the process of converting temperature data to converted temperature data. [Figure 10] An example of the characteristics of the 0th order differential value, the 1st order differential value, and the 2nd order differential value of the frequency adjustment data with respect to the converted temperature data. [Figure 11] 1 shows an example of a temperature data calculation circuit configuration. [Figure 12] A detailed configuration example of the start point setting circuit and multiplication circuit. [Figure 13] 1 shows a detailed configuration example of an adjustment circuit and a connection configuration example of a vibrator, an oscillation circuit, and an adjustment circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0009] 1. Oscillators and circuit devices Fig. 1 shows an example of the characteristics of frequency adjustment data with respect to temperature data. The horizontal axis is the temperature data output by the temperature sensor circuit, and the vertical axis is the frequency adjustment data for adjusting the capacitance value of the variable capacitance circuit connected to the oscillation circuit. Here, an example is described in which the vibrator has a quadratic temperature characteristic with respect to temperature, but the temperature characteristic of the vibrator is not limited to quadratic.

[0010] Since the resonator has quadratic temperature characteristics that are upwardly convex, the characteristics of the frequency adjustment data with respect to the temperature data are quadratic characteristics that are upwardly convex. Although the characteristics of the frequency adjustment data with respect to the temperature data are slightly deformed from the quadratic characteristics due to the nonlinearity of the temperature sensor circuit, the variable capacitance circuit, and the oscillation circuit, they mainly have quadratic characteristics.

[0011] The change range of the frequency adjustment data is 2 10 Greater than 2 11In this case, 11 bits are required as the number of bits of the frequency adjustment data. Here, consider an example in which the oscillator performs temperature compensation using a lookup table. That is, the oscillator stores a lookup table in which frequency adjustment data is stored at each address of the memory, and performs temperature compensation using the frequency adjustment data at the address specified by the temperature data. In this method, the value obtained by multiplying the number of addresses by the number of bits of the frequency adjustment data is the memory capacity required to store the frequency adjustment data. In the example of Figure 1, for example, if frequency adjustment data is stored at 128 addresses, a memory capacity of 128 x 11 bits = 1.4k bits is required.

[0012] Since the accuracy of temperature compensation is determined by the number of addresses and the number of bits of the frequency adjustment data, increasing the accuracy of temperature compensation increases the memory circuit area, while reducing the memory circuit area decreases the accuracy of temperature compensation. In other words, there is a problem in that it is difficult to achieve both high accuracy of temperature compensation and miniaturization of the circuit in temperature compensation using a lookup table.

[0013] 2 shows a configuration example of an oscillator 200 according to this embodiment and a first configuration example of the circuit device 100. The oscillator 200 includes a resonator 10 and the circuit device 100.

[0014] The vibrator 10 is an element that generates mechanical vibration by an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 is a tuning fork type quartz crystal vibrating piece. Alternatively, the vibrator 10 can be realized by a quartz crystal vibrating piece that has a cut angle of AT cut or SC cut, etc., that vibrates in a thickness shear manner. The vibrator 10 of this embodiment can be realized by various vibrating pieces such as a vibrating piece other than a tuning fork type or a thickness shear vibration type, or a piezoelectric vibrating piece formed of a material other than quartz. For example, the vibrator 10 may be a SAW resonator or a MEMS vibrator as a silicon vibrator formed using a silicon substrate. SAW is an abbreviation for Surface Acoustic Wave, and MEMS is an abbreviation for Micro Electro Mechanical Systems.

[0015] The circuit device 100 is electrically connected to the vibrator 10, and drives the vibrator 10 to oscillate the vibrator 10. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be a connection via a passive element or an active element. The circuit device 100 also performs a temperature compensation process that keeps the oscillation frequency of the oscillator 200 constant regardless of temperature. The circuit device 100 is an integrated circuit device known as an IC. The circuit device 100 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate.

[0016] The circuit device 100 includes a temperature sensor circuit 110, a memory circuit 130, a frequency adjustment data calculation circuit 140, a frequency adjustment circuit 150, and an oscillation circuit 160. Note that this embodiment is not limited to the configuration of FIG. 2, and various modifications such as omitting some of the components or adding other components are possible. For example, the interpolation circuit 152 of the frequency adjustment circuit 150 may be omitted. Alternatively, the number of bits of TD[11:0], TD[11:9], TD[8:5], and TD[4:0] shown in FIG. 2 is an example, and may be TD[p:0], TD[p-1:q], TD[q-1:r], and TD[r-1:0]. r is an integer equal to or greater than 1, q is an integer equal to or greater than r+1, and p is an integer equal to or greater than q+1.

[0017] The temperature sensor circuit 110 measures the environmental temperature of the resonator 10 and outputs the result as temperature data TD[11:0]. The temperature data TD[11:0] is data that increases monotonically with respect to temperature in the operating temperature range of the circuit device 100. The temperature data TD[11:0] may be data that decreases monotonically with respect to temperature. The temperature sensor circuit 110 is, for example, a temperature sensor that utilizes the fact that the oscillation frequency of a ring oscillator has temperature dependency. In this case, the temperature sensor circuit 110 includes a ring oscillator and a counter. The counter counts the oscillation signal of the ring oscillator during an enable period defined by the clock signal CLK output by the oscillation circuit 160, and outputs the count value as the temperature data TD[11:0]. However, the temperature sensor circuit 110 is not limited to this, and may include, for example, an analog temperature sensor that outputs a temperature detection voltage by utilizing the fact that the forward voltage of a PN junction has temperature dependency, and an A / D converter that A / D converts the temperature detection voltage and outputs the temperature data TD[11:0].

[0018] The storage circuit 130 stores a lookup table 131. Eight data sets are stored in the lookup table 131, and in each data set, an n-th order differential value of the frequency adjustment data and an initial value of the 0th to n-1th order differential are stored. n is an integer equal to or greater than 1. The storage circuit 130 outputs a data set QLUT designated by the upper bits TD[11:9] of the temperature data among the eight data sets. This will be described in detail later with reference to FIG. 4. The storage circuit 130 is, for example, a semiconductor memory such as a non-volatile memory or a RAM, or a register configured with a latch circuit or the like. The non-volatile memory is, for example, an OTP memory such as a FAMOS memory, but is not limited thereto, and may be an EEPROM such as a MONOS memory or a fuse-type ROM. FAMOS is an abbreviation for Floating gate Avalanche injection Metal Oxide Semiconductor. MONOS is an abbreviation for Metal-Oxide-Nitride-Oxide-Silicon.

[0019] The frequency adjustment data calculation circuit 140 restores the frequency adjustment data CLa and CLb using the n-th order differential value of the frequency adjustment data included in the data set QLUT and the initial value of the 0th to n-1th order differential. CLa is the frequency adjustment data specified by the middle bit TD[8:5] of the temperature data, and CLb is the frequency adjustment data specified by TD[8:5]+1. Details of this will be described later with reference to Figs. 5 and 6. The frequency adjustment data calculation circuit 140 is composed of a logic circuit.

[0020] The frequency adjustment circuit 150 adjusts the oscillation frequency of the oscillation circuit 160 based on the least significant bits TD[4:0] of the temperature data and the frequency adjustment data CLa, CLb.

[0021] The interpolation circuit 152 outputs the adjustment data QCL by interpolating between the frequency adjustment data CLa and the frequency adjustment data CLb based on the lower bits TD[4:0] of the temperature data. The adjustment circuit 154 is connected to the oscillation circuit 160, and adjusts the oscillation frequency of the oscillation circuit to an oscillation frequency corresponding to the adjustment data QCL. The frequency adjustment data is data that reduces the temperature dependency of the oscillation frequency of the oscillation circuit 160 and the vibrator 10, and the oscillation frequency is adjusted using the frequency adjustment data, so that the oscillation frequency becomes constant regardless of the temperature. The interpolation circuit 152 is composed of a logic circuit. The frequency adjustment data calculation circuit 140 and the interpolation circuit 152 may be composed of separate logic circuits, or may be composed of a time-division processing of a DSP. DSP is an abbreviation for Digital Signal Processor.

[0022] As described below, the adjustment circuit 154 is a capacitor array circuit connected to one end or the other end of the vibrator 10. Alternatively, the adjustment circuit 154 may include a D / A converter that performs D / A conversion on the adjustment data QCL, and a variable capacitor connected to one end or the other end of the vibrator 10. The capacitance value of the variable capacitor is controlled according to the output voltage of the D / A converter.

[0023] The oscillator circuit 160 generates an oscillation signal using the oscillator 10. Specifically, the oscillator circuit 160 drives the oscillator 10 to oscillate the oscillator 10, and generates an oscillation signal by the oscillation. An example of the oscillator circuit 160 is a Colpitts type oscillator circuit described later, but is not limited to this. Various types of oscillator circuits may be used as long as the oscillation frequency can be adjusted by the frequency adjustment circuit 150. The clock signal CLK is output based on the oscillation signal. For example, the oscillator circuit 160 may output the oscillation signal as the clock signal CLK, or the circuit device 100 may include an output circuit that outputs the clock signal CLK by buffering or dividing the oscillation signal.

[0024] 2.Look-up table and frequency adjustment data calculation circuit FIG. 3 shows an example of the characteristics of the 0th order differential value, the 1st order differential value, and the 2nd order differential value of the frequency adjustment data with respect to the temperature data. The 0th order differential value is the frequency adjustment data itself. As shown in the upper part of FIG. 3, the frequency adjustment data has the same temperature characteristics as FIG. 1.

[0025] The first-order differential value shown in the middle of Figure 3 is the first-order differential value of the frequency adjustment data with the temperature data as a variable. Specifically, the frequency adjustment data is 128 discrete data corresponding to the 7-bit TD[11:5]. The first-order differential value is the first-order difference value, that is, the difference value between adjacent frequency adjustment data. The range of change of the first-order differential value in the temperature range where temperature compensation is performed is 2. 8 Since the number of bits of the first-order differential value is 8 bits, the amount of data is reduced compared to the 11-bit frequency adjustment data.

[0026] The second-order differential value shown in the lower part of Fig. 3 is a value obtained by second-order differentiation of the frequency adjustment data with the temperature data as a variable. Specifically, the second-order differential value is a second-order difference value, that is, a difference value between adjacent first-order differential values. In the temperature range in which temperature compensation is performed, the change range of the second-order differential value is 2 5The second-order differential value has a bit count of 5 bits, so the amount of data is further reduced compared to the 8-bit first-order differential value. If the frequency adjustment data has ideal second-order temperature characteristics, the second-order differential value becomes a second-order coefficient of a second-order polynomial that approximates the temperature characteristics. In other words, the second-order differential value becomes a constant that does not fluctuate, and can be expressed with a very small amount of data. As described above, although the frequency adjustment data does not have ideal second-order temperature characteristics, the main component is a second-order characteristic, so the amount of data can be significantly reduced by using the second-order differential value. The details will be described later, but the data amount of the second-order differential value is compressed to about half of the data amount of the frequency adjustment data.

[0027] 4 is a diagram for explaining the data sets stored in the lookup table 131. TD[11:5]=0 to 127 is divided into eight regions 0 to 15, 16 to 31, ..., 112 to 127, and data sets 1, 2, ..., 8 are stored correspondingly. The data set to be read is specified by TD[11:9]. That is, when TD[11:9]=0, 1, ..., 7 is input, the memory circuit 130 outputs data sets 1, 2, 3, ..., 8 as data set QLUT.

[0028] As shown in Fig. 5, initial values ​​of 0th to n-1th order differentials of frequency adjustment data and nth order differential values ​​are stored in one data set. In the table of Fig. 5, hatched data is data that is actually stored in lookup table 131. In Fig. 5, n=2, and one data set stores one initial value CL1 of the 0th order differential, one initial value DCL1 of the 1st order differential, and 15 second order differential values ​​DDCL1 to DDCL15.

[0029] CL1 to CL16 are frequency adjustment data corresponding to TD[8:5]=0 to 15, and CL17 is the same value as the frequency adjustment data corresponding to TD[8:5]=0 in the next data set. The first-order differential value is the difference of the frequency adjustment data as described above, and DCL1=CL2-CL1, DCL2=CL3-CL2, . . . , DCL16=CL17-CL16. The second-order differential value is the difference of the first-order differential value as described above, and DDCL1=DCL2-DCL1, DDCL2=DCL3-DCL2, . . . , DDCL15=DCL16-DCL15.

[0030] For example, when the oscillator is manufactured, the frequency adjustment data CL1 to CL17 are measured, and the initial value DCL1 of the first differential and the second differential values ​​DDCL1 to DDCL15 are calculated from the frequency adjustment data CL1 to CL17 and written in the storage circuit 130 in advance.

[0031] The amount of data per data set is 11 bits + 8 bits + 5 bits x 15 = 94 bits, so the amount of data in the entire lookup table is 94 bits x 8 = 0.75k bits. If the frequency adjustment data was stored as is, a memory capacity of 1.4k bits would be required, so by using this embodiment, the memory capacity is reduced to about 0.75k / 1.4k x 100% = 54%.

[0032] 6 shows an example of the configuration of the frequency adjustment data calculation circuit 140. The frequency adjustment data calculation circuit 140 includes delay elements FF1 to FF3, adders AD1 and AD2, and a latch circuit LA. Note that k is an integer between 1 and 16.

[0033] The frequency adjustment data calculation circuit 140 sets DDCL1, DCL1, and CL1 as initial values ​​for delay elements FF1, FF2, and FF3. The adder AD1 adds the output of delay element FF1 to the output of delay element FF2, and the adder AD2 adds the output of delay element FF2 to the output of delay element FF3. With the above initial values ​​set, k=1, the adder AD1 outputs DCL1+DDCL1=DCL1+(DCL2-DCL1)=DCL2, and the adder AD2 outputs CL1+DCL1=CL1+(CL2-CL1)=CL2.

[0034] The delay element FF1 receives DDCL2 read from the look-up table 131. The delay element FF2 receives DCL2 from the adder AD1, and the delay element FF3 receives CL2 from the adder AD2. When one clock advances, k=2, and DDCL2, DCL2, and CL2 are set in the delay elements FF1, FF2, and FF3. The adder AD1 outputs DCL2+DDCL2=DCL2+(DCL3-DCL2)=DCL3, and the adder AD2 outputs CL2+DCL2=CL2+(CL3-CL2)=CL3. After this, when the same process is repeated for 14 clocks, the delay element FF3 sequentially outputs CL4, CL5,...,CL17 when k=4, 5,...,17.

[0035] The latch circuit LA latches the frequency adjustment data CLa, CLb specified by TD[8:5] among CL1 to CL17 output by the delay element FF3. Specifically, when TD[8:5]=0, the latch circuit LA latches CLa=CL1, CLb=CL2. Similarly, when TD[8:5]=1 to 15, the latch circuit LA latches CLa=CL2 to 16, CLb=CL3 to 17.

[0036] Since the calculation is completed in 16 clocks, the adders AD1 and AD2 perform the addition calculation 16×2=32 times. Suppose that TD[11:5]=0 to 127 is not divided into 8 regions, and one data set is prepared for TD[11:5]=0 to 127. In this case, 128×2=256 calculations are required. In this embodiment, TD[11:5]=0 to 127 is divided into 8 regions and 8 data sets are prepared, so that the number of calculations is significantly reduced. As a result, the restoration process required by using the second-order differential value can be realized with as little power consumption as possible.

[0037] 5 and 6, second-order differential values ​​are used in accordance with the second-order temperature characteristics of the vibrator, but n-th order differential values ​​may be used when the order of the temperature characteristics of the vibrator is n. n may be an integer equal to or greater than 2. FIG. 7 shows a data set in the case of n=3 as an example. One data set stores one zeroth order differential initial value CL1, one first order differential initial value DCL1, one second order differential initial value DDCL1, and 14 third order differential values ​​DDDCL1 to DDDCL14.

[0038] The third-order differential value is the difference between adjacent second-order differential values, and DDDCL1 = DDCL2 - DDCL1, DDDCL2 = DDCL3 - DDCL2, ..., DDDCL14 = DDCL15 - DDCL14.

[0039] The configuration of frequency adjustment data calculation circuit 140 is similar to the configuration in Fig. 6. Specifically, a delay element that holds DDDCLk and an adder that calculates DDDCLk+DDCLk=DDCLk+1 are added to the front stage of Fig. 6. The number of additions is 16 x 3 = 48 times. This is a significant reduction in the number of calculations compared to the number of additions, 128 x 3 = 384 times, when TD[11:5] = 0 to 127 is not divided into 8 regions.

[0040] In the above embodiment, the circuit device 100 includes an oscillation circuit 160 that generates an oscillation signal using the resonator 10, a frequency adjustment circuit 150 that adjusts the oscillation frequency of the oscillation circuit 160 based on frequency adjustment data CLa, CLb, a temperature sensor circuit 110 that outputs temperature data TD[11:0], a memory circuit 130, and a frequency adjustment data calculation circuit 140. The memory circuit 130 stores an n-th order differential value of the frequency adjustment data and an initial value of the 0th to n-1th order differential, and outputs the n-th order differential value and the initial value based on the temperature data TD[11:0]. n is an integer equal to or greater than 1. The frequency adjustment data calculation circuit 140 performs an addition process between the n-th order differential value output by the memory circuit 130 and the initial value, thereby outputting frequency adjustment data CLa, CLb corresponding to the temperature data TD[11:0].

[0041] Note that "the storage circuit outputs the n-th order differential value and the initial value based on the temperature data" is not limited to the case where the storage circuit 130 directly references the temperature data and outputs the n-th order differential value and the initial value as shown in Fig. 2. As will be described later in Fig. 8, some conversion process may be performed on the temperature data, and the storage circuit 130 may output the n-th order differential value and the initial value by reference to the converted temperature data.

[0042] According to this embodiment, the n-th order differential value of the frequency adjustment data and the initial value of the 0th to n-1th order differentials are stored in the storage circuit 130, and the frequency adjustment data CLa, CLb corresponding to the temperature data TD[11:0] are restored based on them. As described in FIG. 3, the n-th order differential value is data with a smaller number of bits than the frequency adjustment data itself, so the memory capacity of the lookup table is reduced by using the n-th order differential value compared to the case where the frequency adjustment data is stored as it is as a lookup table. In addition, when the memory capacity is maintained and the stored contents of the lookup table are changed to the n-th order differential value, the number of bits or the number of data of the frequency adjustment data that can be restored increases, so that the accuracy of the temperature compensation can be improved. In this way, according to this embodiment, it is possible to achieve both high accuracy of the temperature compensation and miniaturization of the circuit.

[0043] In this embodiment, the vibrator 10 has an n-th order frequency temperature characteristic.

[0044] If the frequency adjustment data has ideal n-th order temperature characteristics, the n-th order differential value becomes the n-th order coefficient of an n-th order polynomial that approximates the temperature characteristics. In other words, the n-th order differential value becomes a constant that does not fluctuate, making it possible to express it with a very small amount of data. Although the frequency adjustment data does not actually have ideal n-th order temperature characteristics due to the nonlinearity of the circuit, since the main component is the n-th order characteristic, using the n-th order differential value makes it possible to significantly reduce the amount of data.

[0045] In this embodiment, the number of bits of the nth-order differential value stored in the memory circuit 130 is smaller than the number of bits of the initial value. In the example of Fig. 3, the number of bits of the second-order differential value (5) is smaller than the number of bits of the initial value of the first-order differential (8) and the number of bits of the initial value of the zeroth-order differential (11).

[0046] According to this embodiment, the storage circuit 130 mainly stores n-th order differential values ​​having a relatively small number of bits, and only needs to store initial values ​​for 0 to n-1-th order differential values ​​having a larger number of bits than the n-th order differential values. This allows the amount of data stored in the lookup table to be reduced.

[0047] In this embodiment, the memory circuit 130 stores an n-th order differential value and an initial value for each of the plurality of temperature data ranges. The memory circuit 130 outputs the n-th order differential value and the initial value of the temperature data range to which the temperature data TD[11:0] from the temperature sensor circuit 110 belongs among the plurality of temperature data ranges.

[0048] 4, the multiple temperature data ranges are eight temperature data ranges corresponding to TD[11:9]=0 to 7, specifically, eight temperature data ranges of TD[11:5]=0 to 15, 16 to 31, ..., 112 to 127. The temperature data range to which the temperature data belongs is the temperature data range specified by TD[11:9] among the above eight temperature data ranges.

[0049] As described above, the frequency adjustment data is restored by repeating the addition process, so the number of addition processes is reduced when the temperature data range to be restored is narrower. According to this embodiment, since the n-th order differential value and the initial value are stored for each temperature data range, the frequency adjustment data calculation circuit 140 can restore the frequency adjustment data from the n-th order differential value within each temperature data range. As a result, the number of addition processes is reduced compared to the case where a lookup table is configured without dividing the temperature data ranges, and the frequency adjustment data can be restored with low power consumption.

[0050] In this embodiment, n may be 2. The storage circuit 130 stores an initial value of the zeroth order differential, an initial value of the first order differential, and the first to m-2th second order differential values ​​corresponding to the 1st to mth frequency adjustment data. m is an integer of 3 or more. The frequency adjustment data calculation circuit 140 restores the i-th frequency adjustment data of the 1st to mth frequency adjustment data by performing an addition process using the initial value of the zeroth order differential, the initial value of the first order differential, and the 1st to i-2nd second order differential values ​​of the 1st to m-2th second order differential values. i is an integer of 3 or more and m or less.

[0051] In the example of FIG. 5, m=16, and the memory circuit 130 stores the initial value CL1 of the zeroth order differential, the initial value DCL1 of the first order differential, and the first to fourteenth second order differential values ​​DDCL1 to DDCL14 corresponding to the first to sixteenth frequency adjustment data CL1 to CL16. Note that in the example of FIG. 5, the fifteenth second order differential value DDCL15 is further stored, but if the interpolation process is not performed, the fifteenth second order differential value DDCL15 may be omitted. As described in FIG. 6, the second frequency adjustment data CL2 is restored by CL1+DCL1, the first order differential value DCL2 is restored by DCL1+DDCL1, and the third frequency adjustment data CL3 is restored by CL2+DCL2. That is, the restoration of the third frequency adjustment data CL3 is an addition process using the initial value CL1 of the zeroth order differential, the initial value DCL1 of the first order differential, and the first second order differential value DDCL1. This is an example where i=3, but similarly, when i≧4, the restoration of the i-th frequency adjustment data CLi is an addition process using the initial value CL1 of the zeroth order differential, the initial value DCL1 of the first order differential, and the 1st to i-2nd order differential values ​​DDCL1 to DDCLi-2.

[0052] According to this embodiment, the frequency adjustment data calculation circuit 140 can restore the 1st to mth frequency adjustment data using the initial value of the 0th order differential, the initial value of the 1st order differential, and the 1st to m-2nd order differential values ​​stored in the memory circuit 130.

[0053] In this embodiment, n may be 3. The storage circuit 130 stores an initial value of the zeroth order differential, an initial value of the first order differential, an initial value of the second order differential, and the first to m-3rd order differential values ​​corresponding to the 1st to m-th frequency adjustment data. m is an integer of 4 or more. The frequency adjustment data calculation circuit 140 restores the i-th frequency adjustment data of the 1st to m-th frequency adjustment data by performing an addition process using the initial value of the zeroth order differential, the initial value of the first order differential, the initial value of the second order differential, and the 1st to i-3rd order differential values ​​of the 1st to m-3rd order differential values. i is an integer of 4 or more and m or less.

[0054] 7, m=16, and memory circuit 130 stores an initial value CL1 of the zeroth order differential, an initial value DCL1 of the first order differential, an initial value DDCL1 of the second order differential, and first to thirteenth third order differential values ​​DDCL1 to DDCL13 corresponding to the first to sixteenth frequency adjustment data CL1 to CL16. Note that, although a fourteenth third order differential value DDCL14 is further stored in the example of FIG. 7, the fourteenth third order differential value DDCL14 may be omitted if the interpolation process is not performed. The second frequency adjustment data CL2 is restored by CL1+DCL1, the first-order differential value DCL2 is restored by DCL1+DDCL1, the third frequency adjustment data CL3 is restored by CL2+DCL2, the second-order differential value DDCL2 is restored by DDCL1+DDDCL1, the first-order differential value DCL3 is restored by DCL2+DDCL2, and the fourth frequency adjustment data CL4 is restored by CL3+DCL4. That is, the restoration of the fourth frequency adjustment data CL4 is an addition process using the initial value CL1 of the zeroth-order differential, the initial value DCL1 of the first-order differential, the initial value DDCL1 of the second-order differential, and the first third-order differential value DDDCL1. This is an example where i=4, but similarly, for i≧5, the restoration of the i-th frequency adjustment data CLi is an addition process using the initial value CL1 of the zeroth differential, the initial value DCL1 of the first differential, the initial value DDCL1 of the second differential, and the 1st to i-3rd third differential values ​​DDDCL1 to DDDCLi-3.

[0055] According to this embodiment, the frequency adjustment data calculation circuit 140 can restore the 1st to mth frequency adjustment data using the initial value of the 0th order differential, the initial value of the 1st order differential, the initial value of the 2nd order differential, and the 1st to m-3rd order differential values ​​stored in the memory circuit 130.

[0056] 3. Second Configuration Example of Circuit Device 8 shows a second configuration example of the circuit device 100. In the second configuration example, the circuit device 100 further includes a temperature data calculation circuit 120 and a register 170. Hereinafter, descriptions of parts similar to those in the first configuration example will be omitted where appropriate.

[0057] The temperature data calculation circuit 120 is a logic circuit that converts the temperature data TD output by the temperature sensor circuit 110 into converted temperature data ETD[11:0]. The converted temperature data ETD[11:0] is data that increases monotonically with respect to temperature, like the temperature data TD, but the slope of the converted temperature data ETD[11:0] is converted from the slope of the temperature data TD according to the temperature range. Note that the converted temperature data ETD[11:0] may be data that decreases monotonically with respect to temperature. The number of bits of the temperature data TD may be approximately the same as the number of bits of the converted temperature data ETD[11:0], and as an example, it is 12 bits, the same as the number of bits of the converted temperature data ETD[11:0].

[0058] The register 170 stores parameters for the conversion performed by the temperature data calculation circuit 120. The parameters stored in the register 170 are input to the temperature data calculation circuit 120, and the temperature data calculation circuit 120 converts the temperature data TD into converted temperature data ETD[11:0] based on the parameters.

[0059] The memory circuit 130 outputs the data set QLUT designated by the upper bits ETD[11:9] of the converted temperature data among the eight data sets. The frequency adjustment data calculation circuit 140 restores the frequency adjustment data CLa and CLb using the data set QLUT. CLa is the frequency adjustment data designated by the middle bits ETD[8:5] of the converted temperature data, and CLb is the frequency adjustment data designated by ETD[8:5]+1. The interpolation circuit 152 outputs the adjustment data QCL by interpolating between the frequency adjustment data CLa and the frequency adjustment data CLb based on the lower bits ETD[4:0] of the converted temperature data.

[0060] 8 are merely examples, and may be ETD[p:0], ETD[p-1:q], ETD[q-1:r], and ETD[r-1:0], where r is an integer equal to or greater than 1, q is an integer equal to or greater than r+1, and p is an integer equal to or greater than q+1.

[0061] 9 is an example of a conversion process from temperature data TD to converted temperature data ETD. The temperature data range in which temperature compensation is performed is divided into temperature data ranges RA and RB with temperature data TDa as the boundary. In the following, TDa is also referred to as the boundary or the start temperature data of the temperature data range RB. In the following, the temperature data range RB is assumed to be on the lower temperature side than the temperature data range RA, but is not limited to this, and the temperature data range RB may be any temperature data range in which the second derivative value of the frequency adjustment data is relatively large.

[0062] The temperature data calculation circuit 120 outputs the temperature data TD as converted temperature data ETD in the temperature data range RA. That is, ETD=TD in the temperature data range RA. If the range of converted temperature data corresponding to the temperature data range RA is ERA, the width of ERA is the same as the width of RA. The temperature data calculation circuit 120 sets the slope of the converted temperature data ETD relative to the temperature data TD in the temperature data range RB to 2. That is, ETD=2×TD-TDa in the temperature data range RB. If the range of converted temperature data corresponding to the temperature data range RB is ERB, the width of ERB is twice the width of RB.

[0063] FIG. 10 shows an example of characteristics of the 0th order differential value, the 1st order differential value, and the 2nd order differential value of the frequency adjustment data with respect to the converted temperature data.

[0064] 3 shows an example of the characteristics of the 0th order differential value, the 1st order differential value, and the 2nd order differential value of the frequency adjustment data with respect to the temperature data, but the fluctuation of the 2nd order differential value is large on the low temperature side of the peak of the frequency adjustment data characteristics. Therefore, as shown in FIG 10, the temperature data corresponding to the peak of the frequency adjustment data characteristics is set to the boundary TDa, the high temperature side than TDa is set to the range ERA, and the low temperature side than TDa is set to the range ERB.

[0065] In the range ERA, the characteristics of the zeroth-order differential value, the first-order differential value, and the second-order differential value of the frequency adjustment data with respect to the converted temperature data are the same as the characteristics of the zeroth-order differential value, the first-order differential value, and the second-order differential value of the frequency adjustment data with respect to the temperature data described in Figure 3.

[0066] As shown in Fig. 9, the temperature data range RB is expanded to a double range ERB. Therefore, as shown in Fig. 10, in the range ERB of the converted temperature data, the characteristic of the frequency adjustment data is stretched twice, and the change in the characteristic becomes gentler. As a result, the first-order differential value and the second-order differential value become smaller in the range ERB of the converted temperature data, and the change range of the first-order differential value and the second-order differential value in the entire temperature range also becomes smaller. Compared with the characteristic in Fig. 3, the first-order differential value and the second-order differential value can be expressed with a smaller number of bits, so the memory capacity of the lookup table 131 can be further reduced.

[0067] Fig. 11 shows an example of the configuration of the temperature data calculation circuit 120 that performs the conversion shown in Fig. 9. The temperature data calculation circuit 120 includes a start point setting circuit KSA, a multiplication circuit MLA, and an adder circuit 126.

[0068] The start point setting circuit KSA sets the start temperature data TDa of the temperature data range RB in FIG. 9. The start temperature data TDa is the boundary between the adjacent temperature data ranges RA and RB, and in the example of FIG. 9, it is the upper limit of the temperature data range RB. When the temperature data TD is equal to or less than TDa, the start point setting circuit KSA subtracts TDa from the temperature data TD and outputs differential temperature data KSAQ=-(TD-TDa) with an inverted sign, and when the temperature data TD is greater than TDa, it outputs differential temperature data KSAQ=0. The multiplication circuit MLA multiplies the differential temperature data KSAQ by a gain of 1 and outputs output data MLAQ=-(KSAQ×1) with an inverted sign. In the temperature data range RB where TD≦TDa, MLAQ=TD-TDa, and in the temperature data range RA where TD>TDa, MLAQ=0.

[0069] The adder circuit 126 adds the temperature data TD, the output data MLAQ, and the offset value EQOF, and outputs the result as the converted temperature data ETD. In the temperature data range RB, ETD=TD+(TD-TDa)+EQOF=2×TD-TDa+EQOF, and the slope of the converted temperature data ETD is 2. In the temperature data range RA, ETD=TD+EQOF, and the slope of the converted temperature data ETD is 1. In the example of FIG. 9, EQOF=0, but the offset value EQOF may be any value.

[0070] FIG. 12 shows a detailed configuration example of the start point setting circuit KSA and the multiplication circuit MLA.

[0071] The starting point setting circuit KSA includes an addition circuit ADa, a sign inversion circuit SRa1, a selector SLa1, and a ReLU circuit RLa.

[0072] The adder circuit ADa adds an offset OFFa to the temperature data TD. The sign inverter circuit SRa1 inverts the sign of the output data of the adder circuit ADa. The selector SLa1 selects the output data of the adder circuit ADa when the sign selection signal ISGa is 0, and selects the output data of the sign inverter circuit SRa1 when the sign selection signal ISGa is 1. The ReLU circuit RLa outputs 0 when the output data of the selector SLa1 is less than 0, and outputs the data as is when the output data of the selector SLa1 is 0 or greater. The offset OFFa and the sign selection signal ISGa are stored in the register 170.

[0073] In the example of Fig. 9, the offset OFFa is set to -TDa, and the code selection signal ISGa is set to 1. At this time, the output data of the adder circuit ADa is TD-TDa, the selector SLa1 selects -(TD-TDa), and the ReLU circuit RLa outputs KSAQ=-(TD-TDa) when TD≦TDa, and outputs KSAQ=0 when TD>TDa. The start temperature data TDa of the temperature data range RB is specified by the offset OFFa=-TDa. In this manner, the operation of the start point setting circuit KSA described in Fig. 11 is realized.

[0074] The multiplication circuit MLA includes a bit shift circuit BSa, a sign inversion circuit SRa2, and a selector SLa2.

[0075] The bit shift circuit BSa multiplies the differential temperature data KSAQ from the start point setting circuit KSA by a gain by bit-shifting the differential temperature data KSAQ. The bit shift direction and the shift amount are specified by the bit shift value GAa. The shift direction is the LSB direction or the MSB direction, and the shift amount is the number of bits to be shifted. The bit shift gain is 2, 4, 8, . . . in the MSB direction, and 0.5, 0.25, 0.125, . . . in the LSB direction. When the shift amount is zero, the bit shift gain is 1. The sign inversion circuit SRa2 inverts the sign of the output data of the bit shift circuit BSa. The selector SLa2 selects the output data of the bit shift circuit BSa when the sign selection signal QSGa is 0, and selects the output data of the sign inversion circuit SRa2 when the sign selection signal QSGa is 1. The bit shift value GAa and the sign selection signal QSGa are stored in the register 170.

[0076] In the example of FIG. 9, the shift amount of the bit shift value GAa is set to 0 bits. That is, the bit shift gain is 1. Also, the code selection signal QSGa is set to 1. At this time, the output data of the bit shift circuit BSa is -(TD-TDa), and the selector SLa2 selects TD-TDa. As a result, when TD≦TDa, MLAQ=TD-TDa is output, and when TD>TDa, MLAQ=0 is output. In this manner, the operation of the multiplication circuit MLA described in FIG. 11 is realized.

[0077] In the above embodiment, the circuit device 100 includes a temperature data calculation circuit 120 that converts the temperature data TD into converted temperature data ETD[11:0]. The temperature data calculation circuit 120 makes the slope of the converted temperature data ETD in the first temperature data range RB different from the slope of the converted temperature data ETD in the second temperature data range RA. The memory circuit 130 outputs an n-th order differential value and an initial value based on the converted temperature data ETD.

[0078] In the example of FIG. 9, the slope of the converted temperature data ETD in the first temperature data range RB is 2, which is larger than the slope 1 of the converted temperature data ETD in the second temperature data range RA.

[0079] According to this embodiment, by varying the slope of the converted temperature data ETD depending on the temperature data range, it is possible to freely adjust the characteristics of the frequency adjustment data with respect to the converted temperature data ETD. This makes it possible to reduce the range of change in the n-th order differential value in the temperature data range where temperature compensation is performed, and further reduces the memory capacity.

[0080] In this embodiment, the n-th derivative of the frequency-temperature characteristic of the vibrator 10 in the first temperature data range RB is larger than the n-th derivative of the frequency-temperature characteristic in the second temperature data range RA. At this time, the slope of the converted temperature data ETD in the first temperature data range RB is larger than the slope of the converted temperature data ETD in the second temperature data range RA.

[0081] As shown in Fig. 3, the second differential value on the lower temperature side than the peak of the characteristic of the frequency adjustment data is larger than the second differential value on the higher temperature side. In this case, the lower temperature side than the peak of the characteristic of the frequency adjustment data is set to the first temperature data range RB, and the higher temperature side is set to the second temperature data range RA. As shown in Fig. 9, the slope 2 of the converted temperature data ETD in the first temperature data range RB is larger than the slope 1 of the converted temperature data ETD in the second temperature data range RA.

[0082] According to this embodiment, in the range ERB of the converted temperature data corresponding to the first temperature data range RB, the characteristics of the frequency adjustment data are stretched twice, and the change in the characteristics becomes gentler. As a result, the first-order differential value and the second-order differential value become smaller in the range ERB of the converted temperature data, and the change range of the first-order differential value and the second-order differential value in the entire temperature range also becomes smaller. This makes it possible to express the first-order differential value and the second-order differential value with a smaller number of bits.

[0083] 4. Oscillation circuit, frequency adjustment circuit 13 shows a detailed configuration example of the adjustment circuit 154 included in the frequency adjustment circuit 150, and a connection configuration example of the vibrator 10, the oscillation circuit 160, and the adjustment circuit 154. The adjustment circuit 154 includes capacitor array circuits CAC1 and CAC2.

[0084] One end of the vibrator 10 is connected to a terminal TX1, and the other end of the vibrator 10 is connected to a terminal TX2. The terminals TX1 and TX2 are terminals of the circuit device 100, and are, for example, pads provided on a semiconductor substrate. One end of a capacitor CX1 is connected to the terminal TX1, and the other end of the capacitor CX1 is connected to a ground node. One end of a capacitor CX2 is connected to the terminal TX2, and the other end of the capacitor CX2 is connected to the ground node. The capacitors CX1 and CX2 are provided, for example, as external components of the circuit device 100.

[0085] The oscillator circuit 160 generates a drive signal SDR by inverting and amplifying a signal SIN input from the other end of the vibrator 10 via a terminal TX2, and outputs the drive signal SDR to one end of the vibrator 10 via a terminal TX1. The oscillator circuit 160 is, for example, an inverter, and an input node of the inverter is connected to the terminal TX2, and an output node is connected to the terminal TX1. However, the oscillator circuit 160 is not limited to this, and may be various amplifier circuits such as an amplifier circuit using a bipolar transistor. The oscillation signal is, for example, the drive signal SDR, but is not limited to this, and the oscillation signal may be a signal in an oscillation loop formed by the oscillator circuit 160 and the vibrator 10. In addition, the drive signal SDR may be output as the clock signal CLK in FIG. 2, and the circuit device 100 may include an output circuit that outputs the clock signal CLK by buffering or dividing the drive signal SDR.

[0086] The capacitor array circuit CAC1 is connected to a terminal TX1, and the capacitor array circuit CAC2 is connected to a terminal TX2. Although the configuration of the capacitor array circuit CAC1 will be described below as an example, the capacitor array circuit CAC2 has a similar configuration.

[0087] The capacitor array circuit CAC1 includes 1st to sth capacitors and 1st to sth switches, where s is an integer equal to or greater than 2. The jth capacitor and the jth switch are connected in series between the terminal TX1 and the ground node. j=1, 2, . . . , s. Each of the 1st to sth switches is controlled to be on or off by adjustment data QCL from the interpolator 152. As a result, the capacitance value of the capacitor array circuit CAC1 is controlled in accordance with the adjustment data QCL, and the oscillation frequency is adjusted.

[0088] The circuit device of the present embodiment described above includes an oscillation circuit that generates an oscillation signal using a vibrator, a frequency adjustment circuit that adjusts the oscillation frequency of the oscillation circuit based on frequency adjustment data, a temperature sensor circuit that outputs temperature data, a memory circuit, and a frequency adjustment data calculation circuit. The memory circuit stores an n-th order differential value of the frequency adjustment data and an initial value of the 0th to n-1th order differential, and outputs the n-th order differential value and the initial value based on the temperature data. n is an integer equal to or greater than 1. The frequency adjustment data calculation circuit outputs frequency adjustment data corresponding to the temperature data by performing an addition process between the n-th order differential value output by the memory circuit and the initial value.

[0089] According to this embodiment, the n-th order differential value and the initial value of the 0th to n-1th order differential are stored in the lookup table, so that the memory capacity of the lookup table is reduced compared to the case where the frequency adjustment data is stored as it is as a lookup table. Furthermore, when the stored contents of the lookup table are changed to the n-th order differential value and the initial value while maintaining the memory capacity, the number of bits or the number of data of the frequency adjustment data that can be restored increases, so that the temperature compensation can be made more accurate. Thus, according to this embodiment, it is possible to achieve both high accuracy of temperature compensation and miniaturization of the circuit.

[0090] In this embodiment, the vibrator may have an n-th order frequency temperature characteristic.

[0091] If the frequency adjustment data has ideal n-th order temperature characteristics, the n-th order differential value becomes the n-th order coefficient of an n-th order polynomial that approximates the temperature characteristics. In other words, the n-th order differential value becomes a constant that does not fluctuate, making it possible to express it with a very small amount of data. Although the frequency adjustment data does not actually have ideal n-th order temperature characteristics due to the nonlinearity of the circuit, since the main component is the n-th order characteristic, using the n-th order differential value makes it possible to significantly reduce the amount of data.

[0092] In this embodiment, the number of bits of the n-th differential value stored in the storage circuit may be smaller than the number of bits of the initial value.

[0093] According to this embodiment, the memory circuit mainly stores n-th order differential values ​​having a relatively small number of bits, and only stores initial values ​​for 0th to n-1th order differential values ​​having a larger number of bits than the n-th order differential values. This reduces the amount of data stored in the lookup table.

[0094] In the present embodiment, the memory circuit may store an n-th order differential value and an initial value for each of the plurality of temperature data ranges, and may output an n-th order differential value and an initial value for a temperature data range to which the temperature data from the temperature sensor circuit belongs among the plurality of temperature data ranges.

[0095] According to this embodiment, since the n-th order differential value and the initial value are stored for each temperature data range, the frequency adjustment data calculation circuit can restore the frequency adjustment data from the n-th order differential value within each temperature data range. This reduces the number of addition processes compared to when a lookup table is configured without dividing the temperature data ranges, and makes it possible to restore the frequency adjustment data with low power consumption.

[0096] In this embodiment, n may be 2. The storage circuit may store an initial value of the zeroth order differential, an initial value of the first order differential, and the first to m-2th second order differential values ​​corresponding to the 1st to mth frequency adjustment data, where m is an integer of 3 or more. The frequency adjustment data calculation circuit may restore the i-th frequency adjustment data of the 1st to mth frequency adjustment data by performing an addition process using the initial value of the zeroth order differential, the initial value of the first order differential, and the 1st to i-2nd second order differential values ​​of the 1st to m-2th second order differential values. i is an integer of 3 or more and m or less.

[0097] According to this embodiment, the frequency adjustment data calculation circuit can restore the 1st to mth frequency adjustment data using the initial value of the 0th order differential, the initial value of the 1st order differential, and the 1st to m-2nd order differential values ​​stored in the memory circuit.

[0098] In this embodiment, n may be 3. The storage circuit may store an initial value of the zeroth order differential, an initial value of the first order differential, an initial value of the second order differential, and the 1st to (m-3rd) order differential values ​​corresponding to the 1st to mth order frequency adjustment data, where m is an integer of 4 or more. The frequency adjustment data calculation circuit may restore the i-th frequency adjustment data of the 1st to mth order frequency adjustment data by performing an addition process using the initial value of the zeroth order differential, the initial value of the first order differential, the initial value of the second order differential, and the 1st to (i-3rd) order differential values ​​of the 1st to (m-3rd) order differential values. i is an integer of 4 or more and m or less.

[0099] According to this embodiment, the frequency adjustment data calculation circuit can restore the 1st to mth frequency adjustment data using the initial value of the 0th order differential, the initial value of the 1st order differential, the initial value of the 2nd order differential, and the 1st to m-3rd order differential values ​​stored in the memory circuit.

[0100] The circuit device of the present embodiment may further include a temperature data calculation circuit that converts the temperature data into converted temperature data. The temperature data calculation circuit may differentiate a slope of the converted temperature data in a first temperature data range from a slope of the converted temperature data in a second temperature data range. The memory circuit may output an n-th order differential value and an initial value based on the converted temperature data.

[0101] According to this embodiment, by varying the slope of the converted temperature data according to the temperature data range, it is possible to freely adjust the characteristics of the frequency adjustment data with respect to the converted temperature data. This makes it possible to reduce the range of change in the n-th order differential value in the temperature data range where temperature compensation is performed, and further reduces the memory capacity.

[0102] In the present embodiment, the n-th order differential of the frequency-temperature characteristic of the vibrator in the first temperature data range may be larger than the n-th order differential of the frequency-temperature characteristic in the second temperature data range. In this case, the gradient of the converted temperature data in the first temperature data range may be larger than the gradient of the converted temperature data in the second temperature data range.

[0103] According to this embodiment, in the range of converted temperature data corresponding to the first temperature data range, the characteristic of the frequency adjustment data is stretched by the amount of the slope, and the change in the characteristic becomes gentler. As a result, the 1st to nth order differential value becomes small in the range of converted temperature data corresponding to the first temperature data range, and the change width of the 1st to nth order differential value in the entire temperature range also becomes small. This makes it possible to express the 1st to nth order differential value with a smaller number of bits.

[0104] Moreover, an oscillator according to the present embodiment includes any one of the circuit devices described above and a resonator.

[0105] Although the present embodiment has been described in detail as above, it will be readily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the circuit device, resonator, and oscillator are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0106] 10...vibrator, 100...circuit device, 110...temperature sensor circuit, 120...temperature data calculation circuit, 126...addition circuit, 130...memory circuit, 131...lookup table, 140...frequency adjustment data calculation circuit, 150...frequency adjustment circuit, 152...interpolation circuit, 154...adjustment circuit, 160...oscillator circuit, 170...register, 200...oscillator, CL1 to CL17...frequency adjustment data, CLK...clock signal, CLa, CLb...frequency adjustment data, DCL1 to DCL16...first-order differential value, DDCL1 to DDCL15...second-order differential value, DDDCL1 to DDDCL14...third-order differential value, ETD...converted temperature data, RA, RB...temperature data range, TD...temperature data

Claims

1. an oscillator circuit for generating an oscillation signal using an oscillator; a temperature sensor circuit that outputs temperature data; a memory circuit that stores the first frequency adjustment data among first to m-th frequency adjustment data (m is an integer of 3 or more), the first primary differential value among first to m-1-th primary differential values ​​which are differential values ​​between adjacent frequency adjustment data in the first to m-th frequency adjustment data, and first to m-2-th secondary differential values ​​which are differential values ​​between adjacent primary differential values ​​in the first to m-1-th primary differential values; a frequency adjustment data calculation circuit that performs an addition process using the first frequency adjustment data, the first primary differential value, and first to i-2nd secondary differential values ​​(i is an integer between 3 and m) among the first to m-2nd secondary differential values ​​to restore i-th frequency adjustment data corresponding to the temperature data among the first to m-th frequency adjustment data; a frequency adjustment circuit that adjusts an oscillation frequency of the oscillation circuit based on the i-th frequency adjustment data; Including, The number of bits of each of the first to (m-2)th secondary difference values ​​stored in the memory circuit is smaller than the number of bits of the first frequency adjustment data.

2. 2. The circuit device according to claim 1, The circuit device is characterized in that the vibrator has a second-order frequency temperature characteristic.

3. 3. The circuit device according to claim 1, The frequency adjustment data calculation circuit includes: obtaining second to (i-1)th primary difference values ​​by sequentially adding the first to (i-2)th secondary difference values ​​to the first primary difference value; A circuit device which restores the i-th frequency adjustment data by sequentially adding the 1st to (i-1)th primary difference values ​​to the first frequency adjustment data.

4. 4. The circuit device according to claim 1, The memory circuit includes: For each of a plurality of temperature data ranges, the first frequency adjustment data, the first primary differential value, and the first to (m-2)th secondary differential values ​​are stored; A circuit device characterized by outputting the first frequency adjustment data for a temperature data range to which the temperature data from the temperature sensor circuit belongs among the multiple temperature data ranges, the first primary differential value, and the first to m-2th secondary differential values.

5. 5. The circuit device according to claim 1, a temperature data calculation circuit for converting the temperature data into converted temperature data; the temperature data calculation circuit makes a gradient of the converted temperature data in a first temperature data range different from a gradient of the converted temperature data in a second temperature data range; The memory circuit outputs the first frequency adjustment data, the first primary difference value, and the first to (i-2)th secondary difference values ​​based on the converted temperature data.

6. an oscillator circuit for generating an oscillation signal using an oscillator; a temperature sensor circuit that outputs temperature data; a memory circuit that stores the first frequency adjustment data among first to m-th frequency adjustment data (m is an integer equal to or greater than 4), the first primary differential value among first to m-1th primary differential values ​​which are differential values ​​between adjacent frequency adjustment data in the first to m-th frequency adjustment data, the first secondary differential value among first to m-2th secondary differential values ​​which are differential values ​​between adjacent primary differential values ​​in the first to m-1th primary differential values, and first to m-3th tertiary differential values ​​which are differential values ​​between adjacent secondary differential values ​​in the first to m-2th secondary differential values; a frequency adjustment data calculation circuit that performs an addition process using the first frequency adjustment data, the first primary differential value, the first secondary differential value, and the first to i-3rd tertiary differential values ​​(i is an integer between 4 and m) among the first to m-3rd tertiary differential values ​​to restore the i-th frequency adjustment data corresponding to the temperature data among the first to m-th frequency adjustment data; a frequency adjustment circuit that adjusts an oscillation frequency of the oscillation circuit based on the i-th frequency adjustment data; Including, The number of bits of each of the first to (m-3)th third-order differential values ​​stored in the memory circuit is smaller than the number of bits of the first frequency adjustment data.

7. 7. The circuit device according to claim 6, The circuit device is characterized in that the vibrator has a third-order frequency temperature characteristic.

8. 8. The circuit device according to claim 6, The frequency adjustment data calculation circuit includes: obtaining second to (i-2)th second order differential values ​​by sequentially adding the first to (i-3)th tertiary differential values ​​to the first second order differential value; obtaining second to (i-1)th primary difference values ​​by sequentially adding the first to (i-2)th secondary difference values ​​to the first primary difference value; A circuit device which restores the i-th frequency adjustment data by sequentially adding the 1st to (i-1)th primary difference values ​​to the first frequency adjustment data.

9. 9. The circuit device according to claim 6, The memory circuit includes: For each of a plurality of temperature data ranges, the first frequency adjustment data, the first primary differential value, the first secondary differential value, and the first to (m-3)th tertiary differential values ​​are stored; A circuit device characterized by outputting the first frequency adjustment data for a temperature data range to which the temperature data from the temperature sensor circuit belongs among the plurality of temperature data ranges, the first primary differential value, the first secondary differential value, and the first to (m-3)th tertiary differential values.

10. 10. The circuit device according to claim 6, a temperature data calculation circuit for converting the temperature data into converted temperature data; the temperature data calculation circuit makes a gradient of the converted temperature data in a first temperature data range different from a gradient of the converted temperature data in a second temperature data range; The memory circuit outputs the first frequency adjustment data, the first primary differential value, the first secondary differential value, and the first to (i-3) tertiary differential values ​​based on the converted temperature data.

11. A circuit arrangement according to any one of claims 1 to 10; The oscillator; 16. An oscillator comprising:

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