Electronic circuits, semiconductor modules

Abstract

To provide an electronic circuit in which breakage of a reflux diode is prevented, and a semiconductor module.SOLUTION: An electronic circuit includes: a first diode BD0 in which a forward voltage is a first voltage; a second diode SBD0 having a Schottky junction in which a forward voltage is a second voltage; first wiring members 50, 52, 54, and 55 which couple an output terminal and a positive electrode terminal P through the first diode; and second wiring members 50-53 which couple the output terminal and positive electrode terminal through the second diode, and each of which has an inductance larger than the inductance of the first wiring members. When a channel from the output terminal to the positive electrode terminal via the first wiring members is denoted as a first channel and a channel from the output terminal to the positive electrode terminal via the second wiring members is denoted as a second channel, the difference in inductance between the second wiring members and the first wiring members is larger than the product of the difference between the first voltage and second voltage and the reciprocal of time variation of a current of the first channel or second channel, and the reciprocal of time variation of the current of the first channel or second channel is 0.1 to 10 A / nsec.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an electronic circuit and a semiconductor module. [Background technology]

[0002] 2. Description of the Related Art A bridge circuit is known as a circuit that includes an upper arm switching element and a lower arm switching element and drives a load (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-009834 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, for example, when the switching element of the lower arm is turned off, the current flowing through the switching element of the lower arm generally flows via the parasitic diode of the switching element of the upper arm and the freewheeling diode connected to the switching element of the upper arm.

[0005] However, if the forward voltage of the parasitic diode is larger than the forward voltage of the freewheeling diode, much of the current flowing to the load flows to the freewheeling diode, which may destroy the freewheeling diode.

[0006] The present invention has been made in consideration of the above-mentioned problems in the conventional technology, and has an object to provide an electronic circuit and a semiconductor module that can prevent breakdown of a freewheeling diode. [Means for solving the problem]

[0007] An electronic circuit according to a first aspect of the present invention for solving the above-mentioned problems includes a first diode having a PN junction whose forward voltage is a first voltage, a second diode having a Schottky junction whose forward voltage is a second voltage lower than the first voltage, a first wiring member connecting a first terminal and a second terminal via the first diode, and a second wiring member connecting the first terminal and the second terminal via the second diode and having an inductance larger than an inductance of the first wiring member, wherein the first diode is a parasitic diode included in a switching element. The switching element and the second diode are elements that use a wide bandgap semiconductor, and when a first path is from the first terminal via the first wiring member to the second terminal, and a second path is from the first terminal via the second wiring member to the second terminal, the difference between the inductance of the second wiring member and the inductance of the first wiring member is greater than the product of the difference between the first voltage and the second voltage and the reciprocal of the time change of current in the first path or the second path, and the reciprocal of the time change of current in the first path or the second path is 0.1 to 10 A / nsec. Effect of the Invention

[0008] According to the present invention, it is possible to provide an electronic circuit and a semiconductor module that can prevent breakdown of a free wheel diode. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of an electronic circuit 10. [Diagram 2] 11 is a diagram for explaining a current flowing through diodes BD0 and SBD0 in the upper arm. FIG. [Diagram 3] 11 is a diagram for explaining a current flowing through diodes BD2 and SBD2 of the lower arm. FIG. [Figure 4] 2 is a schematic plan view of a semiconductor module 80. FIG. [Diagram 5] 2 is a schematic diagram for explaining the structure of a semiconductor module 80. FIG. [Figure 6]13 is a diagram for explaining a wiring pattern conceptually formed on a conductive pattern 220. FIG. [Figure 7] 13 is a diagram for explaining a current flowing through an element of an upper arm of a semiconductor module 80. FIG. [Figure 8] FIG. 4 is a diagram showing an example of an equivalent circuit of an element in the upper arm. [Figure 9] 13 is a diagram for explaining a current flowing through an element of a lower arm of a semiconductor module 80. FIG. [Figure 10] FIG. 4 is a diagram showing an example of an equivalent circuit of an element of a lower arm. [Figure 11] FIG. 13 is a diagram showing an example of an embodiment in which the length of the wire is adjusted. [Figure 12] FIG. 12 shows an equivalent circuit of the embodiment of FIG. [Figure 13] FIG. 13 is a diagram showing an example of an embodiment in which the cross-sectional area of ​​the wire is adjusted. [Figure 14] 13A and 13B are diagrams illustrating an example of an embodiment in which the curvature of the wire is adjusted. [Figure 15] FIG. 13 is a diagram illustrating an example of an embodiment in which a wiring pattern is adjusted. [Figure 16] 11 is a schematic diagram for explaining the thickness of the conductive patterns 240 and 250. FIG. [Figure 17] 2 is a diagram showing an example of the configuration of an upper arm of a semiconductor module 80. FIG. [Figure 18] FIG. 18 shows an equivalent circuit of the embodiment of FIG. 17. [Figure 19] 4 is a diagram showing an example of the configuration of a lower arm of a semiconductor module 80. FIG. [Figure 20] FIG. 18 shows an equivalent circuit of the embodiment of FIG. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] At least the following points will become apparent from the description of this specification and the accompanying drawings.

[0011] =====This embodiment===== <<<An example of the electronic circuit 10>>> 1 is a diagram showing the configuration of an electronic circuit 10 according to one embodiment of the present invention. The electronic circuit 10 is a half-bridge circuit for driving a load (not shown) such as a motor coil, and includes NMOS transistors (n-type metal-oxide-semiconductor field-effect-transistors) M0-M3, diodes SBD0-SBD3, a positive terminal P, an output terminal U, a negative terminal N, and control terminals IN1 and IN2.

[0012] The NMOS transistor M0 is an upper arm switching element, with a gate electrode (control electrode) connected to the upper arm control terminal IN1, a source electrode connected to the output terminal U, and a drain electrode connected to the positive terminal P. The NMOS transistor M0 also includes a diode BD0 as a parasitic diode (i.e., a body diode).

[0013] The NMOS transistor M1 is an upper arm switching element similar to the NMOS transistor M0, and includes a diode BD1.

[0014] The NMOS transistor M2 is a lower arm switching element, with a gate electrode connected to the control terminal IN2 of the lower arm, a source electrode connected to the negative terminal N, and a drain electrode connected to the output terminal U. The NMOS transistor M2 also includes a diode BD2 as a parasitic diode.

[0015] The NMOS transistor M3 is a lower arm switching element similar to the NMOS transistor M2, and includes a diode BD3.

[0016] Here, in this embodiment, MOS transistors are used as the switching elements, but this is not limited thereto. As the switching elements, RC (Reverse Conducting)-IGBTs, which are reverse conducting IGBTs (Insulated Gate Bipolar Transistors) including bipolar transistors and diodes, may be used. In the case of RC-IGBTs, the PN junction diodes formed inside may be the diodes BD0 to BD3.

[0017] The diodes BD0 to BD3 of this embodiment are PN junction diodes. The NMOS transistors M0 to M3 of this embodiment are elements manufactured using SiC (Silicon Carbide), which is a wide band gap semiconductor. Therefore, the forward voltage Vf1 (first voltage) of the diodes BD0 to BD3, which are body diodes, is a value based on the PN junction of SiC (for example, 2.5 V).

[0018] The diode SBD0 is a Schottky barrier diode including a Schottky junction between a metal and n-type SiC, and is connected in anti-parallel to the NMOS transistor M0. The diodes SBD1 to SBD3 are SiC Schottky barrier diodes similar to the diode SBD0, and are connected in anti-parallel to the NMOS transistors M1 to M3, respectively. Therefore, the diodes SBD0 to SBD3 operate as freewheeling diodes. The forward voltage Vf2 (second voltage) of the diodes SBD0 to SBD3 is a value based on the Schottky junction (for example, 0.7 V).

[0019] In the present embodiment, the switching element and the free wheel diode are manufactured using SiC, but other wide band gap semiconductors such as GaN (Gallium Nitride) may be used. The free wheel diode may be a Schottky barrier diode including a Schottky junction of metal and Si.

[0020] The positive terminal P is a terminal on the power supply side (or high side), the negative terminal N is a terminal on the ground side (or low side), and the output terminal U is a terminal to which a load is connected. A signal that controls the switching of the NMOS transistors M0 and M1, which are the switching elements of the upper arm, is input to the control terminal IN1. A signal that controls the switching of the NMOS transistors M2 and M3, which are the switching elements of the lower arm, is input to the control terminal IN2.

[0021] In such an electronic circuit 10, a load is driven by turning on and off the switching elements of the upper arm and the lower arm. When the electronic circuit 10 drives a load, if the switching elements of the upper arm and the lower arm are simultaneously turned on, a large through current flows from the positive terminal P to the negative terminal N. Therefore, when the load is driven, a dead time period is provided in which both the switching elements of the upper arm and the lower arm are turned off. During the dead time period, a current may flow from the output terminal U to the positive terminal P, for example. Also, during the dead time period, a current may flow from the negative terminal N to the output terminal U, for example.

[0022] <<<About the current from output terminal U to positive terminal P>>> 2 is a diagram for explaining the current flowing through the diodes BD0 and SBD0 of the upper arm during the dead time period, for example. Note that in this embodiment, the current flowing through the diodes BD0 and SBD0 during the dead time period is the same as the current flowing through the diodes BD1 and SBD1, so only the current flowing through the diodes BD0 and SBD0 will be explained here.

[0023] Node x0 in Fig. 2 is a node to which a wiring from the output terminal U, a wiring from the source electrode S1 of the NMOS transistor M0, and a wiring from the anode electrode A0 of the diode SBD0 are connected in Fig. 1. Node x1 is a node to which a wiring from the positive terminal P, a wiring from the drain electrode D1 of the NMOS transistor M0, and a wiring from the cathode electrode K0 of the diode SBD0 are connected. Hereinafter, the anode electrode will be referred to as the anode, and the cathode electrode will be referred to as the cathode.

[0024] Here, the wiring between the output terminal U and the node x0 is a wiring 50 having an inductance La, and the wiring between the node x0 and the anode A0 of the diode SBD0 is a wiring 51 having an inductance Lb. The wiring between the positive terminal P and the node x1 is a wiring 52 having an inductance Lc, and the wiring between the node x1 and the cathode K0 of the diode SBD0 is a wiring 53 having an inductance Ld. Furthermore, the wiring between the source electrode S1 of the NMOS transistor M0 and the node x0 is a wiring 54 having an inductance Li, and the wiring between the drain electrode D1 of the NMOS transistor M0 and the node x1 is a wiring 55 having an inductance Lj. The inductances La to Ld, Li, and Lj are parasitic inductances of the wirings 50 to 55.

[0025] Here, as described above, the diode BD0 is a body diode having a forward voltage Vf1 (e.g., 2.5 V) based on a PN junction of SiC, and the diode SBD0 is a Schottky diode having a forward voltage Vf2 (e.g., 0.7 V) based on a Schottky junction of SiC.

[0026] For this reason, the current from the output terminal U first passes through the diode SBD0 and the path P2 shown by the dashed line to the positive terminal P. At this time, the voltage Vx01 between the node x0 and the node x1 is expressed by the following equation (1).

[0027] Vx01=(Lb+Ld)×di2 / dt+Vf2...(1) In formula (1), the current flowing through path P2 is i2, and di2 / dt is the change over time of the current i2 flowing through path P2. The change over time of the current i2 is a value determined by, for example, the current flowing through the load and the time it takes for the switching element to turn off from on, and is, for example, 0.1 to 10 A / nsec.

[0028] Here, for example, if the values ​​of inductances Lb and Ld are small and the voltage Vx01 does not exceed the forward voltage Vf1 (for example, 2.5 V), all of the current flowing from the output terminal U will flow through the path P2. As a result, the current i2 may exceed the rated current of the diode SBD0, which may destroy the diode SBD0. Therefore, in this embodiment, the values ​​of inductances Lb and Ld are increased so that the current from the output terminal U flows not only through the path P2, but also through the path P1 illustrated by the dotted line via the diode BD0 to the positive terminal P. The values ​​of inductances Lb and Ld are calculated based on the relationship of equation (2).

[0029] (Lb+Ld)×di2 / dt+Vf2>(Li+Lj)×di1 / dt+Vf1...(2) By transforming equation (2) to set the forward voltage Vf1 to 2.5 V, the forward voltage Vf2 to 0.7 V, and di2 / dt (=di1 / dt) to 10 A / nsec, the relational expression shown in equation (3) below is obtained.

[0030] ((Lb+Ld)-(Li+Lj))>(Vf1-Vf2)×dt / di2 >(2.5-0.7)×(1 / 10) >0.18 (3) As a result, if the total value of the inductances Lb and Ld is made larger than the total value of the inductances Li and Lj, for example, by 0.18 nH, the currents i1 and i2 will flow via the paths P1 and P2, preventing a large current from flowing through the diode SBD0.

[0031] In this manner, in this embodiment, the inductance of the wiring of the path P2 is made larger than the inductance of the wiring of the path P1 so that the diode BD0 turns on when a current flows from the output terminal U. As a result, the current i2 that flows through the diode SBD0 out of the current from the output terminal U can be reduced, thereby preventing the breakdown of the diode SBD0.

[0032] 2, for example, three wirings 50, 51, and 54 are modeled as wirings connected to node x0, but when node x0 corresponds to source electrode S1, inductance Li of wiring 54 can be ignored, and Li = 0. Also, for example, when node x0 corresponds to output terminal U, inductance La of wiring 50 can be ignored, and La = 0. Therefore, although details will be described later, by using the circuit of FIG. 2, various semiconductor modules can be expressed by equivalent circuits.

[0033] Here, diode BD0 corresponds to a "first diode", and diode SBD0 corresponds to a "second diode". Also, output terminal U corresponds to a "first terminal", and positive terminal P corresponds to a "second terminal". Furthermore, wiring 50, 52, 54, and 55 connecting output terminal U and positive terminal P via diode BD0 correspond to a "first wiring member", and wiring 50-53 connecting output terminal U and positive terminal P via diode SBD0 correspond to a "second wiring member".

[0034] In this embodiment, the forward voltage Vf1 is 2.5 V and the forward voltage Vf2 is 0.7 V, but these values ​​are merely examples. The values ​​of the forward voltages Vf1 and Vf2 and the value of the wiring inductance change due to manufacturing variations.

[0035] Furthermore, the total value of the required inductances Lb, Ld changes depending on the temperature, current, and time of use. Therefore, it is sufficient that the inductance of the "second wiring member" is at least greater than the inductance of the "first wiring member." Preferably, the inductance of the "second wiring member" is greater than the inductance of the "first wiring member" by 0.18 nH or more. More preferably, the inductance of the "second wiring member" is greater than the inductance of the "first wiring member" by 0.36 nH or more.

[0036] <<About the current from the negative terminal N to the output terminal U>> 3 is a diagram for explaining the current flowing through the diodes SBD2 and BD2 of the lower arm during the dead time period, for example. In this embodiment, the current flowing through the diodes BD2 and SBD2 during the dead time period is the same as the current flowing through the diodes BD3 and SBD3, so only the current flowing through the diodes BD2 and SBD2 will be explained here.

[0037] Node x2 in Fig. 3 is a node to which a wiring from the negative terminal N, a wiring from the source electrode S2 of the NMOS transistor M2, and a wiring from the anode A3 of the diode SBD2 are connected in Fig. 1. Node x3 is a node to which a wiring from the output terminal U, a wiring from the drain electrode D2 of the NMOS transistor M2, and a wiring from the cathode K3 of the diode SBD2 are connected.

[0038] Here, the wiring between the negative terminal N and the node x2 is a wiring 60 having an inductance Le, and the wiring between the node x2 and the anode A3 of the diode SBD2 is a wiring 61 having an inductance Lf. The wiring between the output terminal U and the node x3 is a wiring 62 having an inductance Lg, and the wiring between the node x3 and the cathode K3 of the diode SBD2 is a wiring 63 having an inductance Lh. Furthermore, the wiring between the source electrode S2 of the NMOS transistor M2 and the node x2 is a wiring 64 having an inductance Lm, and the wiring between the drain electrode D2 of the NMOS transistor M2 and the node x3 is a wiring 65 having an inductance Ln. The inductances Le to Lh, Lm, and Ln are parasitic inductances of the wirings 60 to 65.

[0039] In this embodiment, similarly to the upper arm in Fig. 2, when a current flows in from the negative terminal N, the values ​​of inductances Lf and Lh are increased so that a current i3 flows through a path P3 shown by a dotted line via diode BD2, and a current i4 flows through a path P4 shown by a dashed line via diode SBD2. Specifically, based on the above-mentioned formula (3), for example, (Lf+Lh)-(Lm+Ln)>0.18nH. As a result, when a current flows in from the negative terminal N, a large current flows in the diode SBD2 of the lower arm, and it is possible to prevent the diode SBD2 from being destroyed.

[0040] In this case, diode BD2 corresponds to a "first diode", and diode SBD2 corresponds to a "second diode". Furthermore, the negative terminal N corresponds to a "first terminal", and the output terminal U corresponds to a "second terminal". Furthermore, wiring 60, 62, 64, and 65 connecting the negative terminal N and the output terminal U via diode BD2 corresponds to a "first wiring member", and wiring 60-63 connecting the negative terminal N and the output terminal U via diode SBD2 corresponds to a "second wiring member".

[0041] ===An Example of Semiconductor Module 80=== Fig. 4 is a schematic plan view showing an example of a semiconductor module 80 that embodies the electronic circuit 10, and Fig. 5 is a schematic view for explaining the structure of the semiconductor module 80. In this embodiment, the multiple switching elements and free wheel diodes of the electronic circuit 10 are mounted in the semiconductor module 80 with the same structure. Therefore, for convenience, Fig. 5 shows only the NMOS transistor M0 and diode SBD0 of the upper arm.

[0042] The gate electrode G1 and source electrode S1 of the NMOS transistor M0 are formed on the central axis of the NMOS transistor M0, for example, but are illustrated separately here for convenience. In the following, in this embodiment, "electrically connected" refers to the components E1 and E2 being connected so as to be conductive to each other via wiring or a bonding material (e.g., solder), and is also simply referred to as "connected." In addition, "connected" includes a case where the components E1 and E2 are connected via a wiring member, as well as a case where the components E1 and E2 are connected via a conductive pattern or the like provided between them.

[0043] The semiconductor module 80 is a semiconductor device including a plurality of switching elements and free wheel diodes of the electronic circuit 10. In Fig. 4, the switching elements are NMOS transistors M0 to M3, and the free wheel diodes are diodes SBD0 to SBD3. The semiconductor module 80 includes laminated substrates 110 and 111 having conductive patterns 210, 220, 230, 310, 320, and 330, switching elements and free wheel diodes arranged on the conductive patterns 220 and 320, terminals arranged on the conductive patterns 210, 220, 310, 320, and 330, and bonding wires electrically connected to the switching elements, free wheel diodes, and conductive patterns. The semiconductor module 80 may further include a base plate 100.

[0044] The terminal has, for example, a rectangular column shape, one end of which is joined to the conductive pattern and the other end of which extends from the semiconductor module 80 and is electrically connected to an external device (not shown). The terminal is made of, for example, copper, aluminum, or an alloy containing these.

[0045] The bonding wire is made of copper, aluminum, gold, or an alloy containing these. In addition, a material other than the bonding wire can be used as the wiring member. For example, a lead frame can be used as the wiring member.

[0046] The base plate 100 has a smooth bonding surface to which an insulating circuit board is bonded on the upper surface, and has, for example, a rectangular shape in a plan view. The base plate 100 is, for example, a metal plate made of aluminum, copper, or an alloy containing these. As shown in FIG. 5, a laminated substrate 110 is attached to the base plate 100 via a bonding material 101 such as solder. The laminated substrate 111 has a similar configuration to the laminated substrate 110 and is attached to the same base plate 100 as the laminated substrate 110.

[0047] <<Laminated substrate 110 on the upper arm side>> The laminated substrate 110 includes an insulating plate 200 and conductive patterns 210, 220, and 230 formed on the front surface (upper side) of the insulating plate 200. The insulating plate 200 is made of, for example, ceramics or resin. The conductive patterns 210, 220, and 230 are made of, for example, copper, aluminum, or an alloy containing these. The laminated substrate 110 may further include a heat sink 201 on the rear surface (lower side) of the insulating plate 200. The insulating circuit substrate thus configured is formed of, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate. In this embodiment, the laminated substrate 110 is a DBC (Direct Bonded Copper) substrate on which upper arm elements are mounted.

[0048] <<Conductive pattern 210>> A control terminal IN1 to which a signal for controlling the switching element of the upper arm is input is mounted on the conductive pattern 210. Here, as shown in Fig. 5, the control terminal IN1 is attached to the conductive pattern 210 via a bonding material 252 (e.g., solder). The conductive pattern 210 is connected to a gate electrode G1 of the NMOS transistor M0 via a bonding wire (hereinafter simply referred to as a wire), and is connected to a gate electrode of the NMOS transistor M1 via a wire.

[0049] In this embodiment, in the upper arm, the connection relationship between the NMOS transistor M1 and the diode SBD1 and the output terminal U, the positive terminal P, and the control terminal IN1 is the same as the connection relationship between the NMOS transistor M0 and the diode SBD0 and the output terminal U, the positive terminal P, and the control terminal IN1. Therefore, the following description will focus on the NMOS transistor M0 and the diode SBD0.

[0050] <<Conductive pattern 220>> The conductive pattern 220 has a power supply positive terminal P, NMOS transistors M0 and M1, and diodes SBD0 and SBD1 mounted thereon. As shown in Fig. 5, the drain electrode D1 formed on the back surface of the NMOS transistor M0 is attached to the conductive pattern 220 via a bonding material 250 (e.g., solder). In this embodiment, the cathode K1 of the diode BD0 is common to the drain electrode D1, and as a result, the cathode K1 of the diode BD0 is also connected to the conductive pattern 220.

[0051] Moreover, a cathode K0 of a diode SBD0 is attached to the conductive pattern 220 via a bonding material 251. Furthermore, a positive electrode terminal P is attached to the conductive pattern 220 via a bonding material.

[0052] Here, the anode A0 formed on the front surface of the diode SBD0 and the source electrode S1 formed on the front surface of the NMOS transistor M0 are electrically connected via a wire W1. Since the anode A1 of the diode BD0 is common to the source electrode S1, the anode A1 of the diode BD0 and the anode A0 of the diode SBD0 are consequently connected via the wire W1.

[0053] 6 is a diagram for explaining a wiring pattern conceptually generated in the conductive pattern 220. In the conductive pattern 220, for example, a current from the cathode K1 of the diode BD0 flows along a path P10 between the cathode K1 and the positive terminal P. Also, a current from the cathode K0 of the diode SBD0 flows along a path P11 between the cathode K0 and the positive terminal P. Therefore, in the conductive pattern 220, wiring patterns corresponding to the paths P10 and P11 are generated.

[0054] Hereinafter, in this embodiment, the wiring pattern corresponding to the path P10 is referred to as the wiring pattern C10, and the wiring pattern corresponding to the path P11 is referred to as the wiring pattern C11. Since the path P11 is longer than the path P10, the wiring pattern C11 is longer than the wiring pattern C10. Therefore, the inductance of the wiring pattern C11 is larger than the inductance of the wiring pattern C10.

[0055] In addition, since the NMOS transistor M1 and the diode SBD1 are also implemented in the conductive pattern 220 in the same manner as the NMOS transistor M0 and the diode SBD0, detailed description thereof will be omitted here. Also, although the "wiring pattern" here refers to wiring conceptually formed in a part of the conductive pattern, it may be wiring that is actually formed as a pattern.

[0056] <<Conductive pattern 230>> 4 is a pattern electrically connected to the output terminal U. More specifically, it is a pattern to which a wire is connected from a conductive pattern 320 (described later) on which the output terminal U is mounted. The conductive pattern 230 is connected to the source electrode S1 of the NMOS transistor M0 and the anode A1 of the diode BD0 via a wire W0. And the wire W1 from the source electrode S1 is connected to the anode A0 of the diode SBD0.

[0057] <<Laminated substrate 111 on the lower arm side>> The laminated substrate 111 is a DBC substrate on which elements of the lower arm are mounted. Since the laminated substrate 111 has a similar configuration to the laminated substrate 110, detailed description will be omitted. However, the laminated substrate 111 has conductive patterns 310, 320, and 330 formed on the front surface of the insulating plate 300.

[0058] <<Conductive pattern 310>> A control terminal IN2 to which a signal for controlling the switching element of the lower arm is input is mounted on the conductive pattern 310. The control terminal IN2 is attached to the conductive pattern 310 via a bonding material (e.g., solder). The conductive pattern 310 is connected to the gate electrode G2 of the NMOS transistor M2 via a wire, and is also connected to the gate electrode of the NMOS transistor M3 via a wire.

[0059] In the lower arm, the connection relationship between the NMOS transistor M2 and the diode SBD2 and the output terminal U, the negative terminal N, and the control terminal IN2 is the same as the connection relationship between the NMOS transistor M3 and the diode SBD3 and the output terminal U, the negative terminal N, and the control terminal IN2. Therefore, the following description will focus on the NMOS transistor M2 and the diode SBD2.

[0060] <<Conductive pattern 320>> An output terminal U to which a load is connected, NMOS transistors M2 and M3, and diodes SBD2 and SBD3 are mounted on the conductive pattern 320. Note that the connection relationship between these elements and the conductive pattern 320 is the same as the connection relationship between the NMOS transistor M0 and diode SBD0 and the conductive pattern 220 described in FIG.

[0061] Specifically, the drain electrode D2 on the back surface side of the NMOS transistor M2 and the cathode K2 common to the drain electrode D2 are connected to the conductive pattern 320 via a bonding material. Also, the cathode K3 formed on the back surface of the diode SBD2 is connected to the conductive pattern 320 via a bonding material. Furthermore, an output terminal U is attached to the conductive pattern 320 via a bonding material.

[0062] Here, the anode A3 formed on the front surface of the diode SBD2 and the source electrode S2 formed on the front surface of the NMOS transistor M2 are electrically connected via a wire W3. Since the anode A2 of the diode BD2 is common to the source electrode S2, the anode A3 of the diode SBD2 and the anode A2 of the diode BD2 are consequently connected via the wire W3.

[0063] In this case, the distance from the cathode K3 of the diode SBD2 to the output terminal U is longer than the distance from the cathode K2 of the diode BD2 to the output terminal U. Therefore, the inductance of the wiring pattern from the output terminal U to the diode SBD2 is greater than the inductance of the wiring pattern from the output terminal U to the diode BD2. Here, the "distance (or path)" from the output terminal U to the cathode K3 of the diode SBD2 is determined by, for example, the center of the electrode of the cathode K3 and the center of the output terminal U.

[0064] It should be noted that the NMOS transistor M3 and the diode SBD3 are connected to the conductive pattern 320 in a configuration similar to that of the NMOS transistor M2 and the diode SBD2, and therefore a detailed description thereof will be omitted here.

[0065] <<Conductive pattern 330>> A negative terminal N on the ground side is mounted on the conductive pattern 330. The negative terminal N is attached to the conductive pattern 330 via a bonding material (e.g., solder). The conductive pattern 330 is connected to the source electrode S2 of the NMOS transistor M2 via a wire W2, and is connected to the source electrode of the NMOS transistor M3 via a wire.

[0066] <<About the current from output terminal U to positive terminal P>> Here, the current from the output terminal U to the positive terminal P in the semiconductor module 80 will be described with reference to Fig. 7 and Fig. 8. The current from the output terminal U flows to the source electrode S1 of the NMOS transistor M0 (anode A1 of the diode BD0) via the conductive pattern 320, the wire connected between the conductive pattern 320 and the conductive pattern 230, the conductive pattern 230, and the wire W0. The current from the wire W0 is supplied to the anode A0 of the diode SBD0 via the wire W1.

[0067] Here, the wiring from the output terminal U to the source electrode S1 (anode A1 of the diode BD0) of the NMOS transistor M0 can be equivalently represented as the wiring 50 in Fig. 8. Also, the wire W1 from the source electrode S1 to the anode A0 of the diode SBD0 can be equivalently represented as the wiring 51. Note that the configurations denoted by the same reference numerals in Fig. 8 and Fig. 2 are the same.

[0068] 8, and the wiring pattern C11 from the cathode K1 to the positive terminal P. The current supplied to the anode A0 of the diode SBD0 flows to the positive terminal P through the cathode K0 on the back surface and the wiring pattern C10 in FIG. 6. The wiring pattern C10 from the cathode K1 to the positive terminal P can be equivalently represented as the wiring 55 in FIG. 8, and the wiring pattern C11 from the cathode K0 to the positive terminal P can be equivalently represented as the wiring 53 in FIG.

[0069] In this embodiment, the inductance of the wiring of the path P2 in Fig. 8 is increased so that the condition of formula (3) is satisfied. Specifically, for example, the inductances Lb and Ld are increased so that the difference between the inductance (La+Lb+Ld) of the path P2 and the inductance (La+Lj) of the path P1 is 0.18 nH or more.

[0070] As a result, of the current from the output terminal U, the current i1 supplied to the source electrode S1 (anode A1 of diode BD0) on the front surface of the NMOS transistor M0 flows from the anode A1 on the front surface of the diode BD0 through the diode BD0 to the cathode K1 on the back surface, and then flows to the positive terminal P through the wiring pattern C10 in the conductive pattern 220. Also, the current i2 supplied to the anode A0 on the front surface of the diode SBD0 flows from the anode A0 on the front surface of the diode SBD0 through the diode SBD0 to the cathode K0 on the back surface, and then flows to the positive terminal P through the wiring pattern C11 in the conductive pattern 220.

[0071] Thus, in this embodiment, even if a large current flows from the output terminal U, the current flows through both diodes BD0 and SBD0, so that it is possible to prevent the diode SBD0 from being destroyed. Note that in the semiconductor module 80, the wiring member provided on the path P1 (for example, the wire W0 or the wiring pattern C10 in the conductive pattern 220) corresponds to the "first wiring member," and the wiring member provided on the path P2 (for example, the wires W0, W1 or the wiring pattern C11 in the conductive pattern 220) corresponds to the "second wiring member."

[0072] <<About the current from the negative terminal N to the output terminal U>> Next, the current from the negative terminal N to the output terminal U in the semiconductor module 80 will be described with reference to Figures 9 and 10. The current from the negative terminal N flows through the conductive pattern 330 and the wire W2 to the source electrode S2 of the NMOS transistor M2 (the anode A2 of the diode BD2). The current from the wire W2 is supplied to the anode A3 of the diode SBD2 through the wire W3.

[0073] Here, the wire W2 connecting the negative terminal N and the source electrode S2 (anode A2 of diode BD2) of the NMOS transistor M2 can be equivalently represented as the wiring 60 in Fig. 10. The wire W3 connecting the source electrode S2 of the NMOS transistor M2 and the anode A3 of the diode SBD2 can be equivalently represented as the wiring 61 in Fig. 10. Similarly to Fig. 6, the wiring pattern from the cathode K2 to the output terminal U can be equivalently represented as the wiring 65, and the wiring pattern from the cathode K3 to the output terminal U can be equivalently represented as the wiring 63.

[0074] In this embodiment, the inductance of the wiring of the path P4 is increased so that the condition of the formula (3) is satisfied. Specifically, for example, the inductances Lf and Lh are increased so that the difference between the inductance (Le+Lf+Lh) of the path P4 and the inductance (Le+Ln) of the path P3 is 0.18 nH or more.

[0075] Therefore, of the current from the negative terminal N, current i3 supplied to source electrode S2 (anode A2 of diode BD2) on the front surface of NMOS transistor M2 flows from anode A2 on the front surface of diode BD2 through diode BD2 to cathode K2 on the back surface, and then flows to output terminal U through a wiring pattern (not shown) in conductive pattern 320. Current i4 supplied to anode A3 on the front surface of diode SBD2 flows from anode A3 on the front surface of diode SBD2 through diode SBD2 to cathode K3 on the back surface, and then flows to output terminal U through a wiring pattern (not shown) in conductive pattern 320.

[0076] As a result, in this embodiment, even if a large current flows from the negative terminal N, the current flows through both diodes BD2 and SBD2, so that the diode SBD2 can be prevented from being destroyed.

[0077] ===Other embodiments=== Here, for example, in order to prevent the diode SBD0 in the upper arm from being destroyed by a current, at least one of the inductance Lb of the wiring 51 and the inductance Ld of the wiring 53 in FIG. 2 should be increased.

[0078] <<When wiring 51 is realized by wire>> When the wiring 51 is realized by a wire, the inductance Lb can be increased by increasing the length of the wire, decreasing the cross-sectional area of ​​the wire, or increasing the curvature of the wire.

[0079] <<Adjust the length of the wire>> Fig. 11 is a diagram for explaining an embodiment in which the length of the wire is adjusted. In Fig. 11, the configurations denoted with the same reference numerals as in Fig. 4 are the same. Therefore, the following description will focus on the wire W10 to the NMOS transistor M0 and the wire W11 to the diode SBD0. In Fig. 11, the diode SBD0 is mounted at a position away from the NMOS transistor M0 in the conductive pattern 220.

[0080] The wire W10 connects the conductive pattern 230, which is electrically connected to the output terminal U, to the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0).

[0081] The wire W11 is longer than the wire W10, and connects the conductive pattern 230 and the anode A0 of the diode SBD0. Note that the wire W10 and the wire W11 are the same in terms of properties other than the length (e.g., the cross-sectional area of ​​the wire, the curvature of the wire), and therefore the inductance of the wire W11 is greater than the inductance of the wire W10.

[0082] Fig. 12 is a diagram showing the configuration of Fig. 11 in the form of an equivalent circuit. Here, the wiring including the conductive pattern 230 and the wire W10 connecting the output terminal U and the source electrode S1 (anode A1 of the diode BD0) of the NMOS transistor M0 can be equivalently expressed as a wiring 54. Also, the wire W11 connecting the output terminal U and the anode A0 of the diode SBD0 can be equivalently expressed as a wiring 51. Furthermore, the wiring pattern from the cathode K1 of the diode BD0 to the positive terminal P can be equivalently expressed as a wiring 55, and the wiring pattern from the cathode K0 of the diode SBD0 to the positive terminal P can be equivalently expressed as a wiring 53.

[0083] In such an embodiment, the inductance (Lb+Ld) of the path P2 is made larger than the inductance (Li+Lj) of the path P1, and the length of the wire W11 is made longer so that, for example, equation (3) is satisfied. As a result, even if a large current flows from the output terminal U, it is possible to prevent the diode SBD0 from being destroyed. Note that, in this embodiment, the wire W10 corresponds to the "first wire" and the wire W11 corresponds to the "second wire."

[0084] <<Adjusting the cross-sectional area of ​​the wire>> Fig. 13 is a diagram for explaining an embodiment in which the cross-sectional area of ​​the wire is adjusted. In Fig. 13, the configurations denoted by the same reference numerals as in Fig. 4 are the same. Therefore, the following description will focus on the wire W20 to the NMOS transistor M0 and the wire W21 to the diode SBD0.

[0085] The wire W20 is a wire having a larger cross-sectional area (i.e., a larger diameter) than the wire W21, and connects the conductive pattern 230 connected to the output terminal U to the source electrode S1 of the NMOS transistor M0 and the anode A1 of the diode BD0. For example, the wire W20 has a diameter of 400 μm, and the wire W21 has a diameter of 250 μm.

[0086] The wire W21 connects the conductive pattern 230 and the anode A0 of the diode SBD0. Since the wire W20 and the wire W21 have the same items other than the cross-sectional area (for example, the length of the wire, the curvature of the wire), the inductance of the wire W21 is larger than the inductance of the wire W20.

[0087] Since the connection relationship between the output terminal U and the positive terminal P in Fig. 13 is the same as the connection relationship between the output terminal U and the positive terminal P in Fig. 11, the equivalent circuit of the embodiment in Fig. 13 is also that in Fig. 12. Furthermore, when the cross-sectional area of ​​the wire W21 is reduced, the inductance Lb increases, and therefore, the breakdown of the diode SBD0 can be prevented.

[0088] In this embodiment, the number of wires W20 (four) is the same as the number of wires W21 (four), and wires W21 with a smaller cross-sectional area are used, but this is not limited to the above. For example, even if wires W20 and W21 with the same cross-sectional area are used and the number of wires W21 is less than the number of wires W20, the same effect as in this embodiment can be obtained. In this embodiment, wires W20 correspond to the "first wire" and wires W21 correspond to the "second wire."

[0089] <<Adjust the wire curvature>> Fig. 14 is a diagram for explaining an embodiment in which the curvature of the wire is adjusted. In Fig. 14, the configurations denoted by the same reference numerals as in Fig. 4 are the same. Therefore, the following description will focus on the wire W30 to the NMOS transistor M0 and the wire W31 to the diode SBD0.

[0090] The wire W30 connects the conductive pattern 230, which is connected to the output terminal U, to the source electrode S1 of the NMOS transistor M0 and the anode A1 of the diode BD0.

[0091] The wire W31 has a larger curvature than the wire W30, and connects the conductive pattern 230 and the anode A0 of the diode SBD0. When the curvature (degree of bending) of the wire W31 increases, the length of the wire W31 also increases. Here, since the cross-sectional area of ​​the wires W30 and W31 is the same, for example, the inductance of the wire W31 is larger than the inductance of the wire W30.

[0092] Since the connection relationship between the output terminal U and the positive terminal P in FIG. 14 is the same as that between the output terminal U and the positive terminal P in FIG. 11, the equivalent circuit of the embodiment in FIG. 14 is also that in FIG. 12. For example, if the curvature of the wire W31 is increased, the inductance Lb increases, so that the breakdown of the diode SBD0 can be prevented. Here, the wire W30 corresponds to the "first wire" and the wire W31 corresponds to the "second wire."

[0093] <<When wiring 53 is realized by a wiring pattern>> Next, a case where the wiring 53 in Fig. 2 is realized by a wiring pattern will be described. Here, when the wiring 53 is realized by a wiring pattern, for example, the inductance Ld can be increased by lengthening the length of the wiring pattern, reducing the thickness of the wiring pattern, or narrowing the width of the wiring pattern. Note that increasing the inductance Ld by lengthening the wiring pattern has been described with reference to Fig. 6. Therefore, the remaining two methods will be described here.

[0094] <<Adjust the thickness and width of the wiring pattern>> Figures 15 and 16 are diagrams for explaining an embodiment in which the thickness and width of the wiring pattern are adjusted. In Figures 15 and 16, the configurations denoted by the same reference numerals as in Figures 4 and 5 are the same. Therefore, here, the conductive patterns 270, 280 and the wires W40 to W42 will be explained.

[0095] On the conductive pattern 270, a positive terminal P on the power supply side is mounted, and an NMOS transistor M0 is also mounted.

[0096] The conductive pattern 280 is thinner than the conductive pattern 270, and is a pattern on which a diode SBD0 is mounted. In the conductive pattern 280, the width Wx of the region between the region on which the diode SBD0 is mounted and the region to which the wire W40 is connected is narrow. The conductive patterns 270 and 280 are connected by the wire W40.

[0097] The wire W41 connects the conductive pattern 230, which is electrically connected to the output terminal U, to the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0).

[0098] The wire W42 connects the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0) and the anode A0 of the diode SBD0.

[0099] Here, a current from the conductive pattern 230 electrically connected to the output terminal U flows to the source electrode S1 (anode A1) via the wire W41. Then, a current from the source electrode S1 flows to the anode A0 via the wire W42. A current from the anode A1 flows to the positive electrode terminal P via the diode BD0, the cathode K1 on the back side, and the wiring pattern C21 in the conductive pattern 270. Also, a current from the anode A0 flows to the positive electrode terminal P via the diode SBD0, the cathode K2 on the back side, the wiring pattern C20, the wire W40, and the conductive pattern 270. Therefore, the embodiment of FIG. 15 can be expressed by the equivalent circuit shown in FIG. 8, similar to the embodiment of FIG. 4.

[0100] In this embodiment, the conductive pattern 280 on which the path P20 is formed is thinner than the conductive pattern 270, and the width Wx of the path P20 is also narrower. Therefore, the inductance of the wiring pattern C20 conceptually formed on the path P20 is larger than the inductance of the wiring pattern C21 conceptually formed on the path P21. Therefore, by using the wiring pattern C20 with a large inductance, the inductance Ld of the wiring 53 in FIG. 8 can be made large. As a result, by using the configuration shown in FIGS. 15 and 16, it is possible to prevent the breakdown of the diode SBD0.

[0101] <<Other configuration examples of a part of a semiconductor module>> Fig. 17 is a diagram showing the configuration of an element of the upper arm of a semiconductor module. The configurations denoted by the same reference numerals in Fig. 17 and Fig. 4 are the same. Therefore, the following description will focus on conductive patterns 290, 291 and wires W50, W51.

[0102] The conductive pattern 290 is a pattern on which the output terminal U is mounted, and a wire W50 connects the conductive pattern 290 and the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0).

[0103] The conductive pattern 291 is a pattern on which the positive terminal P, the NMOS transistor M0, and the diode SBD0 are mounted. The wire W51 connects the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0) and the anode A0 of the diode SBD0.

[0104] Fig. 18 is a diagram showing the configuration of Fig. 17 in the form of an equivalent circuit. Here, the wiring including the conductive pattern 290 and the wire W50 connecting the output terminal U and the source electrode S1 (anode A1 of the diode BD0) of the NMOS transistor M0 can be equivalently expressed as a wiring 50. Also, the wire W51 connecting the source electrode S1 (anode A1 of the diode BD0) of the NMOS transistor M0 and the anode A0 of the diode SBD0 can be equivalently expressed as a wiring 51. Furthermore, the wiring pattern from the cathode K0 of the diode SBD0 to the cathode K1 of the diode BD0 can be equivalently expressed as a wiring 53, and the wiring pattern from the cathode K1 of the diode BD0 to the positive terminal P can be equivalently expressed as a wiring 52.

[0105] In such an embodiment, the inductance (La+Lb+Lc+Ld) of the path P2 is always greater than the inductance (La+Lc) of the path P1. In this embodiment, the length of the wire W51 is increased, for example, so that the relationship Lb+Ld>0.18 nH is satisfied. As a result, even if a large current flows from the output terminal U, the diode SBD0 can be prevented from being destroyed. Here, the wire W50 corresponds to the "first wire," and the wires W50 and W51 correspond to the "second wire."

[0106] Fig. 19 is a diagram showing the configuration of the elements of the lower arm of the semiconductor module. The configurations denoted with the same reference numerals in Fig. 19 are the same as those in Fig. 4. Therefore, the following description will focus on the conductive patterns 340 and 341 and the wires W60 and W61.

[0107] The conductive pattern 340 is a pattern on which the negative terminal N is mounted, and the wire W60 connects the conductive pattern 340 to the source electrode S2 (anode A2 of the diode BD2) of the NMOS transistor M2. Also, the wire W61 connects the conductive pattern 340 to the anode A3 of the diode SBD2.

[0108] The conductive pattern 341 is a pattern on which the output terminal U, the NMOS transistor M2, and the diode SBD2 are mounted.

[0109] Fig. 20 is a diagram showing the configuration of Fig. 19 in the form of an equivalent circuit. Here, the wiring pattern conceptually formed from the negative terminal N to a position O in the conductive pattern 340 can be equivalently expressed as a wiring 60. Note that the position O is a position in the conductive pattern 340 where the current from the negative terminal N is conceptually divided into the NMOS transistor M2 and the diode SBD2, and corresponds to the node x2.

[0110] The wiring pattern from position O to the source electrode S2 (anode A2 of diode BD2) of NMOS transistor M2 and the wiring including wire W60 can be equivalently represented as wiring 64. The wiring pattern from position O to the anode A3 of diode SBD2 and the wiring including wire W61 can be equivalently represented as wiring 61. Furthermore, the wiring pattern from the cathode K3 of diode SBD2 to the cathode K2 of diode BD2 can be equivalently represented as wiring 63, and the wiring pattern from the cathode K2 of diode BD2 to the output terminal U can be equivalently represented as wiring 62.

[0111] In such an embodiment, for example, the length of the wire W61 is increased so that the inductance (Le+Lf+Lg+Lh) of the path P4 is greater than the inductance (Le+Lm+Lg) of the path P3. As a result, even if a large current flows from the negative terminal N, the diode SBD2 can be prevented from being destroyed. Note that, also in this embodiment, it is preferable that (Lf+Lh)-Lm>0.18nH, and it is more preferable that (Lf+Lh)-Lm>0.36nH. In this way, by making (Lf+Lh) larger, it is possible to make the current flowing through the diode SBD2 smaller, even if, for example, there is variation in the inductance of the wire W60 or the characteristics of the elements.

[0112] ===Summary=== The electronic circuit 10 and the semiconductor module 80 of this embodiment have been described above. As illustrated in Fig. 2, the inductance of the path P2 in the electronic circuit 10 is larger than the inductance of the path P1. Therefore, the current from the output terminal U flows not only through the diode SBD0 of the path P2 but also through the diode BD0 of the path P1. Therefore, in the electronic circuit 10, it is possible to prevent a large current from flowing through the diode SBD0, which is a freewheeling diode, and thus prevent it from being destroyed.

[0113] Moreover, a general bipolar transistor may be used as the switching element. The same effect as in this embodiment can be obtained by connecting a PN diode having a PN junction and a Schottky diode having a Schottky junction to the bipolar transistor as a freewheeling diode. However, in this embodiment, an NMOS transistor M0 is used as the switching element. Therefore, the parasitic diode (body diode) of the NMOS transistor M0 can be used as the freewheeling diode without providing a separate PN diode.

[0114] In addition, the NMOS transistor M0 and the diode SBD0 having a Schottky junction are elements using wide band gap semiconductors, so that in this embodiment, the withstand voltage of the electronic circuit 10 can be improved while the loss when driving a load can be reduced.

[0115] Moreover, a diode SBD0 having a Schottky junction is connected in anti-parallel to the NMOS transistor M0 so as to operate as a freewheeling diode when the NMOS transistor M0 is off.

[0116] Moreover, the semiconductor module 80 is a device including the electronic circuit 10 in which the inductance of the path P2 via the SBD0 is larger than the inductance of the path P1 via the NMOS transistor M0. Therefore, when such a semiconductor module 80 is used, the diode SBD0 having a Schottky junction can be protected from a large current.

[0117] 4, in the semiconductor module 80, the wire W0 from the conductive pattern 230 is connected to a diode BD0 having a PN junction, and the wire W1 from the diode BD0 is connected to a diode SBD0 having a Schottky junction. Therefore, the inductance from the conductive pattern 230 to the diode SBD0 can be made larger than the inductance from the conductive pattern 230 to the diode BD0.

[0118] 7, the conductive pattern 230 and the diode SBD0 may be connected using a wire W11 that is longer than the wire W10. Even in this case, the inductance from the conductive pattern 230 to the diode SBD0 can be made larger than the inductance from the conductive pattern 230 to the diode BD0.

[0119] 8, the conductive pattern 230 and the diode SBD0 may be connected using a wire W21 having a smaller cross-sectional area than the wire W20. Even in this case, the inductance from the conductive pattern 230 to the diode SBD0 can be made larger than the inductance from the conductive pattern 230 to the diode BD0.

[0120] 9, the conductive pattern 230 and the diode SBD0 may be connected using a wire W31 having a larger curvature than the wire W30. Even in this case, the inductance from the conductive pattern 230 to the diode SBD0 can be made larger than the inductance from the conductive pattern 230 to the diode BD0.

[0121] In addition, in the semiconductor module 80, the U terminal (or the conductive pattern 230 connected to the U terminal), the NMOS transistor M0, and the diode SBD0 are arranged in this order along the longitudinal direction (predetermined direction) of the semiconductor module 80. That is, the NMOS transistor M0 is provided between the U terminal and the diode SBD0. If the U terminal, the diode SBD0, and the NMOS transistor M0 are arranged in this order along the longitudinal direction, the inductance of the wiring between the output terminal U and the diode SBD0 is generally smaller than the inductance of the wiring between the U terminal and the diode BD0. However, by arranging each element in the order of this embodiment, the inductance of the wiring between the U terminal and the diode SBD0 can be made larger than the inductance of the wiring between the U terminal and the diode BD0, which is a parasitic element.

[0122] Furthermore, in the semiconductor module 80, of the wires (e.g., wires W0 and W1) that connect the U terminal and diode SBD0, wire W0 is used as the wire that connects the U terminal and diode BD0. In such a case, the inductance of the wire that connects the U terminal and diode SBD0 is necessarily greater than the inductance of the wire that connects the U terminal and diode BD0. In the semiconductor module 80, wires W0 and W1 correspond to the "second wire," and wire W0 corresponds to the "first wire."

[0123] Also, for example, in order to increase the inductance of the path P2, the inductance of the wiring pattern may be increased instead of the wire. Even in such a case, the diode SBD0 can be protected.

[0124] 6, when the path P2 includes a wiring pattern C11 that is longer than the wiring pattern C10, the inductance of the path P2 can be increased. Note that the wiring pattern C10 corresponds to the "first wiring pattern" and the wiring pattern C11 corresponds to the "second wiring pattern."

[0125] 11, the thickness of the conceptually formed wiring pattern C20 may be made thinner than the thickness of the wiring pattern C21. Even in this case, the inductance of the path P2 can be increased.

[0126] Also, for example, as shown in FIG. 10, the inductance of the path P2 can be increased even if the width Wx of the wiring pattern C20 is narrowed.

[0127] As shown in FIG. 6, the wiring pattern C10 is determined based on the distance between the positive terminal P of the conductive pattern 220 and the diode BD0, and the wiring pattern C11 is determined based on the distance between the positive terminal P of the conductive pattern 220 and the diode BD0.

[0128] Furthermore, in the semiconductor module 80, a conductive pattern 220 on which a positive electrode P terminal is mounted is provided between a conductive pattern 210 on which a control terminal IN1 is mounted and a conductive pattern 230 electrically connected to an output terminal U. The conductive pattern 220 corresponds to the "first conductive pattern", the conductive pattern 230 corresponds to the "second conductive pattern", and the conductive pattern 210 corresponds to the "third conductive pattern".

[0129] The above-mentioned embodiment is for the purpose of facilitating understanding of the present invention, and is not intended to limit the present invention. Furthermore, the present invention can be modified or improved without departing from the spirit of the present invention, and it goes without saying that the present invention includes equivalents thereof. [Explanation of symbols]

[0130] 10 Electronic circuit 50~55,60~65 Wiring 80 Semiconductor Module 100 Base plate 101,250,251,252 Bonding material 110,111 Multilayer board 200 Insulating plate 201 Heat sink 210,220,230,270,280,290,291,310,320,330,340,341 Conductive pattern M0~M3 NMOS transistors BD0~BD3, SBD0~SBD3 Diodes G1, G2 gate electrodes S1, S2 source electrodes D1, D2 Drain electrodes K0~K3 Cathode electrodes A0~A3 Anode electrodes La~Lj,Lm,Ln Inductance C10, C11 wiring pattern P1~P4, P20, P21 route W0~W3,W10,W11,W20,W21,W30,W31,W40~W42,W50,W51,W60,W61 Wire O position P positive terminal U Output terminal N negative terminal IN1, IN2 control terminal

Claims

1. a first diode having a PN junction whose forward voltage is a first voltage; a second diode having a Schottky junction whose forward voltage is a second voltage smaller than the first voltage; a first wiring member connecting a first terminal and a second terminal via the first diode; a second wiring member that is connected between the first terminal and the second terminal via the second diode and has an inductance larger than an inductance of the first wiring member; Including, the first diode is a parasitic diode included in a switching element, the switching element and the second diode are elements using wide band gap semiconductors, When a first path is from the first terminal through the first wiring member to the second terminal, and a second path is from the first terminal through the second wiring member to the second terminal, a difference between an inductance of the second wiring member and an inductance of the first wiring member is greater than a product of a difference between the first voltage and the second voltage and an inverse of a time change of a current in the first path or the second path, a time change in current of the first path or the second path is 0.1 to 10 A / nsec; the second diode is connected in anti-parallel to the switching element; The first diode is When a current flows from the first terminal, a current flowing through the second diode is reduced from the current flowing from the first terminal. electronic circuit.

2. 2. The electronic circuit of claim 1, a difference between the inductance of the second wiring member and the inductance of the first wiring member is greater than 0.18 nH; electronic circuit.

3. The electronic circuit according to claim 1 comprises: A plurality of the resistors are provided in parallel between the first terminal and the second terminal. electronic circuit.

4. The electronic circuit according to claim 1 comprises: Used as one element in a bridge circuit, electronic circuit.

5. A semiconductor module comprising the electronic circuit according to any one of claims 1 to 4.

6. A semiconductor module according to claim 5, the first wiring member includes a first wire provided between the first terminal and the first diode, the second wiring member is provided between the first terminal and the second diode and includes a second wire having an inductance greater than an inductance of the first wire; Semiconductor module.

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