Integrated circuit element and method of manufacture thereof

Abstract

To provide an integrated circuit device and a method of manufacturing the same.SOLUTION: An integrated circuit device includes: a plurality of word line structures extending on a substrate in a horizontal direction that is parallel to a main surface of the substrate and overlapping with each other in a vertical direction that is perpendicular to the main surface; a plurality of insulating films stacked alternately with the plurality of word line structures and extending in the horizontal direction; a blocking dielectric film extending while covering the plurality of word line structures and the plurality of insulating films in a channel hole that penetrates through the plurality of word line structures and the plurality of insulating films; a plurality of charge storage films spaced apart from each other corresponding to respective word line structures on the blocking dielectric film in the channel hole, each of the plurality of charge storage films including a first charge storage film on the blocking dielectric film and a second charge storage film covering the first charge storage film. A surface of the second charge storage film that is opposite to the blocking dielectric film has a concave shape toward the blocking dielectric film in the middle portion thereof further than from an upper portion and a lower portion thereof.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an integrated circuit device and a method for manufacturing the same, and more particularly to an integrated circuit device having a non-volatile vertical memory device and a method for manufacturing the same. [Background technology]

[0002] As integrated circuit devices become larger and more highly integrated, vertical memory devices have been proposed that increase memory capacity by stacking a plurality of memory cells vertically on a substrate. When the cell stacking density in the vertical direction is increased in the vertical memory device, the vertical height of each memory cell and the spacing between adjacent memory cells in the vertical direction are reduced, which may result in insufficient charge being stored in the memory cells or interference between adjacent memory cells, resulting in reduced reliability of the integrated circuit device. Summary of the Invention [Problem to be solved by the invention]

[0003] The technical objective of the present invention is to provide an integrated circuit device having a structure that can store sufficient charge in each memory cell and suppress interference between adjacent memory cells to improve reliability even when the vertical height of each memory cell and the spacing between adjacent memory cells in the vertical direction are relatively small in a highly scaled vertical memory device, and a method for manufacturing the same. [Means for solving the problem]

[0004] In order to achieve the above technical objectives, the present invention provides an integrated circuit device and a method for manufacturing the same, as described below.

[0005] and a blocking dielectric layer extending in a channel hole penetrating the wordline structures and the insulating layers and covering the wordline structures and the insulating layers. A plurality of charge storage layers are disposed in the channel hole on the blocking dielectric layer to correspond to the wordline structures, the plurality of charge storage layers being spaced apart from each other, the plurality of charge storage layers being disposed in the channel hole on the blocking dielectric layer and spaced apart from each other, the plurality of charge storage layers being ...

[0006] The integrated circuit device according to the present invention includes a plurality of word line structures extending on a substrate in a horizontal direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface, a plurality of insulating films interposed between each of the plurality of word line structures and extending in the horizontal direction, a channel film extending in the vertical direction within a channel hole penetrating the plurality of word line structures and the plurality of insulating films, a blocking dielectric film extending in the channel hole while covering the plurality of word line structures and the plurality of insulating films, the blocking dielectric film having a surface facing the channel film with a plurality of grooves corresponding to each of the plurality of word line structures, and a plurality of charge storage films at least portions of which are disposed in the plurality of grooves of the blocking dielectric film.

[0007] an integrated circuit device according to the present invention includes a substrate, a plurality of word line structures extending in a horizontal direction parallel to a main surface of the substrate and overlapping each other along a vertical direction perpendicular to the main surface; a plurality of insulating films interposed between each of the plurality of word line structures and extending in the horizontal direction; a channel film extending in the vertical direction within a channel hole penetrating the plurality of word line structures and the plurality of insulating films; a blocking dielectric film extending in the channel hole while covering the plurality of word line structures and the plurality of insulating films; at least one charge storage film disposed on the blocking dielectric film within the channel hole; a tunneling dielectric film covering the blocking dielectric film and the at least one charge storage film within the channel hole; and a channel film covering the tunneling dielectric film, wherein sidewalls of the plurality of insulating films facing the channel film protrude beyond sidewalls of the plurality of word line structures, and a surface of the blocking dielectric film facing the channel film has a plurality of grooves corresponding to each of the plurality of word line structures, and at least a portion of the at least one charge storage film is disposed in the plurality of grooves of the blocking dielectric film.

[0008] A method for manufacturing an integrated circuit device according to the present invention includes the steps of: forming a structure in which a plurality of first films and a plurality of second films are alternately stacked one layer at a time on a substrate; forming a channel hole penetrating the structure; removing a portion of the plurality of second films in the channel hole to form a plurality of indent spaces communicating with the channel hole; forming a blocking dielectric film in the channel hole, the blocking dielectric film extending while covering the plurality of first films and the plurality of second films, and having a plurality of grooves corresponding to the plurality of indent spaces; and forming at least one charge storage film consisting of a first charge storage film filling at least a portion of the plurality of grooves and a second charge storage film covering the first charge storage film. Effect of the Invention

[0009] In an integrated circuit device according to the technical concept of the present invention, a charge storage layer is disposed in a channel hole, so that a sufficient charge can be stored in a memory cell and interference between adjacent memory cells can be prevented.

[0010] Furthermore, the method for manufacturing an integrated circuit device according to the technical concept of the present invention can implement various heights and / or thicknesses of the charge storage layer, thereby manufacturing an integrated circuit device with ensured reliability. [Brief description of the drawings]

[0011] [Figure 1] 1 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept; [Diagram 2] 1 is a plan view illustrating major components of an integrated circuit device according to an embodiment of the inventive concept; [Diagram 3] 3 is a cross-sectional view taken along the line X1-X1' in FIG. 2. [Figure 4A] FIG. 4 is an enlarged cross-sectional view of the dotted line area indicated by P1 in FIG. [Figure 4B] FIG. 4 is an enlarged cross-sectional view of the dotted line area indicated by P1 in FIG. [Figure 4C] FIG. 4 is an enlarged cross-sectional view of the dotted line area indicated by P1 in FIG. [Figure 4D] FIG. 4 is an enlarged cross-sectional view of the dotted line area indicated by P1 in FIG. [Figure 4E] FIG. 4 is an enlarged cross-sectional view of the dotted line area indicated by P1 in FIG. [Figure 4F] FIG. 4 is an enlarged cross-sectional view of the dotted line area indicated by P1 in FIG. [Figure 4G] FIG. 4 is an enlarged cross-sectional view of the dotted line area indicated by P1 in FIG. [Figure 5A] 1A to 1C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5B] 1A to 1C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5C]2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5D] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5E] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5F] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5G] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5H] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5I] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5J] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5K] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5L] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5M] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5N] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5O] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 5P] 2A to 2C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention; [Figure 6A] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6B] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 6C] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 6D] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 7A] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7B] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7C] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7D] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7E] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7F] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7G] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7H] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7I] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 7J] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 8A] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 8B] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 8C] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 8D] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 9A] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 9B] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 10A] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 10B] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 10C] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 10D] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 11] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 12A] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12B]4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12C] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 12D] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 13] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 14A] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 14B] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 15] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 16A] 4A to 4C are enlarged cross-sectional views illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 16B] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 17] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 18] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 19] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 20] 2 is an enlarged cross-sectional view of an integrated circuit device according to another embodiment of the present invention; [Figure 21] 1 is a cross-sectional view of yet another integrated circuit device according to an embodiment of the present invention, specifically, a cross-sectional view taken along line X1-X1' of FIG. [Figure 22] 22 is an enlarged cross-sectional view of the dotted line area indicated by P2 in FIG. 21. [Figure 23A] 10A to 10C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing yet another integrated circuit device according to an embodiment of the present invention; [Figure 23B] 10A to 10C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing yet another integrated circuit device according to an embodiment of the present invention; [Figure 23C] 10A to 10C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing yet another integrated circuit device according to an embodiment of the present invention; [Figure 23D] 10A to 10C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing yet another integrated circuit device according to an embodiment of the present invention; [Figure 23E] 10A to 10C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing yet another integrated circuit device according to an embodiment of the present invention; [Figure 23F] 10A to 10C are enlarged cross-sectional views illustrating a process sequence for explaining a method of manufacturing yet another integrated circuit device according to an embodiment of the present invention; [Figure 24A] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 24B] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 24C] 11 is an enlarged cross-sectional view illustrating an integrated circuit device according to still another embodiment of the present invention; FIG. [Figure 25A] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 25B] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 25C] 11 is an enlarged cross-sectional view illustrating an integrated circuit device according to still another embodiment of the present invention; FIG. [Figure 26A] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 26B] 11 is an enlarged cross-sectional view illustrating an integrated circuit device according to still another embodiment of the present invention; FIG. [Figure 27A] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 27B] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 27C] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 27D] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 27E] 11 is an enlarged cross-sectional view illustrating an integrated circuit device according to still another embodiment of the present invention; FIG. [Figure 28A] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 28B] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 28C] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 28D] 11A to 11C are enlarged cross-sectional views illustrating a method of manufacturing an integrated circuit device according to still another embodiment of the present invention. [Figure 28E] 11 is an enlarged cross-sectional view illustrating an integrated circuit device according to still another embodiment of the present invention; FIG. [Figure 29] 4 is a planar layout diagram of a main region of an integrated circuit device according to still another embodiment of the present invention; [Figure 30A] 1 is a schematic perspective view of an integrated circuit device according to still another embodiment of the present invention; [Figure 30B] 30B is a schematic cross-sectional view of the integrated circuit element illustrated in FIG. 30A. [Diagram 31] 1 is a schematic perspective view illustrating an integrated circuit device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] 1 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the technical concept of the present invention, which illustrates an equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure.

[0013] 1, the memory cell array MCA includes a plurality of memory cell strings MS. The memory cell array MCA includes a plurality of bit lines BL (BL1, BL2, ..., BLm), a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. A plurality of memory cell strings MS are formed between the plurality of bit lines BL (BL1, BL2, ..., BLm) and the common source line CSL.

[0014] Each of the memory cell strings MS includes a string select transistor SST, a ground select transistor GST, and a number of memory cell transistors MC1, MC2, ..., MCn-1, MCn. The drain regions of the string select transistors SST are connected to bit lines BL (BL1, BL2, ..., BLm), and the source regions of the ground select transistors GST are connected to a common source line CSL. The common source line CSL may be a region where the source regions of the ground select transistors GST are commonly connected.

[0015] The string selection transistor SST is connected to a string selection line SSL, and the ground selection transistor GST is connected to a ground selection line GSL. The memory cell transistors MC1, MC2, ..., MCn-1, MCn are respectively connected to a plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn).

[0016] FIG. 2 is a plan view showing the main components of an integrated circuit device according to an embodiment of the technical concept of the present invention, FIG. 3 is a cross-sectional view taken along line X1-X1' in FIG. 2, and FIGS. 4A to 4G are enlarged cross-sectional views of the dotted area indicated by P1 in FIG. 3.

[0017] 2 and 3, an integrated circuit device 100 includes a substrate 102 having an active area AC. A memory cell array MCA is formed on the active area AC of the substrate 102. The memory cell array MCA may have a circuit configuration as described with reference to FIG.

[0018] The substrate 102 has a main surface 102M extending in a first direction (X direction) and a second direction (Y direction) that are horizontal. In one embodiment, the substrate 102 includes Si, Ge, or SiGe. In another embodiment, the substrate 102 includes a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0019] 1 to 3, a plurality of memory cell transistors MC1, MC2, ..., MCn-1, MCn constituting a memory cell string MS in a memory cell array MCA are serially connected along a third direction (Z direction) perpendicular to a main surface 102M of a substrate 102. A string selection transistor SST, a ground selection transistor GST, and a plurality of channel structures CHS required for constituting the plurality of memory cell transistors MC1, MC2, ..., MCn-1, MCn are formed to extend in the third direction (Z direction) perpendicular to the main surface 102M of the substrate 102. The plurality of channel structures CHS are arranged spaced apart from each other at predetermined intervals along a first direction (X direction) and a second direction (Y direction).

[0020] Each of the channel structures CHS includes a semiconductor pattern 120 adjacent to the substrate 102 and partially filling the channel hole CHH, a channel film 150 adjacent to the semiconductor pattern 120 and extending in a third direction (Z direction) in the channel hole CHH, a buried insulating film 156 filling an internal space of the channel film 150, and a drain region 158 in contact with the channel film 150 and filling an upper portion of the inlet side of the channel hole CHH. In one embodiment, the channel film 150 has a cylindrical shape having an internal space, and the internal space of the channel film 150 is filled with the buried insulating film 156. The channel film 150 is made of polysilicon doped with impurities or polysilicon not doped with impurities. The buried insulating film 156 is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the buried insulating film 156 can be omitted, in which case the channel film 150 has a pillar structure without an internal space. The drain region 158 is made of a polysilicon film doped with impurities. The drain regions 158 included in the channel structures CHS are insulated from each other by an insulating pattern 114. The insulating pattern 114 is made of an oxide film, a nitride film, or a combination thereof.

[0021] A blocking dielectric layer 125, a charge storage layer 130, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially disposed in the channel hole CHH, and a drain region 158 is filled in the upper portion of the inlet side of the channel hole CHH.

[0022] In the channel hole CHH, the blocking dielectric layer 125, the tunneling dielectric layer 140, and the channel layer 150 each have a cylindrical shape. In the channel hole CHH, the charge storage layers 130 each have a ring shape or a cylindrical shape spaced apart from each other in a third direction (Z direction). The blocking dielectric layer 125, the tunneling dielectric layer 140, and the channel layer 150 each include a plurality of bent portions formed in a portion covering the plurality of word line structures WS and the plurality of insulating layers 110.

[0023] During the process of forming the blocking dielectric layer 125, the charge storage layer 130, and the tunneling dielectric layer 140, a portion of the top surface of the semiconductor pattern 120 is removed to form a recessed surface 120R on the top surface of the semiconductor pattern 120. The channel layer 150 contacts the recessed surface 120R of the semiconductor pattern 120.

[0024] The multiple word line structures WS extend along the XY plane on the substrate 102 in a horizontal direction parallel to the main surface 102M, and are arranged so as to be spaced apart from each other and overlap each other in a third direction (Z direction) perpendicular to the main surface 102M of the substrate 102.

[0025] The width of the word line structures WS in a first direction (X direction) is defined by the word line cut regions WLC. The word line structures WS are repeatedly arranged at regular intervals separated from each other by the word line cut regions WLC.

[0026] A plurality of common source regions 160 extend in the second direction (Y direction) in the substrate 102. In one embodiment, the plurality of common source regions 160 are impurity regions doped with a high concentration of n-type impurities. The plurality of common source regions 160 function as source regions that supply current to the vertical memory cells.

[0027] A portion of the plurality of word line cut regions WLC is filled with a common source line CSL. The common source line CSL extends in the second direction (Y direction) on the plurality of common source regions 160. An insulating spacer 170 is formed in the word line cut region WLC to cover a sidewall of the common source line CSL. The insulating spacer 170 serves to electrically insulate the common source line CSL from the plurality of word lines WL (WL1, WL2, ..., WLn-1, WLn). The common source line CSL and the insulating spacer 170 are covered with a capping insulating film 172. The common source line CSL is made of a metal such as tungsten, copper, or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, a transition metal such as titanium or tantalum, or a combination thereof. The insulating spacer 170 and the capping insulating film 172 are made of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof, respectively. In one embodiment, a metal silicide layer (not shown) for reducing contact resistance is interposed between the common source region 160 and the common source line CSL. For example, the metal silicide layer is made of cobalt silicide, tungsten silicide, nickel silicide, etc.

[0028] The upper insulating film 180 covers the insulating pattern 114, the drain region 158, and the capping insulating film 172. A string select line cut region SSLC defined by removing a part of the upper insulating film 180, a part of the insulating pattern 114, a part of at least two upper insulating films 110 among the plurality of insulating films 110, and a part of the upper two word line structures WS among the plurality of word line structures WS is filled with a cut insulating film 184. The cut insulating film 184 is made of an oxide film, a nitride film, an air gap, or a combination thereof. As used herein, the term "air gap" refers to a space containing atmosphere or other gases present during the manufacturing process.

[0029] The bit line contact pads 182 fill a plurality of bit line contact holes 180H penetrating a portion of the upper insulating film 180, and the bit lines BL on the upper insulating film 180 are connected to the bit line contact pads 182.

[0030] The word line structures WS between two adjacent word line cut regions WLC include the ground selection line GSL, the word lines WL (WL1, WL2, ..., WLn-1, WLn), and the string selection line SSL, which are described with reference to FIG. 1. The number of the word line structures WS stacked on the substrate 102 along the third direction (Z direction) may be selected in various ways as required. Among the word line structures WS, the word line structure WS closest to the substrate 102 constitutes the ground selection line GSL. Among the word line structures WS, the two word line structures WS on the uppermost side each constitute a string selection line SSL. The string selection line SSL may include a portion separated by a string selection line cut region SSLC.

[0031] The word line structures WS may comprise a metal, such as tungsten, nickel, cobalt, tantalum, a metal silicide, such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, impurity doped polysilicon, or a combination thereof.

[0032] In one embodiment, the word line structure WS further includes a dielectric thin film covering the bottom and top surfaces of the word line structure WS and the sidewalls facing the channel film 150. The dielectric thin film is made of a high dielectric film having a higher dielectric constant than silicon oxide. The high dielectric film is made of a metal oxide, for example, hafnium oxide, aluminum oxide, zirconium oxide, or tantalum oxide.

[0033] Between each of the word line structures WS, an insulating film 110 extends in a horizontal direction parallel to the main surface of the substrate 102. The insulating film 110 is made of a silicon oxide film. In one embodiment, the insulating film 110 may further include an air gap.

[0034] The word line structures WS and the insulating films 110 form a stack structure ST.

[0035] 3 and 4A, the word line structures WS have a structure protruding toward the channel film 150 further than the insulating films 110. The insulating films 110 may have recessed sidewalls 110R that are farther from the channel film 150 than sidewalls WSS of the word line structures WS toward the channel film 150.

[0036] The blocking dielectric layer 125 extends in a third direction (Z direction) covering the word line structures WS and the insulating layers 110, has a bend, and has a first groove GR1 toward the recessed sidewalls 110R of the insulating layers 110. The blocking dielectric layer 125 may conformally cover the sidewalls WSS of the word line structures WS and the recessed sidewalls 110R of the insulating layers 110. The blocking dielectric layer 125 is made of a silicon oxide layer or a silicon oxynitride layer.

[0037] The thickness t1 of the blocking dielectric layer 125 is greater than a width W1 in a first direction (X direction) between sidewalls WSS of the plurality of word line structures WS and recessed sidewalls 110R of the plurality of insulating layers 110. The blocking dielectric layer 125 may completely fill an indent space 110SP defined by bottom and top surfaces of the word line structures WS and the recessed sidewalls 110R of the insulating layer 110, and the first groove GR1 does not extend into the indent space 110SP.

[0038] The plurality of charge storage layers 130 are disposed on the sidewalls WSS of the plurality of word line structures WS with the blocking dielectric layer 125 interposed therebetween. The plurality of charge storage layers 130 are made of silicon nitride, polysilicon, or polysilicon doped with impurities. In one embodiment, the charge storage layer 130 may be a charge trap layer made of silicon nitride. In another embodiment, the charge storage layer 130 may be a floating gate made of polysilicon or polysilicon doped with impurities. In one embodiment, a first height H1 of the word line structure WS in the third direction (Z direction) is greater than a second height H2 of the plurality of charge storage layers 130. In one embodiment, the height of the charge storage layer 130 in the third direction (Z direction) increases from the channel layer 150 side toward the word line structure WS side. For example, the height of the sidewall of the charge storage layer 130 facing the word line structure WS in the third direction (Z direction) is greater than the height of the sidewall of the charge storage layer 130 facing the channel layer 150.

[0039] The tunneling dielectric layer 140 has a bend and extends along a third direction (Z direction) covering the blocking dielectric layer 125 and the plurality of charge storage layers 130. The tunneling dielectric layer 140 conformally covers the blocking dielectric layer 125 and the plurality of charge storage layers 130. The tunneling dielectric layer 140 is made of a silicon oxide layer.

[0040] The channel film 150 covers the tunneling dielectric film 140, extends along the third direction (Z direction), and has a bend.

[0041] The blocking dielectric film 125, the tunneling dielectric film 140, and the channel film 150 extend non-linearly along the third direction (Z direction). The blocking dielectric film 125, the tunneling dielectric film 140, and the channel film 150 each have a protruding shape that protrudes in a direction away from the word line structures WS at a portion facing the word line structures WS. The blocking dielectric film 125, the tunneling dielectric film 140, and the channel film 150 each may have a protruding shape toward the insulating films 110 at a portion facing the insulating films 110.

[0042] 3 and 4B, the integrated circuit device 100 further includes a residual layer 130R disposed in the first groove GR1 between the blocking dielectric layer 125 and the tunneling dielectric layer 140. In one embodiment, the residual layer 130R is made of the same material as the charge storage layer 130. For example, the residual layer 130R is made of silicon nitride, polysilicon, or polysilicon doped with impurities.

[0043] 3 and 4C, the integrated circuit device 100 further includes a residual layer 130Ra disposed in the first groove GR1 between the blocking dielectric layer 125 and the tunneling dielectric layer 140. At least two of the residual layers 130Ra are disposed spaced apart from each other between the blocking dielectric layer 125 and the tunneling dielectric layer 140 in the first groove GR1. In one embodiment, the residual layer 130Ra is made of the same material as the charge storage layer 130.

[0044] 3 and 4D, the integrated circuit device 100 includes a charge storage layer 130Rb disposed between the blocking dielectric layer 125 and the tunneling dielectric layer 140. The charge storage layer 130Rb extends between the blocking dielectric layer 125 and the tunneling dielectric layer 140 such that the charge storage layer 130 and the residual layer 130R shown in FIG. 4B are not separated but are integrated. The thickness of the charge storage layer 130Rb in the first direction (X direction) at a portion facing each of the word line structures WS is greater than the thickness of the portion facing each of the insulating layers 110 in the first direction (X direction).

[0045] 3 and 4E, the thickness t1a of the blocking dielectric layer 125 is smaller than a width W1 in a first direction (X direction) between sidewalls WSS of the plurality of word line structures WS and recessed sidewalls 110R of the plurality of insulating layers 110. The blocking dielectric layer 125 does not completely fill the indented space 110SP defined by the bottom and top surfaces of the word line structures WS and the recessed sidewalls 110R of the insulating layer 110, and the first groove GR1 extends into the indented space 110SP.

[0046] 3 and 4F, the blocking dielectric layer 125 has a seam 125S that extends from a sidewall toward the channel layer 150 toward the recessed sidewall 110R of the insulating layer 110. The seam 125S is formed as the blocking dielectric layer 125 fills the bottom and top surfaces of the word line structures WS and the indented space 110SP defined by the recessed sidewall 110R of the insulating layer 110.

[0047] 3 and 4G, the blocking dielectric layer 125 has a first air gap 125AG therein. The first air gap 125AG is formed as the blocking dielectric layer 125 fills the bottom and top surfaces of the word line structures WS and the indented space 110SP defined by the recessed sidewall 110R of the insulating layer 110.

[0048] Although Figures 4E to 4G all illustrate residual layer 130R, it will be obvious to those skilled in the art that the residual layer 130R may be omitted as shown in Figure 4A, or the residual layer 130R may be replaced with residual layer 130Ra shown in Figure 4C, or the charge storage film 130 and residual layer 130R may be replaced with charge storage film 130Rb shown in Figure 4D.

[0049] Figures 5A to 5P are enlarged cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the technical concept of the present invention. Specifically, Figures 5A to 5P are enlarged cross-sectional views illustrating a position corresponding to a dotted area indicated by P1 in Figure 3, according to a process sequence of the method for manufacturing an integrated circuit device shown in Figure 4B. The methods for manufacturing integrated circuit devices shown in Figures 4A and 4C to 4G will be explained mainly with reference to Figure 3, focusing on differences.

[0050] 5A, a structure is formed in which a plurality of insulating films 110 and a plurality of sacrificial films PL are alternately stacked one on the other on a substrate 102. In one embodiment, the plurality of sacrificial films PL are made of silicon nitride films, and the plurality of insulating films 110 are made of silicon oxide films. The plurality of insulating films 110 and the plurality of sacrificial films PL are formed by a CVD (chemical vapor deposition), PECVD (plasma enhanced CVD), or ALD (atomic layer deposition) process, respectively.

[0051] The sacrificial layers PL each serve to provide a space for forming at least one ground selection line GSL, a plurality of word lines WL, and at least one string selection line SSL shown in FIG. 1 in a subsequent process.

[0052] Of the multiple insulating films 110, the lowest insulating film 110L in contact with the substrate 102 has a smaller thickness than the other insulating films 110. Of the multiple insulating films 110, the insulating film 110 formed directly above the first sacrificial film PL from the substrate 102 among the multiple sacrificial films PL has a larger thickness than the insulating films 110 formed at other positions.

[0053] After forming an insulating pattern 114 on the topmost insulating film 110 among the multiple insulating films 110, the multiple insulating films 110 and the multiple sacrificial films PL are anisotropically etched using the insulating pattern 114 as an etching mask to form a channel hole CHH that exposes the substrate 102.

[0054] The horizontal width of the channel hole CHH becomes smaller closer to the substrate 102. The insulating pattern 114 is made of a single layer or multiple layers of an oxide film, a nitride film, or a combination thereof.

[0055] A selective epitaxial growth (SEG) process is performed using the substrate 102 exposed at the bottom of the channel hole CHH as a seed to form a semiconductor pattern 120 partially filling the channel hole CHH. The top surface of the semiconductor pattern 120 is located at a level between the top surface of the sacrificial film PL closest to the substrate 102 among the plurality of sacrificial films PL and the bottom surface of the insulating film 110 closest to the substrate 102 among the plurality of insulating films 110. The semiconductor pattern 120 serves as a channel similar to the channel film 150. The semiconductor pattern 120 is made of Si or Ge. In one embodiment, the semiconductor pattern 120 is made of a semiconductor doped with impurities.

[0056] 5B, a portion of each of the insulating films 110 is removed through the channel hole CHH to form a plurality of indentation spaces 110SP that are connected to the channel hole CHH at the same level as the insulating films 110. The insulating films 110 have recessed sidewalls 110R that are farther from the center of the channel hole CHH than the sidewalls PLS of the sacrificial films PL that face the channel hole CHH. The sidewalls of the insulating films 110, i.e., the recessed sidewalls 110R, are recessed by a plurality of indentation spaces 110SP from the channel hole CHH further than the sidewalls PLS of the sacrificial films PL. In one embodiment, the indentation spaces 110SP may be formed by removing a portion of each of the insulating films 110 using a wet etching process.

[0057] 5C, a blocking dielectric layer 125 is formed to cover the surfaces of the insulating layers 110 and the sacrificial layers PL exposed in the channel hole CHH. The blocking dielectric layer 125 is formed to cover the sacrificial layers PL and the insulating layers 110, extend along a third direction (Z direction), and have a bend, and have a first groove GR1 toward the recessed sidewalls 110R of the insulating layers 110. The blocking dielectric layer 125 generally conformally covers parts of the top and bottom surfaces of the sacrificial layers PL, the sidewalls PLS, and the recessed sidewalls 110R of the insulating layers 110.

[0058] Depending on the thickness of the blocking dielectric film 125, the blocking dielectric film 125 may completely fill the indentation space 110SP as shown in FIG. 4A, or the blocking dielectric film 125 may not completely fill the indentation space 110SP and the first groove GR1 may extend into the indentation space 110SP as shown in FIG. 4D.

[0059] 5D, a reserve charge storage layer 130P is formed to cover the blocking dielectric layer 125 in the channel hole CHH. The reserve charge storage layer 130P is formed to cover the blocking dielectric layer 125, extend along a third direction (Z direction), and have a bend, and to have a second groove GR2 corresponding to the first groove GR1. The reserve charge storage layer 130P is made of a silicon nitride layer. In one embodiment, the reserve charge storage layer 130P completely fills the first groove GR1.

[0060] 5E, a first cover sacrificial layer SCL1 is formed to cover the preliminary charge storage layer 130P in the channel hole CHH. The first cover sacrificial layer SCL1 is formed to cover the preliminary charge storage layer 130P, extend along a third direction (Z direction), and have a bend and a third groove GR3 corresponding to the second groove GR2. The first cover sacrificial layer SCL1 is made of, for example, polysilicon.

[0061] 5F, a second cover sacrificial layer SCL2 is formed to cover the first cover sacrificial layer SCL1 in the channel hole CHH. The second cover sacrificial layer SCL2 is formed to cover the first cover sacrificial layer SCL1, extend along the third direction (Z direction), and have a bend, filling the third groove GR3. The second cover sacrificial layer SCL2 is made of, for example, a nitride film.

[0062] 5G, the second cover sacrificial layer (SCL2 in FIG. 5F) is anisotropically etched to form a first cover layer CVL1, which is a part of the second cover sacrificial layer SCL2 filling at least a part of the third groove GR3. The first cover layers CVL1 in the channel hole CHH have a ring shape spaced apart from each other in the third direction (Z direction).

[0063] 5H and 5I, a second cover layer CVL2 is formed on the first cover sacrificial layer SCL1 exposed in the channel hole CHH. The second cover layer CVL2 is formed by oxidizing the first cover sacrificial layer SCL1. The second cover layer CVL2 is formed by oxidizing a portion of the first cover sacrificial layer SCL1 that is not covered by the first cover layer CVL1, and is not formed on the first cover layer CVL1. After forming the second cover layer CVL2, the first cover layer CVL1 is removed.

[0064] 5I and 5J, the first cover sacrificial layer SCL1 is isotropically etched using the second cover layer CVL2 as an etching mask to form a third cover layer CVL3, which is a part of the first cover sacrificial layer SCL1 exposing a part of the reserve charge storage layer 130P. The third cover layer CVL3 may be divided into a plurality of pieces by a first recess space RS1 exposing the second groove GR2 of the reserve charge storage layer 130P.

[0065] 5J to 5L, after removing the second cover layer CVL2, a portion of the preliminary charge storage layer 130P exposed through the first recess space RS1 of the third cover layer CVL3 is isotropically etched to form a plurality of charge storage layers 130 spaced apart from each other by a second recess space RS2 communicating with the first recess space RS1. In one embodiment, the second cover layer CVL2 is removed while a portion of the preliminary charge storage layer 130P is isotropically etched or after the plurality of charge storage layers 130 are formed.

[0066] In the process of forming the charge storage film 130 by isotropically etching a part of the reserve charge storage film 130P, another part of the reserve charge storage film 130P remains on the blocking dielectric film 125 in the first groove GR1 as a residual layer 130R. In one embodiment, the part of the reserve charge storage film 130P is completely removed in the first groove GR1 so that there is no residual layer 130R as shown in FIG. 4A. In another embodiment, as shown in FIG. 4C, another part of the reserve charge storage film 130P remains on the blocking dielectric film 125 in the first groove GR1 as at least two residual layers 130Ra spaced apart from each other. In yet another embodiment, in the process of isotropically etching and removing a part of the reserve charge storage film 130P, the charge storage film 130 and the residual layer 130R may be integral, not separated as in the charge storage film 130Rb shown in FIG. 4D. 5M to 5O, after removing the third cover layer (CVL3 in FIG. 5L), a tunneling dielectric layer 140 is formed in the channel hole CHH to cover the charge storage layer 130 and the blocking dielectric layer 125. Then, a portion of the blocking dielectric layer 125 and the tunneling dielectric layer 140 covering the semiconductor pattern 120 is removed, and a channel layer 150 is formed to cover the tunneling dielectric layer 140 and the semiconductor pattern 120. During the process of removing the portion of the blocking dielectric layer 125 and the tunneling dielectric layer 140 covering the semiconductor pattern 120, a portion of the upper surface of the semiconductor pattern 120 is removed, and a recess surface 120R is formed on the upper surface of the semiconductor pattern 120. Then, a buried insulating layer 156 is formed on the channel layer 150 to fill the channel hole CHH.

[0067] 5P, a portion of each of the insulating layers 110 and the sacrificial layers (PL in FIG. 5O) is removed to form word line cut regions WLC, and the sacrificial layers PL are removed through the word line cut regions WLC to form word line spaces DH connected to the word line cut regions WLC. The word line spaces DH are filled with word line structures WS.

[0068] Next, as shown in FIG. 3, a common source region 160, an insulating spacer 170, a common source line CSL, a capping insulating film 172, an upper insulating film 180, a string selection line cut region SSLC, a cut insulating film 184, a plurality of bit line contact holes 180H, a plurality of bit line contact pads 182, and a plurality of bit lines BL are formed to form an integrated circuit element 100.

[0069] Figures 6A, 6C, 7A to 7I, 8A to 8C, 9A, 10A to 10C, 12A to 12C, 14A, and 16A are enlarged cross-sectional views showing a method for manufacturing an integrated circuit device according to an embodiment of the present invention, and Figures 6B, 6D, 7J, 8D, 9B, 10D, 11, 12D, 13, 14B, 15, 16B, 17, 18, 19, and 20 are enlarged cross-sectional views showing an integrated circuit device according to another embodiment of the present invention. Specifically, Figures 6A to 20 are enlarged cross-sectional views showing a position corresponding to the dotted line area indicated by P1 in Figure 3, and the contents overlapping with the description of Figures 3 to 5P are omitted.

[0070] 6A, the corners of the sacrificial layers (PL in FIG. 5B) exposed in the channel holes CHH are partially removed to form a plurality of sacrificial layers PLa having rounded corners PRDa.

[0071] Referring to FIG. 6B, the process described with reference to FIGS. 5C through 5P is carried out on the result of FIG. 6A to form an integrated circuit device 100a.

[0072] Integrated circuit device 100a includes a plurality of rounded word line structures WSa having rounded portions WRDa.

[0073] 6C, a blocking dielectric layer 125a is formed to cover the surfaces of the sacrificial layers PLb exposed in the channel holes CHH from the resultant structure of FIG. 5B. The blocking dielectric layer 125a may be formed by oxidizing a portion adjacent to the exposed surfaces of the sacrificial layers (PL in FIG. 5B). In the process of forming the blocking dielectric layer 125a, a portion of the corners of the sacrificial layers PL is consumed, forming the sacrificial layers PLb having rounded corners PRDb.

[0074] The blocking dielectric film 125a covers all of the surfaces of the sacrificial films PLb in the channel hole CHH, but does not cover a portion of the recessed sidewalls 110R of the insulating films 110.

[0075] Referring to FIG. 6D, the process described with reference to FIGS. 5C through 5P is also carried out on the result of FIG. 6C to form an integrated circuit device 100a1.

[0076] Integrated circuit element 100a1 includes a plurality of rounded word line structures WSb having rounded portions WRDb.

[0077] Referring to FIG. 7A, a reserve charge storage film 130Pa is formed to cover the blocking dielectric film 125 in the channel hole CHH. The reserve charge storage film 130Pa is formed to cover the blocking dielectric film 125, extend along the third direction (Z direction), and have a bend, and to have a second groove GR2a corresponding to the first groove GR1. The reserve charge storage film 130Pa is formed to have a relatively thin thickness compared to the reserve charge storage film 130P shown in FIG. 5D. In one embodiment, the reserve charge storage film 130Pa fills a part of the first groove GR1, and the height of the second groove GR2a in the third direction (Z direction) may be greater than the height of the second groove GR2 of the reserve charge storage film 130P shown in FIG. 5D.

[0078] 7B, a first cover sacrificial layer SCL1a having a third groove GR3a and a second cover sacrificial layer SCL2a are sequentially formed on the preliminary charge storage layer 130Pa in the channel hole CHH. The height of the third groove GR3a in the third direction (Z direction) is greater than the height of the third groove GR3 of the first cover sacrificial layer SCL1 shown in FIG.

[0079] 7C, the second cover sacrificial layer (SCL2a in FIG. 7B) is anisotropically etched to form a first cover layer CVL1a, which is a part of the second cover sacrificial layer SCL2a filling at least a part of the third groove GR3a. In one embodiment, the height of the first cover layer CVL1a in the third direction (Z direction) is greater than the height of the first cover layer CVL1 shown in FIG.

[0080] 7D and 7E, a second cover layer CVL2a is formed on the first cover sacrificial layer SCL1a exposed in the channel hole CHH. The second cover layer CVL2a is formed by oxidizing the first cover sacrificial layer SCL1a, and may not be formed on the first cover layer CVL1a. After the second cover layer CVL2a is formed, the first cover layer CVL1a is removed.

[0081] 7E and 7F, the first cover sacrificial layer SCL1a is isotropically etched using the second cover layer CVL2a as an etching mask to form a third cover layer CVL3a, which is a part of the first cover sacrificial layer SCL1a exposing a part of the reserve charge storage layer 130Pa. The third cover layer CVL3a has a first recess space RS1a exposing the second groove GR2a of the reserve charge storage layer 130Pa.

[0082] 7F to 7H, after removing the second cover layer CVL2a, a portion of the preliminary charge storage film 130Pa exposed through the first recess space RS1a of the third cover layer CVL3a is isotropically etched to form a plurality of charge storage films 130a separated from each other by a second recess space RS2a communicating with the first recess space RS1a. In one embodiment, the second cover layer CVL2a is removed during isotropic etching of a portion of the preliminary charge storage film 130Pa or after forming the plurality of charge storage films 130a.

[0083] Both end portions of each of the plurality of charge storage layers 130a on the blocking dielectric film 125 have a rounded structure extending toward the first hole GR1a.

[0084] 7I and 7J, after removing the third cover layer (CVL3a in FIG. 7H), a tunneling dielectric layer 140 is sequentially formed in the channel hole CHH to cover the charge storage layer 130a and the blocking dielectric layer 125, a channel layer 150 is sequentially formed to cover the tunneling dielectric layer 140 and the semiconductor pattern 120, and a buried insulating layer 156 is sequentially formed on the channel layer 150 to fill the channel hole CHH. Then, a plurality of word line structures WS are formed to fill spaces left by removing the plurality of sacrificial layers PL, thereby completing the integrated circuit device 100b.

[0085] 8A, a trimming process is performed on the resultant structure of FIG. 5B to remove portions adjacent to the surfaces of the sacrificial layers (PL in FIG. 5B) exposed in the channel holes CHH, thereby forming a plurality of sacrificial layers PLc having trimming portions PTR at ends facing the channel holes CHH, the height of the trimming portions PTR being smaller than the height of the remaining portions of the sacrificial layers PLc in a third direction (Z direction).

[0086] The height in the third direction (Z direction) of the indent space 110SPa defined by the bottom and top surfaces of the sacrificial film PLc and the recessed sidewall 110R of the insulating film 110 is greater than the height of the indent space 110SP shown in FIG. 5B.

[0087] Referring to FIG. 8B, a blocking dielectric layer 125b having a first groove GR1b is formed to cover the surfaces of the insulating layers 110 and the sacrificial layers PLc exposed in the channel holes CHH.

[0088] 8C, a preliminary charge storage layer 130Pb, a first sacrificial cover layer SCL1b, and a first cover layer CVL1b are sequentially formed on the blocking dielectric layer 125b in the channel hole CHH by performing processes similar to those in FIGS. 5D to 5G.

[0089] 8D, a charge storage layer 130b, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially formed on a blocking dielectric layer 125b by performing processes similar to those of FIGS. 5H to 5P. Then, a plurality of word line structures WSc are formed to fill spaces obtained by removing the plurality of sacrificial layers (PLc in FIG. 8C), thereby forming an integrated circuit device 100c. Each of the plurality of word line structures WSc has a trimming portion WTR at an end portion toward the channel layer 150, the trimming portion WTR having a height in the third direction (Z direction) smaller than the height of the remaining portion of the word line structure WSc.

[0090] 9A, a plurality of charge storage layers 130c are formed on the blocking dielectric layer 125 by performing processes similar to those of FIGS. 5A to 5M. The plurality of charge storage layers 130c are formed by removing a relatively smaller portion of the preliminary charge storage layer (130P in FIG. 5J) than in the process of forming the plurality of charge storage layers 130 in FIG. 5L. A second height H2a of the charge storage layer 130c in the third direction (Z direction) is greater than the second height H2 of the charge storage layer 130 shown in FIG. 4A.

[0091] 9B, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially formed on the blocking dielectric layer 125 and the charge storage layer 130c by performing processes similar to those of FIG. 5N to FIG. 5P. Then, a plurality of word line structures WS are formed to fill spaces left by removing a plurality of sacrificial layers (PL in FIG. 9B), thereby forming an integrated circuit device 100d.

[0092] In one embodiment, a first height H1 of the word line structure WS in the third direction (Z direction) is smaller than a second height H2a of the plurality of charge storage layers 130c.

[0093] 10A, a fourth cover layer CVL4 is formed on the third cover layer CVL3 of the resultant structure of FIG. 5K. The fourth cover layer CVL4 is formed on the third cover layer CVL3 through a selective epitaxial growth process or a selective deposition process. The fourth cover layer CVL4 is made of, for example, polysilicon.

[0094] The fourth cover layer CVL4 has a first recess space RS1C exposing the second groove GR2 of the reserve charge storage film 130P. The first recess space RS1C is a space remaining after the fourth cover layer CVL4 is filled in the first recess space RS1 shown in Fig. 5K, so that the first recess space RS1C can be reduced by forming the fourth cover layer CVL4.

[0095] Referring to both Figures 10B and 10C, a portion of the preliminary charge storage layer (130P in Figure 10a) exposed through the first recess space RS1C of the fourth cover layer CVL4 is isotropically etched to form multiple charge storage layers 130d separated from each other by second recess spaces RS2C connected to the first recess space RS1C, and then the third cover layer CVL3 and the fourth cover layer CVL4 are removed.

[0096] In an embodiment, each of the charge storage films 130d has both ends in the third direction (Z direction), that is, a top surface and a bottom surface, which are concave.

[0097] 10D, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially formed on the blocking dielectric layer 125 and the charge storage layer 130d by performing processes similar to those of FIG. 5N to FIG. 5P. Then, a plurality of word line structures WS are formed to fill spaces left by removing a plurality of sacrificial layers (PL in FIG. 10C), thereby forming an integrated circuit device 100e.

[0098] 11, an integrated circuit device 100f includes a charge storage layer 130e, which has a different shape from the charge storage layer 130 of the integrated circuit device 100 shown in FIG.

[0099] In one embodiment, the height of the charge storage layer 130e in the third direction (Z direction) decreases from the channel layer 150 side to the word line structure WS side. For example, the height of the sidewall of the charge storage layer 130e facing the word line structure WS in the third direction (Z direction) is smaller than the height of the sidewall of the charge storage layer 130e facing the channel layer 150.

[0100] 12A and 12B, a preliminary charge storage layer 130Pf is formed to cover the blocking dielectric layer 125 in the channel hole CHH. The preliminary charge storage layer 130Pf is formed to have a relatively thinner thickness than the preliminary charge storage layer 130P shown in FIG.

[0101] Then, a process similar to that shown in FIG. 5E to FIG. 5M is performed to etch a portion of the preliminary charge storage layer 130Pf to form a first layer 130f1.

[0102] 12C, a second layer 130f2 conformally covering the blocking dielectric film 125 and the first layer 130f1 is formed in the channel hole CHH to form a precharge layer 130f consisting of the first layer 130f1 and the second layer 130f2. The first layer 130f1 is surrounded by the second layer 130f2 and the blocking dielectric film 125. The second layer 130f2 may surround the top and bottom surfaces and sidewalls of the first layer 130f1 toward the channel film 150.

[0103] The preliminary charge layer 130f is composed of a stacked structure of a first layer 130f1 and a second layer 130f2 at approximately the same level as the plurality of sacrificial films PL, and is composed of only the second layer 130f2 at approximately the same level as the plurality of insulating films 110. That is, the second layer 130f2 has a bend while extending along the third direction (Z direction) covering the blocking dielectric film 125 and the first layer 130f1, but has a larger horizontal width at approximately the same level as the sacrificial films PL than a horizontal width at approximately the same level as the plurality of insulating films 110.

[0104] In one embodiment, the first layer 130f1 and the second layer 130f2 are made of the same material. In another embodiment, the first layer 130f1 and the second layer 130f2 are made of different materials. For example, the first layer 130f1 and the second layer 130f2 are each made of one of silicon nitride and polysilicon.

[0105] 12D, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially formed on the blocking dielectric layer 125 and the charge storage layer 130f by performing processes similar to those of FIG. 5N to FIG. 5P. Then, a plurality of word line structures WS are formed to fill spaces left by removing a plurality of sacrificial layers (PL in FIG. 12C), thereby forming an integrated circuit device 100g.

[0106] 13, an integrated circuit device 100h includes a charge storage layer 130g, which is different from the charge storage layer 130f of the integrated circuit device 100g shown in FIG 12D in that portions of the charge storage layer 130g corresponding to the word line structures WS are spaced apart from each other.

[0107] The charge storage film 130g includes a first layer 130f1 and a second layer 130f2a, and the second layer 130f2a has portions corresponding to the word line structures WS spaced apart from each other, unlike the second layer 130f2 shown in FIG. 12D. The first layer 130f1 is surrounded by the second layer 130f2a and the blocking dielectric film 125. The second layer 130f2a may surround the top and bottom surfaces of the first layer 130f1 and sidewalls facing the channel film 150.

[0108] 14A, a relaxation insulating film 142 is formed to fill a portion of the second recess space (RS2 in FIG. 5M) in the resultant structure of FIG. 5M. The relaxation insulating film 142 is formed by forming a relaxation insulating material layer covering the blocking dielectric layer 125 and the charge storage layer 130 in the channel hole CHH, and then removing a portion of the relaxation insulating material layer by anisotropic etching so that only the second recess space RS2 remains. The relaxation insulating film 142 may reduce a step between the surfaces of the blocking dielectric layer 125 and the charge storage layer 130 exposed in the channel hole CHH.

[0109] 14B, by performing processes similar to those of FIGs. 5N to 5P, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially formed on the relaxation insulating layer 142 and the charge storage layer 130. Then, a plurality of word line structures WS are formed to fill spaces left by removing a plurality of sacrificial layers (PL in FIG. 14A), thereby forming an integrated circuit device 100i.

[0110] 15, the relaxing insulating film 142 of the integrated circuit device 100j has a second air gap 142AG therein.

[0111] 16A, a cover charge storage layer 132 is formed to cover the charge storage layer 130 and the relaxing insulating layer 142 on the resultant structure of FIG. 14A, and an extended charge storage layer 130h including the charge storage layer 130 and the cover charge storage layer 132 is formed.

[0112] 16B, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially formed on the extended charge storage layer 130h by performing processes similar to those of FIG. 5N to FIG. 5P. Then, a plurality of word line structures WS are formed to fill spaces left by removing a plurality of sacrificial layers (PL in FIG. 16A), thereby forming an integrated circuit device 100k.

[0113] The extended charge storage film 130h consisting of the charge storage film 130 and the cover charge storage film 132 corresponds to the charge storage film 130f consisting of the first layer 130f1 and the second layer 130f2 shown in FIG. 12D, and the integrated circuit device 100k is similar to the integrated circuit device 100g shown in FIG. 12D in that a relaxing insulating film 142 is inserted between the blocking dielectric film 125 and the second layer 130f2.

[0114] Referring to FIG. 17, an integrated circuit device 100l includes a charge storage film 130i consisting of a first layer 130i1 and a second layer 130i2.

[0115] In one embodiment, the first layer 130i1 and the second layer 130i2 are made of the same material. In another embodiment, the first layer 130i1 and the second layer 130i2 are made of different materials. For example, each of the first layer 130i1 and the second layer 130i2 is made of one of silicon nitride and polysilicon.

[0116] The second layer 130i2 is surrounded by the first layer 130i1 and the tunneling dielectric film 140. The first layer 130i1 may surround the top surface, bottom surface, and sidewalls towards the word line structure WS of the second layer 130i2.

[0117] In one embodiment, the first layer 130i1 is formed by forming a cover pattern that fills the second groove GR2 and covers a portion of the periphery of the second groove GR2 of the reserve charge storage film 130P in the resultant product of FIG. 5D, and then removing a portion of the reserve charge storage film 130P using the cover pattern as an etching mask, and the second layer 130i2 is formed by filling the portion from which the portion of the reserve charge storage film 130P has been removed.

[0118] 18, an integrated circuit device 100m includes a charge storage layer 130j having a first portion 130j1 and a second portion 130j2. In one embodiment, the first portion 130j1 and the second portion 130j2 are made of the same material.

[0119] The first portion 130j1 and the second portion 130j2 of the charge storage layer 130j corresponding to one word line structure WS are spaced apart from each other in the third direction (Z direction).

[0120] In one embodiment, the first portion 130j1 and the second portion 130j2 are formed by filling the space between the blocking dielectric layer 125 and the third cover layer CVL3 in the resultant structure of FIG. 5L and then removing the charge storage layer 130 shown in FIG. 5L.

[0121] 19, an integrated circuit device 100n includes a charge storage layer 130k including a first portion 130k1, a second portion 130k2, and a third portion 130k3.

[0122] The first and second portions 130k1 and 130k2 of the charge storage layer 130k corresponding to one word line structure WS are spaced apart from each other along the third direction (Z direction), and the third portion 130k3 fills the gap between the first and second portions 130k1 and 130k2. The first and second portions 130k1 and 130k2 contact the top and bottom surfaces of the third portion 130k3, respectively.

[0123] In one embodiment, the first portion 130k1 and the second portion 130k2 are formed in a manner similar to the first portion 130j1 and the second portion 130j2 shown in FIG. 18, and the third portion 130k3 may be a portion of the charge storage film 130 shown in FIG. 5L where the charge storage film 130 has not been removed.

[0124] In one embodiment, the first portion 130k1, the second portion 130k2, and the third portion 130k3 are made of the same material. In another embodiment, the first portion 130k1 and the second portion 130k2 are made of the same material, and the third portion 130k3 is made of a different material than the first portion 130k1 and the second portion 130k2.

[0125] Referring to FIG. 20, an integrated circuit device 100o includes a charge storage film 130l consisting of a first layer 130l1 and a second layer 130l2.

[0126] In one embodiment, the first layer 130l1 and the second layer 130l2 are formed by performing the processes described in Figures 5E to 5M after the preliminary charge storage film 130 shown in Figure 5D is formed to have a stacked structure of a preliminary first layer and a preliminary second layer.

[0127] In one embodiment, the first layer 130l1 and the second layer 130l2 are made of the same material. In another embodiment, the first layer 130l1 and the second layer 130l2 are made of different materials.

[0128] A sidewall of the first layer 130l1 facing the channel film 150 and a sidewall of the second layer 130l2 facing the word line structure WS2 are in contact with each other.

[0129] The integrated circuit devices 100, 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i, 100j, 100k, 100l, 100m, 100n, and 100o according to the present invention include charge storage films 130, 130a, 130b, 130c, 130d, 130e, 130f, 130g, 130h, 130i, 130j, 130k, and 30l is formed in the channel hole CHH, and the height and / or thickness of the charge storage films 130, 130a, 130b, 130c, 130d, 130e, 130f, 130g, 130h, 130i, 130j, 130k, and 130l are embodied in various ways, so that sufficient charge can be stored in the memory cell and interference between adjacent memory cells is prevented.

[0130] Fig. 21 is a cross-sectional view showing yet another integrated circuit device according to an embodiment of the technical concept of the present invention, and Fig. 22 is an enlarged cross-sectional view of a dotted line area indicated by P2 in Fig. 21. Specifically, Fig. 21 is a cross-sectional view at a position corresponding to line X1-X1' in Fig. 2. Of the contents related to Figs. 21 and 22, descriptions that overlap with Figs. 2 and 3 will be omitted.

[0131] 3 and 21, an integrated circuit device 200 includes a substrate 102 having an active region AC. Each of the channel holes CHH includes a semiconductor pattern 120 adjacent to the substrate 102 and partially filling the channel hole CHH, a channel film 150 adjacent to the semiconductor pattern 120 and extending in a third direction (Z direction) within the channel hole CHH, a buried insulating film 156 filling an internal space of the channel film 150, and a drain region 158 in contact with the channel film 150 and filling an upper portion of the inlet side of the channel hole CHH. The drain regions 158 are insulated from each other by an insulating pattern 114.

[0132] A blocking dielectric layer 225, a charge storage layer 230, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 are sequentially disposed in the channel hole CHH, and a drain region 158 is filled in the upper portion of the inlet side of the channel hole CHH.

[0133] In the channel hole CHH, the blocking dielectric layer 225, the tunneling dielectric layer 140, and the channel layer 150 each have a cylindrical shape. In the channel hole CHH, the charge storage layer 230 has a plurality of ring shapes spaced apart from each other in a third direction (Z direction). The blocking dielectric layer 225, the tunneling dielectric layer 140, and the channel layer 150 each include a plurality of bent portions formed in a portion covering the plurality of word line structures WS and the plurality of insulating layers 110.

[0134] During the formation of the blocking dielectric layer 225, the charge storage layer 230, and the tunneling dielectric layer 140, a portion of the top surface of the semiconductor pattern 120 is removed to form a recessed surface 120R on the top surface of the semiconductor pattern 120. The channel layer 150 contacts the recessed surface 120R of the semiconductor pattern 120.

[0135] The word line structures WS extend along the XY plane in a horizontal direction parallel to the main surface 102M on the substrate 102, and are arranged to overlap each other while being spaced apart from each other in a third direction (Z direction) perpendicular to the main surface 102M of the substrate 102. Between each of the word line structures WS, an insulating film 110 extends in the horizontal direction parallel to the main surface of the substrate 102. The word line structures WS and the insulating films 110 constitute a stack structure ST.

[0136] 21 and 22, the insulating films 110 of the integrated circuit device 200 have a structure that protrudes toward the channel film 150 further than the word line structures WS. The word line structures WS have recessed sidewalls WSR that are farther from the channel film 150 than the sidewalls 110S of the insulating films 110 that face the channel film 150.

[0137] The blocking dielectric layer 225 extends in a third direction (Z direction) covering the wordline structures WS and the insulating layers 110, has a bend, and has a first groove GR1c toward the recessed sidewalls WSR of the wordline structures WS. The blocking dielectric layer 225 generally conformally covers the recessed sidewalls WSR of the wordline structures WS and the sidewalls 110S of the insulating layers 110. The blocking dielectric layer 125 is made of a silicon oxide layer or a silicon oxynitride layer.

[0138] In one embodiment, the blocking dielectric layer 225 completely fills the indentation space WSSP defined by the bottom and top surfaces of the insulating layer 110 and the recessed sidewalls WSR of the word line structures WS, and the first groove GR1c does not extend into the indentation space WSSP. In another embodiment, the blocking dielectric layer 125 does not completely fill the indentation space WSSP defined by the bottom and top surfaces of the insulating layer 110 and the recessed sidewalls WSR of the word line structures WS, and the first groove GR1c extends into the indentation space WSSP.

[0139] The plurality of charge storage layers 230 are disposed on the recessed sidewalls WSR of the plurality of word line structures WS with the blocking dielectric layer 225 interposed therebetween. The plurality of charge storage layers 230 are made of silicon nitride, polysilicon, or polysilicon doped with impurities. In one embodiment, the charge storage layer 230 is a charge trap layer made of silicon nitride. In another embodiment, the charge storage layer 230 is a floating gate made of polysilicon or polysilicon doped with impurities. In one embodiment, a first height H1 of the word line structure WS in the third direction (Z direction) is greater than a second height H2b of the plurality of charge storage layers 230.

[0140] The surface of each of the plurality of charge storage films 230 opposite to the blocking dielectric film 225, i.e., toward the tunneling dielectric film 140 and the channel film 150, has a concave shape at the center. For example, the surface of each of the plurality of charge storage films 230 facing the tunneling dielectric film 140 and the channel film 150 has a concave shape at the middle part closer to the blocking dielectric film 225 than the upper and lower parts.

[0141] Each of the plurality of charge storage films 230 includes a first charge storage film 232 filling at least a portion of the first groove GR1c and a second charge storage film 234 covering the first charge storage film 232. The width of the second charge storage film 234 in the horizontal direction (X direction or Y direction) is greater than the width of the first charge storage film 232. The height of the second charge storage film 234 in the vertical direction (Z direction) is greater than the height of the first charge storage film 232. The second charge storage film 234 covers both the first charge storage film 232 and a portion of the blocking dielectric film 225.

[0142] The tunneling dielectric layer 140 covers the blocking dielectric layer 225 and the plurality of charge storage layers 230, and extends along a third direction (Z direction) and has a bend. The channel layer 150 covers the tunneling dielectric layer 140, and extends along the third direction (Z direction) and has a bend.

[0143] The blocking dielectric film 225, the tunneling dielectric film 140, and the channel film 150 extend non-linearly along the third direction (Z direction).

[0144] Figures 23A to 23F are enlarged cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the technical concept of the present invention. Specifically, Figures 23A to 23F are enlarged cross-sectional views illustrating a position corresponding to the dotted line area indicated by P2 in Figure 21, according to the process sequence of the method for manufacturing the integrated circuit device shown in Figure 22. Of the contents related to Figures 23A to 23F, descriptions overlapping with Figures 5A to 5P will be omitted.

[0145] 23A, a plurality of insulating films 110 and a plurality of sacrificial films PL are alternately stacked on a substrate 102. An insulating pattern 114 is formed on the uppermost insulating film 110 among the plurality of insulating films 110, and then the insulating films 110 and the plurality of sacrificial films PL are anisotropically etched using the insulating pattern 114 as an etching mask to form a channel hole CHH exposing the substrate 102. The horizontal width of the channel hole CHH becomes smaller as it approaches the substrate 102.

[0146] 23B, a portion of each of the sacrificial films PL is removed through the channel hole CHH to form a plurality of indent spaces PLSP that are in communication with the channel hole CHH at the same level as the sacrificial films PL. In the indent spaces PLSP, the sacrificial films PL have recessed sidewalls PLR that are farther from the center of the channel hole CHH than sidewalls 110S of the insulating films 110 that face the channel hole CHH. In one embodiment, the indent spaces PLSP are formed by removing a portion of each of the sacrificial films PL using a wet etching process.

[0147] 23C, a blocking dielectric layer 225 is formed to cover the surfaces of the insulating layers 110 and the sacrificial layers PL exposed in the channel hole CHH. The blocking dielectric layer 225 is formed to cover the sacrificial layers PL and the insulating layers 110, extend along a third direction (Z direction), have a bend, and have a first groove GR1c toward the recessed sidewalls PLR of the sacrificial layers PL. The blocking dielectric layer 225 generally conformally covers parts of the top and bottom surfaces of the insulating layers 110, the sidewalls 110S, and the recessed sidewalls PLR of the sacrificial layers PL.

[0148] Depending on the thickness of the blocking dielectric film 225, the blocking dielectric film 225 may completely fill the indentation space PLSP, or the blocking dielectric film 225 may not completely fill the indentation space PLSP and the first groove GR1c may extend into the indentation space PLSP.

[0149] 23D and 23E, a preliminary charge storage layer 232P is formed to cover the blocking dielectric layer 225 in the channel hole CHH. The preliminary charge storage layer 232P covers the blocking dielectric layer 225 and extends in a third direction (Z direction) and has a bend. The preliminary charge storage layer 232P is made of silicon nitride, polysilicon, or polysilicon doped with impurities.

[0150] Next, the preliminary charge storage film 232P is anisotropically etched to form the first charge storage film 232, which is a part of the preliminary charge storage film 232P filling at least a part of the first groove GR1c. The first charge storage film 232 has a surface with a concave center when viewed from the channel hole CHH. For example, the upper and lower parts of the first charge storage film 232 protrude into the channel hole CHH more than the middle part.

[0151] 23F, a second charge storage film 234 is formed on the first charge storage film 232 to form a charge storage film 230 including the first charge storage film 232 and the second charge storage film 234. The second charge storage film 234 is formed through a selective epitaxial growth process or a selective deposition process using the first charge storage film 232 as a seed. In one embodiment, the first charge storage film 232 and the second charge storage film 234 are made of the same material. In another embodiment, the first charge storage film 232 and the second charge storage film 234 are made of different materials. The second charge storage film 234 is made of, for example, a silicon nitride film or polysilicon doped with impurities.

[0152] The second charge storage layer 234 completely covers the exposed surface of the first charge storage layer 232 at the channel hole CHH as shown in FIG. 23F. In one embodiment, the second charge storage layer 234 further covers a portion of the surface of the blocking insulating layer 225 adjacent to the first charge storage layer 232. The second charge storage layer 234 has a surface with a concave center when viewed from the channel hole CHH. For example, the upper and lower portions of the second charge storage layer 234 protrude into the channel hole CHH more than the middle portion.

[0153] 5N to 5P, a tunneling dielectric layer 140 is sequentially formed in the channel hole CHH to cover the charge storage layer 230 and the blocking dielectric layer 225, a channel layer 150 is sequentially formed to cover the tunneling dielectric layer 140 and the semiconductor pattern (120 in FIG. 21), and a buried insulating layer 156 is sequentially formed to fill the channel hole CHH on the channel layer 150. Then, a plurality of word line structures (WS in FIG. 22) are formed to fill spaces left by removing the plurality of sacrificial layers PL, thereby completing the integrated circuit device 200.

[0154] Figures 24A and 24B, 25A and 25B, 26A, 27A to 27D, and 28A to 28D are enlarged cross-sectional views for explaining a method for manufacturing an integrated circuit device according to another embodiment of the present invention, and Figures 24C, 25C, 26B, 27E, and 28E are enlarged cross-sectional views for explaining an integrated circuit device according to another embodiment of the present invention. Specifically, Figures 24A to 28E are enlarged cross-sectional views showing a position corresponding to the dotted line area indicated by P2 in Figure 21, and the contents overlapping with the description of Figures 21 to 23F will be omitted.

[0155] 24A, the preliminary charge storage layer 232P of the resultant structure of FIG. 23D is anisotropically etched to form a first charge storage layer 232a, which is a part of the preliminary charge storage layer 232P filling at least a part of the first groove GR1c. The first charge storage layer 232a has a flat surface when viewed from the channel hole CHH. That is, the sidewall of the first charge storage layer 232a facing the channel hole CHH has a flat surface.

[0156] Referring to FIG. 24B, a second charge storage layer 234a is formed on the first charge storage layer 232a, thereby forming a charge storage layer 230a including the first charge storage layer 232a and the second charge storage layer 234a.

[0157] The second charge storage film 234a has a surface with a concave center when viewed from the channel hole CHH. For example, the upper and lower parts of the second charge storage film 234a protrude into the channel hole CHH more than the middle part.

[0158] 24C, by performing the processes described in Figures 5N to 5P, a tunneling dielectric layer 140 covering the charge storage layer 230a and the blocking dielectric layer 225 in the channel hole CHH, a channel layer 150 covering the tunneling dielectric layer 140 and the semiconductor pattern (120 in Figure 21), and a buried insulating layer 156 filling the channel hole CHH on the channel layer 150. Then, a plurality of word line structures WS are formed to fill spaces left by removing a plurality of sacrificial layers (PL in Figure 24B), thereby completing an integrated circuit device 200a.

[0159] 25A, the preliminary charge storage layer 232P of the resultant structure of FIG. 23D is anisotropically etched to form a first charge storage layer 232b, which is a part of the preliminary charge storage layer 232P filling at least a part of the first groove GR1c. At least two first charge storage layers 232b are disposed on the blocking dielectric layer 225 in the first groove GR1c and spaced apart from each other.

[0160] 25B, a second charge storage film 234b is formed on the first charge storage film 232b to fill the first groove GR1c, thereby forming a charge storage film 230b consisting of at least two first charge storage films 232b and a second charge storage film 234b. The second charge storage film 234b is formed by integrally combining portions formed through a selective epitaxial growth process or a selective deposition process of at least two first charge storage films 232b spaced apart from each other on the blocking dielectric film 225 in the first groove GR1c. That is, the second charge storage film 234b is formed integrally on at least two first charge storage films 232b spaced apart from each other.

[0161] The second charge storage film 234b has a surface with a concave center when viewed from the channel hole CHH. For example, the upper and lower parts of the second charge storage film 234b protrude into the channel hole CHH more than the middle part.

[0162] 25C, by performing the processes described in Figures 5N to 5P, a tunneling dielectric layer 140 covering the charge storage layer 230b and the blocking dielectric layer 225 in the channel hole CHH, a channel layer 150 covering the tunneling dielectric layer 140 and the semiconductor pattern (120 in Figure 21), and a buried insulating layer 156 filling the channel hole CHH on the channel layer 150. Then, a plurality of word line structures WS are formed to fill spaces obtained by removing a plurality of sacrificial layers (PL in Figure 25B), thereby completing an integrated circuit device 200b.

[0163] 26A, at least two second charge storage films 234c spaced apart from each other are formed on the at least two first charge storage films 232b, respectively, of the resultant structure of FIG. 25A, to form a charge storage film 230c consisting of at least two first charge storage films 232b and at least two second charge storage films 234c. The at least two second charge storage films 234c are formed through a selective epitaxial growth process or selective deposition process from at least two first charge storage films 232b spaced apart from each other on the blocking dielectric film 225 in the first groove GR1c, and are not bonded to each other but are spaced apart. The at least two second charge storage films 234c may not completely fill the first groove GR1c.

[0164] 26B, by performing the processes described in FIG. 5N to FIG. 5P, a tunneling dielectric layer 140 covering the charge storage layer 230c and the blocking dielectric layer 225 in the channel hole CHH, a channel layer 150 covering the tunneling dielectric layer 140 and the semiconductor pattern (120 in FIG. 21), and a buried insulating layer 156 filling the channel hole CHH on the channel layer 150. Then, a plurality of word line structures WS are formed to fill spaces left by removing a plurality of sacrificial layers (PL in FIG. 26A), thereby completing an integrated circuit device 200c.

[0165] 27A, a trimming process is performed on the resultant structure of FIG. 23B to remove a portion adjacent to the surface of the insulating films (110 in FIG. 23B) exposed in the channel holes CHH, thereby forming a plurality of insulating films 110a having trimmed portions 110TR at ends facing the channel holes CHH, the height of the trimmed portions 110TR being smaller than the height of the remaining portions of the insulating films 110a in a third direction (Z direction).

[0166] The height in the third direction (Z direction) of the indent space (PLSPa) defined by the bottom and top surfaces of the insulating film 110a and the recessed sidewall PLR of the sacrificial film PL has a value greater than the height of the indent space PLSP shown in FIG. 23B.

[0167] Referring to FIG. 27B, a blocking dielectric layer 225a having a first groove GR1d is formed to cover the exposed surfaces of the insulating layers 110a and the sacrificial layers PL in the channel holes CHH.

[0168] 27C, a first charge storage layer 232d is formed to fill at least a portion of the first groove GR1d by performing processes similar to those of FIGS. 23D and 23E. The height of the first charge storage layer 232d in the third direction (Z direction) is greater than the height of the first charge storage layer 232 shown in FIG. 23E.

[0169] 27D, a second charge storage film 234d is formed on the first charge storage film 232d to form a charge storage film 230d including the first charge storage film 232d and the second charge storage film 234d. The height of the second charge storage film 234d in the third direction (Z direction) is greater than the height of the second charge storage film 234 shown in FIG.

[0170] The second charge storage film 234d has a surface with a concave center when viewed from the channel hole CHH. For example, the upper and lower parts of the second charge storage film 234d protrude into the channel hole CHH more than the middle part.

[0171] 27E, by performing the processes described in Figures 5N to 5P, a tunneling dielectric layer 140 covering the charge storage layer 230d and the blocking dielectric layer 225a in the channel hole CHH, a channel layer 150 covering the tunneling dielectric layer 140 and the semiconductor pattern (120 in Figure 21), and a buried insulating layer 156 filling the channel hole CHH on the channel layer 150. Then, a plurality of word line structures WS are formed to fill spaces obtained by removing a plurality of sacrificial layers (PL in Figure 27D), thereby completing an integrated circuit device 200d.

[0172] In one embodiment, a first height H1 of the word line structure WS in the third direction (Z direction) is smaller than a second height H2c of the plurality of charge storage layers 230d.

[0173] 28A, a reserve charge storage layer 230Pe is formed in the channel hole CHH to cover the blocking dielectric layer 225a in the resultant structure of FIG. 27B. The reserve charge storage layer 230Pe is formed to cover the blocking dielectric layer 225a, extend in the third direction (Z direction), and have a bend and a second groove GR2d corresponding to the first groove GR1d. The reserve charge storage layer 230Pe is made of a silicon nitride layer.

[0174] Referring to FIG. 28B, a process similar to that of FIGS. 27C and 27D is performed to form a mask pattern layer 235 consisting of a first mask pattern 237 filling at least a portion of the second groove GR2d and a second mask pattern 239 covering the first mask pattern 237.

[0175] The first mask pattern 237 and the second mask pattern 239 are formed in a similar manner to the method of forming the first charge storage film 232d shown in FIG. 27C and the second charge storage film 234d shown in FIG. 27D. For example, a preliminary mask pattern similar to the preliminary charge storage film 232P shown in FIG. 23D is formed, and then the preliminary mask pattern is anisotropically etched to form the first mask pattern 237, and the second mask pattern 239 is formed through a selective epitaxial growth process or a selective deposition process using the first mask pattern 237 as a seed. In one embodiment, the first mask pattern 237 and the second mask pattern 239 are made of the same material. In another embodiment, the first mask pattern 237 and the second mask pattern 239 are made of different materials. The first mask pattern 237 and the second mask pattern 239 are made of, for example, a silicon nitride film or polysilicon doped with impurities.

[0176] 28C and 28D, the preliminary charge storage layer (230Pe in FIG. 28B) is isotropically etched using a mask pattern layer 235 consisting of a first mask pattern 237 and a second mask pattern 239 as an etching mask to form a charge storage layer 230e, which is a part of the preliminary charge storage layer 230Pe.

[0177] Next, the mask pattern layer 235 consisting of the first mask pattern 237 and the second mask pattern 239 is removed.

[0178] 28E, by performing the processes described in FIG. 5N to FIG. 5P, a tunneling dielectric layer 140 covering the charge storage layer 230e and the blocking dielectric layer 225a in the channel hole CHH, a channel layer 150 covering the tunneling dielectric layer 140 and the semiconductor pattern (120 in FIG. 21), and a buried insulating layer 156 filling the channel hole CHH on the channel layer 150. Then, a plurality of word line structures WS are formed to fill spaces left by removing a plurality of sacrificial layers (PL in FIG. 28D), thereby completing an integrated circuit device 200e.

[0179] The integrated circuit devices 200, 200a, 200b, 200c, 200d, and 200e according to the present invention form charge storage layers 230, 230a, 230b, 230c, 230d, and 230e in the channel holes CHH and implement various heights and / or thicknesses of the charge storage layers 230, 230a, 230b, 230c, 230d, and 230e, thereby enabling sufficient charge to be stored in the memory cells and preventing interference between adjacent memory cells.

[0180] 29 is a planar layout diagram of major regions of an integrated circuit device according to another embodiment of the present invention. Referring to FIG 29, an integrated circuit device 500 includes a memory cell array region 512, a first peripheral circuit region 514, a second peripheral circuit region 516, and a bonding pad region 518.

[0181] The memory cell array region 512 includes a plurality of memory cell arrays MCA having the configuration as described with reference to FIG.

[0182] The first peripheral circuit region 514 and the second peripheral circuit region 516 include control units for controlling data input or output from the memory cell array region 512. In the first peripheral circuit region 514 and the second peripheral circuit region 516, peripheral circuits for driving the vertical memory cells included in the memory cell array region 512 are arranged.

[0183] The first peripheral circuit region 514 may be arranged to vertically overlap the memory cell array region 512, thereby reducing the planar size of a chip including the integrated circuit device 500.

[0184] In one embodiment, the peripheral circuits disposed in the first peripheral circuit region 514 may be circuits capable of high-speed processing of data input / output to / from the memory cell array region 512. For example, the peripheral circuits disposed in the first peripheral circuit region 514 may be a page buffer, a latch circuit, a cache circuit, a column decoder, a sense amplifier, or a data in / out circuit.

[0185] The second peripheral circuit region 516 is disposed on one side of the memory cell array region 512 in a region that does not overlap with the memory cell array region 512 and the first peripheral circuit region 514. The peripheral circuit formed in the second peripheral circuit region 516 is, for example, a row decoder. In one embodiment, unlike the example of FIG. 29, at least a portion of the second peripheral circuit region 516 may be disposed below the memory cell array region 512.

[0186] The bonding pad region 518 is formed on the other side of the memory cell array region 512. The bonding pad region 518 is a region where wiring connected from each word line of the vertical memory cells of the memory cell array region 512 is formed.

[0187] Fig. 30A is a schematic perspective view of an integrated circuit element according to yet another embodiment of the technical concept of the present invention, and Fig. 30B is a schematic cross-sectional view of an integrated circuit element 600 illustrated in Fig. 30A. The integrated circuit element 600 illustrated in Fig. 30A and Fig. 30B has the same planar layout as the integrated circuit element 500 in Fig. 29. In Fig. 30A and Fig. 30B, the same reference numerals as those in Fig. 1 to Fig. 4G indicate the same members, and detailed description thereof will be omitted here.

[0188] 30A and 30B, an integrated circuit device 600 includes a first peripheral circuit region 514 formed in a first level on a substrate 502, and a memory cell array region 512 formed in a second level on the substrate 502 that is higher than the first level. As used herein, the term "level" refers to a height in a third direction (Z direction) from the substrate 502. On the substrate 502, the first level is closer to the substrate 502 than the second level.

[0189] In one embodiment, the substrate 502 has a major surface 502M extending in a first direction (X direction) and a second direction (Y direction). Further details regarding the substrate 502 are substantially the same as those described for the substrate 102 with reference to FIG.

[0190] An active region AC for a peripheral circuit is defined in the substrate 502 by an isolation film 504. A plurality of transistors TR constituting a first peripheral circuit region 514 are formed on the active region AC of the substrate 502. Each of the plurality of transistors TR includes a gate G, a gate dielectric film GD, and a source / drain region SD. Both side walls of the gate G are covered with an insulating spacer 106, and an etch stop film 108 is formed on the gate G and the insulating spacer 106. The etch stop film 108 includes an insulating material such as silicon nitride or silicon oxynitride.

[0191] A plurality of interlayer insulating films 112A, 112B, 112C, and 112D are sequentially stacked on the etching stop film 108. The plurality of interlayer insulating films 112A, 112B, 112C, and 112D may include silicon oxide, silicon oxynitride, silicon oxynitride, or the like.

[0192] The first peripheral circuit region 514 includes a multi-layer wiring structure 630 electrically coupled to the plurality of transistors TR. The multi-layer wiring structure 630 is insulated from one another by a plurality of interlayer insulating films 112A, 112B, 112C, and 112D.

[0193] The multi-layer wiring structure 630 includes a first contact 116A, a first wiring layer 118A, a second contact 116B, a second wiring layer 118B, a third contact 116C, and a third wiring layer 118C that are sequentially stacked on the substrate 502 and electrically connected to each other. In one embodiment, the first wiring layer 118A, the second wiring layer 118B, and the third wiring layer 118C are each made of a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the first wiring layer 118A, the second wiring layer 118B, and the third wiring layer 118C include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

[0194] 30A and 30B, the multilayer wiring structure 630 is illustrated as having a three-layer wiring structure including the first wiring layer 118A, the second wiring layer 118B, and the third wiring layer 118C, but the technical idea of ​​the present invention is not limited to what is illustrated in Fig. 30A and 30B. For example, the multilayer wiring structure 630 may have a two-layer or four or more-layer multilayer wiring structure depending on the layout of the first peripheral circuit region 514 and the type and arrangement of the gates G.

[0195] A semiconductor layer 520 covering the multiple interlayer insulating films 112A, 112B, 112C, and 112D is formed on the first peripheral circuit region 514. A memory cell array region 512 is formed on the semiconductor layer 520. The memory cell array region 512 has substantially the same configuration as that described for the memory cell array MCA of the integrated circuit element 100 with reference to Figures 1 to 4G or the integrated circuit element 200 with reference to Figures 21 and 22.

[0196] A plurality of common source regions 572 are formed in the semiconductor layer 520. A more detailed configuration of the plurality of common source regions 572 is substantially the same as that described for the common source region 160 with reference to FIG.

[0197] The common source regions 572 are formed by doping impurities into the semiconductor layer 520. As illustrated in FIGS. 30A and 30B, the depth of the common source regions 572 is substantially the same as the thickness of the semiconductor layer 520. As a result, the bottom surfaces of the common source regions 572 are in contact with the uppermost interlayer insulating film among the interlayer insulating films 112A, 112B, 112C, and 112D that constitute the first peripheral circuit region 514.

[0198] In the integrated circuit device 600, the memory cell array region 512 and the first peripheral circuit region 514 are electrically connected through at least one connecting plug (not shown) extending in a third direction (Z direction). The at least one connecting plug is formed penetrating at least a portion of the interlayer insulating films 112A, 112B, 112C, and 112D constituting the first peripheral circuit region 514 and the semiconductor layer 520. The at least one connecting plug electrically connects the wiring structure formed in the memory cell array region 512 and the wiring structure formed in the first peripheral circuit region 514 to each other.

[0199] The integrated circuit device 600 illustrated in Figures 30A and 30B has a multi-layer device structure in which first level semiconductor devices and second level semiconductor devices having different functions are stacked to vertically overlap each other at different levels. Therefore, the number of layers of the multi-layer wiring structure formed on the plurality of common source lines CSL and the plurality of channel structures CHS in the memory cell array region 512 is reduced. This prevents the density of the wiring pattern constituting the multi-layer wiring structure in the memory cell array region 512 from becoming excessively high, and simplifies the manufacturing process of the integrated circuit device. In addition, by reducing the number of stacked metal wiring layers in the multi-layer wiring structure, physical stress due to the metal wiring can be reduced, thereby preventing the warping of the substrate.

[0200] Fig. 31 is a schematic perspective view for explaining an integrated circuit device according to an embodiment of the technical idea of ​​the present invention. In Fig. 31, the same reference numerals as in Figs. 1 to 30B indicate the same members, and detailed description thereof will be omitted here.

[0201] Referring to FIG. 31, an integrated circuit element 700 includes a substrate 102, a lower stack LST including a plurality of lower word lines LWL stacked vertically on the substrate 102 so as to overlap each other, and an upper stack UST including a plurality of upper word lines UWL stacked vertically on the lower stack LST so as to overlap each other.

[0202] A plurality of channel structures CHS extend vertically through the lower stack LST and the upper stack UST on the substrate 102. The plurality of channel structures CHS are connected to a plurality of bit lines BL through a plurality of bit line contact pads 182. The lower stack LST and the upper stack UST each include one of the stack structures ST illustrated in FIG. 3 and FIG. 21. The plurality of channel structures CHS each include one of the channel structures CHS illustrated in FIG. 2, FIG. 3, and FIG. 21.

[0203] The lower word lines LWL and the upper word lines UWL have a smaller width in the Y direction as they are farther from the substrate 102. Thus, the lower stack LST and the upper stack UST each have a pyramid shape. The Y direction edge portion of each of the lower word lines LWL is used as a lower contact pad CP1, and the Y direction edge portion of each of the upper word lines UWL is used as an upper contact pad CP2. Although FIG. 31 shows both edge portions in the Y direction of the lower stack LST and the upper stack UST having a stepped structure, the technical idea of ​​the present invention is not limited thereto, and the direction in which the stepped structure is formed may be selected in various ways.

[0204] The lower word lines LWL are electrically connected to a word line driving circuit (not shown) through a plurality of lower contacts CON1 in contact with the lower contact pad CP1 and a plurality of wirings 712, 714 connected to the lower contacts CON1. ​​The upper word lines UWL are electrically connected to the word line driving circuit (not shown) through a plurality of upper contacts CON2 in contact with the upper contact pad CP2 and a plurality of wirings 722, 724 connected to the upper contacts CON2. Among the upper word lines UWL, at least one upper word line UWL used as a string selection line SSL is connected to a selection line driving circuit (not shown) through a plurality of wirings 726.

[0205] In the integrated circuit device 700, the inclusion of a lower stack LST and an upper stack UST that are vertically overlapped with each other increases the integration density.

[0206] Although the present invention has been described in detail above with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and alterations can be made by those having ordinary skill in the art within the technical spirit and scope of the present invention. [Explanation of symbols]

[0207] 100, 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i, 100j, 100k, 100l, 100m, 100n, 100o, 200, 200a, 200b, 200c, 200d, 200e, 500, 600, 700: integrated circuit elements 130, 130a, 130b, 130c, 130d, 130e, 130f, 130g, 130h, 130i, 130j, 130k, 130l, 230, 230a, 230b, 230c, 230d, 230e: charge storage film

Claims

1. a plurality of word line structures extending on a substrate in a horizontal direction parallel to a major surface of the substrate and overlapping each other along a vertical direction perpendicular to the major surface; a plurality of insulating layers interposed between the word line structures and extending in the horizontal direction; a blocking dielectric layer extending to cover the word line structures and the insulating layers within a channel hole passing through the word line structures and the insulating layers; a plurality of charge storage layers disposed on the blocking dielectric layer in the channel hole and spaced apart from each other to correspond to each of the plurality of word line structures, the charge storage layers being formed of a first charge storage layer on the blocking dielectric layer and a second charge storage layer covering the first charge storage layer; sidewalls of the insulating films facing the blocking dielectric film protrude beyond sidewalls of the wordline structures, thereby forming a plurality of indentation spaces between the sidewalls of the wordline structures and the insulating films; A surface of the blocking dielectric film facing the charge storage film has a plurality of grooves corresponding to the plurality of indentation spaces, and at least a portion of each of the plurality of charge storage films is disposed on the plurality of grooves of the blocking dielectric film; the charge storage layer protrudes from both the indentation space and the groove of the blocking dielectric layer; a surface of the second charge storage layer opposite the blocking dielectric layer, the surface having a middle portion that is more concave than upper and lower portions; The first charge storage layer of each of the plurality of charge storage layers has at least two portions spaced apart from each other.

2. 2. The integrated circuit device of claim 1, further comprising: a tunneling dielectric layer covering the blocking dielectric layer and the plurality of charge storage layers in the channel hole; and a channel layer covering the tunneling dielectric layer.

3. 2. The integrated circuit device of claim 1, wherein the second charge storage layer has a width greater than a width of the first charge storage layer.

4. The integrated circuit device of claim 1 , wherein the second charge storage layer has a height greater than a height of the first charge storage layer.

5. 2. The integrated circuit device of claim 1, wherein the height of each of the charge storage layers is greater than the height of each of the word line structures.

6. A plurality of word line structures extending on a substrate in a horizontal direction parallel to a major surface of the substrate and overlapping each other along a vertical direction perpendicular to the major surface; a plurality of insulating films interposed between the word line structures, the insulating films extending in the horizontal direction, the recessed sidewalls of the word line structures and the insulating films forming a plurality of indentation spaces; a channel film extending in the vertical direction within a channel hole penetrating the plurality of word line structures and the plurality of insulating films; a blocking dielectric layer extending in the channel hole to cover the word line structures and the insulating layers, the blocking dielectric layer having a surface facing the channel layer and a plurality of grooves corresponding to the plurality of indentation spaces; a plurality of charge storage layers at least partially disposed within the plurality of grooves of the blocking dielectric layer; the charge storage layer protrudes from both the indentation space and the groove of the blocking dielectric layer; the surfaces of the charge storage films facing the channel film have a concave center; The plurality of charge storage films are a first charge storage layer filling at least a portion of the grooves; and a second charge storage layer covering the first charge storage layer, The first charge storage layer of each of the plurality of charge storage layers has at least two portions spaced apart from each other.

7. The integrated circuit device of claim 6 , wherein a surface of the first charge storage layer facing the channel layer has a flat shape.

8. 7. The integrated circuit device of claim 6, wherein a surface of the second charge storage layer facing the channel layer has a concave center.

9. The integrated circuit device of claim 6 , wherein the height of the second charge storage layer is greater than the height of the first charge storage layer.

10. a plurality of word line structures extending on a substrate in a horizontal direction parallel to a major surface of the substrate and overlapping each other along a vertical direction perpendicular to the major surface; a plurality of insulating layers interposed between the word line structures and extending in the horizontal direction; a channel film extending in the vertical direction within a channel hole penetrating the plurality of word line structures and the plurality of insulating films; a blocking dielectric layer extending within the channel hole and covering the word line structures and the insulating layers; at least one charge storage layer disposed on the blocking dielectric layer within the channel hole; a tunneling dielectric layer covering the blocking dielectric layer and the at least one charge storage layer in the channel hole, and a channel layer covering the tunneling dielectric layer, sidewalls of the insulating films facing the channel film protrude beyond sidewalls of the word line structures; a surface of the blocking dielectric film facing the channel film has a plurality of grooves corresponding to the word line structures; and at least a portion of the at least one charge storage film is disposed in the plurality of grooves of the blocking dielectric film; the at least one charge storage layer includes a first charge storage layer filling at least a portion of the plurality of grooves, and a second charge storage layer covering the first charge storage layer; At least two of the first charge storage layers are disposed in each of the plurality of grooves and spaced apart from each other.

11. The integrated circuit device of claim 10 , wherein the first charge storage layer has upper and lower portions protruding toward the channel layer from a middle portion.

12. The integrated circuit device of claim 10 , wherein a sidewall of the first charge storage layer facing the channel layer has a flat surface.

13. The integrated circuit device of claim 10 , wherein the second charge storage layer has upper and lower portions protruding toward the channel layer from a middle portion.

14. The integrated circuit device of claim 10, wherein the second charge storage layers are at least two and disposed on at least two of the first charge storage layers spaced apart from each other.

15. forming a structure in which a plurality of first films and a plurality of second films are alternately stacked one layer at a time on a substrate; forming a channel hole through the structure; removing portions of the second film within the channel hole to form a plurality of indentation spaces communicating with the channel hole; forming a blocking dielectric layer in the channel hole, the blocking dielectric layer extending to cover the first and second layers and having a plurality of grooves corresponding to the indentation spaces; forming at least one charge storage layer, the charge storage layer including a first charge storage layer filling at least a portion of the plurality of grooves, and a second charge storage layer covering the first charge storage layer; the charge storage layer is formed to protrude from both the indentation space and the groove of the blocking dielectric layer; The second charge storage layer is formed through a selective epitaxial growth process or a selective deposition process using the first charge storage layer as a seed.

16. 16. The method of claim 15, wherein the first charge storage layer is formed by removing a portion of a preliminary charge storage layer formed in the channel hole to fill the grooves and cover the blocking dielectric layer by anisotropic etching.

17. 16. The method of claim 15, wherein the second charge storage layer is formed to have a width greater than a width of the first charge storage layer.

18. 16. The method of claim 15, wherein the second charge storage layer is formed to have a height greater than a height of the first charge storage layer.

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