Highway jumpers enable long-range connections for superconducting quantum computer chips

Abstract

According to one embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest neighbor qubits are connected within the pattern. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit within the pattern.

Description

[Technical field]

[0001] The presently claimed embodiments of the present invention relate to quantum computer chips, and more particularly to highway jumpers that enable long range connectivity for superconducting quantum computer chips. [Background technology]

[0002] Superconducting quantum chips have limitations in qubit connections. Currently, the superconducting quantum chip connection scheme is by “nearest neighbor.” Each qubit in a quantum chip may be connected to multiple nearest neighbor qubits. However, the nearest neighbor qubits may only be a small subset of the qubits contained on the superconducting quantum chip. Thus, a given qubit may be connected to a majority of the qubits on the quantum chip only through one or more additional qubits. In this case, if a two-qubit operation is desired, multiple swap gates may be required to enable the operation. However, qubit state swapping adds operational overhead, which requires the quantum system to remain coherent for longer periods of time. Thus, a system and method are needed to enable long-range connections between qubits on a quantum chip. Summary of the Invention

[0003] According to one embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, where nearest neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, where the first and second qubits are separated by at least a third qubit in the pattern. The long-range connector enables two-qubit operations to be performed on non-nearest neighbor qubits on the qubit chip with a reduced number of swap gates. The long-range connector thus reduces the operational overhead of two-qubit gates performed on non-nearest neighbor qubits.

[0004] According to one embodiment of the present invention, an interposer chip includes a substrate, a first coupling portion formed on the substrate, the first coupling portion positioned to align with a first qubit on the qubit chip, a second coupling portion formed on the substrate, the second coupling portion positioned to align with a second qubit on the qubit chip, and a bus formed on the substrate, the bus connecting the first coupling portion to the second coupling portion. The interposer chip is configured to be bonded to the qubit chip such that the first coupling portion couples to the first qubit and the second coupling portion couples to the second qubit. The interposer provides long-range connections between qubits, enabling two-qubit gates to be performed for non-nearest neighbor qubits with reduced operational overhead.

[0005] According to one embodiment of the present invention, a method for enabling long-range connection of qubits on a qubit chip includes providing a qubit chip including a plurality of qubits arranged in a pattern, where nearest neighbor qubits in the pattern are connected. The method further includes providing a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, where the first and second qubits are separated by at least a third qubit in the pattern. The method reduces the operational overhead of a two-qubit gate that operates on non-nearest neighbor qubits in the pattern. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic diagram of a quantum processor according to one embodiment of the present invention; [Diagram 2] FIG. 1 is a schematic diagram of a quantum processor including 30 qubits connected in a grid to facilitate explanation of some concepts of the present invention. [Diagram 3] FIG. 1 is a schematic diagram of a quantum processor including a long-range connector between qubit Q02 and qubit Q52, according to one embodiment of the present invention. [Figure 4] 1 is a schematic diagram of a quantum processor including a long-range connector disposed on a first surface of a substrate of a qubit chip, according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a schematic diagram of a qubit chip including two non-nearest neighbor qubits formed on a first surface of a substrate and a long-range connector disposed on a second surface of the qubit chip substrate, according to one embodiment of the present invention. [Figure 6] FIG. 2 is a schematic diagram of a qubit chip including a long-range connector including two coupled coils, according to one embodiment of the present invention. [Figure 7]1 is a schematic diagram of a qubit chip including a long-range connector including a coupling pad and a coupling coil, according to one embodiment of the present invention. [Figure 8] FIG. 1 is a schematic diagram of a qubit chip having a first portion of a long-range connector disposed on a first surface of a substrate of the qubit chip and a second portion of the long-range connector disposed on a second surface of the substrate, according to one embodiment of the present invention. [Figure 9] 1 is a schematic diagram of a quantum processor including a qubit chip and an interposer chip, according to one embodiment of the present invention. [Figure 10] 1 is a schematic diagram of an interposer chip including a long-range connector according to one embodiment of the present invention. [Figure 11] FIG. 2 is a schematic diagram of a qubit chip bonded to an interposer chip, according to one embodiment of the present invention. [Figure 12] 1 is a schematic diagram of a quantum processor including a qubit chip and an interposer chip, where the interposer chip includes a long-range connector that capacitively couples to first and second qubits on the qubit chip, according to one embodiment of the present invention. [Figure 13] 1 is a schematic diagram of a quantum processor including a qubit chip and an interposer chip, where the interposer chip includes a long-range connector that inductively couples to first and second qubits on the qubit chip, according to one embodiment of the present invention. [Figure 14] 1 is a schematic diagram of a quantum processor including a qubit chip and an interposer chip, where the interposer chip includes a long-range connector that capacitively couples to a first qubit and inductively couples to a second qubit, according to one embodiment of the present invention. [Figure 15] 1A-1D are schematic diagrams of various patterns of qubits and various configurations of long-range connectors, according to some embodiments of the present invention. [Figure 16] 1 is a flow chart illustrating a method for enabling long-range connections of qubits on a qubit chip, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] 1 is a schematic diagram of a quantum processor 100 according to one embodiment of the present invention. Quantum processor 100 includes a qubit chip 102. Qubit chip 102 includes a substrate 104 and a plurality of qubits 106 formed on a first surface 108 of substrate 104. The plurality of qubits 106 are arranged in a pattern, where nearest neighbor qubits in the pattern are connected. For example, nearest neighbor qubits 110, 112 are connected as shown by line 114 connecting nearest neighbor qubits 110, 112. Quantum processor 100 includes a long-range connector 115 configured to connect a first qubit 112 of the plurality of qubits 106 to a second qubit 116 of the plurality of qubits 106. The first and second qubits 112, 116 are separated by at least a third qubit 118 in the pattern.

[0008] The long-range connectors 115 reduce the number of swaps required to perform a two-qubit gate on non-nearest qubits. FIG. 2 is a schematic diagram of a quantum processor 200 that includes 30 qubits connected in a grid. The grid connects the nearest qubits but does not include connections between the non-nearest qubits. Thus, a two-qubit gate operating on a pair of non-nearest qubits requires "state swapping," which swaps the quantum states of the two qubits. State swapping allows the quantum state of a qubit to be converted from one qubit to another qubit that is the nearest qubit, or vice versa, resulting in the state of the two qubits being swapped. State swapping allows the gate to act on non-nearest qubits, but adds an operation to the quantum circuit. For example, if a qubit Q 00 202 and Cubit Q 54 The CNOT operation between 204 requires 16 swaps along 206-220 in addition to the (closest) CNOT gate.

[0009] Figure 3 shows the qubit Q 02 304 and Cubit Q 52 FIG. 3 is a schematic diagram of a quantum processor 300 including a long-range connector 302 between qubit Q and 306. 00 308 and Qubit Q 54 The CNOT gate acting on 310 requires only eight swaps along with 312, 314, 302, and 316. Thus, the long-range connector 302 reduces the number of swap gates required to perform a two-qubit operation on a non-nearest neighbor qubit.

[0010] According to some embodiments of the invention, the long-range connector is disposed on a first surface of a substrate of a qubit chip. FIG. 4 is a schematic diagram of a quantum processor 400. Quantum processor 400 includes a qubit chip including a plurality of qubits 402 formed on a first surface 404 of a substrate 406 of the qubit chip. The plurality of qubits 402 are arranged in a pattern, where nearest neighbor qubits in the pattern are connected. Quantum processor 400 includes a plurality of long-range connectors 408-416. Long-range connectors 408-416 are disposed on a first surface 404 of a substrate 406 of the qubit chip. Qubit chips according to some embodiments may include a single long-range connector or multiple long-range connectors.

[0011] The long-range connectors 408-416 may be disposed on the first surface 404 of the substrate 406 using methods and materials similar to those used to form connections between nearest neighbor qubits in the pattern. That is, no new processes are required for this configuration. A quantum processor may require a limited number of long-range connectors so that the first surface 404 of the substrate 406 is not overly crowded. The long-range connectors 408-416 may co-optimize with the algorithm the quantum processor is configured to execute. However, embodiments of the invention are not limited to quantum processors configured to execute specific algorithms. The long-range connectors 408-416 may connect qubits on the periphery of the pattern, since qubits on the periphery often have unused bus bond pads. These long-range connectors 408-416 may also connect to the same qubit.

[0012] According to some embodiments of the invention, the long-range connector is disposed on a second surface of the substrate of the qubit chip, the second surface facing away from the first surface. Placing the long-range connector on the second surface frees up space on the first surface if a high Q value of the bus can be maintained. A 3D integration process may be used to form the long-range connector on the second surface of the substrate. FIG. 5 is a schematic diagram of a qubit chip 500 including two non-nearest neighbor qubits 504, 506 formed on a first surface 508 of a substrate 502. The qubit chip 500 includes a long-range connector 510 disposed on a second surface 512 of the substrate 502 of the qubit chip 500. The long-range connector 510 connects the two non-nearest neighbor qubits 504, 506.

[0013] According to some embodiments of the invention, the long-range connector 510 includes a first bond pad 514 arranged to align with the first qubit 504, a second bond pad 516 arranged to align with the second qubit 506, and a bus 518 connecting the first bond pad 514 to the second bond pad 516. In operation, the first bond pad 514 capacitively couples to the first qubit 504 and the second bond pad 516 capacitively couples to the second qubit 506. As shown in FIG. 5, the qubit chip 500 may be bonded to an interposer chip 520 by a number of bumps 522, 524. The interposer chip 520 may include a readout resonator configured to couple to the qubits 504, 506. The qubits 504 or 506 may also have more than one long-range connector coupled to them.

[0014] According to some embodiments of the invention, a long-range connector is disposed on a second surface of a substrate of a qubit chip, which includes two coupling coils. FIG. 6 is a schematic diagram of a qubit chip 600 including two non-nearest neighbor qubits 604, 606 formed on a first surface 608 of a substrate 602. The qubit chip 600 includes a long-range connector 610 disposed on a second surface 612 of the substrate 602. The long-range connector 610 includes a first coupling coil 614 arranged to align with the first qubit 604, a second coupling coil 616 arranged to align with the second qubit 606, and a bus 618 connecting the first coupling coil 614 to the second coupling coil 616. In operation, the first coupling coil 614 inductively couples to the first qubit 604, and the second coupling coil 616 inductively couples to the second qubit 606. Thus, the long-range connector 610 connects the first qubit 604 to the second qubit 606. As shown in FIG. 6, the qubit chip 600 may be bonded to an interposer chip 620 by a number of bumps 622, 624. The interposer chip 620 may include a readout resonator configured to couple to the qubits 604, 606. The qubits 604 or 606 may also have more than one long-range connector coupled to them.

[0015] According to some embodiments of the invention, a long-range connector is disposed on a second surface of a substrate of a qubit chip, which includes a coupling pad and a coupling coil. FIG. 7 is a schematic diagram of a qubit chip 700 including two non-nearest neighbor qubits 704, 706 formed on a first surface 708 of a substrate 702. The qubit chip 700 includes a long-range connector 710 disposed on a second surface 712 of the substrate 702. The long-range connector 710 includes a coupling pad 714 arranged to align with the first qubit 704, a coupling coil 716 arranged to align with the second qubit 706, and a bus 718 connecting the coupling pad 714 to the coupling coil 716. In operation, the coupling pad 714 capacitively couples to the first qubit 704 and the coupling coil 716 inductively couples to the second qubit 706, thereby connecting the first qubit 704 to the second qubit 706. 7, qubit chip 700 may be bonded to interposer chip 720 by a number of bumps 722, 724. Interposer chip 720 may include a readout resonator configured to couple to qubits 704, 706. Qubit 704 or 706 may also have two or more long-range connectors coupled to it.

[0016] According to some embodiments of the invention, a first portion of the long-range connector is disposed on a first surface of a substrate of the qubit chip, and a second portion of the long-range connector is disposed on a second surface of the substrate. FIG. 8 is a schematic diagram of a qubit chip 800 including two non-nearest neighbor qubits 804, 806 formed on a first surface 808 of a substrate 802. The qubit chip 800 includes a long-range connector 810. A first portion 812 of the long-range connector 810 is disposed on the first surface 808 of the substrate 802 of the qubit chip 800. A second portion 814 of the long-range connector 810 is disposed on a second surface 816 of the substrate 802 of the qubit chip 800. The qubit chip 800 includes a through via 818 connecting the first portion 812 to the second portion 814. As shown in FIG. 8, the qubit chip 800 may include a number of through vias 818, 820 connecting the first portion 812 to the second portion 814. The vias 818, 820 allow the second portion 814 of the long-range connector 810 to be formed on the second surface 816 of the substrate 802, reducing the amount of space on the first surface 808 that the long-range connector 810 occupies. The vias 818, 820 also allow the second portion 814 of the long-range connector 810 to overlap features formed on the first surface 808 of the substrate 802. The qubits 804 or 806 may also have more than one long-range connector coupled to them.

[0017] According to some embodiments of the invention, a quantum processor includes an interposer chip. FIG. 9 is a schematic diagram of a quantum processor 900 including a qubit chip 902 and an interposer chip 904. The qubit chip 902 includes two non-nearest neighbor qubits 906, 908 formed on a first surface 910 of a substrate 912. A first portion 914 of a long-range connector is formed on the first surface 910 of the substrate 912 of the qubit chip 902. A second portion 916 of the long-range connector is formed on a surface 917 of the interposer chip 904. In operation, the qubit chip 902 is bonded to the interposer chip 904 such that the first portion 914 of the long-range connector is coupled to the second portion 916 of the long-range connector. The long-range connector may be enabled by flip-chip technology. For example, solder bumps 918, 920 can connect the first portion 914 to the second portion 916 of the long-range connector. The solder bumps 918, 920 can include a superconducting material, such as an elemental superconductor such as indium (In) or tin (Sn), or a compound superconductor. The configuration of the quantum processor 900 utilizes space on the surface of the interposer chip 904, which is often underutilized and may be less crowded than the first surface of the qubit chip. The first portion 914 of the long-range connector may be capacitively coupled to the qubits 906, 908. The qubits 906 or 908 can also have two or more long-range connectors coupled to them.

[0018] According to some embodiments of the invention, in addition to the long-range connector or a portion of a long-range connector, the interposer chip includes a plurality of readout resonators configured to couple to a plurality of qubits formed on a first surface of a substrate of the qubit chip. FIG. 10 is a schematic diagram of an interposer chip 1000 including a long-range connector (or a portion of a long-range connector) 1002. The interposer chip 1000 also includes a plurality of readout resonators 1004-1008 configured to couple to qubits formed on a first surface of a substrate of the qubit chip.

[0019] 11 is a schematic diagram of a qubit chip 1100 bonded to an interposer chip 1102. The qubit chip 1100 includes a plurality of qubits 1106 arranged in a pattern. The interposer chip 1102 includes a long-range connector 1108. The long-range connector 1108 is configured to connect two non-nearest neighbor qubits 1110, 1112 in the pattern. The interposer chip 1102 also includes a plurality of readout resonators 1114-1120. The readout resonators 1114-1120 are configured to couple to qubits 1122, 1124, 1110, 1112 formed on the qubit chip 1100. Embodiments of the present invention are not limited to any particular type of qubit. For example, combinatorial embodiments can include phase, charge, and flux qubits, as well as variants and hybridizations thereof, such as transmon qubits, fluxonium qubits, Xmon qubits, capacitively shunted flux qubits (CSFQ), and asymmon qubits.

[0020] According to some embodiments of the invention, the interposer chip includes a long-range connector that capacitively couples to a first and a second qubit on the qubit chip. Figure 12 is a schematic diagram of a quantum processor 1200 including a qubit chip 1202 and an interposer chip 1204. The qubit chip 1202 includes two non-nearest neighbor qubits 1206, 1208 formed on a first surface 1210 of a substrate 1212. The interposer chip 1204 includes a long-range connector including a first bond pad 1214 arranged to align with the first qubit 1206 and a second bond pad 1216 arranged to align with the second qubit 1208. The long-range connector includes a bus 1218 connecting the first bond pad 1214 to the second bond pad 1216. In operation, qubit chip 1202 is bonded to interposer chip 1204 such that first bond pad 1214 capacitively couples to first qubit 1206 and second bond pad 1216 capacitively couples to second qubit 1208, thereby connecting first qubit 1206 to second qubit 1208. Simulation and design optimization may be used to mitigate mixing of coupling and readout signals. Qubit 1206 or 1208 may also have two or more long-range connectors coupled to it.

[0021] According to some embodiments of the invention, the interposer chip includes a long-range connector that inductively couples to a first and a second qubit on the qubit chip. Figure 13 is a schematic diagram of a quantum processor 1300 including a qubit chip 1302 and an interposer chip 1304. The qubit chip 1302 includes two non-nearest neighbor qubits 1306, 1308 formed on a first surface 1310 of a substrate 1312. The interposer chip 1304 includes a long-range connector including a first coupling coil 1314 arranged to align with the first qubit 1306 and a second coupling coil 1316 arranged to align with the second qubit 1308. The long-range connector includes a bus 1318 that connects the first coupling coil 1314 to the second coupling coil 1316. In operation, qubit chip 1302 is bonded to interposer chip 1304 such that first coupling coil 1314 inductively couples to a first qubit 1306 and second coupling coil 1316 inductively couples to a second qubit 1308, thereby connecting first qubit 1306 to second qubit 1308. Qubit 1306 or 1308 may also have two or more long-range connectors coupled to it.

[0022] According to some embodiments of the invention, the interposer chip includes a long-range connector that capacitively couples to a first qubit on the qubit chip and inductively couples to a second qubit. Figure 14 is a schematic diagram of a quantum processor 1400 including a qubit chip 1402 and an interposer chip 1404. The qubit chip 1402 includes two non-nearest neighbor qubits 1406, 1408 formed on a first surface 1410 of a substrate 1412. The interposer chip 1404 includes a long-range connector including a coupling pad 1414 arranged to align with the first qubit 1406 and a coupling coil 1416 arranged to align with the second qubit 1408. The long-range connector includes a bus 1418 connecting the coupling pad 1414 to the coupling coil 1416. In operation, qubit chip 1402 is bonded to interposer chip 1404 such that coupling pad 1414 capacitively couples to a first qubit 1406 and coupling coil 1416 inductively couples to a second qubit 1408, thereby connecting the first qubit 1406 to the second qubit 1408. A combination of capacitive and inductive coupling can couple the qubits with different strengths. For example, coupling pad 1414 may be strongly coupled to the first qubit 1406 by capacitive coupling, while coupling coil 1416 may be weakly coupled to the second qubit 1408 by inductive coupling. Qubits 1406 or 1408 can also have two or more long-range connectors coupled to them.

[0023] An interposer chip according to some embodiments of the invention includes a plurality of readout resonators configured to couple to a plurality of qubits formed on a first surface of a substrate of a qubit chip. For example, the interposer chip illustrated generally in Figures 12-14 may include a plurality of readout resonators in addition to a long-range connector.

[0024] According to some embodiments of the invention, an interposer chip includes a substrate, a first coupling portion formed on the substrate, the first coupling portion positioned to align with a first qubit on the qubit chip, a second coupling portion formed on the substrate, the second coupling portion positioned to align with a second qubit on the qubit chip, and a bus formed on the substrate, the bus connecting the first coupling portion to the second coupling portion. The interposer chip is configured to be bonded to the qubit chip such that the first coupling portion couples to the first qubit and the second coupling portion couples to the second qubit. Examples of interposer chips are shown generally in Figures 12-14.

[0025] According to some embodiments of the invention, the first and second coupling portions are first and second bond pads, and the interposer chip is configured to be bonded to the qubit chip such that the first bond pad capacitively couples to a first qubit and the second bond pad capacitively couples to a second qubit. An example of this configuration of the interposer chip is shown generally in FIG.

[0026] According to some embodiments of the invention, the first and second coupling portions are first and second coupling coils, and the interposer chip is configured to be bonded to the qubit chip such that the first coupling coil inductively couples to the first qubit and the second coupling coil inductively couples to the second qubit. An example of this configuration of the interposer chip is shown generally in FIG.

[0027] According to some embodiments of the invention, the first coupling portion is a coupling pad and the second coupling portion is a coupling coil, and the interposer chip is configured to be bonded to the qubit chip such that the coupling pad capacitively couples to the first qubit and the coupling coil inductively couples to the second qubit. An example of this configuration of the interposer chip is shown generally in FIG.

[0028] According to some embodiments of the invention, the interposer chip further includes first and second readout resonators formed on the substrate. The first and second readout resonators are configured to couple to the first and second qubits, respectively. Figure 11 is a schematic diagram of an interposer chip 1102 including first and second readout resonators 1118, 1120 configured to couple to the first and second qubits 1110, 1112, respectively.

[0029] According to some embodiments of the invention, the first and second qubits connected by the long-range connector are located at the periphery of the pattern. Alternatively, one or both of the first and second qubits may be located in the interior of the pattern. According to some embodiments, the first and second qubits are separated in the pattern by at least three qubits. The embodiments of the invention are not limited to a particular pattern of qubits. The pattern of qubits and the configuration of the long-range connector can be selected for a specific application. For example, if a quantum processor is used to execute an algorithm of depth D, the long-range connector may be configured to jump fewer than D qubits.

[0030] 15A-15D are schematic diagrams of various patterns of qubits and various configurations of long-range connectors according to some embodiments of the present invention. The long-range connectors may be located on the qubit chip, on the interposer chip, or a combination thereof. FIG. 15A is a schematic diagram of qubits arranged in a square pattern. Long-range connectors 1500-1506 connect non-nearest neighbor qubits located on the periphery of the pattern. FIG. 15B is a schematic diagram of qubits arranged in a triangular pattern. Long-range connector 1508 connects a first qubit 1510 and a second qubit 1512, which are separated by three qubits 1514-1518 in the pattern. FIG. 15C is a schematic diagram of qubits arranged in a square pattern. A single long-range connector 1520 connects non-nearest neighbor qubits located on the periphery of the pattern. Figure 15D is a schematic diagram of qubits arranged in a hexagonal pattern. Long-range connectors 1522-1526 connect non-nearest neighbor qubits that are separated by at least four qubits in the pattern. The schematic diagrams in Figures 15A-D are presented as non-limiting examples of qubit patterns and long-range connector configurations.

[0031] 16 is a flow chart illustrating a method 1600 for enabling long-range connection of qubits on a qubit chip according to one embodiment of the present invention. The method 1600 includes providing a qubit chip including a plurality of qubits arranged in a pattern, where nearest neighbor qubits in the pattern are connected (1602). The method 1600 includes providing a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, where the first and second qubits are separated by at least a third qubit in the pattern (1604).

[0032] According to some embodiments of the invention, providing the long-range connector includes forming the long-range connector on a qubit chip. According to some embodiments, providing the long-range connector includes providing an interposer chip. The interposer chip includes a substrate, a first coupling portion formed on the substrate, the first coupling portion positioned to align with a first qubit on the qubit chip, a second coupling portion formed on the substrate, the second coupling portion positioned to align with a second qubit on the qubit chip, and a bus formed on the substrate, the bus connecting the first coupling portion to the second coupling portion. The method 1600 further includes bonding the interposer chip to the qubit chip such that the first coupling portion couples to the first qubit and the second coupling portion couples to the second qubit.

[0033] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications or technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A quantum processor, comprising: a qubit chip, the qubit chip comprising: Substrate, and a plurality of qubits formed on a first surface of the substrate, the plurality of qubits being arranged in a pattern, with nearest neighbor qubits in the pattern being connected, the quantum processor further comprising: a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, the first and second qubits being separated by at least a third qubit in the pattern, and at least a portion of the long-range connector being disposed on a second surface different from the first surface.

2. 10. The quantum processor of claim 1, wherein the long-range connector reduces the number of swap gates required to perform a two-qubit operation on a non-nearest neighbor qubit.

3. The quantum processor of claim 1 or 2, wherein a portion of the long-range connector is disposed on the first surface of the substrate of the qubit chip.

4. 3. The quantum processor of claim 1, wherein the long-range connector is disposed on the second surface, the second surface being a surface of the substrate opposite the first surface.

5. The long range connector comprises: a first bond pad arranged to align with the first qubit; a second bond pad arranged to align with the second qubit; a bus connecting the first bond pad to the second bond pad; 5. The quantum processor of claim 4, wherein in operation the first bond pad capacitively couples to the first qubit and the second bond pad capacitively couples to the second qubit.

6. The long range connector comprises: a first coupling coil arranged to align with the first qubit; a second coupling coil arranged to align with the second qubit; a bus connecting the first coupling coil to the second coupling coil; 5. The quantum processor of claim 4, wherein in operation, the first coupling coil inductively couples to the first qubit and the second coupling coil inductively couples to the second qubit.

7. The long range connector comprises: a bond pad arranged to align with the first qubit; a coupling coil arranged to align with the second qubit; a bus connecting said coupling pads to said coupling coil; 5. The quantum processor of claim 4, wherein in operation, the coupling pad capacitively couples to the first qubit and the coupling coil inductively couples to the second qubit.

8. a first portion of the long-range connector is disposed on the first surface of the substrate of the qubit chip; a second portion of the long-range connector is disposed on the second surface, the second surface being a surface of the substrate of the qubit chip facing away from the first surface; The quantum processor of claim 1 or 2, wherein the qubit chip comprises through vias connecting the first portion to the second portion.

9. Further comprising an interposer chip; a first portion of the long-range connector is formed on the first surface of the substrate of the qubit chip; a second portion of the long-range connector is formed on the second surface, the second surface being a surface of the interposer chip; 3. The quantum processor of claim 1, wherein in operation, the qubit chip is bonded to the interposer chip such that the first portion of the long-range connector is bonded to the second portion of the long-range connector.

10. 10. The quantum processor of claim 9, wherein the interposer chip further comprises a plurality of readout resonators configured to couple to a plurality of qubits formed on the first surface of the substrate of the qubit chip.

11. an interposer chip, the long-range connector being formed on a surface of the interposer chip, the surface of the interposer chip being the second surface, and the long-range connector being a first bond pad arranged to align with the first qubit; a second bond pad arranged to align with the second qubit; a bus connecting the first bond pad to the second bond pad; 3. The quantum processor of claim 1, wherein in operation the qubit chip is bonded to the interposer chip such that the first bond pad capacitively couples to the first qubit and the second bond pad capacitively couples to the second qubit.

12. 12. The quantum processor of claim 11 , wherein the interposer chip further comprises a plurality of readout resonators configured to couple to a plurality of qubits formed on the first surface of the substrate of the qubit chip.

13. an interposer chip, the long-range connector being formed on a surface of the interposer chip, the surface of the interposer chip being the second surface, and the long-range connector being a first coupling coil arranged to align with the first qubit; a second coupling coil arranged to align with the second qubit; a bus connecting the first coupling coil to the second coupling coil; 3. The quantum processor of claim 1, wherein during operation, the qubit chip is bonded to the interposer chip such that the first coupling coil inductively couples to the first qubit and the second coupling coil inductively couples to the second qubit.

14. an interposer chip, the long-range connector being formed on a surface of the interposer chip, the surface of the interposer chip being the second surface, and the long-range connector being a bond pad arranged to align with the first qubit; a coupling coil arranged to align with the second qubit; a bus connecting said coupling pads to said coupling coil; 3. The quantum processor of claim 1, wherein in operation the qubit chip is bonded to the interposer chip such that the coupling pad capacitively couples to the first qubit and the coupling coil inductively couples to the second qubit.

15. 15. The quantum processor of claim 1, wherein the first qubit and the second qubit are located on the periphery of the pattern.

16. 16. The quantum processor of claim 1, wherein the first qubit and the second qubit are separated in the pattern by at least three qubits.

17. An interposer chip, comprising: A substrate; a first coupling portion formed on a surface of the substrate, the first coupling portion being positioned to align with a first qubit of a plurality of qubits on a qubit chip comprising a plurality of qubits; a second coupling portion formed on a surface of the substrate, the second coupling portion positioned to align with a second qubit of the plurality of qubits on the qubit chip; a bus formed on a surface of the substrate, the bus connecting the first coupling portion to the second coupling portion; wherein the plurality of qubits are arranged in a pattern, nearest neighbor qubits in the pattern are connected, and the first and second qubits are separated by at least a third qubit in the pattern, and the interposer chip is configured to be bonded to the qubit chip such that the first coupling portion couples to the first qubit and the second coupling portion couples to the second qubit.

18. the first and second bonding portions being first and second bond pads; 20. The interposer chip of claim 17, wherein the interposer chip is configured to be bonded to the qubit chip such that the first bond pad capacitively couples to the first qubit and the second bond pad capacitively couples to the second qubit.

19. the first and second coupling portions being first and second coupling coils; 20. The interposer chip of claim 17, wherein the interposer chip is configured to be bonded to the qubit chip such that the first coupling coil inductively couples to the first qubit and the second coupling coil inductively couples to the second qubit.

20. the first coupling portion is a coupling pad and the second coupling portion is a coupling coil; 20. The interposer chip of claim 17, wherein the interposer chip is configured to be bonded to the qubit chip such that the bond pad capacitively couples to the first qubit and the coupling coil inductively couples to the second qubit.

21. 21. The interposer chip of claim 17, further comprising first and second readout resonators formed on the substrate, the first and second readout resonators configured to couple to first and second qubits, respectively.

22. 1. A method for enabling long-range connections of qubits on a qubit chip, comprising: providing a qubit chip forming a plurality of qubits arranged in a pattern on a first surface of a substrate of the qubit chip, wherein nearest neighbor qubits in the pattern are connected; coupling a first qubit of the plurality of qubits to a second qubit of the plurality of qubits with a long-range connector, the first and second qubits being separated by at least a third qubit in the pattern, and at least a portion of the long-range connector being disposed on a second surface different from the first surface; A method comprising:

23. The method of claim 22, further comprising forming a portion of the long-range connector on the qubit chip.

24. Providing an interposer chip, comprising: The interposer chip comprises: substrate, a first coupling portion formed on a surface of the substrate, the first coupling portion being positioned to align with the first qubit on the qubit chip; a second coupling portion formed on a surface of the substrate and positioned to align with the second qubit on the qubit chip; and providing the interposer chip with a bus formed on a surface of the substrate, the bus connecting the first coupling portion to the second coupling portion; bonding the interposer chip to the qubit chip such that the first coupling portion couples to the first qubit and the second coupling portion couples to the second qubit; 23. The method of claim 22, comprising: a surface of the substrate of the interposer chip being a second surface.

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