Electronic Components

Abstract

To provide an electronic component including a terminal electrode structure where heat resistance during solder mounting and under a usage environment can be ensured.SOLUTION: A chip resistor 10 includes: an insulated substrate (component body) 1 where a resistive element 3 is formed; connection terminals (front electrode 2, end face electrode 6 and back electrode 5) formed on both ends of the insulated substrate 1; an under layer 7 formed by electrolytic plating so as to cover the connection terminals; a barrier layer 8 formed by electrolytic plating so as to cover the under layer 7; and an external connection layer 9 formed on the surface of the barrier layer 8 and containing tin as a main component. The barrier layer 8 comprises alloy plating containing 3-15% of tin with nickel as a main component, and the under layer 7 comprises a copper plating layer that is richer in at least one of malleability and ductility than the barrier layer 8.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to electronic components such as chip components and connectors, and more particularly to an electrode terminal structure for soldering formed on the component body of an electronic component. [Background technology]

[0002] When electronic components such as chip components and connectors are mounted on a circuit board, a plating layer made of Sn (tin) or Sn-Pb (lead) is formed as an external connection layer on the surface of the connection terminal of the electronic component body, and this external connection layer is joined to the land of the wiring pattern provided on the circuit board using a solder material. For example, in the case of a surface-mount component such as a chip resistor in which the external connection layers formed on both ends of the component body are soldered, solder paste (solder material) is applied to the land of the wiring pattern, and then the electronic component is placed on the circuit board so that the external connection layer overlaps the solder paste, and in this state the plating layer of the external connection layer and the solder paste are melted by the heat of a reflow furnace, and then the solder paste is cooled and solidified to connect the connection terminal and the land. In the case of lead components such as connectors, in which pin-shaped connection terminals that protrude from the main body of the component are soldered, the connection terminals are inserted into through-holes in the circuit board, and then the external connection layer (plating layer) of the connection terminal and the solder material are melted with heat from a soldering iron or the like, and the solder material is then cooled and solidified to connect the connection terminal and the land.

[0003] As a solder material used when mounting electronic components on a circuit board, for example, eutectic solder, which is a mixture of tin (Sn) and lead (Pb) in a ratio of about 6:4 (Sn 63% - Pb 37%), is known. The melting point of eutectic solder with this composition is 183°C, but since it is necessary to apply heat above the melting point to melt the solder, there is a risk of a phenomenon called "solder erosion," in which Ag and Cu constituting the connection terminal melt into the solder material due to the heat during soldering. A barrier layer is provided to prevent this solder erosion, and electrode terminal structures have been proposed in which a barrier layer made of nickel or lead is provided between the connection terminal of the electronic component and the external connection layer to prevent solder erosion (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2001-210545 A Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, lead-free soldering has been recommended from the viewpoint of global environmental protection, and lead-free solder that contains almost no lead is being used. Here, for example, when lead-free solder with a composition of Sn96.5%-Ag3%-Cu0.5% is used, the melting point of this lead-free solder is 220°C, and the heating temperature during solder mounting is higher than when eutectic solder is used. Therefore, even if the barrier layer is made of nickel, nickel tends to diffuse into the solder material side, and the barrier layer cannot function sufficiently. Therefore, it is necessary to make the nickel plating layer thicker to delay solder erosion, but if the plating layer is formed thick, not only will cracks be more likely to occur due to external and internal stresses, but plating time and material costs will also increase.

[0006] In the automotive industry, the technology of automatic driving devices and safety devices has been rapidly developed in recent years, and the number of electronic components installed in cars is rapidly increasing. Electronic components installed in cars are required to be more reliable than consumer components, and the operating environment is also harsh, so the demand for high heat resistance is particularly high, and high heat resistance that can be used without problems even in environments around 200°C is required. However, when electronic components are used in high-temperature environments close to 200°C, the nickel plating layer that constitutes the barrier layer diffuses to the surface and cannot function as a barrier layer. In other words, the conventional electrode terminal structure had a problem in that it was difficult to ensure heat resistance not only during solder mounting but also in the operating environment.

[0007] The present invention has been made in consideration of the current state of the prior art, and its object is to provide an electronic component having a terminal electrode structure that can ensure heat resistance during solder mounting and in the usage environment. [Means for solving the problem]

[0008] In order to achieve the above object, the electronic device of the present invention comprises: Rectangular shaped The component body includes a connection terminal formed on the component body, a base layer formed by electrolytic plating so as to cover the connection terminal, a barrier layer formed by electrolytic plating so as to cover the base layer, and an external connection layer mainly composed of tin formed on the surface of the barrier layer, the barrier layer covering the entire surface of the base layer over the front surface, end faces and back surface of the component body, the barrier layer being made of an alloy plating of nickel with 3% to 15% phosphorus added, and the base layer being The underlayer is made of copper or an alloy mainly composed of copper, and the thickness of the underlayer is set in the range of 3 μm to 25 μm. It is characterized by the following.

[0009] In the electronic component thus constructed, the barrier layer covered by the external connection layer is made of an alloy (Ni-P) plating mainly composed of nickel (Ni) and containing 3% to 15% phosphorus (P), and since this alloy plating diffuses into tin more slowly than nickel, the heat resistance during solder mounting and in the usage environment can be ensured without forming the barrier layer unnecessarily thick. Moreover, a metal layer that is more malleable or ductile than the barrier layer is formed as an underlayer for the barrier layer, This metal layer is made of copper or an alloy mainly composed of copper and has a thickness of 3 μm to 25 μm. Even if the internal stress increases with the addition of phosphorus to nickel, the stress is mitigated by the underlayer. By Therefore, the occurrence of cracks can be suppressed.

[0012] Furthermore, in an electronic component having the above configuration, if a magnetic layer is formed between the connection terminal and the barrier layer, the magnetic properties of the magnetic layer can be utilized to magnetically stabilize the posture of the product, for example, during a taping process in which the product is stored in a tape-like packaging body, or when the product is removed from the packaging body and mounted on a circuit board. Effect of the Invention

[0013] According to the electronic component of the present invention, it is possible to realize a terminal electrode structure that can ensure heat resistance during solder mounting and in the usage environment, and also to suppress the occurrence of cracks. [Brief description of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view of a chip resistor according to a first embodiment of the present invention. [Diagram 2] 3A to 3C are cross-sectional views showing a manufacturing process of the chip resistor. [Diagram 3] FIG. 4 is a cross-sectional view of a chip resistor according to a second embodiment of the present invention. [Figure 4] 3A to 3C are cross-sectional views showing a manufacturing process of the chip resistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a chip resistor according to a first embodiment of the present invention.

[0016] As shown in FIG. 1, a chip resistor 10, which is an example of an electronic component, is mainly composed of a rectangular insulating substrate 1, a pair of front electrodes 2 formed on both longitudinal ends of the surface of the insulating substrate 1, a resistor 3 formed so as to bridge the pair of front electrodes 2, a protective layer 4 covering the entire resistor 3 and part of the front electrode 2, a pair of back electrodes 5 formed on both longitudinal ends of the back surface of the insulating substrate 1, a pair of end electrodes 6 formed on both longitudinal ends of the insulating substrate 1 and conducting between corresponding front electrodes 2 and back electrodes 5, a pair of base layers 7 covering the front electrodes 2, back electrodes 5, and end electrodes 6, a pair of barrier layers 8 covering each of the base layers 7, and a pair of external connection layers 9 covering each of the barrier layers 8.

[0017] The insulating substrate 1 is a component body made of ceramics or the like, and a large number of insulating substrates 1 are obtained by dividing a large-sized substrate, which will be described later, along vertical and horizontal dividing grooves.

[0018] A pair of front electrodes 2 are formed on opposing short sides of insulating substrate 1 with a predetermined gap between them, and these front electrodes 2 are formed by screen printing an Ag-based paste, followed by drying and firing.

[0019] The resistor 3 is formed by screen printing a resistive paste such as ruthenium oxide, followed by drying and baking, and both ends of the resistor 3 overlap the front electrodes 2. The resistor 3 has a trimming groove (not shown) formed therein, and the resistance value of the resistor 3 is adjusted by this trimming groove.

[0020] The protective layer 4 has a two-layer structure consisting of an undercoat layer 4a and an overcoat layer 4b. The undercoat layer 4a is formed by screen printing and baking a glass paste, and this undercoat layer 4a is formed so as to cover the resistor element 3 before the trimming groove is formed. The overcoat layer 4b is formed by screen printing and heat curing an epoxy resin paste, and this overcoat layer 4b is formed so as to entirely cover the resistor element 3 and the undercoat layer 4a, including the trimming groove, after the trimming groove is formed in the resistor element 3 from above the undercoat layer 4a.

[0021] A pair of back electrodes 5 are formed at positions corresponding to the front electrodes 2 on the back surface of the insulating substrate 1 with a predetermined distance therebetween, and these back electrodes 5 are formed by screen printing Ag paste, followed by drying and firing.

[0022] The pair of end electrodes 6 are formed by sputtering Ni-Cr on the end faces of the insulating substrate 1, or by applying an Ag-based paste to the end faces of the insulating substrate 1 and then heating and hardening it. The end electrodes 6 are formed so as to provide electrical continuity between the corresponding front electrodes 2 and back electrodes 5, and the front electrodes 2, end electrodes 6, and back electrodes 5 form a connection terminal with a U-shaped cross section.

[0023] The pair of underlayers 7 are copper plating layers formed by electrolytic plating so as to cover the connection terminals, and the underlayers 7 relieve the internal stress that occurs with the plating of the barrier layer 8 in a later process. If the underlayers 7 are insufficiently thick, the stress relief effect is not fully exerted, and conversely, if the underlayers 7 are too thick, the cost and productivity are reduced, so the thickness of the underlayers 7 is set in the range of 3 μm to 25 μm. These underlayers 7 may be gold, silver, platinum, or alloys mainly made of these metals, so long as they are metal layers that are more malleable or ductile than the barrier layer 8. However, in this embodiment, copper or an alloy mainly made of copper is used because it is more cost-effective than these metals.

[0024] The pair of barrier layers 8 are alloy platings (Ni-P plating layers) containing nickel (Ni) as a main component and phosphorus (P) formed by electrolytic plating to cover the underlayer 7, and the thickness is set in the range of 2 μm to 15 μm. Here, the alloy plating constituting the barrier layer 8 can suppress diffusion into the tin plating constituting the external connection layer 9 as the content of phosphorus in the nickel increases, and if the content of phosphorus in the nickel is insufficient, the diffusion prevention effect is not fully exhibited. However, if the content of phosphorus is too high, the internal stress becomes too high to be relaxed even by the underlayer 7, so the content of phosphorus relative to nickel in the barrier layer 8 is set in the range of 3% to 15%.

[0025] The pair of external connection layers 9 are tin (Sn) plated layers formed by electrolytic plating so as to cover the barrier layer 8, and the thickness thereof is set in the range of 2 μm to 15 μm.

[0026] Next, a method for manufacturing the chip resistor 10 configured as above will be described with reference to the cross-sectional view shown in FIG.

[0027] First, a large-sized substrate from which a large number of insulating substrates 1 are to be cut is prepared. This large-sized substrate is provided in advance with a primary division groove and a secondary division groove in a lattice pattern, and each of the squares divided by the two division grooves becomes one chip area. Although a large-sized substrate 10A corresponding to one chip is shown as a representative in Fig. 2, in reality, each process described below is performed collectively on a large-sized substrate corresponding to many chip areas.

[0028] 2(a), an Ag-Pd paste is screen-printed on the front surface of the large-sized substrate 10A and dried to form a pair of front electrodes 2 facing each other at a predetermined distance at both ends of the longitudinal direction of each chip-forming region. At the same time, or before or after this, an Ag paste is screen-printed on the back surface of the large-sized substrate 10A and dried to form a pair of back electrodes 5 facing each other at a predetermined distance at both ends of the longitudinal direction of each chip-forming region.

[0029] Next, as shown in FIG. 2(b), a resistor paste containing ruthenium oxide or the like is screen-printed on the surface of the large-sized substrate 10A and dried to form a resistor 3 with both ends overlapping the front electrodes 2, and then this is fired at a high temperature of about 850°C. Next, a glass paste is screen-printed on the area covering the resistor 3 and dried to form an undercoat layer 4a covering the resistor 3, and then this is fired at a temperature of about 600°C. Next, a laser beam is irradiated from above the undercoat layer 4a to form a trimming groove (not shown) in the resistor 3 to adjust the resistance value. Thereafter, an epoxy resin paste is screen-printed on the undercoat layer 4a, and this is heated and cured at a temperature of about 200°C to form an overcoat layer 4b, thereby forming a two-layered protective layer 4 consisting of the undercoat layer 4a and the overcoat layer 4b.

[0030] Next, the large-sized substrate 10A is primarily divided into rectangular substrates 10B along the primary division grooves, and then Ni / Cr is sputtered onto the divided surfaces of the rectangular substrates 10B to form end electrodes 6 connecting the front electrodes 2 and back electrodes 5 provided on both the front and back surfaces of the rectangular substrate 10B, as shown in Fig. 2(c). Note that instead of sputtering Ni / Cr onto the divided surfaces of the rectangular substrate 10B, the end electrodes 6 may be formed by applying an Ag-based paste and heating and hardening it.

[0031] Next, the rectangular substrate 10B is secondarily divided along the secondary division grooves into a plurality of chip-like substrates 10C, and then electrolytic plating is performed on these chip-like substrates 10C to form an underlayer 7 covering the connection terminals (front electrode 2, end electrode 6, and back electrode 5) on both ends of the chip-like substrate 10C, as shown in Fig. 2(d). This underlayer 7 is made of a copper plating layer, and its thickness is set in the range of 3 µm to 25 µm (10 µm in this embodiment).

[0032] Next, the chip-like substrate 10C is subjected to electrolytic plating to form a barrier layer 8 covering the underlayer 7, as shown in Fig. 2(e). The barrier layer 8 is made of an alloy plating (Ni-P plating layer) containing nickel (Ni) as a main component and phosphorus (P), and its thickness is set in the range of 2 µm to 15 µm (5 µm in this embodiment). The phosphorus content relative to nickel in the barrier layer 8 is set in the range of 3% to 15% (5% in this embodiment), and even if internal stress occurs due to the addition of phosphorus to nickel, the stress is alleviated by the underlayer 7.

[0033] Next, the chip-shaped substrate 10C is subjected to electrolytic plating to form an external connection layer 9 that covers the surface of the barrier layer 8, as shown in Fig. 2(f). The external connection layer 9 is a Sn-plated layer containing tin (Sn) as a main component, and its thickness is set to a range of 2 µm to 15 µm. As a result, a terminal electrode structure with excellent heat resistance characteristics is formed, which is made up of the barrier layer 8, the external connection layer 9, etc., and the chip resistor 10 shown in Fig. 1 is completed.

[0034] As described above, in the chip resistor 10 according to the first embodiment, the barrier layer 8 covered with the external connection layer 9 made of tin plating is made of an alloy (Ni-P) plating containing nickel (Ni) as the main component and 3% to 15% phosphorus (P), and since this alloy plating diffuses into tin more slowly than nickel, the heat resistance during solder mounting and in the usage environment can be ensured without forming the barrier layer 8 unnecessarily thick. Moreover, since a copper plating layer is formed by electrolytic plating as the base layer 7 of the barrier layer 8, even if internal stress increases due to the addition of phosphorus to nickel, the stress can be alleviated by the base layer 7, and the occurrence of cracks due to the internal stress can be suppressed.

[0035] Furthermore, because the base layer 7, barrier layer 8, and external connection layer 9 are formed by electrolytic plating, each is formed as a dense film, making it possible to maximize the properties (stress relaxation, barrier function, solderability) of each. Since it is possible to perform plating in a series, it is possible to prevent environmental corrosion as much as possible between the plating processes that form each layer, while ensuring adhesion and productivity at the boundaries between each layer.

[0036] 3 is a cross-sectional view of a chip resistor 20 according to a second embodiment of the present invention. The chip resistor 20 according to the second embodiment differs from the chip resistor 10 according to the first embodiment in that a magnetic layer 11 is formed between the connection terminal (the front electrode 2, the end electrode 6, and the back electrode 5) and the barrier layer 8, but the other configurations are basically the same.

[0037] That is, as shown in FIG. 3, this chip resistor 20 is mainly composed of a rectangular insulating substrate 1, a pair of front electrodes 2 formed on both longitudinal ends of the surface of the insulating substrate 1, a resistor 3 formed so as to bridge the pair of front electrodes 2, a protective layer 4 covering the entire resistor 3 and part of the front electrode 2, a pair of back electrodes 5 formed on both longitudinal ends of the back surface of the insulating substrate 1, a pair of end electrodes 6 formed on both longitudinal ends of the insulating substrate 1 and conducting between corresponding front electrodes 2 and back electrodes 5, a pair of magnetic layers 11 covering the front electrodes 2, back electrodes 5 and end electrodes 6, a pair of base layers 7 covering each of the magnetic layers 11, a pair of barrier layers 8 covering each of the base layers 7, and a pair of external connection layers 9 covering each of the barrier layers 8.

[0038] The pair of magnetic layers 11 are nickel (Ni) plating layers formed by electrolytic plating so as to cover the connection terminals, and the thickness is set in the range of 2 μm to 15 μm. The magnetic layer 11 can increase the magnetism of the barrier layer 8, which is reduced by adding phosphorus to nickel, and may be formed between the underlayer 7 and the barrier layer 8. Note that the configuration other than the magnetic layer 11 is the same as that of the first embodiment, and therefore the same reference numerals as in FIG. 1 are used to omit redundant description here.

[0039] Next, a method for manufacturing the chip resistor 20 configured as described above will be described with reference to the cross-sectional view shown in Fig. 4. In the manufacturing process shown in Fig. 4, Fig. 4(a) corresponds to Fig. 2(c) in the first embodiment, and the process before that is the same as that in the first embodiment.

[0040] That is, after forming a front electrode 2, resistor 3, protective layer 4 (undercoat layer 4a and overcoat layer 4b), and back electrode 5 on a large-sized substrate (not shown), Ni / Cr is sputtered onto the divided surfaces of a rectangular substrate 10B obtained by first dividing the large-sized substrate, thereby forming end electrodes 6 that connect the front electrodes 2 and back electrodes 5 provided on both the front and back surfaces of the rectangular substrate 10B, as shown in Figure 4(a).

[0041] Next, the rectangular substrate 10B is secondarily divided along the secondary division grooves into a plurality of chip-like substrates 10C, and then electrolytic plating is performed on these chip-like substrates 10C to form magnetic layers 11 covering the connection terminals (front electrodes 2, end electrodes 6, and back electrodes 5) on both ends of the chip-like substrates 10C, as shown in Fig. 4(b). The magnetic layers 11 are made of a nickel (Ni) plating layer, and the thickness thereof is set to a range of 2 µm to 15 µm (5 µm in this embodiment).

[0042] Next, electrolytic plating is applied to the chip-shaped substrate 10C to form an underlayer 7 covering the magnetic layer 11 on both ends of the chip-shaped substrate 10C, as shown in Fig. 4(c). The underlayer 7 is made of a copper plating layer, and its thickness is set in the range of 3 µm to 25 µm (10 µm in this embodiment).

[0043] Next, the chip-shaped substrate 10C is subjected to electrolytic plating to form a barrier layer 8 covering the underlayer 7, as shown in Fig. 4(d). The barrier layer 8 is made of an alloy plating (Ni-P plating layer) containing nickel (Ni) as a main component and phosphorus (P), and has a thickness set in the range of 2 µm to 15 µm (5 µm in this embodiment). The phosphorus content relative to nickel in the barrier layer 8 is set in the range of 3% to 15% (5% in this embodiment).

[0044] Next, the chip-like substrate 10C is subjected to electrolytic plating to form an external connection layer 9 covering the surface of the barrier layer 8, as shown in Fig. 4(e). The external connection layer 9 is a Sn-plated layer containing tin (Sn) as a main component, and its thickness is set in the range of 2 µm to 15 µm. As a result, a terminal electrode structure having excellent heat resistance characteristics, consisting of the barrier layer 8, the external connection layer 9, etc., is formed, and the chip resistor 20 shown in Fig. 3 is completed.

[0045] As described above, in the chip resistor 20 of the second embodiment, the magnetic layer 11 made of a nickel-plated layer is formed between the connection terminals (the front electrode 2, the end electrode 6, and the back electrode 5) and the barrier layer 8. Therefore, by utilizing the magnetic properties of the magnetic layer 11, it is possible to magnetically stabilize the posture of the product, for example, during the taping process in which the product is stored in a tape-like packaging body, or when the product is removed from the packaging body and mounted on a circuit board.

[0046] In the chip resistor 20 according to the second embodiment, the magnetic layer 11 is formed between the connection terminals (the front electrode 2, the end electrode 6, and the back electrode 5) and the underlayer 7, but there is no problem if the magnetic layer 11 is formed between the connection terminals and the barrier layer 8. That is, the magnetic layer 11 may be formed between the underlayer 7 and the barrier layer 8, or the magnetic layer 11 may be formed both between the connection terminals and the underlayer 7 and between the underlayer 7 and the barrier layer 8.

[0047] In addition, in each of the above embodiments, the present invention has been described as being applied to a chip resistor, which is an example of a surface mount component, but the present invention can also be applied to electronic components other than chip resistors, for example, lead components having pin-shaped connection terminals, such as connectors. [Explanation of symbols]

[0048] 1 Insulating substrate (component body) 2 Front electrode (connection terminal) 3. Resistor 4 protective layer 4a Undercoat layer 4b Overcoat layer 5 Back electrode (connection terminal) 6 End electrode (connection terminal) 7 Base layer 8. Barrier Layer 9 External Connection Layer 10 Chip resistors (electronic components) 11 Magnetic layer

Claims

1. The component includes a rectangular parallelepiped main body, a connection terminal formed on the main body, a base layer formed by electrolytic plating so as to cover the connection terminal, a barrier layer formed by electrolytic plating so as to cover the base layer, and an external connection layer mainly composed of tin formed on a surface of the barrier layer, the barrier layer covers the entire surface of the base layer, including the front surface, end surfaces, and back surface of the component body; the barrier layer is made of an alloy plating of nickel with 3% to 15% phosphorus added, and the undercoat layer is made of copper or an alloy mainly composed of copper, The electronic component is characterized in that the film thickness of the underlayer is set in the range of 3 μm to 25 μm.

2. 2. The electronic component according to claim 1, An electronic component comprising: a magnetic layer formed between the connection terminal and the barrier layer.

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