Shunt resistor, manufacturing method thereof, and semiconductor device

Abstract

To provide a shunt resistor, a manufacturing method thereof, and a semiconductor device which can be miniaturized.SOLUTION: A shunt resistor A1 includes: a resistor layer 10; a first electrode layer 11 laminated on a first side in a z direction and having a first mounting surface 111; and a second electrode layer 12 laminated on a second side in the z direction and having a second mounting surface 121. The resistor layer includes a copper-based alloy or a nichrome-based alloy, the first electrode layer contains at least one of copper, silver, gold, and nickel, and the second electrode layer contains at least one of copper, silver, gold, and nickel.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a shunt resistor, a method for manufacturing a shunt resistor, and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses an example of a conventional resistor. The resistor disclosed in the document includes a resistive body and a pair of electrodes. This resistor is configured as a shunt resistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-163238 A

[0004] [overview] When a resistor is mounted in an electric device or the like, it is necessary to secure a space for mounting the resistor.

[0005] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a shunt resistor that can be miniaturized, a manufacturing method for a shunt resistor, and a semiconductor device.

[0006] A shunt resistor provided by a first aspect of the present disclosure comprises a resistor layer, a first electrode layer laminated on a first side in a thickness direction of the resistor layer, and a second electrode layer laminated on a second side in the thickness direction of the resistor layer.

[0007] A semiconductor device provided by a second aspect of the present disclosure includes a first substrate including a first conductive layer, a second substrate including a second conductive layer, a first switching element having a first drain electrode, a first source electrode, and a first gate electrode and constituting an upper arm circuit, a second switching element having a second drain electrode, a second source electrode, and a second gate electrode and constituting a lower arm circuit, and a shunt resistor provided by the first aspect of the present disclosure, wherein the first conductive layer and the second conductive layer face each other in a thickness direction, the first drain electrode is conductively joined to the first conductive layer, the second drain electrode is conductively joined to the second conductive layer, the first source electrode and the second conductive layer are conductive, and the shunt resistor is disposed between the first substrate and the second substrate in the thickness direction and is electrically disposed in a conduction path of a current switched by at least one of the first switching element and the second switching element.

[0008] A manufacturing method for a shunt resistor provided by a third aspect of the present disclosure includes a step of preparing a resistor layer, a step of forming a laminated metal material by forming a first electrode layer by plating on a first side in a thickness direction of the resistor layer and a step of forming a second electrode layer by plating on a second side in a thickness direction of the resistor layer, and a step of singulating the laminated metal material.

[0009] A manufacturing method for a shunt resistor provided by a fourth aspect of the present disclosure includes a step of forming a laminated metal material by pressure-bonding a resistor layer, a first electrode layer located on a first side in a thickness direction of the resistor layer, and a second electrode layer located on a second side in the thickness direction of the resistor layer, and a step of singulating the laminated metal material.

[0010] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0011] [Figure 1]FIG. 1 is a perspective view showing a shunt resistor according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a cross-sectional view showing a shunt resistor according to the first embodiment of the present disclosure. [Diagram 3] FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a shunt resistor according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a shunt resistor according to the first embodiment of the present disclosure. [Diagram 5] FIG. 5 is a cross-sectional view showing an example of a method for manufacturing a shunt resistor according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a circuit diagram showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 13] FIG. 13 is a cross-sectional view showing another example of a shunt resistor according to the first embodiment of the present disclosure.

[0012] [Detailed Description] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the drawings.

[0013] The terms "first," "second," "third," etc. in this disclosure are used merely for identification purposes and are not intended to impose any ordering on their objects.

[0014] In this disclosure, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B in contact with a certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B". Furthermore, unless otherwise specified, "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in this disclosure, "a surface A faces (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0015] 1 and 2 show a shunt resistor according to a first embodiment of the present disclosure. The shunt resistor A1 of this embodiment includes a resistor layer 10, a first electrode layer 11, and a second electrode layer 12. The shape of the shunt resistor A1 is not limited in any way and is a rectangle having two sides extending in the x or y direction when viewed in the z direction. The thickness t of the shunt resistor A1 is not limited in any way and is, for example, 0.7 mm or more and 5.0 mm or less. The area of ​​the shunt resistor A1 when viewed in the z direction is also not limited in any way and is, for example, 10 mm 2 More than 50mm 2 The following is the result.

[0016] The resistor layer 10 is a main component that determines the resistance value of the shunt resistor A1. The resistor layer 10 has a thickness direction in the z direction and is flat and extends along the x and y directions. The thickness t0 of the resistor layer 10 is not limited and is, for example, 0.5 mm or more and 2.0 mm or less. In this embodiment, the resistor layer 10 is rectangular when viewed in the z direction.

[0017] The material of the resistor layer 10 is appropriately selected depending on, for example, the resistance value that the shunt resistor A1 should have, the environment in which the shunt resistor A1 is used, etc. Examples of materials for the resistor layer 10 include copper-based alloys and nichrome-based alloys, and specific examples thereof include a Cu-Mn-Sn alloy (Zeranin: registered trademark), a Cu-Mn-Ni alloy (Manganin: registered trademark), a Cu-Ni alloy (GCN49: Tokyo Resistance Wire Co., Ltd.), and a Ni-Cr alloy (NCH-1: Tokyo Resistance Wire Co., Ltd.).

[0018] The first electrode layer 11 is laminated on a first side in the z direction of the resistor layer 10 (the lower side in FIG. 2). The material of the first electrode layer 11 has a lower electrical resistivity than the material of the resistor layer 10. The material of the first electrode layer 11 is not limited in any way, and examples thereof include metals such as Cu (copper), Ag (silver), Au (gold), Ni (nickel), Sn (tin), etc., or alloys of these metals.

[0019] The thickness t1 of the first electrode layer 11 is not limited in any way and is, for example, 0.1 mm or more and 1.0 mm or less. The shape and size of the first electrode layer 11 may be the same as or different from those of the resistor layer 10. In this embodiment, the first electrode layer 11 is rectangular when viewed in the z direction. When viewed in the z direction, the outer edge of the resistor layer 10 and the outer edge of the first electrode layer 11 coincide with each other. That is, the first electrode layer 11 has the same shape and size as the resistor layer 10 when viewed in the z direction.

[0020] The first electrode layer 11 has a first mounting surface 111. The first mounting surface 111 faces a first side in the z direction. As shown in Fig. 2, the first mounting surface 111 is used when mounting the shunt resistor A1 on a mounting object C.

[0021] The second electrode layer 12 is laminated on a second side in the z direction of the resistor layer 10 (upper side in FIG. 2). The material of the second electrode layer 12 has a lower electrical resistivity than the material of the resistor layer 10. The material of the second electrode layer 12 is not limited in any way, and examples thereof include metals such as Cu (copper), Ag (silver), Au (gold), Ni (nickel), Sn (tin), etc., or alloys thereof.

[0022] The thickness t2 of the second electrode layer 12 is not limited in any way and is, for example, 0.1 mm or more and 2.0 mm or less. The shape and size of the second electrode layer 12 may be the same as or different from those of the resistor layer 10. In this embodiment, the second electrode layer 12 is rectangular when viewed in the z direction. When viewed in the z direction, the outer edge of the resistor layer 10 and the outer edge of the second electrode layer 12 coincide with each other. That is, the second electrode layer 12 has the same shape and size as the resistor layer 10 when viewed in the z direction.

[0023] The second electrode layer 12 has a second mounting surface 121. The second mounting surface 121 faces a second side in the z direction. As shown in Fig. 2, the second mounting surface 121 is used when mounting the shunt resistor A1 on a mounting object C.

[0024] Next, an example of a method for manufacturing the shunt resistor A1 will be described below with reference to FIGS.

[0025] First, a resistor layer 10 is prepared as shown in FIG. 3. In this example, the resistor layer 10 is large enough to form a plurality of shunt resistors A1. Next, the resistor layer 10 is immersed in a plating solution Ps. Then, metal layers are formed on both sides of the resistor layer 10, for example, by electrolytic plating. One of these metal layers becomes the first electrode layer 11, and the other becomes the second electrode layer 12, and a laminated metal material M shown in FIG. 4 is obtained.

[0026] Next, the laminated metal material M is cut along cutting lines CL to separate the laminated metal material M. As a result, a plurality of shunt resistors A1 are obtained.

[0027] Next, another example of a method for manufacturing the shunt resistor A1 will be described below with reference to FIG.

[0028] First, as shown in Fig. 5, a resistor layer 10, a first electrode layer 11, and a second electrode layer 12 are prepared. The resistor layer 10, the first electrode layer 11, and the second electrode layer 12 are large enough to form a plurality of shunt resistors A1. Next, the first electrode layer 11 is disposed on a first side in the thickness direction of the resistor layer 10, and the second electrode layer 12 is disposed on a second side in the thickness direction of the resistor layer 10. Then, the resistor layer 10, the first electrode layer 11, and the second electrode layer 12 are pressure-bonded.

[0029] The specific method of this compression bonding is not limited in any way, and in this example, the resistor layer 10, the first electrode layer 11, and the second electrode layer 12 are rolled by rollers RL from both sides in the thickness direction of the resistor layer 10. By performing the rolling process by the rollers RL, a laminated metal material M having the resistor layer 10, the first electrode layer 11, and the second electrode layer 12 is obtained.

[0030] Thereafter, for example, the laminated metal material M shown in FIG. 4 is singulated to obtain a plurality of shunt resistors A1.

[0031] 6 to 12 show an example of a semiconductor device using the shunt resistor A1. The semiconductor device B1 of this embodiment includes the shunt resistor A1, a first substrate 2, a second substrate 3, a first switching element 4, and a second switching element 5. The semiconductor device B1 further includes a positive terminal 81, a negative terminal 82, an output terminal 83, a first gate terminal 84, a second gate terminal 85, and detection terminals 86 and 87.

[0032] There is no limitation on the specific use of the semiconductor device B1. In the semiconductor device B1, the first switching element 4 constitutes an upper arm circuit, and the second switching element 5 constitutes a lower arm circuit, thereby forming a half-bridge circuit. The semiconductor device B1 constitutes, for example, an inverter for converting DC power into AC power and supplying power to a drive source such as a motor. The semiconductor device B1 of this embodiment will be described taking the case where it has one half-bridge circuit as an example, but it may also be configured to have, for example, three half-bridge circuits and supply power to a so-called three-phase AC motor.

[0033] As shown in FIG. 8 and FIG. 9, the first substrate 2 has a first conductive layer 21, a third conductive layer 22, a first insulating layer 20, and a first metal layer 25, and is configured as, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate. The first conductive layer 21 is a layer having a thickness direction in the z direction, and contains, for example, Cu (copper). The third conductive layer 22 is separated from the first conductive layer 21. The third conductive layer 22 is a layer having a thickness direction in the z direction, and contains, for example, Cu (copper). The first substrate 2 is not limited to the above-mentioned configuration, and may be configured without the first insulating layer 20 and the first metal layer 25, for example.

[0034] The first insulating layer 20 is a layer whose thickness direction is in the z direction and has insulating properties. The first insulating layer 20 is made of, for example, ceramic.

[0035] The first metal layer 25 is a layer whose thickness direction is the z direction, and is laminated on opposite sides in the z direction from the first conductive layer 21 and the third conductive layer 22 with the first insulating layer 20 interposed therebetween. The first metal layer 25 contains, for example, Cu (copper).

[0036] First substrate 2 is not limited to the above-mentioned configuration, and may have a configuration that does not include first insulating layer 20 and first metal layer 25, for example.

[0037] The second substrate 3 has a second conductive layer 31, a fourth conductive layer 32, a second insulating layer 30, and a second metal layer 35, and is configured as, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate. The second conductive layer 31 is a layer whose thickness direction is the z direction and contains, for example, Cu (copper). The fourth conductive layer 32 is separated from the second conductive layer 31. The fourth conductive layer 32 is a layer whose thickness direction is the z direction and contains, for example, Cu (copper).

[0038] The second insulating layer 30 is a layer whose thickness direction is in the z direction and has insulating properties. The second insulating layer 30 is made of, for example, ceramic.

[0039] The second metal layer 35 is a layer whose thickness direction is the z direction, and is laminated on the opposite side in the z direction from the second conductive layer 31 and the fourth conductive layer 32 with the second insulating layer 30 interposed therebetween. The second metal layer 35 contains, for example, Cu (copper).

[0040] The second substrate 3 is not limited to the above-mentioned configuration, and may have a configuration that does not include the second insulating layer 30 and the second metal layer 35, for example.

[0041] At least a portion of the first conductive layer 21 and a portion of the second conductive layer 31 face each other in the z direction. Also, a portion of the third conductive layer 22 and a portion of the second conductive layer 31 face each other in the z direction. Also, at least a portion of the third conductive layer 22 and a portion of the fourth conductive layer 32 face each other in the z direction.

[0042] The first switching elements 4 are made of a semiconductor material. The semiconductor material may be, for example, SiC (silicon carbide), Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride). In the present embodiment, each of the first switching elements 4 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first switching elements 4 are not limited to MOSFETs, and may be field-effect transistors including metal-insulator-semiconductor FETs (MISFETs). The first switching element 4 has a first drain electrode 41, a first source electrode 42, and a first gate electrode 43. The first drain electrode 41 is disposed on the opposite side in the z direction to the first source electrode 42 and the first gate electrode 43.

[0043] The first switching element 4 is disposed between the first conductive layer 21 and the second conductive layer 31 in the z direction. The first drain electrode 41 is conductively joined to the first conductive layer 21. The first source electrode 42 is conductively joined to the second conductive layer 31. There are no limitations on the method of these conductive joints, and for example, solder bonding, bonding with a silver baked material, solid-phase diffusion bonding, or the like may be used as appropriate.

[0044] The second switching elements 5 are made of a semiconductor material. The semiconductor material may be, for example, SiC (silicon carbide), Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride). In this embodiment, each of the second switching elements 5 is a MOSFET. The second switching elements 5 are not limited to MOSFETs, and may be field effect transistors including MISFETs. The second switching element 5 has a second drain electrode 51, a second source electrode 52, and a second gate electrode 53. The second drain electrode 51 is disposed on the opposite side in the z direction to the second source electrode 52 and the second gate electrode 53.

[0045] The second switching element 5 is disposed between the third conductive layer 22 and the second conductive layer 31 in the z direction. The second drain electrode 51 is conductively joined to the second conductive layer 31. The second source electrode 52 is conductively joined to the third conductive layer 22. There are no limitations on the method of these conductive joints, and for example, solder bonding, bonding with a silver baked material, solid-phase diffusion bonding, or the like may be used as appropriate.

[0046] 9, the positive electrode terminal 81 is conductively joined to the first conductive layer 21. The method of this conductive joining is not limited in any way, and for example, solder joining, joining using a silver baked material, laser welding, solid-phase diffusion joining, etc. are appropriately used. The positive electrode terminal 81 contains, for example, Cu (copper).

[0047] 8, the negative electrode terminal 82 is conductively joined to the fourth conductive layer 32. The method of this conductive joining is not limited in any way, and for example, solder joining, joining with a silver baked material, laser welding, solid-phase diffusion joining, etc. are appropriately used. The negative electrode terminal 82 contains, for example, Cu (copper).

[0048] 8 and 9, the output terminal 83 is conductively joined to the second conductive layer 31. There are no limitations on the method of this conductive joining, and for example, solder joining, joining with a silver baked material, laser welding, solid-phase diffusion joining, etc. are appropriately used. The output terminal 83 includes, for example, Cu (copper).

[0049] 10, the first gate terminal 84 is conductively joined to the first gate electrode 43 of the first switching element 4. There are no limitations on the method of this conductive joining, and for example, solder joining, joining using a silver baked material, solid-phase diffusion bonding, etc. may be used as appropriate.

[0050] 11, the second gate terminal 85 is conductively joined to the second gate electrode 53 of the second switching element 5. The method of this conductive joining is not limited in any way, and for example, solder joining, joining using a silver baked material, solid-phase diffusion bonding, etc. can be used as appropriate.

[0051] As shown in FIG. 8, the shunt resistor A1 is disposed between the first substrate 2 and the second substrate 3 in the z direction. The shunt resistor A1 is electrically disposed in a conduction path of a current switched by at least one of the first switching element 4 and the second switching element 5. In this embodiment, the shunt resistor A1 is disposed between the third conductive layer 22 and the fourth conductive layer 32. The first mounting surface 111 of the first electrode layer 11 is conductively joined to the third conductive layer 22. In addition, the second mounting surface 121 of the second electrode layer 12 is conductively joined to the fourth conductive layer 32. There is no limitation on the method of these conductive joints, and for example, solder bonding, bonding using a silver baked material, solid-phase diffusion bonding, etc. may be used as appropriate.

[0052] For example, in order to arrange the first switching element 4, the second switching element 5, the first gate terminal 84, the second gate terminal 85, etc. between the first substrate 2 and the second substrate 3, when the distance in the z direction between the third conductive layer 22 and the fourth conductive layer 32 is relatively large, the shunt resistor A1 may be configured as shown in FIG. 13. In this example, the thickness t1 of the first electrode layer 11 and the thickness t2 of the second electrode layer 12 are greater than the thickness t0 of the resistor layer 10. This allows the thickness t of the shunt resistor A1 to be increased. Even if the thicknesses t1 and t2 are increased, the resistance value of the shunt resistor A1 can be maintained at a desired value as long as the thickness t0 of the resistor layer 10 is not changed.

[0053] The detection terminals 86 and 87 are terminals used for current detection using the shunt resistor A1. The detection terminal 86 is conductively joined to, for example, the third conductive layer 22. The detection terminal 87 is conductively joined to, for example, the fourth conductive layer 32.

[0054] The sealing resin 7 covers at least a portion of each of the first substrate 2, the second substrate 3, the first switching element 4, the second switching element 5, the positive electrode terminal 81, the negative electrode terminal 82, the output terminal 83, the first gate terminal 84, the second gate terminal 85, and the detection terminals 86 and 87. The sealing resin 7 has insulating properties and contains, for example, an epoxy resin.

[0055] The positive electrode terminal 81, the negative electrode terminal 82, the output terminal 83, the first gate terminal 84, the second gate terminal 85, and the detection terminals 86, 87 each have a portion protruding from the sealing resin 7. However, the specific configurations of the positive electrode terminal 81, the negative electrode terminal 82, the output terminal 83, the first gate terminal 84, the second gate terminal 85, and the detection terminals 86, 87 are not limited in any way, and various configurations may be adopted as long as they are capable of being electrically connected to the outside.

[0056] One side of each of the first metal layer 25 and the second metal layer 35 is exposed from the sealing resin 7.

[0057] FIG. 12 is a circuit diagram showing a semiconductor device B1. As shown in the figure, the first switching element 4 constitutes an upper arm circuit, and the second switching element 5 constitutes a lower arm circuit. The positive terminal 81 and the negative terminal 82 are terminals to which DC power is input. The output terminal 83 is a terminal connected to a drive source or the like to which AC power is supplied. In this embodiment, the shunt resistor A1 is electrically disposed between the negative terminal 82 and the second switching element 5, and is electrically disposed in the conduction path of the current switched by the second switching element 5. Unlike this embodiment, the shunt resistor A1 may be electrically disposed between the positive terminal 81 and the first switching element 4, and thus be electrically disposed in the conduction path of the current switched by the first switching element 4.

[0058] When supplying power to a three-phase AC motor, a configuration may be provided in which three sets of the first switching element 4, the second switching element 5, and the output terminal 83 are provided.

[0059] The first gate terminal 84 is a terminal for controlling the switching of the first switching element 4. The second gate terminal 85 is a terminal for controlling the switching of the second switching element 5.

[0060] The detection terminals 86 and 87 are terminals for electrically connecting a detector (not shown) for detecting a current flowing through the shunt resistor A1 in parallel to the shunt resistor A1.

[0061] Next, the functions of the shunt resistor A1 and the semiconductor device B1 will be described.

[0062] According to this embodiment, the shunt resistor A1 has the first electrode layer 11 and the second electrode layer 12 disposed on both sides in the thickness direction with the resistor layer 10 sandwiched therebetween. This makes it possible to dispose the mounting object C of the shunt resistor A1 on both sides in the z direction of the shunt resistor A1, as shown in Fig. 2. This makes it possible to reduce the size in the x and y directions of the mounting structure including the mounting object C on which the shunt resistor A1 is mounted.

[0063] Since the first electrode layer 11 has the first mounting surface 111 and the second electrode layer 12 has the second mounting surface 121, the mounting object C is disposed so as to overlap the shunt resistor A1 when viewed in the z direction. This is preferable for reducing the size of the above-mentioned mounting structure in the x and y directions.

[0064] In the semiconductor device B1, the shunt resistor A1 is disposed between the first substrate 2 and the second substrate 3 in the z direction. This makes it possible to avoid an increase in the size of the semiconductor device B1 in the x direction or the y direction due to the provision of the shunt resistor A1. This makes it possible to miniaturize the semiconductor device B1.

[0065] The shunt resistor, the manufacturing method of the shunt resistor, and the semiconductor device according to the present disclosure are not limited to the above-described embodiment. The specific configurations of the shunt resistor, the manufacturing method of the shunt resistor, and the semiconductor device according to the present disclosure can be freely designed in various ways.

[0066] [Appendix 1] A resistor layer; a first electrode layer laminated on a first side of the resistor layer in a thickness direction; a second electrode layer laminated on a second side of the resistor layer in the thickness direction; A shunt resistor. [Appendix 2] The shunt resistor of claim 1, wherein the first electrode layer has a first mounting surface facing the first side in the thickness direction. [Appendix 3] The shunt resistor of claim 2, wherein the second electrode layer has a second mounting surface facing the second side in the thickness direction. [Appendix 4] 4. The shunt resistor according to claim 3, wherein an outer edge of the resistor layer and an outer edge of the first electrode layer coincide with each other when viewed in the thickness direction. [Appendix 5] 5. The shunt resistor according to claim 3, wherein an outer edge of the resistor layer and an outer edge of the second electrode layer coincide with each other when viewed in the thickness direction. [Appendix 6] 6. The shunt resistor according to claim 3, wherein the resistor layer includes a copper-based alloy or a nichrome-based alloy. [Appendix 7] 7. The shunt resistor according to claim 3, wherein the first electrode layer contains at least one of copper, silver, gold, and nickel. [Appendix 8] 8. The shunt resistor according to claim 3, wherein the second electrode layer contains at least one of copper, silver, gold, and nickel. [Appendix 9] a first substrate including a first conductive layer; a second substrate including a second conductive layer; a first switching element having a first drain electrode, a first source electrode, and a first gate electrode, and constituting an upper arm circuit; a second switching element having a second drain electrode, a second source electrode, and a second gate electrode, and constituting a lower arm circuit; A shunt resistor according to any one of appendix 3 to 8, the first conductive layer and the second conductive layer face each other in the thickness direction, the first drain electrode is conductively joined to the first conductive layer; the second drain electrode is conductively joined to the second conductive layer; the first source electrode and the second conductive layer are electrically connected to each other; The shunt resistor is disposed between the first substrate and the second substrate in the thickness direction and is electrically disposed in a conduction path of a current switched by at least one of the first switching element and the second switching element. [Appendix 10] the first substrate further includes a third conductive layer facing the second conductive layer in the thickness direction, the second substrate further includes a fourth conductive layer facing the third conductive layer in the thickness direction, the first mounting surface is conductively joined to the second conductive layer; 10. The semiconductor device according to claim 9, wherein the second mounting surface is conductively joined to the third conductive layer. [Appendix 11] the first substrate has a first metal layer located on a side opposite to the first conductive layer in the thickness direction, and a first insulating layer interposed between the first conductive layer and the first metal layer; 11. The semiconductor device of claim 9, wherein the second substrate has a second metal layer located on the opposite side of the second conductive layer in the thickness direction, and a second insulating layer interposed between the second conductive layer and the second metal layer. [Appendix 12] a sealing resin covering the first switching element, the second switching element, the first conductive layer, and the second conductive layer; 12. The semiconductor device according to claim 11, wherein the first metal layer and the second metal layer are exposed from the sealing resin. [Appendix 13] providing a resistor layer; forming a first electrode layer by plating on a first side in a thickness direction of the resistor layer, and forming a second electrode layer by plating on a second side in the thickness direction of the resistor layer, thereby forming a laminated metal material; singulating the laminated metal material; A method for manufacturing a shunt resistor comprising: [Appendix 14] forming a laminated metal material by compression bonding a resistor layer, a first electrode layer located on a first side in a thickness direction of the resistor layer, and a second electrode layer located on a second side in the thickness direction of the resistor layer; singulating the laminated metal material; A method for manufacturing a shunt resistor comprising: [Explanation of symbols]

[0067] A1: Shunt resistor B1: Semiconductor device 2: First board 3: Second board 4: First switching element 5: Second switching element 7: Sealing resin 10:Resistor layer 11:First electrode layer 12:Second electrode layer 20: First insulating layer 21: First conductive layer 22: Third conductive layer 25: 1st metal layer 30: Second insulating layer 31: Second conductive layer 32: Fourth conductive layer 35: 2nd metal layer 41: First drain electrode 42: First source electrode 43: First gate electrode 51: Second drain electrode 52: Second source electrode 53: Second gate electrode 81: Positive terminal 82: Negative terminal 83: Output terminal 84: First gate terminal 85: Second gate terminal 86: Detection terminal 87: Detection terminal 111: First mounting surface 121: Second mounting surface C: Object to be implemented CL: Cutting line M: Laminated metal material Ps: Plating solution RL: Laura t, t0, t1, t2: thickness

Claims

1. A resistor layer; a first electrode layer laminated on a first side of the resistor layer in a thickness direction; a second electrode layer laminated on a second side of the resistor layer in the thickness direction; A shunt resistor.

2. The shunt resistor according to claim 1 , wherein the first electrode layer has a first mounting surface facing the first side in the thickness direction.

3. The shunt resistor according to claim 2 , wherein the second electrode layer has a second mounting surface facing the second side in the thickness direction.

4. The shunt resistor according to claim 3 , wherein an outer edge of the resistor layer and an outer edge of the first electrode layer coincide with each other when viewed in the thickness direction.

5. The shunt resistor according to claim 3 , wherein an outer edge of the resistor layer and an outer edge of the second electrode layer coincide with each other when viewed in the thickness direction.

6. The shunt resistor of claim 3 , wherein the resistor layer comprises a copper-based alloy or a nichrome-based alloy.

7. The shunt resistor according to claim 3 , wherein the first electrode layer includes at least one of copper, silver, gold, and nickel.

8. The shunt resistor according to claim 3 , wherein the second electrode layer includes at least one of copper, silver, gold, and nickel.

9. a first substrate including a first conductive layer; a second substrate including a second conductive layer; a first switching element having a first drain electrode, a first source electrode, and a first gate electrode, and constituting an upper arm circuit; a second switching element having a second drain electrode, a second source electrode, and a second gate electrode, and constituting a lower arm circuit; and a shunt resistor according to any one of claims 3 to 8, the first conductive layer and the second conductive layer face each other in the thickness direction, the first drain electrode is conductively joined to the first conductive layer; the second drain electrode is conductively joined to the second conductive layer; the first source electrode and the second conductive layer are electrically connected to each other; The shunt resistor is disposed between the first substrate and the second substrate in the thickness direction and is electrically disposed in a conduction path of a current switched by at least one of the first switching element and the second switching element.

10. the first substrate further includes a third conductive layer facing the second conductive layer in the thickness direction, the second substrate further includes a fourth conductive layer facing the third conductive layer in the thickness direction, the first mounting surface is conductively joined to the second conductive layer; The semiconductor device according to claim 9 , wherein the second mounting surface is conductively joined to the third conductive layer.

11. the first substrate has a first metal layer located on a side opposite to the first conductive layer in the thickness direction, and a first insulating layer interposed between the first conductive layer and the first metal layer; 10. The semiconductor device of claim 9, wherein the second substrate has a second metal layer located on the opposite side of the second conductive layer in the thickness direction, and a second insulating layer interposed between the second conductive layer and the second metal layer.

12. a sealing resin covering the first switching element, the second switching element, the first conductive layer, and the second conductive layer; The semiconductor device according to claim 11 , wherein the first metal layer and the second metal layer are exposed from the sealing resin.

13. providing a resistor layer; forming a first electrode layer by plating on a first side in a thickness direction of the resistor layer, and forming a second electrode layer by plating on a second side in the thickness direction of the resistor layer, thereby forming a laminated metal material; singulating the laminated metal material; A method for manufacturing a shunt resistor comprising:

14. forming a laminated metal material by compression bonding a resistor layer, a first electrode layer located on a first side in a thickness direction of the resistor layer, and a second electrode layer located on a second side in the thickness direction of the resistor layer; singulating the laminated metal material; A method for manufacturing a shunt resistor comprising:

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