Overcurrent protection circuit, switch device, electronic device, vehicle

Abstract

To provide an overcurrent protection circuit that can provide appropriate diagnostic output, and a switch device, an electronic apparatus, and a vehicle, each using such an overcurrent protection circuit.SOLUTION: An overcurrent protection circuit 100 includes: an overcurrent detection unit 101 configured to compare an output current Io flowing through a switch element and an overcurrent detection value Iocp to generate an overcurrent detection signal S101; an output activation detection unit 102 configured to compare an output voltage Vo appearing on one end of the switch element and a threshold voltage Vth to generate an output activation detection signal S102; a logic unit 103 configured to combine the detection signals S101, S102 to generate a logic operation signal S103; and a diagnostic output unit 104 configured to provide diagnostic output on the basis of the logic operation signal. The logic unit shifts the logic operation signal to a logic level of abnormal state when the detection signal S101 is shifted to a logic level of overcurrent detection state, and holds the logic operation signal at the logic level of abnormal state even when the detection signal S101 is subsequently shifted to a logic level of overcurrent non-detection state, unless the detection signal S102 is shifted to a logic level of output activation state.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The invention disclosed in this specification relates to an overcurrent protection circuit, and a switch device, electronic device, and vehicle using the same. [Background technology]

[0002] The applicant of the present application has proposed many new technologies relating to switch devices such as in-vehicle IPDs (intelligent power devices) (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 187785 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional switch devices, there is room for further improvement in the diagnostic output function (function of reporting an abnormality to the outside of the device) of the overcurrent protection circuit.

[0005] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide an overcurrent protection circuit capable of providing an appropriate diagnostic output, and a switch device, electronic device, and vehicle using the same. [Means for solving the problem]

[0006] For example, an overcurrent protection circuit disclosed in this specification may have an overcurrent detection unit configured to generate an overcurrent detection signal by comparing an output current flowing through a switch element with a predetermined overcurrent detection value, an output start-up detection unit configured to generate an output start-up detection signal by comparing an output voltage appearing at one end of the switch element with a predetermined threshold voltage, a logic unit configured to generate a logical operation signal by combining the overcurrent detection signal and the output start-up detection signal, and a diagnostic output unit configured to perform a diagnostic output based on the logical operation signal, and the logic unit may be configured to set the logical operation signal to an abnormality logical level when the overcurrent detection signal reaches a logical level when an overcurrent is detected, and thereafter maintain the logical operation signal at the abnormality logical level even if the overcurrent detection signal reaches a logical level when an overcurrent is not detected as long as the output start-up detection signal does not reach the output start-up logical level.

[0007] However, other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto. Effect of the Invention

[0008] According to the invention disclosed in this specification, it is possible to provide an overcurrent protection circuit capable of providing an appropriate diagnostic output, and a switch device, electronic device, and vehicle using the same. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a basic configuration of a semiconductor integrated circuit device. [Diagram 2] FIG. 2 is a diagram illustrating an example of the configuration of the gate control unit. [Diagram 3] FIG. 3 is a diagram illustrating a comparative example of an overcurrent protection circuit. [Figure 4] FIG. 4 is a diagram showing an example of a diagnosis output operation in the comparative example. [Diagram 5] FIG. 5 illustrates a novel embodiment of an overcurrent protection circuit. [Figure 6]FIG. 6 is a diagram illustrating an example of a configuration of the logic unit. [Figure 7] FIG. 7 is a diagram (truth table) showing the arithmetic operation of the logic unit. [Figure 8] FIG. 8 is a timing chart showing the arithmetic operation of the logic section. [Figure 9] FIG. 9 is a diagram illustrating an example of a diagnosis output operation in the embodiment. [Figure 10] FIG. 10 is an external view showing an example of a configuration of a vehicle. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Semiconductor integrated circuit device (basic configuration)> 1 is a diagram showing the basic configuration of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of this configuration example is an in-vehicle high-side switch LSI (a type of in-vehicle IPD) that establishes / cuts conduction between an application terminal of a power supply voltage VBB and a load 3 in response to an instruction from an ECU [electronic control unit] 2.

[0011] The semiconductor integrated circuit device 1 includes external terminals T1 to T4 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving a supply of a power supply voltage VBB (for example, 12 V) from a battery (not shown). The external terminal T2 is a load connection terminal or an output terminal (OUT pin) for externally connecting a load 3 (such as a bulb lamp, a relay coil, a solenoid, a light-emitting diode, or a motor). The external terminal T3 is a signal input terminal (IN pin) for receiving an external input of an external control signal Si from the ECU 2. The external terminal T4 is a signal output terminal (SENSE pin) for externally outputting a state notification signal So to the ECU 2. An external sense resistor 4 is externally attached between the external terminal T4 and a ground terminal.

[0012] In addition, the semiconductor integrated circuit device 1 is configured by integrating an NMOSFET 10, an output current monitoring unit 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormality protection unit 70, an output current detection unit 80, and a signal output unit 90.

[0013] The NMOSFET 10 is a high-voltage (e.g., 42 V) power transistor with its drain connected to the external terminal T1 and its source connected to the external terminal T2. The NMOSFET 10 connected in this manner functions as a switch element (high-side switch) for connecting / cutting a current path from the application terminal of the power supply voltage VBB to the ground terminal via the load 3. The NMOSFET 10 is turned on when the gate drive signal G1 is at a high level, and turned off when the gate drive signal G1 is at a low level.

[0014] The NMOSFET 10 may be designed so that its on-resistance Ron is several tens of milliohms. However, the lower the on-resistance Ron of the NMOSFET 10, the more likely it is that an overcurrent will flow and abnormal heat will be generated when a ground fault (= a short circuit abnormality to the ground terminal or an equivalent low-potential terminal) occurs at the external terminal T2. Therefore, the lower the on-resistance Ron of the NMOSFET 10, the more important the overcurrent protection circuit 71 and the temperature protection circuit 73, which will be described later, become.

[0015] The output current monitoring unit 20 includes NMOSFETs 21 and 22 and a sense resistor 23, and generates a sense voltage Vs (corresponding to a sense signal) according to the output current Io flowing through the NMOSFET .

[0016] Both NMOSFETs 21 and 22 are sense transistors driven in synchronization with the NMOSFET 10, and generate sense currents Is and Is2 according to the output current Io. The size ratio between the NMOSFET 10 and the NMOSFETs 21 and 22 is m:1 (where m>1). Therefore, the sense currents Is and Is2 have a magnitude obtained by reducing the output current Io by 1 / m. Like the NMOSFET 10, the NMOSFETs 21 and 22 are turned on when the gate drive signal G1 is at a high level and turned off when the gate voltage G1 is at a low level.

[0017] The sense resistor 23 (resistance value: Rs) is connected between the source of the NMOSFET 21 and the external terminal T2, and is a current / voltage conversion element that generates a sense voltage Vs (=Is×Rs+Vo, where Vo is the output voltage appearing at the external terminal T2) according to the sense current Is.

[0018] The gate control unit 30 generates a gate drive signal G1 with an increased current capability of the gate control signal S1 and outputs the signal to the gate of the NMOSFET 10 (as well as NMOSFETs 21 and 22), thereby controlling the on / off of the NMOSFET 10. The gate control unit 30 has a function of controlling the NMOSFET 10 so as to limit the output current Io in response to the overcurrent protection signal S71.

[0019] The control logic unit 40 receives the internal power supply voltage Vreg and generates the gate control signal S1. For example, when the external control signal Si is at a high level (=a logic level when turning on the NMOSFET 10), the internal power supply voltage Vreg is supplied from the internal power supply unit 60, so that the control logic unit 40 is in an operating state and the gate control signal S1 is at a high level (=Vreg). On the other hand, when the external control signal Si is at a low level (=a logic level when turning off the NMOSFET 10), the internal power supply voltage Vreg is not supplied from the internal power supply unit 60, so that the control logic unit 40 is in an inoperable state and the gate control signal S1 is at a low level (=GND). In addition, the control logic unit 40 monitors various abnormality protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and undervoltage protection signal S74). The control logic unit 40 also has a function of generating an output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the abnormality protection signals mentioned above.

[0020] The signal input unit 50 is a Schmitt trigger that receives an input of an external control signal Si from the external terminal T3 and transmits it to the control logic unit 40 and the internal power supply unit 60. Note that the external control signal Si goes to a high level when turning on the NMOSFET 10, and goes to a low level when turning off the NMOSFET 10, for example.

[0021] The internal power supply unit 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies it to each unit of the semiconductor integrated circuit device 1. The operation of the internal power supply unit 60 is controlled according to an external control signal Si. More specifically, the internal power supply unit 60 is in an operating state when the external control signal Si is at a high level, and in a non-operating state when the external control signal Si is at a low level.

[0022] The abnormality protection unit 70 is a circuit block that detects various abnormalities in the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and an undervoltage protection circuit 74.

[0023] The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the monitoring result of the sense voltage Vs (=whether or not an overcurrent abnormality occurs in the output current Io). Note that the overcurrent protection signal S71 is at a low level when no abnormality is detected, and at a high level when an abnormality is detected, for example.

[0024] The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (=whether or not an open abnormality has occurred in the load 3). Note that the open protection signal S72 is, for example, at a low level when no abnormality is detected, and at a high level when an abnormality is detected.

[0025] The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation in the semiconductor integrated circuit device 1 (particularly in the vicinity of the NMOSFET 10), and generates a temperature protection signal S73 according to the detection result (=whether or not abnormal heat generation has occurred). Note that the temperature protection signal S73 is at a low level when no abnormality is detected, and at a high level when an abnormality is detected, for example.

[0026] The undervoltage protection circuit 74 generates a undervoltage protection signal S74 according to the monitoring result (=whether or not a undervoltage abnormality occurs) of the power supply voltage VBB or the internal power supply voltage Vreg. Note that the undervoltage protection signal S74 is at a low level when no abnormality is detected, and at a high level when an abnormality is detected, for example.

[0027] The output current detection unit 80 uses a bias means (not shown) to match the source voltage of the NMOSFET 22 with the output voltage Vo, thereby generating a sense current Is2 (=Io / m) according to the output current Io and outputting it to the signal output unit 90.

[0028] The signal output unit 90 selectively outputs one of the sense current Is2 (corresponding to the detection result of the output current Io) and the fixed voltage V90 (corresponding to an abnormality flag, not shown in the figure) to the external terminal T4 based on the output switching signal S2. When the sense current Is2 is selected and output, an output detection voltage V80 (=Is2×R4) obtained by current / voltage conversion of the sense current Is2 by an external sense resistor 4 (resistance value: R4) is transmitted to the ECU 2 as the status notification signal So. The output detection voltage V80 becomes higher as the output current Io increases, and becomes lower as the output current Io decreases. On the other hand, when the fixed voltage V90 is selected and output, the fixed voltage V90 is transmitted to the ECU 2 as the status notification signal So. Note that, when the current value of the output current Io is to be read from the status notification signal So, the status notification signal So may be subjected to A / D [analog-to-digital] conversion. On the other hand, when reading the abnormality flag from the status notification signal So, the logic level of the status notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

[0029] <Gate control section> 2 is a diagram showing an example of the configuration of the gate control unit 30. The gate control unit 30 in this diagram includes a gate driver 31, an oscillator 32, a charge pump 33, a clamper 34, an NMOSFET 35, a resistor 36 (resistance value: R36), a capacitor 37 (capacitance value: C37), and a Zener diode 38.

[0030] The gate driver 31 is connected between the output terminal (= application terminal of the boosted voltage VG) of the charge pump 33 and the external terminal T2 (= application terminal of the output voltage Vo), and generates a gate drive signal G1 that enhances the current capability of the gate control signal S1. Note that the gate drive signal G1 is at a high level (= VG) when the gate control signal S1 is at a high level, and is at a low level (= Vo) when the gate control signal S1 is at a low level.

[0031] The oscillator 32 generates a clock signal CLK of a predetermined frequency and outputs it to the charge pump 33. The operation of the oscillator 32 is controlled in response to an enable signal SA from the control logic unit .

[0032] The charge pump 33 is an example of a boosting section that generates a boosted voltage VG higher than the power supply voltage VBB by driving a flying capacitor using a clock signal CLK and supplies it to the gate driver 31. Note that the operation enable / disable of the charge pump 33 is controlled according to an enable signal SB from the control logic section 40.

[0033] The clamper 34 is connected between the external terminal T1 (= the applied terminal of the power supply voltage VBB) and the gate of the NMOSFET 10. In an application where an inductive load 3 is connected to the external terminal T2, when the NMOSFET 10 is switched from on to off, the output voltage Vo becomes a negative voltage (< GND) due to the back electromotive force of the load 3. Therefore, a clamper 34 (so-called active clamp circuit) is provided for energy absorption.

[0034] The drain of the NMOSFET 35 is connected to the gate of the NMOSFET 10. The source of the NMOSFET 35 is connected to the external terminal T2. The gate of the NMOSFET 35 is connected to the applied terminal of the overcurrent protection signal S71. Also, a resistor 36 and a capacitor 37 are connected in series between the drain and gate of the NMOSFET 35.

[0035] The cathode of the Zener diode 38 is connected to the gate of the NMOSFET 10. The anode of the Zener diode 38 is connected to the source of the NMOSFET 10. The Zener diode 38 connected in this way functions as a clamping element that limits the voltage between the gate and source of the NMOSFET 10 (= VG - Vo) to a predetermined value or less.

[0036] In the gate control unit 30 of this configuration example, when the overcurrent protection signal S71 rises to the high level, the gate drive signal G1 is pulled down from the high level (=VG) in the steady state at a predetermined time constant τ (=R36×C37). As a result, since the conductivity of the NMOSFET 10 gradually decreases, a limit is imposed on the output current Io. On the other hand, when the overcurrent protection signal S71 falls to the low level, the gate drive signal G1 is pulled up at a predetermined time constant τ. As a result, since the conductivity of the NMOSFET 10 gradually increases, the limit on the output current Io is released.

[0037] As described above, the gate control unit 30 of this configuration example has a function of controlling the gate drive signal G1 so as to limit the output current Io according to the overcurrent protection signal S71.

[0038] <Overcurrent Protection Circuit (Comparative Example)> FIG. 3 is a diagram showing a comparative example of an overcurrent protection circuit (an example of a general configuration compared with a novel embodiment to be described later). The overcurrent protection circuit 100 of this comparative example is a circuit block corresponding to the previously described overcurrent protection circuit 71, and includes an overcurrent detection unit 101 and a diagnostic output unit 104.

[0039] The overcurrent detection unit 101 compares the output current Io flowing through the NMOSFET 10 with a predetermined overcurrent detection value Iocp and generates an overcurrent detection signal S101 (corresponding to the previously described overcurrent protection signal S71). The overcurrent detection signal S101 becomes high level, for example, when an overcurrent is detected (Io>Iocp), and becomes low level when no overcurrent is detected (Io<Iocp). Although not explicitly shown in this figure, the overcurrent detection signal S101 is also input to the previously described gate control unit 30, and the gate drive signal G1 is controlled so as to limit the output current Io according to the overcurrent detection signal S101.

[0040] The diagnosis output unit 104 is an open-drain type signal output stage that performs a diagnosis output to the ECU 2 based on the overcurrent detection signal S101, and can be understood as a circuit block that replaces the above-mentioned signal output unit 90, or a circuit block that is provided in addition to the signal output unit 90. The diagnosis output unit 104 includes, for example, an inverter 104a, an NMOSFET 104b, a resistor 104c, and an external terminal 104d.

[0041] The inverter 104a generates a gate signal Gb for the NMOSFET 104b by logically inverting the overcurrent detection signal S101. Therefore, the gate signal Gb is at a low level when the overcurrent detection signal S101 is at a high level, and is at a high level when the overcurrent detection signal S101 is at a low level.

[0042] The source of the NMOSFET 104b is connected to the ground terminal. The drain of the NMOSFET 104b is connected to the external terminal 104d. The gate of the NMOSFET 104b is connected to the output terminal (corresponding to the application terminal of the gate signal Gb) of the inverter INV104a. The NMOSFET 104b connected in this manner is turned off when the gate signal Gb is at a low level, and turned on when the gate signal Gb is at a high level.

[0043] The resistor 104c is a pull-up resistor externally connected between the external terminal 104d and the power supply terminal. Therefore, the diagnostic output signal ST (corresponding to a status flag) appearing at the external terminal 104d is at a high level (=logical level in an abnormal state) when the NMOSFET 104b is off, and at a low level (=logical level in a normal state) when the NMOSFET 104b is on. In this way, the diagnostic output signal ST is a binary signal having the same logical level as the overcurrent detection signal S101.

[0044] The external terminal 104d is a diagnostic output terminal of the overcurrent protection circuit 100 (corresponding to an external output terminal of the diagnostic output signal ST) and is connected to the ECU 2, for example.

[0045] In this way, the semiconductor integrated circuit device 1 has an overcurrent protection circuit 100 built in so as to prevent destruction of the semiconductor integrated circuit device 1 even if the output current Io becomes an overcurrent state due to a ground fault at the external terminal T2, for example.

[0046] In the overcurrent protection circuit 100 of this comparative example, the overcurrent detection signal S101 is substantially directly output as the diagnosis output signal ST for notifying the ECU 2 whether or not the output current Io is in an overcurrent state.

[0047] FIG. 4 is a diagram showing an example of diagnostic output operation in this comparative example, depicting, from top to bottom, an input signal IN (corresponding to the external control signal Si input to the aforementioned IN pin), a diagnostic output signal ST, and an output current Io.

[0048] For example, when the external terminal T2 (= the output terminal for externally connecting the load 3) is grounded via a harness with a large inductance component, and the input signal IN is raised to a high level (= the logic level when on), as shown in the figure, the ringing of the output current Io during overcurrent limiting becomes large. As a result, the output current Io falls into a state where it repeatedly increases and decreases across the overcurrent detection value Iocp, and as shown by the dashed-dotted line frame α in the figure, there is a risk that the diagnostic output signal ST will erroneously switch to a low level (= the logic level when an abnormality occurs). Below, we propose a new embodiment that can solve the above problem.

[0049] <Overcurrent protection circuit (embodiment)> 5 is a diagram showing a new embodiment of an overcurrent protection circuit. The overcurrent protection circuit 100 of this embodiment is based on the above-mentioned comparative example (FIG. 3) and further includes an output start detection unit 102 and a logic unit 103.

[0050] The output start detection unit 102 compares the output voltage Vo appearing at the external terminal T2 (= the source of the NMOSFET 10) with a predetermined threshold voltage Vth to generate an output start detection signal S102. The output start detection signal S102 becomes high level, for example, at the time of output start (Vo > Vth), and becomes low level at the time of non-output start (Vo < Vth).

[0051] In this way, when the external terminal T1 is a power supply terminal and the external terminal T2 is an output terminal, that is, when the foregoing NMOSFET 10 is a high-side switch connected between the power supply terminal and the output terminal, the output start detection unit 102 sets the output start detection signal S102 to high level (= the logic level at the time of output start) when the output voltage Vo appearing at the external terminal T2 (= the output terminal) is higher than the threshold voltage Vth, and sets the output start detection signal S102 to low level (= the logic level at the time of non-output start) when the output voltage Vo is lower than the threshold voltage Vth.

[0052] In this case, the output start detection unit 102 can be understood as a ground fault detection unit for detecting whether the external terminal T2 (= the output terminal) is grounded. If the external terminal T2 is not grounded, Vo > Vth, so the output start detection signal S102 becomes high level. On the other hand, if the external terminal T2 is grounded, Vo < Vth, so the output start detection signal S102 becomes low level.

[0053] Also, although not shown again, the overcurrent protection circuit 100 of the present embodiment can be applied not only to the high-side switch IC but also to the low-side switch IC. For example, assuming that the external terminal T1 is an output terminal and the external terminal T2 is a ground terminal, that is, assuming that the foregoing NMOSFET 10 is a low-side switch connected between the output terminal and the ground terminal, the output start detection unit 102 sets the output start detection signal S102 to high level (= the logic level at the time of output start) when the output voltage Vo appearing at the external terminal T1 (= the output terminal) is lower than the threshold voltage Vth, and sets the output start detection signal S102 to low level (= the logic level at the time of non-output start) when the output voltage Vo is higher than the threshold voltage Vth.

[0054] In this case, the output start detection unit 102 can be understood as a short-circuit detection unit for detecting whether the external terminal T1 (= output terminal) is short-circuited. Short-circuit refers to a short-circuit abnormality to a power supply terminal or a high-potential terminal equivalent thereto. If the external terminal T1 is not short-circuited, Vo < Vth, so the output start detection signal S102 becomes high level. On the other hand, if the external terminal T1 is short-circuited, Vo > Vth, so the output start detection signal S102 becomes low level.

[0055] The logic unit 103 combines the overcurrent detection signal S101 and the output start detection signal S102 to generate a logic operation signal S103. For example, when the overcurrent detection signal S101 becomes high level (= logic level at the time of overcurrent detection), the logic operation signal S103 is set to high level (= logic level at the time of abnormality), and thereafter, as long as the output start detection signal S102 does not become high level (= logic level at the time of output start) even if the overcurrent detection signal S101 becomes low level (= logic level at the time of no overcurrent detection), the logic operation signal S103 is held at high level (= logic level at the time of abnormality).

[0056] In addition, the logic unit 103 further receives an input signal IN for turning on / off the NMOSFET 10. When the input signal IN is at low level (= logic level at the time of off), the logic operation signal S103 is set to low level (= logic level at the time of normal) regardless of the overcurrent detection signal S101 and the output start detection signal S102.

[0057] The above-described logic operation of the logic unit 103 will be described in detail later.

[0058] The diagnostic output unit 104 receives an input of the logic operation signal S103 from the logic unit 103 instead of the overcurrent detection signal S101, and performs a diagnostic output to the ECU 2 based on the logic operation signal S103. The circuit configuration of the diagnostic output unit 104 is the same as that of the previous comparative example (FIG. 3), and the diagnostic output signal ST is basically a binary signal having the same logic level as the logic operation signal S103.

[0059] 6 is a diagram showing an example of the configuration of the logic unit 103. As shown in this diagram, the logic unit 103 of this example includes an inverter INV1, AND gates AND1 and AND2, and an OR gate OR1.

[0060] The inverter INV1 generates an internal signal Sx by logically inverting the output start detection signal S102. The internal signal Sx goes to a low level when the output start detection signal S102 is at a high level, and goes to a high level when the output start detection signal S102 is at a low level.

[0061] The logical AND gate AND1 generates an internal signal Sy by logical ANDing the internal signal Sx and the logical operation signal S103. The internal signal Sy is at low level when at least one of the internal signal Sx and the logical operation signal S103 is at low level, and is at high level when both the internal signal Sx and the logical operation signal S103 are at high level.

[0062] The OR gate OR1 generates an internal signal Sz by performing an OR operation on the overcurrent detection signal S102 and the internal signal Sy. The internal signal Sz is at a high level when at least one of the overcurrent detection signal S102 and the internal signal Sy is at a high level, and is at a low level when both the overcurrent detection signal S102 and the internal signal Sy are at a low level.

[0063] The logical AND gate AND2 generates a logical operation signal S103 by logical ANDing the input signal IN and the internal signal Sz. The logical operation signal S103 is at low level when at least one of the input signal IN and the internal signal Sz is at low level, and is at high level when both the input signal IN and the internal signal Sz are at high level.

[0064] FIG. 7 is a diagram (truth table) showing the arithmetic operation of logic unit 103, depicting, from the left column to the right column, the logic levels of input signal IN, overcurrent detection signal S101, output start detection signal S102, and logical operation signal S103.

[0065] As shown in the first row, when the input signal IN is at a low level, the logical operation signal S103 is set to a low level regardless of the overcurrent detection signal S101 and the output start detection signal S102.

[0066] As shown in the second row, when the input signal IN is at a high level and the overcurrent detection signal S101 and the output start detection signal S102 are both at a low level, the logical operation signal S103 is held at the previous logical level.

[0067] As shown in the third row, when the input signal IN is at a high level, the overcurrent detection signal S101 is at a low level, and the output start detection signal S102 is at a high level, the logical operation signal S103 is at a low level.

[0068] As shown in the fourth line, when the input signal IN and the overcurrent detection signal S101 are both at a high level, the logical operation signal S103 is set to a high level regardless of the output start detection signal S102.

[0069] FIG. 8 is a diagram (timing chart) showing the calculation operation of the logic unit 103, depicting, from top to bottom, an input signal IN, an overcurrent detection signal S101, an output start detection signal S102, a logical calculation signal S103, and a diagnostic output signal ST (embodiment / comparison example).

[0070] For example, when the external terminal T2 (=output terminal) is grounded, as shown by the dashed-dotted frame β in the figure, even if the input signal IN rises to a high level, the output voltage Vo does not exceed the threshold voltage Vth, so the output start detection signal S102 remains at a low level. When the output current Io becomes excessive in this state and the overcurrent detection signal S101 rises to a high level, the logical operation signal S103 switches to a high level, and the diagnosis output signal ST also switches to a high level (corresponding to the fourth row in FIG. 7).

[0071] Then, consider a case where the overcurrent detection signal S101 erroneously switches to a low level (= a logic level when an overcurrent is not detected) due to ringing of the output current Io during overcurrent limiting. In this case, in the above-mentioned comparative example, the diagnosis output signal ST also falls to a low level in synchronization with the overcurrent detection signal S101, as shown in the bottom row of the figure.

[0072] On the other hand, in this embodiment, once the logical operation signal S103 rises to a high level, even if the overcurrent detection signal S101 subsequently becomes a low level, the logical operation signal S103 is maintained at a high level as long as the output activation detection signal S102 is at a low level (=a logical level when the output has not yet been activated, i.e., a logical level when a ground fault is detected) (corresponding to the second line in FIG. 7). Therefore, it is possible to prevent an erroneous response of the diagnosis output signal ST.

[0073] Fig. 9 is a diagram showing an example of the diagnostic output operation in this embodiment, and similarly to Fig. 4, from the top, an input signal IN (corresponding to the external control signal Si input to the IN pin), a diagnostic output signal ST, and an output current Io are depicted. Note that the dashed line of the diagnostic output signal ST shows the behavior in the comparative example (Fig. 4) for comparison.

[0074] As is clear from a comparison of the solid line (present embodiment) and the dashed line (comparison example) of the diagnostic output signal ST, by adopting this embodiment, even if the output current Io falls into a state in which it repeatedly increases and decreases across the overcurrent detection value Iocp due to ringing of the output current Io during overcurrent limiting, it is possible to prevent erroneous reactions by maintaining the diagnostic output signal ST at a high level (= the logical level during abnormality), as shown by the dashed-dotted frame α in the figure.

[0075] <Application to vehicles> 10 is an external view showing one configuration example of a vehicle. The vehicle X of this configuration example is equipped with a battery (not shown in this figure) and various electronic devices X11 to X18 that operate by receiving power supply from the battery.

[0076] Vehicle X includes not only engine vehicles but also electric vehicles (xEVs such as BEVs (battery electric vehicles), HEVs (hybrid electric vehicles), PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0077] It should be noted that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for the sake of convenience.

[0078] The electronic device X11 is an electronic control unit that performs engine-related control (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related control (such as torque control and power regeneration control).

[0079] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamps) and DRL (daytime running lamps).

[0080] The electronic device X13 is a transmission control unit that performs control related to the transmission.

[0081] The electronic device X14 is a body control unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0082] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0083] The electronic device X16 is an electronic device that is installed in the vehicle X at the factory as a standard equipment or a manufacturer's option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0084] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0085] The electronic device X18 is an electronic device equipped with a high-voltage resistant motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0086] The semiconductor integrated circuit device 1, the ECU 2, and the load 3 described above can be incorporated into any of the electronic devices X11 to X18.

[0087] <Summary> The various embodiments described above will be generally described below.

[0088] For example, the overcurrent protection circuit disclosed in this specification may have an overcurrent detection unit configured to generate an overcurrent detection signal by comparing an output current flowing through a switch element with a predetermined overcurrent detection value, an output start-up detection unit configured to generate an output start-up detection signal by comparing an output voltage appearing at one end of the switch element with a predetermined threshold voltage, a logic unit configured to generate a logical operation signal by combining the overcurrent detection signal and the output start-up detection signal, and a diagnostic output unit configured to perform a diagnostic output based on the logical operation signal, and the logic unit may be configured to set the logical operation signal to an abnormality logical level when the overcurrent detection signal becomes a logical level when an overcurrent is detected, and thereafter maintain the logical operation signal at the abnormality logical level even if the overcurrent detection signal becomes a logical level when an overcurrent is not detected as long as the output start-up detection signal does not become a logical level when an output is started (a first configuration).

[0089] In the overcurrent protection circuit of the first configuration described above, the logic unit may further receive an input signal for turning the switch element on / off, and when the input signal is at an off logic level, the logical operation signal may be at a normal logic level regardless of the overcurrent detection signal and the output start detection signal (second configuration).

[0090] Furthermore, in the overcurrent protection circuit of the second configuration described above, the overcurrent detection signal may be at a high level when an overcurrent is detected and at a low level when an overcurrent is not detected, the output start detection signal may be at a high level when the output is started and at a low level when the output is not started, and the input signal may be at a high level when on and at a low level when off (third configuration).

[0091] Furthermore, in the overcurrent protection circuit of the third configuration described above, the logic unit may be configured (fourth configuration) to include an inverter configured to generate a first internal signal by logically inverting the output start detection signal, a first logical AND gate configured to generate a second internal signal by logically ANDing the first internal signal and the logical operation signal, a logical OR gate configured to generate a third internal signal by logically ORing the overcurrent detection signal and the second internal signal, and a second logical AND gate configured to generate the logical operation signal by logically ANDing the input signal and the third internal signal.

[0092] In the overcurrent protection circuit of any one of the above first to fourth configurations, the diagnostic output section may be configured as an open-drain type (fifth configuration).

[0093] Also, for example, the switch device disclosed in this specification may be configured (sixth configuration) to have a switch element and an overcurrent protection circuit of any of the first to fifth configurations that monitors the output current flowing through the switch element.

[0094] Furthermore, in the switch device of the sixth configuration, the switch element may be connected between a power supply terminal and an output terminal, and the output start-up detection unit may be configured (seventh configuration) to set the output start-up detection signal to a logic level at the time of output start-up when the output voltage appearing at the output terminal is higher than the threshold voltage.

[0095] Furthermore, in the switch device of the sixth configuration, the switch element may be connected between an output terminal and a ground terminal, and the output start-up detection unit may be configured (eighth configuration) to set the output start-up detection signal to a logic level at the time of output start-up when the output voltage appearing at the output terminal is lower than the threshold voltage.

[0096] Furthermore, for example, the electronic device disclosed in this specification may have a configuration (ninth configuration) including a switch device having any one of the sixth to eighth configurations and a load connected to the switch device.

[0097] Also, for example, the vehicle disclosed in this specification may be configured (tenth configuration) to include the electronic device of the ninth configuration described above.

[0098] <Other Modifications> In the above embodiment, an in-vehicle high-side switch LSI and a low-side switch LSI are exemplified, however, the application of the overcurrent protection circuit disclosed in this specification is in no way limited thereto, and the circuit can be widely applied to, for example, other in-vehicle IPDs (such as in-vehicle power supply LSIs) as well as semiconductor integrated circuit devices for non-in-vehicle use (for example, general-purpose power supply control circuits).

[0099] In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiment. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention is indicated by the claims, not the description of the above-mentioned embodiment, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0100] 1. Semiconductor integrated circuit device (switch device) 2 ECU 3. Load 4 External Sense Resistor 10 NMOSFET (switching element) 20 Output current monitor 21, 22 NMOSFET 23 Sense resistor 30 Gate control section 31 Gate Driver 32 Oscillators 33 Charge pump (boost section) 34 Clamper 35 NMOSFET 36 Resistance 37 Capacitor 38 Zener diode (clamp element) 40 Control logic section 50 Signal input section 60 Internal power supply section 70 Abnormal protection section 71 Overcurrent protection circuit 72 Open circuit protection circuit 73 Temperature protection circuit 74 Undervoltage protection circuit 80 Output current detection section 90 Signal output section 100 Overcurrent protection circuit 101 Overcurrent detection section 102 Output start detection unit 103 Logic Section 104 Diagnostic output unit 104a Inverter 104b NMOSFET 104c resistance 104d External terminal AND1, AND2 logical AND gates INV1 Inverter OR1 Logical OR Gate T1~T4 External terminals X Vehicle X11~X18 Electronic equipment

Claims

1. an overcurrent detection unit configured to compare an output current flowing through the switch element with a predetermined overcurrent detection value to generate an overcurrent detection signal; an output start-up detection unit configured to generate an output start-up detection signal by comparing an output voltage appearing at one end of the switch element with a predetermined threshold voltage; a logic unit configured to combine the overcurrent detection signal and the output activation detection signal to generate a logical operation signal; a diagnostic output unit configured to perform a diagnostic output based on the logical operation signal; having The logic unit sets the logical operation signal to an abnormal logical level when the overcurrent detection signal becomes the logical level when an overcurrent is detected, and thereafter maintains the logical operation signal at the abnormal logical level unless the output start detection signal becomes the logical level when an output start is detected, even if the overcurrent detection signal becomes the logical level when an overcurrent is not detected.

2. 2. The overcurrent protection circuit according to claim 1, wherein the logic unit further receives an input signal for turning the switch element on and off, and when the input signal is at an off logic level, the logic operation signal is set to a normal logic level regardless of the overcurrent detection signal and the output start detection signal.

3. 3. The overcurrent protection circuit of claim 2, wherein the overcurrent detection signal is at a high level when an overcurrent is detected and at a low level when an overcurrent is not detected, the output start detection signal is at a high level when an output is started and at a low level when an output is not started, and the input signal is at a high level when on and at a low level when off.

4. The logic unit includes: an inverter configured to generate a first internal signal by logically inverting the output activation detection signal; a first AND gate configured to generate a second internal signal by ANDing the first internal signal and the logic operation signal; an OR gate configured to generate a third internal signal by performing an OR operation on the overcurrent detection signal and the second internal signal; a second AND gate configured to generate the logical operation signal by ANDing the input signal and the third internal signal; 4. The overcurrent protection circuit of claim 3, comprising:

5. 5. The overcurrent protection circuit according to claim 1, wherein the diagnostic output section is of an open drain type.

6. A switch element; an overcurrent protection circuit according to any one of claims 1 to 5, which monitors an output current flowing through the switch element; A switch device having the following features:

7. 7. The switch device according to claim 6, wherein the switch element is connected between a power supply terminal and an output terminal, and the output start-up detection unit sets the output start-up detection signal to a logic level at the time of output start-up when the output voltage appearing at the output terminal is higher than the threshold voltage.

8. 7. The switch device according to claim 6, wherein the switch element is connected between an output terminal and a ground terminal, and the output start-up detection unit sets the output start-up detection signal to a logic level at the time of output start-up when the output voltage appearing at the output terminal is lower than the threshold voltage.

9. A switch device according to any one of claims 6 to 8, A load connected to the switch device; An electronic device having

10. A vehicle comprising the electronic device according to claim 9.

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