Josephson double-balanced mixer

Abstract

Techniques are provided for facilitating quantum gates between qubits using tunable couplers. In one example, the quantum coupler device can include a Josephson ring modulator (JRM) operably coupled to first and second qubits via respective first and second capacitive devices in a balanced bridge topology. The JRM provides tunable coupling between the first and second qubits.

Description

[Technical field]

[0001] The present disclosure relates to quantum coupler devices, and more particularly, to quantum coupler devices that facilitate quantum gates between quantum bits (qubits). Summary of the Invention

[0002] The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements, nor is it intended to delineate the scope of particular embodiments or claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, device, computer-implemented method, and / or computer program product that uses tunable couplers to facilitate quantum gates between qubits is described.

[0003] According to an embodiment, a quantum coupler device can include a Josephson ring modulator (JRM) operably coupled to first and second quantum bits via respective first and second capacitive devices in a balanced bridge topology, the JRM providing a tunable coupling between the first and second quantum bits.

[0004] In an embodiment, the quantum coupler device may further comprise a bias component that applies a bias to the JRM to facilitate control of the coupling between the first and second quantum bits. In an embodiment, the first and second quantum bits remain separated until a bias is applied to the JRM. In an embodiment, the bias component applies a radio frequency (RF) charge bias signal to the JRM to drive the parametric conversion between the first and second quantum bits. In an embodiment, the bias component applies an RF flux bias signal to the JRM to drive the parametric conversion between the first and second quantum bits. In an embodiment, the RF charge bias signal and / or the RF flux bias signal include a difference frequency defined by the respective frequencies of the first and second quantum bits.

[0005] In an embodiment, the first and second qubits are degenerate qubits. In this embodiment, application of a DC flux bias signal to the JRM drives an excitation exchange between the first and second qubits. In an embodiment, the first and second qubits are non-degenerate qubits. In this embodiment, application of a DC flux bias signal to the JRM drives a ZZ interaction between the first and second qubits. In an embodiment, the quantum coupler device may further comprise a flux bias line constructed on the interposer that forms a loop under the JRM. In an embodiment, the flux bias line comprises an input flux bias line and a return path routed along the input flux bias line. In an embodiment, a first capacitive device is formed inside the paddle of the first qubit.

[0006] According to another embodiment, the computer-implemented method can include operably coupling a JRM to first and second qubits via respective first and second capacitive devices in a balanced bridge topology. The computer-implemented method can further include tunably coupling the first and second qubits using the JRM.

[0007] In an embodiment, the computer-implemented method may further include applying a bias to the JRM to facilitate control of the coupling between the first and second quantum bits. In an embodiment, the first and second quantum bits remain isolated until a bias is applied to the JRM. In an embodiment, the computer-implemented method may further include controlling a polarity of the coupling between the first and second quantum bits by adjusting a polarity of the bias applied to the JRM.

[0008] In an embodiment, the computer-implemented method may further include applying an RF charge bias signal to the JRM to drive a parametric conversion between the first and second qubits. In an embodiment, the computer-implemented method may further include applying an RF flux bias signal to the JRM to drive a parametric conversion between the first and second qubits. In an embodiment, the first and second qubits are degenerate qubits. In this embodiment, the computer-implemented method may further include applying a DC flux bias signal to the JRM to drive an excitation exchange between the first and second qubits. In an embodiment, the first and second qubits are non-degenerate qubits. In this embodiment, the computer-implemented method may further include applying a DC flux bias signal to the JRM to drive a ZZ interaction between the first and second qubits.

[0009] According to another embodiment, a quantum coupling system can include a Josephson Ring Modulator (JRM), a first qubit, and a second qubit. The first qubit is coupled to the JRM via a first inductive component. The second qubit is coupled to the JRM via a second inductive component. The first and second qubits are coupled to the JRM via respective first and second inductive devices in a balanced bridge topology. The JRM can provide a tunable coupling between the first and second qubits. In an embodiment, the system further includes a bias component that applies a bias to the JRM to control the coupling between the first and second qubits. In an embodiment, the first and second qubits remain isolated until a bias is applied to the JRM. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 illustrates a circuit diagram of an example, non-limiting device that can facilitate quantum gates between qubits using Josephson Ring Modulators (JRMs) in accordance with one or more embodiments described herein. [Diagram 2] FIG. 1 illustrates a circuit diagram of an example, non-limiting device that can facilitate quantum gates between qubits using Josephson Ring Modulators (JRMs) in accordance with one or more embodiments described herein. [Diagram 3] FIG. 1 illustrates a circuit diagram of an example, non-limiting device that can facilitate quantum gates between qubits using Josephson Ring Modulators (JRMs) in accordance with one or more embodiments described herein. [Figure 4] FIG. 1 illustrates a circuit diagram of an example, non-limiting device that can facilitate quantum gates between qubits using Josephson Ring Modulators (JRMs) in accordance with one or more embodiments described herein. [Diagram 5]1A-1D are diagrams illustrating example, non-limiting modes of a JRM and a qubit, in accordance with one or more embodiments described herein. [Figure 6] FIG. 2 illustrates a schematic diagram of an exemplary reduced non-limiting combination circuit for use in a simulation in accordance with one or more embodiments described herein. [Figure 7] FIG. 7 is a graph depicting WRSpice simulation results of the circuit of FIG. 6. [Figure 8] FIG. 2 illustrates an example, non-limiting graph plotting energy levels of a device versus flux bias (in units of flux quanta) in accordance with one or more embodiments described herein. [Figure 9] FIG. 13 illustrates an example non-limiting colorized graph illustrating ZZ coupling versus flux bias and frequency of a second qubit in accordance with one or more embodiments described herein. [Figure 10] FIG. 1 illustrates an example non-limiting graph plotting ZZ coupling versus flux bias (in units of magnetic flux quanta) in accordance with one or more embodiments described herein. [Figure 11] FIG. 1 illustrates an example non-limiting graph plotting −ZZ coupling versus flux bias (in units of flux quanta) in accordance with one or more embodiments described herein. [Figure 12] FIG. 1 illustrates an example, non-limiting graph depicting applied flux bias versus time for executing a two-qubit phase gate in accordance with one or more embodiments described herein. [Figure 13] FIG. 13 illustrates an example, non-limiting graph depicting the relative phase difference between the |01> and |11> quantum states versus time for the applied magnetic flux profile of FIG. 12 in accordance with one or more embodiments described herein. [Figure 14] FIG. 1 illustrates an example non-limiting graph plotting eigenstate occupancy |Cn|^2 versus number of eigenstates n, in accordance with one or more embodiments described herein. [Figure 15]FIG. 1 shows an example, non-limiting graph depicting expected values ​​of excitation of a first and second quantum bit versus time when the first and second quantum bits are coupled via a ring modulator in accordance with one or more embodiments described herein. [Figure 16] FIG. 13 illustrates an example, non-limiting graph depicting expected values ​​of excitations of a first and second quantum bit versus time as the first and second quantum bits are coupled via a JRM during an exchange operation in accordance with one or more embodiments described herein. [Figure 17] FIG. 1 illustrates a top view of an example non-limiting device that can reduce wiring complexity associated with crossover features in a multidimensional array of qubits in accordance with one or more embodiments described herein. [Figure 18] FIG. 1 illustrates a top view of an example, non-limiting device including a multidimensional qubit array in accordance with one or more embodiments described herein. [Figure 19] FIG. 1 illustrates a top view of an exemplary non-limiting device that can facilitate improved bonding in accordance with one or more embodiments described herein. [Figure 20] FIG. 2 illustrates an example, non-limiting graph depicting the relative phase difference between |01> and |11> quantum states versus time, in accordance with one or more embodiments described herein. [Figure 21] FIG. 2 illustrates an example, non-limiting graph depicting occupancy rates for eigenstates, in accordance with one or more embodiments described herein. [Figure 22] FIG. 13 illustrates an example, non-limiting graph depicting expected values ​​of excitation versus time, in accordance with one or more embodiments described herein. [Figure 23] FIG. 13 illustrates an example, non-limiting graph depicting applied flux bias versus time for executing a two-qubit gate via a JRM in accordance with one or more embodiments described herein. [Figure 24]FIG. 2 illustrates a top view of an example non-limiting device that can facilitate magnetic flux coupling in accordance with one or more embodiments described herein. [Diagram 25] FIG. 2 illustrates a top view of an example non-limiting device that can facilitate magnetic flux coupling in accordance with one or more embodiments described herein. [Figure 26] FIG. 1 illustrates a flow diagram of an example, non-limiting, computer-implemented method in which a JRM can be used to facilitate quantum gates between qubits in accordance with one or more embodiments described herein. [Figure 27] FIG. 1 illustrates a flow diagram of an example, non-limiting, computer-implemented method in which a JRM can be used to facilitate quantum gates between qubits in accordance with one or more embodiments described herein. [Figure 28] FIG. 1 illustrates a block diagram of an exemplary non-limiting operating environment that can facilitate one or more embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The following detailed description is merely exemplary and is not intended to limit the embodiments or the application and / or uses of the embodiments, nor is it intended to be bound by any express or implied information presented in the preceding "Technical Field" or "Summary" sections or in the "Description of the Preferred Embodiments" section.

[0012] One or more embodiments are now described with reference to the drawings, in which like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it will be apparent that in various instances, one or more embodiments may be practiced without these specific details.

[0013] Classical computers operate on binary numbers (or bits), which store or represent information as binary states, to perform computations and information processing functions. In contrast, quantum computing devices operate on quantum bits (or qubits), which store or represent information as both binary states and superpositions of binary states. As such, quantum computing devices exploit quantum mechanical phenomena such as entanglement and interference.

[0014] Quantum computing uses quantum bits as its basic units instead of classical computational bits. A quantum bit (e.g., a quantum binary digit) is the quantum mechanical analogue of a classical bit. While a classical bit can only use one of two basis states (e.g., 0 or 1), a quantum bit can use any superposition of these basis states (e.g., α|0>+β|1>, where α and β are |α| 2 +|β| 2A quantum computer (e.g., a computer that employs qubits rather than just classical bits) can theoretically use a quantum number of qubits, which can hold exponentially more information than the same number of classical bits. Thus, a quantum computer (e.g., a computer that employs qubits rather than just classical bits) can theoretically quickly solve problems that can be extremely difficult for classical computers. A classical computer's bits are simply binary digits that have a value of either 0 or 1. Almost any device that has two distinct states, such as a switch, a valve, a magnet, or a coin, can serve to represent a classical bit. Qubits, which share the quantum mystique, can occupy a superposition of the 0 and 1 states. This does not mean that a qubit can have an intermediate value, such as 0.63, but that if the state of a qubit is measured, the result will be either 0 or 1. However, in the course of a computation, a qubit can function as if it were a mixture of states, such as 63 percent 0 and 37 percent 1. A typical quantum program requires coordination of the quantum and classical parts of the computation. One way to think about a general quantum program is to identify the processes and abstractions involved in specifying a quantum algorithm, translating that algorithm into an executable form, running an experiment or simulation, and analyzing the results. A concept that runs through these processes is the use of intermediate representations. An intermediate representation (IR) of a computation is neither a source language description nor a target machine instruction, but something in between. A compiler may use multiple IRs during the process of translating and optimizing a program. The input is source code that describes the quantum algorithm and compile-time parameters. The output is a combined quantum / classical program, represented using high-level IR. The difference between quantum and classical computers is that quantum computers are probabilistic, and therefore measurements of the output of an algorithm provide a good solution within a confidence interval specific to the algorithm. The computation is then repeated until a satisfactory degree of certainty of a likely solution can be reached.

[0015] By processing information using the laws of quantum mechanics, quantum computers offer new ways to perform computational tasks such as molecular calculations, financial risk calculations, and optimization.

[0016] A key element of any nontrivial quantum computing device is the two-qubit gate, which facilitates the exchange of information between adjacent qubits. Current techniques for coupling two qubits employ a number of different methods, each with their own advantages and disadvantages in terms of the gate's speed, fidelity, and ease of operation.

[0017] For example, viable cross-resonant gates typically involve adjacent qubits that are relatively close in frequency (e.g., within anharmonicity) but do not actually overlap. This enforces stringent requirements on the frequency of the coupled qubit pair. As another example, techniques that employ static coupling between adjacent qubits (e.g., using capacitors) typically must deal with qubit-to-qubit interactions, which are always on even when the associated controller is not actively running a two-qubit gate. Cross-resonant gate architectures can reduce residual crosstalk between adjacent qubits using intermediate qubits. The intermediate qubit can reduce the residual crosstalk to a relatively low level, but the reduced residual crosstalk does not become zero. In some instances, the residual crosstalk can result in unintentional coherent rotations or coherent qubit errors that adversely affect the fidelity of the gate.

[0018] 1 illustrates a circuit diagram of an exemplary, non-limiting device 100 that can facilitate a quantum gate between qubits using a Josephson Ring Modulator (JRM) in accordance with one or more embodiments described herein. As illustrated by the example embodiment shown in FIG. 1, device 100 includes a JRM 110, a first qubit 120, a second qubit 130, a first capacitive device 140, and a second capacitive device 150. JRM 110 includes four Josephson Junctions (JJs) 112, 114, 116, and 118 arranged in a ring configuration. In an embodiment, the ring configuration is a Wheatstone bridge configuration.

[0019] Those skilled in the art will recognize that the JRM 110 includes three orthogonal electrical modes. With reference to FIGS. 5(A)-5(C), the three orthogonal electrical modes of the JRM 110 are represented by Φ X The X mode represented by Φ in Fig. 5(B) Y The Y mode represented by, and Φ in Fig. 5(C) Z In an embodiment, the Hamiltonian of the JRM 110 may be approximated using the Hamiltonian defined by Equation 1.

[0020]

number

[0021] According to Equation 1 above, E C denotes the electrostatic charge energy of each Josephson junction,

number

number

number

[0022] First qubit 120 comprises a JJ 122 coupled in parallel with capacitive device 124. First qubit 120 further comprises a capacitive device 128 coupling JJ 122 to ground. Second qubit 130 comprises a JJ 132 coupled in parallel with capacitive device 134. Second qubit 130 further comprises a capacitive device 138 coupling JJ 132 to ground. Capacitive devices 126 and 136 couple first qubit 120 and second qubit 130, respectively, to an external circuit. Examples of qubits suitable for implementing first qubit 120 and / or second qubit 130 include, but are not limited to, fixed frequency qubits, tunable qubits, transmon qubits, fixed frequency transmon qubits, tunable transmon qubits, etc. Referring to FIG. 5(D), first qubit 120 and second qubit 130 each include electrical modes represented by Φ1 and Φ2, respectively.

[0023] First capacitive device 140 includes capacitive device 142, which couples node 121 of first qubit 120 to node 111 of JRM 110, and capacitive device 148, which couples node 123 of first qubit 120 to node 115 of JRM 110. First capacitive device 140 further includes capacitive device 144 and capacitive device 146 coupled in parallel to JRM 110 via nodes 111 and 115. Second capacitive device 150 includes capacitive device 152, which couples node 131 of second qubit 130 to node 113 of JRM 110, and capacitive device 158, which couples node 133 of second qubit 130 to node 117 of JRM 110. The second capacitive device 150 further includes a capacitive device 154 and a capacitive device 156 coupled in parallel to the JRM 110 via nodes 113 and 117 .

[0024] 2 illustrates a circuit diagram of another exemplary, non-limiting device 200 that can use a JRM to facilitate a quantum gate between qubits in accordance with one or more embodiments described herein. Similar to device 100 of FIG. 1, device 200 also includes a JRM 110, a first qubit 120, and a second qubit 130. As shown in FIG. 2, device 200 further includes a first reacting device 240 and a second reacting device 250.

[0025] The first responsive device 240 includes an inductive device 242 coupled in parallel to the JRM 110 via nodes 111 and 115. The first responsive device 240 further includes a capacitive device 244 interposed between the node 121 of the first qubit 120 and the inductive device 242. The second responsive device 250 includes an inductive device 252 coupled in parallel to the JRM 110 via nodes 113 and 117. The second responsive device 250 further includes a capacitive device 254 interposed between the node 131 of the second qubit 130 and the inductive device 252. In an embodiment, the inductive device 242 and / or the inductive device 252 may be implemented using a three winding transformer having a 1:1:1 turns ratio.

[0026] Various embodiments described herein relate to quantum coupling devices that facilitate two-qubit gates with zero quiescent coupling in the off-state and high coupling (e.g., above 1 gigahertz (GHz)) in the on-state. To that end, adjacent qubits (e.g., first qubit 120 and second qubit 130) are connected via a JRM (e.g., JRM 110) in a balanced bridge topology. This balanced bridge topology can weakly couple the modes of the JRM (e.g., X-mode, Y-mode, or Z-mode, or combinations thereof, of JRM 110, shown in Figures 5(A)-5(C), respectively) to the modes of the adjacent qubits (e.g., modes of first qubit 120 and second qubit 130, shown in Figure 5(D)) via capacitance or mutual inductance.

[0027] For example, device 100 of Figure 1 illustrates an embodiment in which adjacent qubits are capacitively coupled to a JRM to form a balanced bridge topology. In this example, JRM 110 is operably coupled to first qubit 120 and second qubit 130 in the balanced bridge topology via first capacitive device 140 and second capacitive device 150, respectively. As another example, device 200 of Figure 2 illustrates an embodiment in which adjacent qubits are mutually coupled to a JRM to form a balanced bridge topology. In this example, JRM 110 is operably coupled to first qubit 120 and second qubit 130 in the balanced bridge topology via first reactive device 240 and second reactive device 250, respectively.

[0028] By connecting the first qubit 120 and the second qubit 130 via the JRM 110 in a balanced bridge topology, the first qubit 120 and the second qubit 130 remain isolated until a bias is applied to the JRM 110. In other words, the devices 100 and / or 200 facilitate a two-qubit gate that has zero stationary coupling when no bias (e.g., charge, flux, or current, or a combination thereof) is applied to the JRM 110. Notably, the zero stationary coupling provided by embodiments of the present disclosure is agnostic to detuning between the coupled qubits.

[0029] One aspect of the present disclosure that facilitates such zero quiescent coupling is that the critical currents of each of the four JJs 112, 114, 116, and 118 that form the JRM 110 are nominally equivalent. Furthermore, by having nominally equivalent critical currents, the Josephson inductances of each of the four JJs 112, 114, 116, and 118 are also nominally equivalent. As an example, oscillation of the first qubit 120 of FIG. 1 can induce equal voltages with opposite polarity on nodes 111 and 115 of the JRM 110. Due to the symmetry of the four JJs 112, 114, 116, and 118 that form the JRM 110, no voltages are induced on nodes 113 and 117 of the JRM 110. In this case, nodes 113 and 117 of the JRM 110 become virtual grounds. As a result of nodes 113 and 117 being virtual ground, no signal is coupled from first qubit 120 to second qubit 130 .

[0030] By unbalancing the balanced bridge topology while the first qubit 120 and the second qubit 130 remain isolated until a bias is applied to the JRM 110, the tunable coupling of the first qubit 120 and the second qubit 130 is facilitated. As such, embodiments of the present disclosure utilize bias components that apply a bias to the JRM to facilitate control of the coupling between the first qubit 120 and the second qubit 130. Figures 3-4 illustrate example bias components that may be implemented in accordance with embodiments of the present disclosure to facilitate tunable coupling of adjacent qubits.

[0031] FIG. 3 illustrates a circuit diagram of another exemplary, non-limiting device 300 that can use a JRM to facilitate a quantum gate between qubits in accordance with one or more embodiments described herein. As illustrated in FIG. 3, the device 300 includes a bias component 310 for applying a bias signal to the device 100. In FIG. 3, the bias component 310 includes a current source 320 and a flux bias line 330 that forms a loop within the JRM 110 of the device 100. The current source 320 can generate a flux bias signal for application to the JRM 110 via the flux bias line 330. In an embodiment, the current source 320 can generate a flux bias signal having an adjustable amplitude. Application of the flux bias signal to the JRM 110 via the flux bias line 330 drives current equally through the four JJs 112, 114, 116, and 118 that form the JRM 110.

[0032] In an embodiment, bias component 310 applies a direct current (DC) flux bias signal to JRM 110. In this embodiment, application of the DC flux bias signal to JRM 110 modulates the critical currents of each of the four JJs 112, 114, 116, and 118 that form JRM 110. By modulating the critical currents, the inductances of each of the four JJs 112, 114, 116, and 118 that form JRM 110 are also modulated. Such modulation breaks the symmetry of JRM 110 by breaking the matching of inductances between the nodes (e.g., nodes 111, 113, 115, and 117) of JRM 110. Breaking the symmetry of JRM 110 unbalances the balanced bridge topology and facilitates providing tunable coupling between first qubit 120 and second qubit 130.

[0033] In embodiments in which the first qubit 120 and the second qubit 130 are degenerate qubits, application of a DC flux bias signal to the JRM 110 drives an excitation exchange between the first qubit 120 and the second qubit 130. For example, application of a DC flux bias signal to the JRM 110 can drive an XX-like exchange interaction between the first qubit 120 and the second qubit 130. In embodiments in which the first qubit 120 and the second qubit 130 are non-degenerate qubits, application of a DC flux bias signal to the JRM 110 drives a ZZ interaction between the first qubit 120 and the second qubit 130.

[0034] In an embodiment, bias component 310 applies a radio frequency (RF) flux bias signal to JRM 110. In an embodiment, the RF flux bias signal includes a difference frequency defined by the respective frequencies of first qubit 120 and second qubit 130. For example, the difference frequency is defined by the respective resonant frequencies of first qubit 120 and second qubit 130. In an embodiment in which first qubit 120 and second qubit 130 are non-degenerate qubits, application of the RF flux bias signal to JRM 110 drives a parametric conversion between first qubit 120 and second qubit 130. In an embodiment in which first qubit 120 and second qubit 130 are non-degenerate qubits, application of the RF flux bias signal to JRM 110 drives a three-wave mixing operation in JRM 110 to implement excitation exchange between first qubit 120 and second qubit 130.

[0035] In an embodiment, device 300 further comprises a polarity component 340 that can control the polarity of the coupling between first qubit 120 and second qubit 130. Polarity component 340 controls the polarity of the coupling by adjusting the polarity of the flux bias signal applied to JRM 110. As an example, application of the flux bias signal to JRM 110 implements the coupling between first qubit 120 and second qubit 130. Because the JJs (e.g., the four JJs 112, 114, 116, and 118 that form JRM 110) are nonlinear inductors, a current induced by each qubit (i.e., first qubit 120 and second qubit 130) flowing in the JRM 110 in the same direction as the flux bias signal experiences a higher inductance than an induced current flowing against the flux bias signal.

[0036] As a result, polarity component 340 can control the polarity of the coupling between first qubit 120 and second qubit 130 by controlling the polarity of the flux bias signal generated by bias component 330. In particular, if the flux bias signal is applied to JRM 110 in a first direction (or polarity), the excitations of each qubit can be coupled together with positive polarity. Alternatively, if the flux bias signal is applied to JRM 110 in a second direction (or polarity) opposite the first direction, the excitations of each qubit can be coupled together with negative polarity. This aspect of the disclosure is described in further detail below with respect to Figures 6-7.

[0037] FIG. 4 illustrates a circuit diagram of another exemplary, non-limiting device 400 that can use a JRM to facilitate a quantum gate between qubits in accordance with one or more embodiments described herein. As illustrated in FIG. 4, the device 400 includes a bias component 410 for applying a bias signal to the device 100. In FIG. 4, the bias component 410 includes a voltage source 420 and a pair of charge bias lines (i.e., charge bias lines 432 and 434). The voltage source 410 can generate a charge bias signal for application to the JRM 110 via the charge bias lines 432 and 434. In an embodiment, the voltage source 410 can generate a charge bias signal having an adjustable amplitude and an adjustable frequency. In an embodiment, application of the charge bias signal to the JRM 110 via the charge bias lines 432 and 434 drives a Z-mode of the JRM 110 (e.g., the Z-mode of FIG. 5(C)).

[0038] In an embodiment, the bias component 410 applies an RF charge bias signal to the JRM 110. In an embodiment, the RF charge bias signal includes a difference frequency defined by the respective frequencies of the first qubit 120 and the second qubit 130. For example, the difference frequency is defined by the respective resonant frequencies of the first qubit 120 and the second qubit 130. In an embodiment in which the first qubit 120 and the second qubit 130 are non-degenerate qubits, application of the RF charge bias signal to the JRM 110 drives a parametric conversion between the first qubit 120 and the second qubit 130. In an embodiment in which the first qubit 120 and the second qubit 130 are non-degenerate qubits, application of the RF charge bias signal to the JRM 110 drives a three-wave mixing operation in the JRM 110 to implement excitation exchange between the first qubit 120 and the second qubit 130.

[0039] Device 100, 200, 300, or 400, or combinations thereof, may comprise semiconductor devices and / or superconducting devices that may be implemented in a quantum device. Examples of suitable quantum devices in which device 100, 200, 300, or 400, or combinations thereof may be implemented include, but are not limited to, quantum hardware, quantum processors, quantum computers, and the like.

[0040] Fabrication of various embodiments of the subject disclosure described herein and / or illustrated in the figures (e.g., devices 100, 200, 300, or 400, or combinations thereof) can include a sequence of multiple steps, such as photolithographic and / or chemical processing steps, that facilitate the step-by-step creation of an electronic-based system, device, component, or circuit, such as a semiconductor device or superconducting device or both (e.g., an integrated circuit). For example, various embodiments of the subject disclosure described herein and / or illustrated in the figures (e.g., devices 100, 200, 300, or 400, or combinations thereof) may be fabricated using techniques that include, but are not limited to, photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive tone photoresist, negative tone photoresist, hybrid tone photoresist, etc.), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), deposition techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), and the like. The semiconductor device may be fabricated on a substrate (such as, for example, a silicon (Si) substrate) by employing techniques including, but not limited to, epitaxy, electrochemical deposition (ECD), chemical-mechanical planarization (CMP), backgrinding techniques, or another technique for manufacturing integrated circuits, or a combination thereof.

[0041] Various embodiments of the subject disclosure described herein and / or illustrated in the figures (e.g., devices 100, 200, 300, or 400, or combinations thereof) may be fabricated using a variety of materials. For example, various embodiments of the subject disclosure described herein and / or illustrated in the figures (e.g., devices 100, 200, 300, or 400, or combinations thereof) may be fabricated using materials from one or more different material classes, including, but not limited to, conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymeric materials, organic materials, inorganic materials, non-conductive materials, or other materials that may be utilized in one or more of the aforementioned techniques for fabricating integrated circuits, or combinations thereof.

[0042] 6 illustrates a circuit diagram of an exemplary, non-limiting, reduced coupling circuit 600 for use in a simulation in accordance with one or more embodiments described herein. As illustrated in FIG. 6, the reduced coupling circuit 600 provides an example in which adjacent qubits are mutually coupled to a JRM to form a balanced bridge topology. In this example, a JRM 610 is operably coupled to a first qubit 620 and a second qubit 630 via a first inductive device 640 and a second inductive device 650, respectively, in the balanced bridge topology.

[0043] Figure 7 shows graph 700 depicting WRSpice simulation results for the circuit of Figure 6. In Figure 7, graph 700 is a color-coded graph illustrating results obtained from a simulation of reduced coupling circuit 600, including a second qubit bias current shown as Bias Current 2 and represented on the Y-axis (e.g., the vertical axis of graph 700) in microamperes (μA), a first qubit bias current shown as Bias Current 1 and represented on the X-axis (e.g., the horizontal axis of graph 700) in microamperes (μA), and a bias current of approximately -2*e as indicated by the legend for J depicted in Figure 7. 7 radian / second ~2*e 7The resulting two-qubit coupling between the first qubit 620 and the second qubit 630 may be plotted as represented by changing color on the Z-axis (e.g., the axis of the graph 700 extending into or out of the page), which corresponds with radians / second within the range of radians / second.

[0044] In an example embodiment, to generate graph 700, the coupler is simulated, with the qubits replaced by RF tone sources, using a simulated scattering matrix. In this example, the simulation calculates the transmission scattering matrix element S21, which is then converted to an impedance matrix, and the coupling strength J is calculated from the impedance matrix. In this example, the simulation uses the following parameters: each mutual inductance (M) between each qubit and the JRM=160 picohenries (pH), an initial frequency (e.g., resonant frequency) ω of the first qubit 620, and qb,1 = 2πX5 GHz, and the initial frequency (e.g., resonant frequency) ω of the second qubit 630 qb,2 =2πX5GHz.

[0045] As shown by graph 700, the resulting two-qubit coupling J is relatively low (e.g., about 0 Hz) for a relatively wide range of bias currents. This result indicates that reduced coupling circuit 600 can implement a coupling device that is very insensitive to flux noise. Graph 700 further illustrates that by adjusting the polarity of each bias current, the polarity of the resulting two-qubit coupling J can be adjusted from positive to negative. This result indicates that by adjusting the polarity of each bias current, a maximum two-qubit coupling J of more than 2 megahertz (MHz) can be achieved.

[0046] 8 illustrates an example, non-limiting graph 800 depicting energy levels of a device versus flux bias in accordance with one or more embodiments described herein. In FIG. 8, energy states are labeled according to their occupancy at a flux bias of zero, as indicated by the depicted legend.

[0047] 9 shows an example, non-limiting colorized graph 900 depicting ZZ coupling versus flux bias and frequency of second qubit 120 in accordance with one or more embodiments described herein. As shown by graph 900, for detune within region 910, which corresponds to a flux bias of zero, the ZZ coupling is relatively low (e.g., around 10 kHz). Graph 900 further illustrates that outside of region 910, the ZZ coupling can be relatively high (e.g., above 1 GHz).

[0048] 10 illustrates an example, non-limiting graph 1000 depicting ZZ coupling versus flux bias, in accordance with one or more embodiments described herein. As illustrated in graph 1000, within a stable off region 1010, which corresponds to a flux bias of zero, ZZ coupling can be substantially zero. In an embodiment, stable off region 1010 corresponds to an off state that can be set by changing the flux bias. Graph 1000 further illustrates that in an on state outside region 1010, ZZ coupling can be relatively large (e.g., on the order of several MHz or more).

[0049] FIG. 11 illustrates an example non-limiting graph 1100 illustrating −ZZ coupling versus flux bias in units of flux quanta in accordance with one or more embodiments described herein.

[0050] FIG. 12 shows an example non-limiting graph 1200 illustrating applied flux bias versus time for implementing a two-qubit controlled phase gate in accordance with one or more embodiments described herein.

[0051] FIG. 13 shows an example non-limiting graph 1300 depicting the relative phase difference between the |01> and |11> quantum states versus time for the applied magnetic flux profile of FIG. 12 in accordance with one or more embodiments described herein.

[0052] FIG. 14 illustrates an example non-limiting graph 1400 plotting eigenstate occupancy |Cn|^2 versus the number of eigenstates n, in accordance with one or more embodiments described herein.

[0053] FIG. 15 shows an example, non-limiting graph 1500 depicting expected values ​​of excitation of first and second quantum bits versus time when the first and second quantum bits are coupled via a ring modulator in accordance with one or more embodiments described herein.

[0054] 16 shows an example, non-limiting graph 1600 depicting expected values ​​of excitations of first and second qubits versus time when the first and second qubits are coupled via a JRM during an exchange operation, in accordance with one or more embodiments described herein. In an embodiment, graph 1600 was obtained by driving a parametric conversion (or exchange) between first qubit 120 and second qubit 130 using example device 400 of FIG. 4. In this embodiment, first qubit 120 and second qubit 130 are detuned by about 600 MHz.

[0055] FIG. 17 illustrates a top view of an exemplary non-limiting device 1700 that can reduce the wiring and / or layout complexities associated with crossover features in a multi-dimensional (e.g., 2D) array of qubits in accordance with one or more embodiments described herein. Crossover features, such as crossover feature 170 of FIG. 1, can cause undesirable effects (e.g., crosstalk, noise, etc.) that adversely affect the operation of the device. Such undesirable effects can be mitigated by properly routing traces or properly placing components during the design stage. However, as scaling of quantum computing technology advances, complex multi-qubit architectures (e.g., the multi-dimensional qubit array of FIG. 18) bring about increasingly complex wiring and layout concerns.

[0056] To reduce such wiring and / or layout complexity, the exemplary device 1700 implements Manhattan junctions creating a tunnel junction shape that also functions as a crossover feature. In particular, the device 1700 includes a JRM 1710 comprising four JJs 1712, 1714, 1716, and 1718 arranged in a ring configuration. The JRM 1710 further comprises a first connection 1720 coupled to the JJ 1714 and a second connection 1730 coupled to the JJ 1718. The connections 1720, 1730, 1740, and 1750 couple the JRM 1710 to either capacitive qubit couplers or inductive qubit couplers.

[0057] FIG. 18 illustrates a top view of an exemplary, non-limiting device 1800 including a multi-dimensional qubit array in accordance with one or more embodiments described herein. The device 1800 includes four qubits (i.e., a first qubit 1810, a second qubit 1820, a third qubit 1830, and a fourth qubit 1840) arranged in a 2D array. In an embodiment, the four qubits of the device 1800 are quadrupole qubits that can provide full 2D connectivity. In the device 1800, the first qubit 1810 is coupled to the second qubit 1820 via a JRM 1850, the second qubit 1820 is coupled to the third qubit 1830 via a JRM 1860, the third qubit 1830 is coupled to the fourth qubit 1840 via a JRM 1870, and the fourth qubit 1840 is connected to the first qubit 1810 via a JRM 1880. As shown in FIG. 18, each JRM of device 1800 includes four Manhattan junctions.

[0058] 19 illustrates a top view of an exemplary, non-limiting device 1900 that can facilitate improved coupling in accordance with one or more embodiments described herein. Device 1900 includes a qubit 1910 that includes four voltage paddles or paddles (i.e., paddle 1912, paddle 1914, paddle 1916, and paddle 1918). As shown in FIG. 19, two capacitive devices are formed inside or within the footprint of each paddle that includes qubit 1910. For example, capacitive device 1920 and capacitive device 1930 are formed inside or within the footprint of paddle 1912.

[0059] 20-23 show example non-limiting graphs corresponding to simulation results obtained for the example device 1900 of FIG. 19. FIG. 20 shows an example non-limiting graph 2000 illustrating the relative phase difference between |01> and |11> quantum states versus time, according to one or more embodiments described herein. FIG. 21 shows an example non-limiting graph 2100 illustrating the occupation probability for eigenstates, according to one or more embodiments described herein. FIG. 22 shows an example non-limiting graph 2200 illustrating the expectation value of an excitation versus time, according to one or more embodiments described herein. FIG. 23 shows an example non-limiting graph 2300 illustrating the applied flux bias versus time executing a two-qubit gate via JRM, according to one or more embodiments described herein.

[0060] 24 illustrates a top view of an exemplary non-limiting device 2400 that can facilitate magnetic flux coupling in accordance with one or more embodiments described herein. The device 2400 includes a JRM 2410 disposed on an interposer 2420. A flux bias line 2430 constructed on the interposer 2420 that forms a loop under the JRM 2410 is interposed between the JRM 2410 and the interposer 2420.

[0061] 25 illustrates a top view of an example non-limiting device 2500 that can facilitate magnetic flux coupling in accordance with one or more embodiments described herein. The device 2500 includes a JRM 2510 and a flux bias line 2520 comprising an input flux bias line 2522 that forms a loop adjacent to the JRM 2510. Instead of coupling the flux bias line 2520 to ground for a return path, the flux bias line 2520 further comprises a return path 2524 that is routed along the input flux bias line 2522. In an embodiment, providing the flux bias line 2520 with the return path 2524 routed along the input flux bias line 2522 facilitates limiting unintentional stray magnetic flux coupling within the device 2500.

[0062] FIG. 26 illustrates a diagram illustrating a flow diagram of an exemplary, non-limiting computer-implemented method 2600 for facilitating a quantum gate between qubits using a JRM, according to one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. At 2602, the computer-implemented method 2600 can include operably coupling a JRM (e.g., JRM 110) to first and second qubits (e.g., first qubit 120 and second qubit 130) via respective first and second capacitive devices (e.g., first capacitive device 140 and second capacitive device 150) in a balanced bridge topology. At 2604, the computer-implemented method 2600 can include tunably coupling the first and second qubits using the JRM. In an embodiment, the first and second qubits remain isolated until a bias is applied to the JRM.

[0063] FIG. 27 illustrates a flow diagram of another exemplary, non-limiting computer-implemented method 2700 for facilitating a quantum gate between qubits using a JRM, according to one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. At 2702, the computer-implemented method 2700 can include operably coupling a JRM (e.g., JRM 110) to first and second qubits (e.g., first qubit 120 and second qubit 130) via respective first and second capacitive devices (e.g., first capacitive device 140 and second capacitive device 150) in a balanced bridge topology. At 2704, the computer-implemented method 2700 can include tunably coupling the first and second qubits using the JRM. At 2706, the computer-implemented method 2700 can include applying a bias to the JRM to facilitate control of the coupling between the first and second qubits.

[0064] In an embodiment, the first and second qubits remain isolated until a bias is applied to the JRM. In an embodiment, the computer-implemented method 2700 may further include applying an RF charge bias signal to the JRM to drive a parametric conversion between the first and second qubits. For example, the bias component 410 of FIG. 4 may be used to apply the RF charge bias signal to the JRM. In an embodiment, the computer-implemented method 2700 may further include applying an RF flux bias signal to the JRM to drive a parametric conversion between the first and second qubits. For example, the bias component 310 of FIG. 3 may be used to apply the RF flux bias signal to the JRM.

[0065] In an embodiment, the first and second qubits are degenerate qubits. In this embodiment, the computer-implemented method 2700 may further include applying a DC flux bias signal to the JRM to drive excitation exchange between the first and second qubits. For example, the bias component 310 of FIG. 3 may be used to apply the DC flux bias signal to the JRM. In an embodiment, the first and second qubits are non-degenerate qubits. In this embodiment, the computer-implemented method 2700 may further include applying a DC flux bias signal to the JRM to drive ZZ interaction between the first and second qubits. For example, the bias component 310 of FIG. 3 may be used to apply the DC flux bias signal to the JRM. In an embodiment, the computer-implemented method 2700 may further include controlling the polarity of the coupling between the first and second qubits by adjusting the polarity of the bias applied to the JRM. For example, the polarity components 340 and / or 440 of FIGS. 3-4 may be used to adjust the polarity of the bias applied to the JRM, respectively.

[0066] To provide background for various aspects of the disclosed subject matter, FIG. 28 and the following description are intended to provide an overview of a suitable environment in which various aspects of the disclosed subject matter may be implemented. FIG. 28 illustrates a block diagram of an exemplary non-limiting operating environment 2800 that may facilitate one or more embodiments described herein. For example, as described below, the operating environment 2800 may be used to implement the exemplary non-limiting multi-step manufacturing sequence described above with reference to FIGS. 1-4 that may be implemented to manufacture a device (e.g., device 100, 200, 300, or 400, or combinations thereof) according to one or more embodiments of the subject matter disclosure described herein. In another example, as described below, the operating environment 2800 may be used to implement one or more of the exemplary non-limiting computer-implemented methods 2600 and / or 2700 described above with reference to FIGS. 26-27. Repetition of descriptions of similar elements and / or processes employed in other embodiments described herein has been omitted for the sake of brevity.

[0067] The exemplary, non-limiting, multi-step manufacturing sequence described above with reference to FIGS. 1-4 that may be performed to manufacture device 100, 200, 300, or 400, or combinations thereof, may be performed by a computing system (e.g., operating environment 2800 shown in FIG. 28 and described below) and / or a computing device (e.g., computer 2812 shown in FIG. 28 and described below). In non-limiting example embodiments, such a computing system (e.g., operating environment 2800) and / or such a computing device (e.g., computer 2812) may comprise one or more processors and one or more memory devices capable of storing executable instructions that, when executed by the one or more processors, may facilitate performance of the exemplary, non-limiting, multi-step manufacturing sequence described above with reference to FIGS. 1-4. As a non-limiting example, the one or more processors may facilitate performance of the exemplary, non-limiting multi-step manufacturing sequence described above with reference to FIGS. 1-4 by managing and / or controlling one or more systems and / or equipment that function to perform the fabrication of semiconductor and / or superconductor devices.

[0068] In another example, one or more of the exemplary non-limiting computer-implemented methods 2600 and / or 2700 described above with reference to Figures 26-27 may be implemented (e.g., executed) by operating environment 2800. As a non-limiting example, one or more processors of such a computing device (e.g., computer 2812) may facilitate the performance of one or more of the exemplary non-limiting computer-implemented methods 2600 and / or 2700 described above with reference to Figures 26-27 by managing and / or controlling one or more systems and / or equipment (e.g., bias component 310, bias component 410, polar component 340, and / or polar component 440) that function to perform the operations and / or routines of such computer-implemented methods.

[0069] For ease of explanation, computer-implemented methods are shown and described as a series of operations. It should be understood that the subject innovation is not limited by the operations shown and / or by the order of operations, e.g., operations can occur in various orders, or simultaneously, or both, with other operations not presented and described herein. Moreover, not all operations shown may be required to perform a computer-implemented method in accordance with the disclosed subject matter. In addition, those skilled in the art will appreciate that a computer-implemented method may alternatively be represented as a series of interrelated states or events via a state diagram. It should be further understood that the computer-implemented methods disclosed below and throughout this specification may be stored in an article of manufacture to facilitate transporting or transferring such computer-implemented methods to a computer. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or computer-readable storage medium.

[0070] 28, a suitable operating environment 2800 for implementing various aspects of the disclosure may include a computer 2812. The computer 2812 may also include a processing unit 2814, a system memory 2816, and a system bus 2818. The system bus 2818 couples system components including, but not limited to, the system memory 2816 to the processing unit 2814. The processing unit 2814 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be employed as the processing unit 2814. The system bus 2818 can be any of several types of bus structures including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnects (PCI), Cardbus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).

[0071] The system memory 2816 may also include volatile memory 2820 and nonvolatile memory 2822. A basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 2812, such as during start-up, is stored in the nonvolatile memory 2822. The computer 2812 may also include removable and non-removable, volatile and non-volatile computer storage media. For example, FIG. 28 illustrates disk storage 2824. The disk storage 2824 may also include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. The disk storage 2824 may also include storage media, either separately or in combination with other storage media. To facilitate connection of the disk storage 2824 to the system bus 2818, a removable or non-removable interface, such as an interface 2826, is typically used. 28 also illustrates software that acts as an intermediary between users and the basic computer resources described in suitable operating environment 2800. Such software may include, for example, an operating system 2828. The operating system 2828, which may be stored on disk storage 2824, acts to control and allocate resources of the computer 2812.

[0072] System applications 2830 take advantage of management of resources by operating system 2828 through program modules 2832 and program data 2834 stored, for example, in either system memory 2816 or disk storage 2824. It is to be understood that the present disclosure may be implemented using various operating systems or combinations of operating systems. A user enters commands or information into computer 2812 through input devices 2836. Input devices 2836 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to processing unit 2814 through system bus 2818 via interface ports 2838. Interface ports 2838 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). The output device(s) 2840 use some of the same types of ports as the input device(s) 2836. Thus, for example, a USB port may be used to provide input to the computer 2812 and output information from the computer 2812 to the output device(s) 2840. Output adapter 2842 is provided to illustrate the presence of some output device(s) 2840 such as monitors, speakers, and printers, among other output devices 2840 that require special adapters. Examples of output adapter 2842 include, but are not limited to, video cards and sound cards that provide a means of connection between the output device(s) 2840 and the system bus 2818. It should be noted that other devices and / or systems of devices, such as the remote computer 2844, provide both input and output capabilities.

[0073] The computer 2812 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 2844. The remote computer 2844 can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device, or other common network node, and typically can include many or all of the elements described in connection with the computer 2812. For simplicity, only a memory storage device 2846 is shown with the remote computer 2844. The remote computer 2844 is logically connected to the computer 2812 through a network interface 2848 and then physically connected through a communication connection 2850. The network interface 2848 encompasses wired and / or wireless communication networks, such as local-area networks (LANs), wide-area networks (WANs), cellular networks, and the like. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection(s) 2850 refers to the hardware / software employed to connect network interface 2848 to system bus 2818. Communications connection(s) 2850 is shown within computer 2812 for clarity of illustration, but may also be external to computer 2812.The hardware / software for connecting to the network interface 2848 may include, by way of example only, internal and external technologies such as modems, including ordinary telephone grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0074] The present invention may be a system, a method, an apparatus, or a computer program product, or a combination thereof, at any possible level of technical detail of integration. The computer program product may include a computer readable storage medium containing computer readable program instructions for causing a processor to perform aspects of the present invention. The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves in which the instructions are recorded, and any suitable combinations of these. As used herein, computer-readable storage media should not itself be construed as being ephemeral signals such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over wires.

[0075] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to each computing device / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof) that may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing device / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage on a computer readable storage medium within each computing device / processing device. The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on each of the user's computer and a remote computer, or entirely on the remote computer or server.In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection can be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, to perform aspects of the invention, electronic circuitry, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0076] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks included in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions. These computer readable program instructions can be provided to a processor of a general purpose computer, a special purpose computer, or other programmable data processing apparatus to create a machine, where the instructions executed via a processor of the computer or other programmable data processing apparatus create means for performing the functions / operations specified in the blocks of the flowcharts and / or block diagrams. These computer readable program instructions can also be stored on a computer readable storage medium and can instruct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer readable storage medium on which the instructions are stored comprises an article of manufacture including instructions for performing aspects of the functions / operations specified in the blocks of the flowcharts and / or block diagrams. The computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to generate a computer-implemented process and cause a series of operable operations to be performed on the computer, other programmable apparatus, or other device, such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / operations specified in the flowchart and / or block diagram blocks.

[0077] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur in a different order than the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously or in reverse order, depending on the functionality involved. It is also noted that each block in the block diagrams and / or flowchart illustrations, as well as combinations of blocks included in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0078] Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product executed on one or more computers, or both, those skilled in the art will recognize that the present disclosure may be combined with or implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Furthermore, those skilled in the art will appreciate that the computer-implemented methods of the present invention may be practiced using other computer system configurations, including single-processor or multi-processor computer systems, minicomputing devices, mainframe computers, computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects may also be practiced in a distributed computing environment, where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure may be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices. For example, in one or more embodiments, the computer-executable components may be executed from a memory, which may include or consist of one or more distributed memory units. As used herein, "memory" and "memory unit" are interchangeable. Furthermore, one or more embodiments described herein may execute the code of the computer-executable components in a distributed manner, e.g., with multiple processors coupled or acting in concert to execute the code from one or more distributed memory units.As used herein, the term "memory" can encompass a single memory or memory unit in one location or multiple memories or memory units in one or more locations.

[0079] As used in this application, terms such as "component," "system," "platform," "interface," and the like, can refer to and / or include a computer-related or operable machine-related entity that includes one or more specific functions. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. As an example, both an application running on a server and the server can be a component. One or more components can reside within a process and / or a thread of execution, and a component can be localized on one computer or distributed between two or more computers, or / and. In another example, each component can execute from various computer readable media having various data structures stored thereon. A component may communicate via local and / or remote processes, such as according to signals containing one or more data packets (e.g., data from one component communicating with another component in a local or distributed system, or communicating with other systems via signals over a network such as the Internet, or both). As another example, a component may be a device having a specific function provided by mechanical parts operated by electrical or electronic circuits, and operated by a software or firmware application executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application.As yet another example, a component can be a device that provides a particular functionality through electronic components that do not include mechanical parts, and those electronic components can include a processor or other means for executing software or firmware that provides at least a portion of the functionality of the electronic component. In one aspect, a component can emulate an electronic component through a virtual machine, for example, in a cloud computing system.

[0080] In addition, the term "or" is intended to mean an inclusive or rather than an exclusive or. That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A, X employs B, or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing cases. Furthermore, the articles "a" and "an" used in this specification and the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or clear from the context to cover the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0081] As used herein, the term "processor" may refer to virtually any computing unit or device, including, but not limited to, single-core processors, single processors with software multithreaded execution capabilities, multi-core processors, multi-core processors with software multithreaded execution capabilities, multi-core processors with hardware multithreading techniques, parallel platforms, and parallel platforms with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization and improve performance of user equipment. A processor may be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component that relate to the operation and functionality of a component are used to refer to a "memory component," an entity embodied in a "memory," or a component that comprises a memory.It should be understood that the memory and / or memory components described herein can be either volatile or non-volatile memory, or can include both volatile and non-volatile memory. Examples of non-volatile memory include, but are not limited to, read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include RAM, which can act as an external cache memory, for example. For example, RAM is available in many forms, including, but not limited to, synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the memory components of the systems or computer-implemented methods disclosed herein are intended to include memory, including, but not limited to, these and any other suitable types of memory.

[0082] The foregoing includes merely examples of systems and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many other combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "including," "having," "possessing," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a similar manner to the term "comprising" as "comprising" is interpreted when used as a transitional term in the claims.

[0083] The description of various embodiments is presented for illustrative purposes, but is not intended to be exhaustive and is not limited to the disclosed embodiments. Many changes and modifications that do not depart from the scope and spirit of the described embodiments will be apparent to those skilled in the art. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A quantum coupling device comprising: a Josephson ring modulator (JRM) operably coupled to first and second quantum bits via respective first and second capacitive devices in a balanced bridge topology, the JRM providing a tunable coupling between the first and second quantum bits.

2. 10. The quantum coupling device of claim 1, further comprising a bias component that applies a bias to the JRM to facilitate control of the coupling between the first and second quantum bits.

3. The quantum coupling device of claim 2 , wherein the first and second qubits remain separated until the bias is applied to the JRM.

4. 4. The quantum coupling device of claim 2, further comprising a polarity component that controls the polarity of the coupling between the first and second quantum bits by adjusting the polarity of the bias applied to the JRM.

5. 5. The quantum coupling device of claim 2, wherein the bias component applies a radio frequency (RF) charge bias signal to the JRM to drive parametric conversion between the first and second quantum bits.

6. 6. The quantum coupling device of claim 5, wherein the RF charge bias signal comprises a difference frequency defined by the respective frequencies of the first and second quantum bits.

7. 7. The quantum coupling device of claim 2, wherein the bias component applies a radio frequency (RF) flux bias signal to the JRM to drive parametric conversion between the first and second quantum bits.

8. The quantum coupling device of claim 7 , wherein the RF flux bias signal comprises a difference frequency defined by the respective frequencies of the first and second quantum bits.

9. 9. The quantum coupling device of claim 1, wherein the first and second qubits are degenerate qubits and application of a DC flux bias signal to the JRM drives excitation exchange between the first and second qubits.

10. 10. The quantum coupling device of claim 1, wherein the first and second qubits are non-degenerate qubits, and application of a DC flux bias signal to the JRM drives a ZZ interaction between the first and second qubits.

11. The quantum coupling device of claim 1 , further comprising a flux bias line constructed on the interposer that forms a loop under the JRM.

12. The quantum coupling device of claim 11 , wherein the flux bias line comprises an input flux bias line and a return path routed along the input flux bias line.

13. 13. The quantum coupling device of claim 1, wherein the first capacitive device is formed within a paddle of the first qubit.

14. operatively coupling a Josephson ring modulator (JRM) to first and second qubits via respective first and second capacitive devices in a balanced bridge topology; and tunably coupling the first and second qubits using the JRM.

15. 15. The computer-implemented method of claim 14, further comprising applying a bias to the JRM to facilitate control of the coupling between the first and second quantum bits.

16. 16. The computer-implemented method of claim 15, wherein the first and second qubits remain isolated until the bias is applied to the JRM.

17. 17. The computer-implemented method of claim 15, further comprising controlling a polarity of the coupling between the first and second quantum bits by adjusting a polarity of the bias applied to the JRM.

18. 18. The computer-implemented method of claim 15, further comprising applying a radio frequency (RF) charge bias signal to the JRM to drive a parametric conversion between the first and second qubits.

19. 19. The computer-implemented method of claim 15, further comprising applying a radio frequency (RF) flux bias signal to the JRM to drive a parametric conversion between the first and second qubits.

20. 20. The computer-implemented method of claim 15, wherein the first and second qubits are degenerate qubits, the method further comprising applying a DC flux bias signal to the JRM to drive excitation exchange between the first and second qubits.

21. 21. The computer-implemented method of claim 15, wherein the first and second qubits are non-degenerate qubits, the method further comprising applying a DC flux bias signal to the JRM to drive a ZZ interaction between the first and second qubits.

22. Josephson Ring Modulator (JRM); a first qubit coupled to the JRM via a first inductive component; and a second qubit coupled to the JRM via a second inductive component, wherein the first and second qubits are coupled to the JRM via respective first and second reactive coupling devices in a balanced bridge topology, and the JRM is capable of providing a tunable coupling between the first and second qubits.

23. 23. The quantum coupling system of claim 22, further comprising a bias component that applies a bias to the JRM to control the coupling between the first and second quantum bits.

24. 24. The quantum coupled system of claim 22 or 23, wherein the first and second qubits remain separated until a bias is applied to the JRM.

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