Apparatus and method for performing non-local means filtering using motion estimation circuitry of a graphics processor - Patents.com

Abstract

To provide an apparatus and method for non-local mean filtering using a media processing block of a graphics processor.SOLUTION: A processor comprises: ray tracing circuitry to execute a first set of one or more commands to traverse rays through a bounding volume hierarchy (BVH) to identify BVH nodes and / or primitives intersected by the ray; shader execution circuitry to execute one or more shaders responsive to a second set of one or more commands to render a sequence of image frames based on the BVH nodes and / or primitives intersected by the ray; and a media processor comprising motion estimation circuitry to execute a third set of one or more commands to perform non-local mean filtering to remove noise from the sequence of image frames based on a mean pixel value collected across the sequence of image frames.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates generally to the field of graphics processors, and more particularly to an apparatus and method for performing stable, low-latency sorting operations. [Background technology]

[0002] Ray tracing is a technique where light transport is simulated through physically based rendering. Ray tracing is widely used in cinematic rendering, but only a few years ago it was considered too resource intensive for real-time performance. One of the key operations in ray tracing is the processing of visibility queries for ray-scene intersections, known as "ray traversal", which computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH). [Brief description of the drawings]

[0003] A fuller understanding of the invention can be obtained from the following detailed description taken in conjunction with the following drawings.

[0004] [Figure 1] FIG. 1 is a block diagram of a computer system including a processor having one or more processor cores and a graphics processor.

[0005] [Figure 2A] 1 illustrates a computing system and a graphics processor provided by embodiments described herein. [Figure 2B] 1 illustrates a computing system and a graphics processor provided by embodiments described herein. [Figure 2C] 1 illustrates a computing system and a graphics processor provided by embodiments described herein. [Figure 2D] 1 illustrates a computing system and a graphics processor provided by embodiments described herein.

[0006] [Figure 3A] FIG. 1 illustrates a block diagram of an additional graphics processor and compute accelerator architecture provided by embodiments described herein. [Figure 3B] FIG. 1 illustrates a block diagram of an additional graphics processor and compute accelerator architecture provided by embodiments described herein. [Figure 3C] FIG. 1 illustrates a block diagram of an additional graphics processor and compute accelerator architecture provided by embodiments described herein.

[0007] [Figure 4] FIG. 1 is a block diagram of a graphics processing engine for a graphics processor.

[0008] [Figure 5A] 5 illustrates thread execution logic 500 including an array of processing elements utilized in a graphics processor core according to embodiments described herein. [Figure 5B] 5 illustrates thread execution logic 500 including an array of processing elements utilized in a graphics processor core according to embodiments described herein.

[0009] [Figure 6] 6 illustrates an additional execution unit 600 according to one embodiment.

[0010] [Figure 7] 1 shows the instruction format of a graphics processor execution unit.

[0011] [Figure 8]FIG. 1 is a block diagram of a graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a rendering output pipeline.

[0012] [Figure 9A] FIG. 2 is a block diagram showing a command format of a graphics processor.

[0013] [Figure 9B] FIG. 2 is a block diagram showing a graphics processor command sequence.

[0014] [Figure 10] 1 illustrates an exemplary graphics software architecture for a data processing system.

[0015] [Figure 11A] 1 illustrates an example of an IP core development feature of one embodiment.

[0016] [Figure 11B] 1 illustrates various packaging features of different embodiments. [Figure 11C] 1 illustrates various packaging features of different embodiments. [Figure 11D] 1 illustrates various packaging features of different embodiments.

[0017] [Figure 12] 1 illustrates an exemplary system-on-chip integrated circuit that can be manufactured using one or more IP cores.

[0018] [Figure 13] 1 illustrates an exemplary graphics processor of a system-on-chip integrated circuit that may be manufactured using one or more IP cores.

[0019] [Figure 14]13. A graphics processor 1340 is shown including one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of the graphics processor 1310 of FIG.

[0020] [Figure 15] 1 illustrates an architecture for performing initial training of a machine learning architecture.

[0021] [Figure 16] We show how the machine learning engine is continuously trained and updated during runtime.

[0022] [Figure 17] We show how the machine learning engine is continuously trained and updated during runtime.

[0023] [Figure 18A] Shows how machine learning data is shared across networks. [Figure 18B] Shows how machine learning data is shared across networks.

[0024] [Figure 19] A method for training a machine learning engine is presented.

[0025] [Figure 20] 13 illustrates how nodes exchange ghost region data to perform distributed denoising operations.

[0026] [Figure 21] 1 illustrates an architecture in which image rendering and denoising operations are distributed across multiple nodes.

[0027] [Figure 22] Further details about the architecture for distributed rendering and denoising are presented.

[0028] [Diagram 23] A method for performing distributed rendering and denoising is presented.

[0029] [Figure 24] Demonstrate machine learning methods.

[0030] [Diagram 25] 1 shows multiple interconnected general-purpose graphics processors.

[0031] [Figure 26] A set of convolutional and fully connected layers for machine learning implementation is shown.

[0032] [Figure 27] Here is an example of a convolutional layer.

[0033] [Figure 28] 1 illustrates an example of a set of interconnected nodes in a machine learning implementation.

[0034] [Figure 29] We present a training framework in which a neural network learns using a training dataset.

[0035] [Figure 30A] 1 shows an example of model parallelism and data parallelism.

[0036] [Figure 30B] Indicates a system on chip (SoC).

[0037] [Diagram 31] 1 illustrates a processing architecture including a ray tracing core and a tensor core.

[0038] [Diagram 32] 1 shows an example of a beam.

[0039] [Diagram 33] 1 shows an apparatus for performing beam tracing.

[0040] [Diagram 34] 1 shows an example of a beam hierarchy.

[0041] [Diagram 35] 1 illustrates a method for performing beam tracing.

[0042] [Diagram 36] 1 shows an example of a distributed ray tracing engine.

[0043] [Figure 37] 1 illustrates the compression performed in a ray tracing system. [Figure 38] 1 illustrates the compression performed in a ray tracing system.

[0044] [Figure 39] The method is shown implemented in a ray tracing architecture.

[0045] [Diagram 40] 1 illustrates an exemplary hybrid ray tracing apparatus.

[0046] [Diagram 41] 1 shows the stack used for ray tracing operations.

[0047] [Diagram 42] Further details are given for a hybrid ray tracing device.

[0048] [Diagram 43] 2 shows the bounding volume hierarchy.

[0049] [Diagram 44] Shows the call stack and traversal state storage.

[0050] [Diagram 45] Methods for traversal and intersection are presented.

[0051] [Figure 46A] Indicates how multiple dispatch cycles are required to execute a particular shader. [Figure 46B] Indicates how multiple dispatch cycles are required to execute a particular shader.

[0052] [Figure 47] Shows how a single dispatch cycle can execute multiple shaders.

[0053] [Figure 48] Shows how a single dispatch cycle can execute multiple shaders.

[0054] [Figure 49] 1 illustrates an architecture for executing ray tracing instructions.

[0055] [Figure 50] A method for executing ray tracing instructions within a thread is presented.

[0056] [Figure 51] 1 illustrates one embodiment of an architecture for asynchronous ray tracing.

[0057] [Figure 52] 1 illustrates an embodiment of a ray traversal circuit.

[0058] [Diagram 53] 1 illustrates one embodiment of the present invention for performing non-local means filtering.

[0059] [Figure 54] 1 illustrates a method according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to one skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the underlying principles of the embodiments of the invention. Exemplary Graphics Processor Architecture and Data Types System Overview

[0061] 1 is a block diagram of a processing system 100 according to one embodiment. System 100 may be used in a single-processor desktop system, a multi-processor workstation system, or a server system having multiple processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in a mobile device, a handheld device, or an embedded device, such as in an Internet of Things (IoT) device with wired or wireless connectivity to a local or wide area network.

[0062] In one embodiment, the system 100 can include, couple to, or be integrated with a server-based gaming platform, a gaming console, including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, the system 100 is part of a mobile internet-connected device, such as a mobile phone, a smart phone, a tablet computing device, or a laptop, for example, with low internal storage capacity. The processing system 100 can also include, couple to, or be integrated with a wearable device, such as a smart watch type wearable device, augmented reality (AR) or virtual reality (VR) enhanced smart eyewear or smart clothing that provides visual, audio, or tactile output to supplement a real-world visual, audio, or tactile experience, or otherwise provides text, audio, graphics, video, holographic images or video, or tactile feedback, other augmented reality (AR) devices, or other virtual reality (VR) devices. In some embodiments, the processing system 100 includes or is part of a television or set-top box device. In one embodiment, system 100 may include, be coupled to, or be integrated into an autonomous vehicle, such as, for example, a bus, a tractor trailer, an automobile, a motor or power cycle, an airplane or glider (or any combination thereof), etc. The autonomous vehicle may use system 100 to process the sensed environment around the vehicle.

[0063] In some embodiments, the one or more processors 102 each include one or more processor cores 107 that process instructions that, when executed, perform operations for system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The one or more processor cores 107 may process different instruction sets 109, which may include instructions to facilitate emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as, for example, digital signal processors (DSPs).

[0064] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may include a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherency techniques. A register file 106 may also be included in the processor 102 and may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0065] In some embodiments, the one or more processors 102 are coupled to one or more interface buses 110 that carry communication signals, such as address, data, or control signals, between the processors 102 and other components of the system 100. In one embodiment, the interface bus 110 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In one embodiment, the processor 102 includes an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, and the platform controller hub (PCH) 130 provides connectivity to I / O devices via a local I / O bus.

[0066] The memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with suitable performance to act as a process memory. In one embodiment, the memory device 120 operates as a system memory for the system 100 and may store data 122 and instructions 121 used by the one or more processors 102 when executing applications or processes. The memory controller 116 also couples to an optional external graphics processor 118, which may communicate with the one or more graphics processors 108 of the processor 102 to perform graphics and media operations. In some embodiments, graphics, media, or compute operations may be assisted by an accelerator 112, which is a co-processor that may be configured to perform a dedicated set of graphics, media, and / or compute operations. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or compute operations. In one embodiment, accelerator 112 is a ray tracing accelerator that can be used to perform ray tracing operations in conjunction with graphics processor 108. In one embodiment, external accelerator 119 can be used instead of or in conjunction with accelerator 112.

[0067] In some embodiments, a display device 111 may be connected to the processor 102. The display device 111 may be one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display device 111 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0068] In some embodiments, the platform controller hub 130 allows peripherals to be connected to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as, for example, a 3G, 4G, 5G, or Long Term Evolution (LTE) transceiver. Firmware interface 128 allows for communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). Network controller 134 may allow for network connectivity to a wired network. In some embodiments, a high performance network controller (not shown) couples to interface bus 110. Audio controller 146, in one embodiment, is a multi-channel high definition audio controller. In one embodiment, system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. Platform controller hub 130 may also be connected to one or more Universal Serial Bus (USB) controllers 142 for connecting input devices, such as, for example, a keyboard and mouse combination 143, a camera 144, or other USB input devices.

[0069] It will be understood that the illustrated system 100 is illustrative and not limiting, as other types of separately configured data processing systems may also be used. For example, instances of memory controller 116 and platform controller hub 130 may be integrated into a separate external graphics processor, such as external graphics processor 118. In one embodiment, platform controller hub 130 and / or memory controller 116 may be external to one or more processors 102. For example, system 100 may include platform controller hub 130, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that communicates with external memory controller 116 and processor 102.

[0070] For example, a circuit board ("sled") on which components such as CPUs, memory, and other components are located may be used and designed for enhanced thermal performance. In some examples, processing components such as processors are located on the top side of the sled, while nearby memory such as DIMMs are located on the bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than typical systems, thereby increasing performance. Additionally, the sleds are configured to blindly mate with power and data communication cables in the rack, thus enhancing their ability to be quickly removed, upgraded, and / or reinstalled or replaced. Similarly, the individual components located on the sled, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from one another. In an exemplary embodiment, the components further include hardware attestation features to attest to their authenticity.

[0071] Data centers can utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and omnipath. The threads can be coupled to switches via optical fiber. Optical fiber provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Cat 5, Cat 5e, Cat 6, etc.). With a high bandwidth and low latency interconnect and network architecture, data centers can pool resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural networks, and / or artificial intelligence accelerators, etc.), and data storage drives that are physically separate when in use, and provide these resources to compute resources (e.g., processors) as needed, allowing the compute resources to access the pooled resources as if they were local.

[0072] A power supply or power source can provide voltage and / or current to system 100 or any component or system described herein. In one example, the power supply includes an AC-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such an AC power source can be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware that charges by proximity to a charging field. In one example, the power supply can include an internal battery, an AC supply, a motion-based power supply, a solar power supply, or a fuel cell power source.

[0073] 2A-2D illustrate a computing system and a graphics processor provided by embodiments described herein. Elements of FIG. 2A-2D having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0074] FIG. 2A is a block diagram of one embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. Processor 200 may include additional cores up to and including additional core 202N, depicted in a dashed box. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206. The internal cache units 204A-204N and shared cache unit 206 represent a cache memory hierarchy within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as, for example, a level 2 (L2), level 3 (L3), level 4 (L4), or other level cache. The highest level of cache before external memory is classified as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.

[0075] In some embodiments, processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as, for example, one or more PCI or PCI Express buses. System agent core 210 provides management functions for various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 for managing access to various external memory devices (not shown).

[0076] In some embodiments, one or more of processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, system agent core 210 includes components for coordinating and operating cores 202A-202N during multiple thread processing. System agent core 210 may further include a power control unit (PCU), which includes logic and components for coordinating the power state of processor cores 202A-202N and graphics processor 208.

[0077] In some embodiments, processor 200 further includes a graphics processor 208 that performs graphics processing operations. In some embodiments, graphics processor 208 couples with the set of shared cache units 206 and with system agent core 210 and includes one or more integrated memory controllers 214. In some embodiments, system agent core 210 also includes a display controller 211 that drives the graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled with the graphics processor via at least one interconnect or may be integrated within graphics processor 208.

[0078] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of processor 200. However, alternative interconnect units may be used, such as, for example, a point-to-point interconnect, a switched interconnect, or other technologies, including those known in the art. In some embodiments, graphics processor 208 couples to ring interconnect 212 via I / O link 213.

[0079] Exemplary I / O link 213 represents at least one of a number of various I / O interconnects, including on-package I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of processor cores 202A-202N and graphics processor 208 may use embedded memory module 218 as a shared last-level cache.

[0080] In some embodiments, the processor cores 202A-202N are homogenous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous with respect to instruction set architecture (ISA), where one or more of the processor cores 202A-202N execute a first instruction set while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to microarchitecture, where one or more cores that consume relatively high power are coupled with one or more power cores that consume less power. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to computing functionality. Additionally, the processor 200 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components in addition to other components.

[0081] FIG. 2B is a block diagram of hardware logic of a graphics processor core 219 according to some embodiments described herein. Elements of FIG. 2B having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Graphics processor core 219, sometimes referred to as a core slice, may be one or more graphics cores in a modular graphics processor. Graphics processor core 219 is an example of one graphics core slice, and graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 may include a fixed function block 230 coupled with multiple sub-cores 221A-221F, also referred to as sub-slices, that include modular blocks of general purpose and fixed function logic.

[0082] In some embodiments, fixed function block 230 includes a geometry / fixed function pipeline 231 that may be shared by all sub-cores of graphics processor core 219, for example in a low performance and / or low power graphics processor implementation. In various embodiments, geometry / fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., 3D pipeline 312 as seen in Figures 3A-3C and 4 described below), a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer (e.g., unified return buffer 418 of Figure 4 described below).

[0083] In one embodiment, the fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores in the system-on-chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that can be configured to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and pre-fetching. The media pipeline 234 (e.g., media pipeline 316 of FIGS. 3A-3C and 4) includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. The media pipeline 234 implements media operations via requests to compute or sampling logic in the sub-cores 221-221F.

[0084] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with general-purpose application processor cores (e.g., CPUs) and / or other components in the SoC, including memory hierarchy elements such as, for example, shared last level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 232 may also enable communication with fixed function devices in the SoC, such as, for example, a camera imaging pipeline, and may enable the use and / or implementation of global memory atomics that may be shared between the graphics processor core 219 and CPUs in the SoC. The SoC interface 232 may also implement power management controls for the graphics processor core 219 and enable an interface between the clock domain of the graphics core 219 and other clock domains in the SoC. In one embodiment, the SoC interface 232 enables the receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. Commands and instructions may be dispatched to the media pipeline 234 when media operations are being performed, or to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 231, geometry and fixed function pipelines 237) when graphics processing operations are being performed.

[0085] Graphics microcontroller 233 can be configured to perform various scheduling and management tasks for graphics processor core 219. In one embodiment, graphics microcontroller 233 can perform graphics and / or compute workload scheduling to various graphics parallel engines in execution unit (EU) arrays 222A-222F, 224A-224F in sub-cores 221A-221F. In this scheduling model, host software running on a CPU core of an SoC that includes graphics processor core 219 can present a workload to one of multiple graphics processor doorbells that invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, presenting the workload to a command streamer, preempting existing workloads running on the engines, monitoring the progress of the workload, and notifying host software when the workload is complete. In one embodiment, graphics microcontroller 233 may also facilitate low power or idle states for graphics processor core 219 and may provide graphics processor core 219 with the ability to conserve and restore registers within graphics processor core 219 upon transition to a low power state independent of the operating system and / or graphics driver software on the system.

[0086] Graphics processor core 219 may have more or less than the illustrated sub-cores 221A-221F, up to N modular sub-cores. For each set of N sub-cores, graphics processor core 219 may also include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipeline 237, and additional fixed function logic 238 that accelerates various graphics and compute processing operations. Shared function logic 235 may include logical units associated with shared function logic 420 of FIG. 4 (e.g., samplers, math, and / or inter-thread communication logic), which may be shared by each of the N sub-cores in graphics processor core 219. Shared and / or cache memory 236 may be a last level cache for the set of N sub-cores 221A-221F in graphics processor core 219, and may also act as a shared memory accessible by multiple sub-cores. Geometry / fixed function pipeline 237 may be included in place of geometry / fixed function pipeline 231 in fixed function block 230 and may include the same or similar logical units.

[0087] In one embodiment, graphics processor core 219 includes additional fixed function logic 238 that may include various fixed function acceleration logic for use by graphics processor core 219. In one embodiment, additional fixed function logic 238 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are two geometry pipelines: a full geometry pipeline in geometry / fixed function pipeline 238, 231, and a culling pipeline, which is an additional geometry pipeline that may be included in additional fixed function logic 238. In one embodiment, the culling pipeline is a limited-feature version of the full geometry pipeline. The full pipeline and the culling pipeline may run different instances of the same application, each instance having a separate context. Position-only shading may hide lengthy culling runs of discarded triangles, allowing shading to complete faster in some instances. For example, in one embodiment, the culling pipeline logic in additional fixed function logic 238 may run position shaders in parallel with the main application, and generally produce significant results faster than the full pipeline. The reason is that the culling pipeline only fetches and shades vertex position attributes, and does not rasterize and render pixels to the framebuffer. The culling pipeline can use the generated nontrivial results to calculate visibility information for all triangles, regardless of whether these triangles are culled or not. The full pipeline (which in this example might be called the replay pipeline) can skip the culled triangles and consume the visibility information to shade only the visible triangles that are eventually sent to the rasterization stage.

[0088] In one embodiment, the additional fixed function logic 238 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations involving optimization of machine learning training or inference.

[0089] Contained within each graphics sub-core 221A-221F is a set of execution resources that can be used to execute graphics, media, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. The graphics sub-cores 221A-221F include a number of EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD / IC) logic 223A-223F, 3D (e.g., texture) samplers 225A-225F, media samplers 206A-206F, shader processors 227A-227F, and shared local memories (SLMs) 228A-228F. Each of the EU arrays 222A-222F, 224A-224F includes multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs, in service of graphics, media, or compute operations. The TD / IC logic 223A-223F performs local thread dispatch and thread control operations for the execution units in the sub-cores and facilitates communication between threads executing on the execution units of the sub-cores. The 3D samplers 225A-225F can read textures or other 3D graphics related data into memory. The 3D samplers can read different texture data based on the configured sample state and the texture format associated with a given texture. The media samplers 206A-206F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each of the graphics sub-cores 221A-221F can alternately include an integrated 3D and media sampler. Threads executing on execution units within each of the sub-cores 221A-221F can utilize shared local memory 228A-228F within each sub-core, allowing threads executing within a thread group to execute using a common pool of on-chip memory.

[0090] 2C illustrates a graphics processing unit (GPU) 239 that includes a set of dedicated graphics processing resources arranged in multi-core groups 240A-240N. Although details of only a single multi-core group 240A are provided, it will be understood that the other multi-core groups 240B-240N may include the same or similar sets of graphics processing resources.

[0091] As shown, multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. A scheduler / dispatcher 241 schedules and dispatches graphics threads for execution on the various cores 243, 244, 245. A set of register files 242 store operand values ​​used by the cores 243, 244, 245 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a composite set of vector registers.

[0092] One or more combined level 1 (L1) and cache and shared memory units 247 store graphics data, such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally to each multicore group 240A. One or more texture units 247 may also be used to perform texturing operations, such as texture mapping and sampling. A level 2 (L2) cache 253, shared by all or a subset of the multicore groups 240A-240N, stores graphics data and / or instructions for multiple concurrent graphics threads. As shown, the L2 cache 253 may be shared across multiple multicore groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to memory 249, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0093] Input / output (I / O) circuitry 250 couples GPU 239 to one or more I / O devices 252, such as a digital signal processor (DSP), a network controller, or a user input device. An on-chip interconnect may be used to couple I / O device 252 to GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of I / O circuitry 250 couple I / O device 252 directly to system memory 249. In one embodiment, IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, I / O device 252, CPU 246, and GPU 239 may share the same virtual address space.

[0094] In one implementation, IOMMU 251 supports virtualization. In this case, IOMMU 251 may manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., in system memory 249). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out upon context switch (e.g., so that a new context is provided with access to the relevant set of page tables). Although not shown in FIG. 2C, each of cores 243, 244, 245 and / or multicore groups 240A-240N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical, guest physical to host physical, and guest virtual to host physical translations.

[0095] In one embodiment, CPU 246, GPU 239, and I / O devices 252 are integrated into a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated on the same chip or may be coupled to memory controller 248 via an off-chip interface. In one implementation, memory 249 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0096] In one embodiment, tensor cores 244 include multiple execution units specifically designed to perform matrix operations, which are fundamental compute operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for training and inference of neural networks. Tensor cores 244 may perform matrix operations using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half-bytes (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene and potentially combines details from multiple frames to construct a high-quality final image.

[0097] In a deep learning implementation, parallel matrix multiplication operations may be scheduled for execution on tensor cores 244. Training neural networks, in particular, requires a significant number of matrix dot-product operations. To process the inner product formulation of N×N×N matrix multiplication, tensor cores 244 may include at least N dot-product processing elements. Before the matrix multiplication begins, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded every N cycles. In each cycle, there are N dot products processed.

[0098] Matrix elements may be stored with different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for tensor cores 244 to ensure that the most efficient precision is used for different workloads (e.g., inference workloads that can tolerate quantization to bytes and half-bytes).

[0099] In one embodiment, ray tracing core 245 accelerates ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, ray tracing core 245 includes ray traversal / intersection circuitry for performing ray traversal using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 245 may also include circuitry for depth testing and culling (e.g., using a Z-buffer or similar mechanism). In one implementation, ray tracing core 245 performs traversal and intersection operations in conjunction with image denoising techniques described herein, at least some of which may be executed on tensor core 244. For example, in one embodiment, tensor core 244 implements a deep learning neural network to perform denoising of frames generated by ray tracing core 245. However, the CPU 246, the graphics core 243, and / or the ray tracing core 245 may also implement all or part of the denoising algorithm and / or the deep learning algorithm.

[0100] Additionally, as mentioned above, a distributed approach to denoising may be utilized in which the GPU 239 resides in a computing device that is coupled to other computing devices via a network or high speed interconnect. In this embodiment, the interconnected computing devices share neural network learning / training data to improve the speed at which the overall system learns and performs denoising for different types of image frames and / or different graphics applications.

[0101] In one embodiment, the ray tracing core 245 handles all BVH traversal and ray-primitive intersections, preventing the graphics core 243 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of dedicated circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of dedicated circuitry for performing ray-triangle intersection tests (e.g., intersecting traversed rays). Thus, in one embodiment, the multi-core group 240A only needs to initiate ray probes, and the ray tracing core 245 independently performs ray traversal and intersection and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or compute work, and the ray tracing core 245 performs the traversal and intersection operations.

[0102] In one embodiment, each ray tracing core 245 includes a traversal unit that performs BVH test operations and an intersection unit that performs ray-primitive intersection tests. The intersection unit generates a "hit", "no hit", or "multiple hits" response and provides it to the appropriate thread. During traversal and intersection operations, the execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed up to perform other forms of graphics work.

[0103] In one particular embodiment, described below, a hybrid rasterization / ray tracing approach is used, in which work is distributed between the graphics core 243 and the ray tracing core 245.

[0104] In one embodiment, the ray tracing core 245 (and / or other cores 243, 244) includes hardware support for a ray tracing instruction set, such as Microsoft's DirectX Raytracing (DXR). DXR includes a DispatchRays command, as well as ray-generation, closest-hit, any-hit, and miss shaders, which allow for a unique set of shaders and textures to be assigned per object. Another ray tracing platform that may be supported by the ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, it should be noted that the underlying principles of the present invention are not limited to any particular ray tracing ISA.

[0105] In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes instructions / functions for ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions. More specifically, one embodiment includes ray tracing instructions to perform the following functions: ray generation: The ray generation instruction may be executed per pixel, per sample, or other user-defined work allocation. closest hit: The closest hit instruction may be executed to find the closest intersection point between a ray and a primitive in the scene. any hit: The any hit instruction identifies multiple intersections between rays and primitives in the scene, and in some cases identifies a new closest intersection point. intersection: The intersection instruction performs a ray-primitive intersection test and outputs the result. per-primitive bounding box construction: This instruction constructs a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure); miss: indicates that the ray missed all geometry in the scene or in a specified region of the scene; visit: indicates a child volume that the ray will traverse; exceptions: contains different kinds of exception handlers (e.g., called for various error conditions).

[0106] 2D is a block diagram of a general purpose graphics processing unit (GPGPU) 270 that may be configured as a graphics processor and / or compute accelerator, according to embodiments described herein. GPGPU 270 may be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system buses and / or memory buses. In one embodiment, memory 271 is a system memory that may be shared with one or more CPUs 246, and memory 272 is a device memory dedicated to GPGPU 270. In one embodiment, each component in GPGPU 270 and device memory 272 may be mapped to memory addresses accessible by one or more CPUs 246. Access to memories 271 and 272 may be facilitated via memory controller 268. In one embodiment, memory controller 268 may include an internal direct memory access (DMA) controller 269 or logic to perform operations that would otherwise be performed by a DMA controller.

[0107] GPGPU 270 includes multiple cache memories, including L2 cache 253, L1 cache 254, instruction cache 255, and shared memory 256, where at least a portion of shared memory 256 may also be partitioned as a cache memory. GPGPU 270 also includes multiple compute units 260A-260N. Each compute unit 260A-260N includes a set of vector registers 261, scalar registers 262, vector logic unit 263, and scalar logic unit 264. Compute units 260A-260N may also include local shared memory 265 and program counter 266. Compute units 260A-260N may be coupled to constant cache 267, which may be used to store constant data, which is data that does not change during execution of a kernel or shader program executing on GPGPU 270. In one embodiment, constant cache 267 is a scalar data cache, and cached data can be fetched directly into scalar registers 262 .

[0108] During operation, one or more CPUs 246 may write commands to registers or memory that are mapped into an accessible address space within GPGPU 270. Command processor 257 may read commands from registers or memory and determine how these commands are to be processed within GPGPU 270. Thread dispatcher 258 may then be used to dispatch threads to compute units 260A-260N to execute these commands. Each compute unit 260A-260N may execute threads independently of the other compute units. Additionally, each compute unit 260A-260N may be independently configured for conditional computation and may conditionally output the results of the computation to memory. Command processor 257 may interrupt one or more CPUs 246 when a sent command is completed.

[0109] 3A-3C show block diagrams of additional graphics processor and compute accelerator architectures provided by embodiments described herein. Elements of FIGs. 3A-3C having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0110] 3A is a block diagram of a graphics processor 300. Graphics processor 300 may be a discrete graphics processing unit, multiple processing cores, or a graphics processor integrated with other semiconductor devices, such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates with registers on the graphics processor and commands placed in the processor memory via a memory-mapped I / O interface. In some embodiments, graphics processor 300 includes a memory interface 314 to access memory. Memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0111] In some embodiments, the graphics processor 300 also includes a display controller 302 that drives display output data to a display device 318. The display controller 302 includes hardware for one or more overlay planes for displaying and compositing multiple layers of video or for user interface elements. The display device 318 can be an internal or external display device. In one embodiment, the display device 318 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, the graphics processor 300 includes a video codec engine 306 for encoding, decoding, or transcoding media into or between one or more media encoding formats. These media encoding formats include, but are not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC and H.265 / HEVC, Alliance for Open Media (AOMedia) VP8 and VP9, ​​and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

[0112] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0113] In some embodiments, the GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 312 includes programmable and fixed-function elements. These elements perform various tasks within the element and / or spawn execution threads in the 3D / media subsystem 315. While the 3D pipeline 312 may be used to perform media operations, one embodiment of the GPE 310 also includes a media pipeline 316 that is used specifically to perform media operations, such as video post-processing and image correction.

[0114] In some embodiments, the media pipeline 316 includes a fixed function or programmable logic unit that performs one or more specialized media operations, such as, for example, video decode acceleration, video deinterlacing, and video encode acceleration, instead of or in lieu of the video codec engine 306. In some embodiments, the media pipeline 316 also includes a thread generation unit that generates threads for execution in the 3D / media subsystem 315. The generated threads perform calculations for the media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0115] In some embodiments, the 3D / Media subsystem 315 includes logic for executing threads created by the 3D pipeline 312 and the media pipeline 316. In one embodiment, these pipelines send thread execution requests to the 3D / Media subsystem 315. The 3D / Media subsystem 315 includes thread dispatch logic for coordinating and dispatching the various requests to available thread execution resources. These execution resources include an array of graphics execution units for processing the 3D threads and the media threads. In some embodiments, the 3D / Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0116] FIG. 3B illustrates a graphics processor 320 having a tile architecture according to an embodiment described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A in graphics engine tiles 310A-310D. Each graphics engine tile 310A-310D may be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D may also be connected to a memory module or memory device 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D may use any graphics memory technology. For example, the memory devices 326A-326D may be graphics double data rate (GDDR) memory. The memory devices 326A-326D are, in one embodiment, high bandwidth memory (HBM) modules that may be on-die with the respective graphics engine tiles 310A-310D. In one embodiment, memory devices 326A-326D are stacked memory devices that can be stacked on top of their respective graphics engine tiles 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D resides in a separate chiplet, which is bonded to a base die or base substrate, as described in further detail in Figures 11B-11D.

[0117] The graphics processing engine cluster 322 can be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 can enable communication between the graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engines 304 may be used to move data between the memory devices 326A-326D and between the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 may also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable connection to an external display device 318. The graphics processor may also be configured as a graphics accelerator or a compute accelerator. In an accelerator configuration, the display controller 302 and the display device 318 may be omitted.

[0118] Graphics processor 320 may be connected to a host system via host interface 328. Host interface 328 may allow communication between graphics processor 320, system memory, and / or other system components. Host interface 328 may be, for example, a PCI Express bus or another type of host system interface.

[0119] FIG. 3C illustrates a compute accelerator 330 according to an embodiment described herein. The compute accelerator 330 may include architectural similarities to the graphics processor 320 of FIG. 3B and is optimized for compute acceleration. The compute engine cluster 332 may include a set of compute engine tiles 340A-340D that include execution logic optimized for parallel or vector-based general-purpose compute operations. In some embodiments, the compute engine tiles 340A-340D do not include fixed-function graphics processing logic, but in one embodiment, one or more of the compute engine tiles 340A-340D may include logic for performing media acceleration. The compute engine tiles 340A-340D may be connected to memories 326A-326D via memory interconnects 325A-325D. The memories 326A-326D and memory interconnects 325A-325D may be of similar technology as found in the graphics processor 320 or may be different. The graphics compute engine tiles 340A-340D may be interconnected via a set of tile interconnects 323A-323F, and may be connected to and / or by the fabric interconnect 324. In one embodiment, the compute accelerator 330 includes a large L3 cache 336, which may be configured as a device-wide cache. The compute accelerator 330 may also be connected to a host processor and memory via a host interface 328, in a manner similar to the graphics processor 320 of FIG. 3B. Graphics Processing Engine

[0120] FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor, according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A and may represent the graphics engine tiles 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and media pipeline 316 of FIG. 3A are shown. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included in the GPE 410. For example, in at least one embodiment, a separate media and / or image processor is coupled to the GPE 410.

[0121] In some embodiments, the GPE 410 couples with or includes a command streamer 403 that provides a command stream to the 3D pipeline 312 and / or the media pipeline 316. In some embodiments, the command streamer 403 couples with memory, which may be system memory or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 403 receives commands from memory and sends the commands to the 3D pipeline 312 and / or the media pipeline 316. These commands are instructions fetched from a ring buffer, which stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may further include a batch command buffer that stores a batch of multiple commands. Commands for the 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 312 and / or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process commands and data by running operations through logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, the graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core 415A, graphics core 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources including general purpose and graphics-specific execution logic for performing graphics and compute operations, and fixed function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0122] In various embodiments, the 3D pipeline 312 may include fixed function logic and programmable logic for processing one or more shader programs by processing instructions and dispatching execution threads to the graphics core array 414. The shader programs may be vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. General purpose execution logic (e.g., execution units) within the graphics cores 415A-414B of the graphics core array 414 includes support for a variety of 3D API shader languages ​​and can execute multiple concurrent threads associated with multiple shaders.

[0123] In some embodiments, graphics core array 414 includes execution logic for performing media functions such as video processing and / or image processing. In one embodiment, the execution unit includes general purpose logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic can perform processing operations in parallel or in conjunction with general purpose logic present in processor core 107 of FIG. 1 or cores 202A-202N as seen in FIG. 2A.

[0124] Output data generated by threads executing in graphics core array 414 can output data to memory in unified return buffer (URB) 418. URB 418 can store data for multiple threads. In some embodiments, URB 418 can be used to send data between different threads executing in graphics core array 414. In some embodiments, URB 418 can also be used for synchronization between the threads of the graphics core array and fixed function logic in shared function logic 420.

[0125] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of GPE 410. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0126] The graphics core array 414 couples with shared functionality logic 420, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functionality in the shared functionality logic 420 is a hardware logic unit that provides dedicated, complementary functionality to the graphics core array 414. In various embodiments, the shared functionality logic 420 includes, but is not limited to, sampler logic 421, math logic 422, and inter-thread communication (ITC) logic 423. Additionally, some embodiments implement one or more caches 425 in the shared functionality logic 420.

[0127] Shared functionality is implemented at least when the demand for a given dedicated functionality is insufficient to justify inclusion in the graphics core array 414. Instead, a single instantiation of this dedicated functionality is implemented in the shared functionality logic 420 as a standalone entity and shared among the execution resources in the graphics core array 414. The exact set of functionality shared among and included in the graphics core array 414 varies across embodiments. In some embodiments, certain shared functionality in the shared functionality logic 420 that is used extensively by the graphics core array 414 may be included in the shared functionality logic 416 in the graphics core array 414. In various embodiments, the shared functionality logic 416 in the graphics core array 414 may include some or all of the logic in the shared functionality logic 420. In one embodiment, all logic elements in the shared functionality logic 420 may overlap with logic elements in the shared functionality logic 416 of the graphics core array 414. In one embodiment, the shared functionality logic 420 is excluded in favor of the shared functionality logic 416 in the graphics core array 414. [Execution unit]

[0128] 5A-5B illustrate thread execution logic 500 including an array of processing elements utilized in a graphics processor core, according to embodiments described herein. Elements in FIGS. 5A-5B having the same reference numbers (or names) as elements in any other figures herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. FIGS. 5A-5B provide an overview of thread execution logic 500, which may be representative of the hardware logic illustrated with each of sub-cores 221A-221F in FIG. 2B. FIG. 5A is representative of an execution unit in a general-purpose graphics processor, and FIG. 5B is representative of an execution unit that may be used in a compute accelerator.

[0129] 5A, in some embodiments, the thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including multiple execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D, ..., 508N-1, and 508N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect fabric that links each of the components. In some embodiments, the thread execution logic 500 includes one or more connections to memory, such as system memory or cache memory, through one or more of the instruction cache 506, data port 514, sampler 510, and execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a stand-alone programmable general-purpose computational unit capable of executing multiple simultaneous hardware threads while processing multiple data elements per thread in parallel. In various embodiments, the array of execution units 508A-508N is scalable to include any number of individual execution units.

[0130] In some embodiments, the execution units 508A-508N are primarily used to execute shader programs. The shader processor 502 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 504. In one embodiment, the thread dispatcher includes logic to coordinate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more of the execution units 508A-508N. For example, the geometry pipeline can dispatch vertex shaders, tessellation shaders, or geometry shaders to thread execution logic for processing. In some embodiments, the thread dispatcher 504 can also handle run-time thread creation requests from running shader programs.

[0131] In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions, allowing shader programs from graphics libraries (e.g., Direct 3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute shaders and media shaders). Each of the execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution, allowing multi-threaded operations to enable an efficient execution environment despite high-latency memory accesses. Each hardware thread within each execution unit has an independent thread state associated with a dedicated high-bandwidth register file. Execution is multi-issue per clock for a pipeline capable of integer operations, single and double precision floating point operations, SIMD branching performance, logical operations, transcendental operations, and a variety of other operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units 508A-N puts the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit may execute operations for a pixel shader, fragment shader, or another type of shader program that includes a different vertex shader. Various embodiments may be applicable to employ execution using single instruction multiple threads (SIMT) as an alternative to or in addition to using SIMD. References to SIMD cores or operations may also apply to SIMT, or to SIMD in combination with SIMT.

[0132] Each execution unit in execution units 508A-508N operates on an array of data elements. The number of data elements is the "execution size" or number of channels for an instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating point data types.

[0133] The execution unit instruction set includes SIMD instructions. Various data elements may be stored in registers as packed data types, and the execution unit will process the various elements based on the data size of these elements. For example, when processing a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit processes the vector as four separate 54-bit packed data elements (quadword (QW) sized data elements), eight separate 32-bit packed data elements (doubleword (DW) sized data elements), sixteen separate 16-bit packed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0134] In one embodiment, one or more execution units may be combined into fused execution units 509A-509N with thread control logic (507A-507N) common to the fused EUs. Multiple EUs may be fused into EU groups. Each EU in a fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group may vary depending on the embodiment. Furthermore, various SIMD widths may be implemented per EU, including but not limited to SIMD8, SIMD16, SIMD32. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, fused execution unit 509A includes a first EU 508A, a second EU 508B, and thread control logic 507A common to the first EU 508A and the second EU 508B. Thread control logic 507A controls the threads executing in fused graphics execution unit 509A, and enables each EU in fused execution units 509A-509N to execute using a common instruction pointer register.

[0135] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 for caching thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included for caching thread data during thread execution. Threads executing in the execution logic 500 may also store explicitly managed data in shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling to 3D operations and media sampling to media operations. In some embodiments, the sampler 510 includes dedicated texture or media sampling functionality for processing texture or media data during the sampling process before providing the sampling data to the execution units.

[0136] At run time, the graphics and media pipeline sends thread start requests to the thread execution logic 500 via thread generation dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) in the shader processor 502 is invoked to further compute output information and write the results to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, a pixel shader or fragment shader calculates values ​​for various vertex attributes that are interpolated across the rasterized objects. In some embodiments, the pixel processor logic in the shader processor 502 then executes pixel shader or fragment shader programs that are provided by an application programming interface (API). To execute the shader programs, the shader processor 502 dispatches threads to the execution units (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses texture sampling logic in the sampler 510 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment or discard one or more pixels from further processing.

[0137] In some embodiments, data port 514 provides a memory access mechanism to thread execution logic 500 and outputs processed data to memory for further processing in the graphics processor output pipeline. In some embodiments, data port 514 includes or couples to one or more cache memories (e.g., data cache 512) for caching data for memory access via the data port.

[0138] In one embodiment, the execution logic 500 may also include a ray tracer 505 that may provide ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be similar to or different from the ray tracing instruction set supported by the ray tracing core 245 of FIG. 2C.

[0139] 5B illustrates exemplary internal details of execution unit 508, according to multiple embodiments. GSU 508 may include an instruction fetch unit 537, a general purpose register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD floating point units (FPUs) 534, and in one embodiment, a set of dedicated integer SIMD ALUs 535. GRF 524 and ARF 526 include a set of general purpose register files and architectural register files associated with each concurrent hardware thread that may be active in GSU 508. In one embodiment, per-thread architectural state is maintained in ARF 526, and data used during thread execution is stored in GRF 524. Execution state of each thread, including a per-thread instruction pointer, may be held in thread-specific registers in ARF 526.

[0140] In one embodiment, the GSU 508 has an architecture that combines simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT), with a modular structure that can be tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, and execution unit resources are divided across the logic used to execute multiple simultaneous threads. The number of logical threads that can be executed by the GSU 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0141] In one embodiment, the graphics execution unit 508 can issue multiple instructions simultaneously, each of which can be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch the instruction to one of the send unit 530, the branch unit 532, or the SIMD FPU 534 for execution. Each execution thread can access 128 general purpose registers in the GRF 524, each of which can store 32 bytes accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread can access 4K bytes in the GRF 524, although embodiments are not so limited and other embodiments may be provided with more or less register resources. In one embodiment, the graphics execution unit 508 is also partitioned into seven hardware threads that can independently perform computational operations, although the number of threads per execution unit can also vary depending on the embodiment. For example, in one embodiment, a maximum of 16 hardware threads are supported. In one embodiment, where the seven threads can access 4K bytes, the GRF 524 can store a total of 28K bytes. If 16 threads can access 4K bytes, then GRF524 can store a total of 64K bytes. Flexible addressing modes can allow multiple registers to be addressed together, effectively building wide registers or representing sequentially arranged rectangular block type data structures.

[0142] In one embodiment, memory operations, sampler operations, and other long latency system communications are dispatched via "send" instructions executed by a message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

[0143] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating point units (FPUs) 534 to perform floating point operations. In one embodiment, the FPUs 534 also support integer calculations. In one embodiment, the FPU(s) 534 can SIMD execute up to M 32-bit floating point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPUs provides extended math capabilities supporting high throughput transcendental math functions and double precision 54-bit floating point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present and may be specifically optimized to perform operations associated with machine learning calculations.

[0144] In one embodiment, an array of multiple instances of the graphics execution unit 508 may be instantiated into a graphics sub-core group (e.g., a sub-slices). For scalability, the exact number of execution units per sub-core group may be selected by the product designer. In one embodiment, the execution unit 508 may execute instructions across multiple execution channels. In a further embodiment, each thread executing on the graphics execution unit 508 may execute on a different channel.

[0145] FIG. 6 illustrates an additional execution unit 600 according to one embodiment. The execution unit 600 may be, for example, a compute-optimized execution unit for use in the compute engine tiles 340A-340D as seen in FIG. 3C, but is not so limited. Variations of the execution unit 600 may also be used in the graphics engine tiles 310A-310D as seen in FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604. The execution unit 600 further includes a register file 606 that stores registers that may be assigned to hardware threads within the execution unit. The execution unit 600 further includes a send unit 607 and a branch unit 608. In one embodiment, the send unit 607 and the branch unit 608 may operate similarly to the send unit 530 and the branch unit 532 of the graphics execution unit 508 of FIG. 5B.

[0146] The execution unit 600 also includes a compute unit 610 that includes multiple different types of functional units. In one embodiment, the compute unit 610 includes an ALU unit 611 that includes an array of arithmetic logic units. The ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. The integer and floating point operations can be performed simultaneously. The compute unit 610 can also include a systolic array 612 and a math unit 613. The systolic array 612 includes a wide (W) deep (D) network of data processing units that can be used to perform vector operations or other data parallel operations in a systolic manner. In one embodiment, the systolic array 612 can be configured to perform matrix operations, such as matrix dot product operations. In one embodiment, the systolic array 612 supports 16-bit floating point operations, as well as 8-bit and 4-bit integer operations. In one embodiment, the systolic array 612 can be configured to accelerate machine learning operations. In such an embodiment, systolic array 612 may be configured to support the bfloat 16-bit floating point format. In one embodiment, math unit 613 may be included to perform a particular subset of math operations efficiently and in a lower power manner than ALU unit 611. Math unit 613 may include variations of math logic that may be found in shared function logic of graphics processing engines provided according to other embodiments (e.g., math logic 422 of shared function logic 420 of FIG. 4). In one embodiment, math unit 613 may be configured to perform 32-bit and 64-bit floating point operations.

[0147] The thread control unit 601 includes logic for controlling the execution of threads in the execution units. The thread control unit 601 may include thread coordination logic for starting, stopping, and preempting the execution of threads in the execution units 600. The thread state unit 602 may be used to store thread states for threads assigned to execute in the execution units 600. Storing thread states in the execution units 600 allows for rapid preemption of threads when they become blocked or idle. The instruction fetch / prefetch unit 603 may fetch instructions from an instruction cache of a higher level execution logic (e.g., instruction cache 506 as seen in FIG. 5A). The instruction fetch / prefetch unit 603 may also issue prefetch requests for instructions to be loaded into the instruction cache based on an analysis of currently executing threads. The instruction decode unit 604 may be used to decode instructions to be executed by the compute units. In one embodiment, the instruction decode unit 604 may be used as a secondary decoder that decodes complex instructions into component micro-operations.

[0148] Execution unit 600 further includes a register file 606 that may be used by hardware threads executing in execution unit 600. The registers of register file 606 may be divided throughout logic used to execute multiple simultaneous threads within compute units 610 of execution unit 600. The number of logical threads that may be executed by graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads may be assigned to each hardware thread. The size of register file 606 may vary from embodiment to embodiment based on the number of hardware threads supported. In one embodiment, register renaming may be used to dynamically allocate registers to hardware threads.

[0149] 7 is a block diagram illustrating an instruction format 700 of a graphics processor according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid boxes indicate components that are typically included in an execution unit instruction, while dashed lines include optional components or components that are included in only a subset of the instructions. In some embodiments, the instruction format 700 described and shown are macro-instructions. These macro-instructions are instructions that are fed to the execution units, as opposed to micro-operations that result from decoding an instruction each time an instruction is processed.

[0150] In some embodiments, the graphics processor execution units natively support instructions in 128-bit instruction format 710. A 64-bit compressed instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, with some options and operations restricted to the 64-bit format 730. The native instructions available in the 64-bit format 730 vary by embodiment. In some embodiments, the instructions are partially compressed using a set of index values ​​in index field 713. The execution unit hardware looks up a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instruction in the 128-bit instruction format 710. Other sizes and formats of instructions may be used.

[0151] For each format, an instruction opcode 712 defines the operation that the execution unit performs. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation on each color channel representing a texture or picture element. By default, the execution unit performs each instruction on all data channels of an operand. In some embodiments, an instruction control field 714 allows control over certain execution options, such as channel selection (e.g., predication), data channel order (e.g., swizzle), etc. For instructions in the 128-bit instruction format 710, an execution size field 716 limits the number of data channels that are executed in parallel. In some embodiments, the execution size field 716 is not available for the 64-bit compressed instruction format 730.

[0152] Some execution unit instructions have up to three operands, including two source operands src0 720 and src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions, where one of these destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2 724), and the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value sent with the instruction.

[0153] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether a direct or indirect register addressing mode is used. When a direct register addressing mode is used, the register addresses of one or more operands are provided directly in the instruction, bit by bit.

[0154] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment of the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, and the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and in a second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0155] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. If the direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. If the indirect register addressing mode is used, the register address of one or more operands may be calculated based on an address register value and an address immediate field in the instruction.

[0156] In some embodiments, to simplify opcode decode 740, instructions are grouped based on a bit field of the opcode 712. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is only an example. In some embodiments, the move and logical opcode group 742 includes data movement instructions and logical instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logical group 742 shares the five most significant bits (MSBs), with move (mov) instructions being of the form 0000xxxxb and logical instructions being of the form 0001xxxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions in the form 0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes a mix of instructions and includes synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 748 performs arithmetic operations on data channels in parallel. A vector math group 750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic, such as a dot product calculation, on vector operands. The illustrated opcode decode 740 may be used in one embodiment to determine which portion of the execution units are used to execute the decoded instruction. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be sent to a ray tracing core or ray tracing logic within a slice or partition of the execution logic. [Graphics Pipeline]

[0157] Figure 8 is a block diagram of another embodiment of a graphics processor 800. Elements of Figure 8 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0158] In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by command streamer 803, which provides instructions to individual components of geometry pipeline 820 or media pipeline 830.

[0159] In some embodiments, command streamer 803 directs the operation of vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides the vertex data to vertex shader 807, which performs coordinate space transformation and lighting operations for each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute the vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

[0160] In some embodiments, the execution units 852A-852B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, the execution units 852A-852B have an associated L1 cache 851 that is specific to each array or shared between arrays. This cache may be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0161] In some embodiments, the geometry pipeline 820 includes a tessellation component that performs hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operations. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellator 813 operates under the direction of the hull shader 811 and includes dedicated logic to generate a set of detailed geometric objects based on a coarse geometric model provided as input to the geometry pipeline 820. In some embodiments, the tessellation components (e.g., the hull shader 811, the tessellator 813, and the domain shader 817) may be bypassed if tessellation is not used.

[0162] In some embodiments, a complete geometric object can be processed by the geometry shader 819 via one or more threads dispatched to execution units 852A-852B, or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as found in earlier stages of the graphics pipeline. If tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, the geometry shader 819 is programmable by the geometry shader program to perform geometry tessellation if the tessellation units are disabled.

[0163] Prior to rasterization, a clipper 829 processes the vertex data. Clipper 829 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, a rasterizer and depth test component 873 of rendering output pipeline 870 dispatches pixel shaders to convert geometric objects into per-pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 850. In some embodiments, an application can bypass rasterizer and depth test component 873 and access un-rasterized vertex data via stream-out unit 823.

[0164] The graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing between the major components of the processor. In some embodiments, the execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via data port 856 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, the sampler 854, caches 851, 858, and the execution units 852A-852B each have a separate memory access path. In one embodiment, the texture cache 858 may be configured as a sampler cache.

[0165] In some embodiments, the render output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed function triangle and line rasterization. In some embodiments, an associated re-rendering cache 878 and depth cache 879 are also available. A pixel operations component 877 performs pixel-based operations on the data, although in some instances pixel operations associated with 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 841 or transposed at display time by the display controller 843 using overlay display planes. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing data to be shared without using main system memory.

[0166] In some embodiments, graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from a command streamer 803. In some embodiments, the media pipeline 830 includes a separate command streamer. In some embodiments, the video front end 834 processes the media commands before sending the commands to the media engine 837. In some embodiments, the media engine 837 includes a thread spawning function that spawns threads for dispatch to the thread execution logic 850 via the thread dispatcher 831.

[0167] In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples to the graphics processor via ring interconnect 802 or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 includes dedicated logic operable independently of the 3D pipeline. In some embodiments, display controller 843 couples to a display device (not shown), which may be a system integrated display device such as found in a laptop computer, or an external display device attached via a display device connector.

[0168] In some embodiments, the geometry pipeline 820 and the media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the graphics processor's driver software translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and compute APIs, all from the Khronos Group. In some embodiments, support for the Direct3D library from Microsoft Corporation may also be provided. In some embodiments, combinations of these libraries may be supported. Support for the open source computer vision library (OpenCV) may also be provided. Future APIs with compatible 3D pipelines will also be supported, provided that a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor. [Graphics Pipeline Programming]

[0169] Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to one embodiment. The solid box in Figure 9A illustrates components that are typically included in a graphics command, while the dashed boxes include optional components or components that are included in only a subset of the graphics commands. The example graphics processor command format 900 of Figure 9A includes data fields that identify a client 902, a command operation code (opcode) 904, and data for the command 906. Sub-opcodes 905 and a command size 908 are also included in some commands.

[0170] In some embodiments, the client 902 specifies a client unit of the graphics device that will process the command data. In some embodiments, the graphics processor command parser inspects the client field of each command, coordinates further processing of the command, and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the command. When a command is received by a client unit, the client unit reads the opcode 904 and, if present, the sub-opcode 905 to determine the operation to perform. The client unit executes the command using the information in the data field 906. In some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned via multiples of double words. Other command formats may be used.

[0171] The flow diagram of Figure 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses versions of the command sequence shown to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only, as embodiments are not limited to these particular commands or this command sequence. Furthermore, commands may be issued as a batch of commands in the command sequence, such that the graphics processor will process a series of commands in at least partial agreement.

[0172] In some embodiments, the graphics processor command sequence 910 may begin with a pipeline flush command 912, causing any active graphics pipelines to complete any commands currently pending in the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. A pipeline flush is executed, causing the active graphics pipelines to complete any pending commands. In response to the pipeline flush, the graphics processor's command parser will pause command processing until the active drawing engines have completed pending operations and the associated read caches are invalidated. Optionally, any data in the rendering cache that is marked as "dirty" may be flushed to memory. In some embodiments, the pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0173] In some embodiments, the pipeline select command 913 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 913 is only needed once in an execution context before issuing a pipeline command unless the context issues commands to both pipelines. In some embodiments, a pipeline flush command 912 is needed just before a pipeline switch via the pipeline select command 913.

[0174] In some embodiments, pipeline control commands 914 are used to configure the graphics pipeline for operations and to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and to clear data from one or more cache memories in the active pipeline before processing a batch of commands.

[0175] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for each pipeline to write data to. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers to which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform inter-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0176] The remaining commands in the command sequence differ based on the active pipeline of the operation. Based on a pipeline decision 920, the command sequence is either aligned with the 3D pipeline 922 beginning at a 3D pipeline state 930, or aligned with the media pipeline 924 beginning at a media pipeline state 940.

[0177] The commands that configure the 3D pipeline state 930 include 3D state setting commands for vertex buffer states, vertex element states, certain color states, depth buffer states, and other state variables that are configured before 3D primitive commands are processed. The values ​​of these commands are determined, at least in part, based on the particular 3D API in use. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0178] In some embodiments, 3D primitive 932 commands are used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters passed to the graphics processor via 3D primitive 932 commands are forwarded to a vertex fetch function of the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 932 commands are used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline 922 dispatches shader execution threads to the graphics processor execution units.

[0179] In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel backend operations may also be included in these operations.

[0180] In some embodiments, the graphics processor command sequence 910 follows the media pipeline 924 path when performing a media operation. In general, the particular use and manner of programming for the media pipeline 924 depends on the media or compute operation being performed. Certain media decode operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0181] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands that configure the media pipeline state 940 is dispatched or placed in a command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 contain data to configure the media pipeline elements that will be used to process the media object. This includes data that configures the video decoding logic and video encoding logic in the media pipeline, such as the encoding format or decoding format. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0182] In some embodiments, the media object command 942 provides a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing the video data to be processed. In some embodiments, all media pipeline state must be valid before issuing the media object command 942. Once the pipeline state is configured and the media object command 942 is queued, the media pipeline 924 is triggered by an execute command 944 or an equivalent execution event (e.g., a register write). The output from the media pipeline 924 may then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a similar manner to the media operations. [Graphics Software Architecture]

[0183] 10 illustrates an exemplary graphics software architecture for a data processing system 1000 in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each execute in system memory 1050 of the data processing system.

[0184] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language, such as Direct3D High Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0185] In some embodiments, the operating system 1020 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX®-style operating system, or an open source UNIX-style operating system that uses a variant of the Linux® kernel. The operating system 1020 can support a graphics API 1022, such as, for example, the Direct3D API, the OpenGL API, or the Vulkan API. If the Direct3D API is used, the operating system 1020 uses a front-end shader compiler 1024 to compile any shader instructions 1012 in HLSL into a lower-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can perform shader pre-compilation. In some embodiments, the high-level shaders are compiled into low-level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate format, such as, for example, a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0186] In some embodiments, the user mode graphics driver 1026 includes a back-end shader compiler 1027 for converting the shader instructions 1012 into a hardware-specific representation. If the OpenGL API is used, the shader instructions 1012 in the GLSL high-level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 communicates with a kernel mode graphics driver 1029 using operating system kernel mode functions 1028. In some embodiments, the kernel mode graphics driver 1029 communicates with a graphics processor 1032 to dispatch commands and instructions. [IP core implementation]

[0187] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as, for example, a processor. For example, the machine-readable medium may include instructions that represent various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations, known as "IP cores," are reusable units of integrated circuit logic that may be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be provided to various customers or manufacturing facilities that load the hardware model into a manufacturing machine that produces the integrated circuit. The integrated circuit may be manufactured such that the circuit performs the operations described in connection with any of the embodiments described herein.

[0188] FIG. 11A is a block diagram illustrating an IP core development system 1100 that may be used to manufacture an integrated circuit that performs operations, according to one embodiment. The IP core development system 1100 may be used to generate modular, reusable designs that may be incorporated into larger designs or may be used to build an entire integrated circuit (e.g., an SoC integrated circuit). A design facility 1130 may generate a software simulation 1110 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 1110 may be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and / or timing simulation. A register transfer level (RTL) design 1115 may then be created or synthesized from the simulation model 1112. The RTL design 1115 is an extraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is executed using the modeled digital signals. In addition to the RTL design 1115, a lower level design at the logic or transistor level may also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

[0189] The RTL design 1115 or equivalent may be further synthesized by a design facility into a hardware model 1120, which may be a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 1140 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design may be transmitted (e.g., via the Internet) by a wired connection 1150 or a wireless connection 1160. The manufacturing facility 1165 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0190] 11B illustrates a vertical cross-sectional view of an integrated circuit package assembly 1170 according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processors or accelerator devices described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 coupled to a substrate 1180. The logic 1172, 1174 may be at least partially implemented in configurable logic hardware or fixed function logic hardware and may include one or more portions of any of the processor cores, graphics processors, or other accelerator devices described herein. Each unit of logic 1172, 1174 may be implemented on a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180 and may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1170 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0191] In some embodiments, the units of logic 1172, 1174 are electrically coupled with a bridge 1182 configured to route electrical signals between the logic 1172 and 1174. The bridge 1182 may be a high density interconnect structure that provides paths for the electrical signals. The bridge 1182 may include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing features may be formed in the bridge substrate to provide chip-to-chip connections between the logic 1172 and 1174.

[0192] Although two units of logic 1172, 1174 and a bridge 1182 are shown, embodiments described herein may include more or fewer logic units on one or more dies. If logic is included in a single die, bridge 1182 may be omitted, and one or more dies may be connected with zero or more bridges. Alternatively, multiple dies or multiple logic units may be connected with one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

[0193] FIG. 11C illustrates a package assembly 1190 including multiple units of hardware logic chiplets connected to a substrate 1180 (e.g., a base die). Graphics processing units, parallel processors, and / or compute accelerators described herein may be composed of various silicon chiplets that are manufactured separately. In this context, a chiplet is an integrated circuit that is at least partially packaged and includes separate units of logic that may be assembled with other chiplets into a larger package. A set of various chiplets with different IP core logic can be assembled into a single device. Furthermore, chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP cores can be manufactured using different process technologies and configured during manufacturing. This avoids the complexity of converging multiple IPs on the same manufacturing process, especially in large SoCs with several flavors of IP. Enabling the use of multiple process technologies improves time to market and provides a cost-effective way to create multiple product SKUs. Additionally, the decomposed IP is more amenable to being independently power-gated, allowing components not being used in a given workload to be powered off, reducing overall power consumption.

[0194] The hardware logic chiplets can include dedicated hardware logic chiplets 1172, logic or I / O chiplets 1174, and / or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I / O chiplets 1174 can be implemented at least in part in configurable logic or fixed function logic hardware and can include one or more portions of any of the processor cores, graphics processors, parallel processors, or other accelerator devices described herein. The memory chiplets 1175 can be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0195] Each chiplet can be fabricated as a separate semiconductor die and coupled to substrate 1180 via interconnect structures 1173. Interconnect structures 1173 can be configured to route electrical signals between the various chiplets and logic within substrate 1180. Interconnect structures 1173 can include interconnects such as, for example, but not limited to, bumps or pillars. In some embodiments, interconnect structures 1173 can be configured to route electrical signals such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic, I / O, and memory chiplets.

[0196] In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package assembly 1190 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 for routing electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0197] In some embodiments, the logic or I / O chiplets 1174 and the memory chiplets 1175 may be electrically coupled via a bridge 1187 configured to route electrical signals between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 may be a high density interconnect structure that provides routing of electrical signals. The bridge 1187 may include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing mechanisms may be formed on the bridge substrate to provide chip-to-chip connections between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 1187 is an embedded multi-die interconnect bridge (EMIB) in some embodiments. In some embodiments, the bridge 1187 may simply be a direct connection from one chiplet to another.

[0198] Substrate 1180 may include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. Fabric 1185 may be embedded in substrate 1180 to enable communication between the various logic chiplets and logic 1191, 1193 within substrate 1180. In one embodiment, I / O 1191, fabric 1185, cache, bridges, and other hardware logic 1193 may be integrated into a base die that is layered on top of substrate 1180.

[0199] In various embodiments, package assembly 1190 may include fewer or more components and chiplets interconnected by fabric 1185 or one or more bridges 1187. Chiplets in package assembly 1190 may be arranged in a 3D or 2.5D arrangement. In general, bridge structures 1187 may be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. Fabric 1185 may be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, cache memory 1192 in the substrate may serve as a global cache for package assembly 1190, i.e., part of a distributed global cache or a dedicated cache for fabric 1185.

[0200] FIG. 11D illustrates a package assembly 1194 including compatible chiplets 1195, according to one embodiment. The compatible chiplets 1195 can be assembled as standardized slots of one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197. The bridge interconnect 1197 can be similar to other bridge interconnects described herein, for example, an EMIB. Memory chiplets can also be connected to logic or I / O chiplets via bridge interconnects. I / O and logic chiplets can communicate via an interconnect fabric. The base chiplets can each support one or more slots in a standardized format for one of logic or I / O or memory / cache.

[0201] In one embodiment, SRAM and power delivery circuits may be fabricated as one or more of the base chiplets 1196, 1198. These circuits may be fabricated using a different process technology relative to the compatible chiplets 1195 stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 may be fabricated using a large scale process technology, while the compatible chiplets may be fabricated using a small scale process technology. One or more of the compatible chiplets 1195 may be memory (e.g., DRAM chiplets). Different memory densities may be selected for the package assembly 1194 based on the capacity and / or performance targeted for the product using the package assembly 1194. Furthermore, logic chiplets with different numbers and types of functional units may be selected upon assembly based on the power and / or performance targeted for the product. Furthermore, chiplets containing different types of IP logic cores may be inserted into compatible chiplet slots, enabling hybrid processor designs that may mix and match different technology IP blocks. [Exemplary System-on-Chip Integrated Circuit]

[0202] 12-14 illustrate an exemplary integrated circuit and associated graphics processor that may be manufactured using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0203] 12 is a block diagram illustrating an example system-on-chip integrated circuit 1200 that may be manufactured using one or more IP cores, according to one embodiment. The example integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may further include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same design facility or multiple different design facilities. The integrated circuit 1200 includes a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller 1236. 2 S / I 2 The integrated circuit may further include peripheral or bus logic including a C controller 1240. Additionally, the integrated circuit may include a display device 1245 coupled to one or more of a High-Definition Multimedia Interface (HDMI®) controller 1250 and a Mobile Industry Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including a flash memory and a flash memory controller. A memory interface may be provided via a memory controller 1265 to access an SDRAM or SRAM memory device. Some integrated circuits further include an embedded security engine 1270.

[0204] 13-14 are block diagrams illustrating an example graphics processor for use in an SoC, according to an embodiment described herein. FIG. 13 illustrates an example graphics processor 1310 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 13 illustrates a further example graphics processor 1340 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. The graphics processor 1310 of FIG. 13 is an example of a low power graphics processor core. The graphics processor 1340 of FIG. 13 is an example of a higher performance graphics processor core. Each of the graphics processors 1310, 1340 may be a variation of the graphics processor 1210 of FIG. 12.

[0205] As shown in FIG. 13, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, ..., 1315N-1, and 1315N). Because the graphics processor 1310 can execute different shader programs through separate logic, the vertex processor 1305 is optimized to execute operations for a vertex shader program, and one or more fragment processors 1315A-1315N execute fragment (e.g., pixel) shading operations for a fragment shader program or a pixel shader program. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on a display device. In one embodiment, the fragment processors 1315A-1315N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0206] Graphics processor 1310 further includes one or more memory management units (MMUs) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual-to-physical address mapping for graphics processor 1310, including vertex processor 1305 and / or fragment processors 1315A-1315N, and graphics processor 1310 may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1325A-1325B. In one embodiment, one or more MMUs 1320A-1320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 of Figure 12, so that each processor 1205-1220 may participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 1330A-1330B enable the graphics processor 1310 to interface with other IP cores in the SoC via the SoC's internal bus or via direct connections.

[0207] As shown in Figure 14, graphics processor 1340 includes one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of graphics processor 1310 of Figure 13. Graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F, ..., 1355N-1, and 1355N) that provide a unified shader core architecture in which a single core or type or cores can execute any type of programmable shader code, including shader program code implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary between embodiments and implementations. Additionally, graphics processor 1340 includes an inter-core task manager 1345 that acts as a thread dispatcher that dispatches execution threads to one or more shader cores 1355A-1355N and to a tiling unit 1358 that accelerates tiling operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize internal cache usage. [Ray tracing with machine learning]

[0208] As mentioned above, ray tracing is a graphics processing technique in which light transport is simulated through physically based rendering. One of the important operations in ray tracing is processing visibility queries that require traversal and intersection testing of nodes in a bounding volume hierarchy (BVH).

[0209] Ray and path tracing based techniques compute images by tracing rays and paths through each pixel and using random sampling to compute advanced effects such as shadows, glossiness, indirect lighting, etc. Using only a few samples will produce a fast but noisy image, while using many samples will produce a high quality image but is too expensive.

[0210] Machine learning includes any circuitry, program code, or combination thereof that can improve performance of a particular task over time or make increasingly more accurate predictions or decisions. Some machine learning engines can perform tasks or make predictions / decisions without being explicitly programmed to do so. There are a variety of machine learning techniques, including, but not limited to, supervised learning, semi-supervised learning, unsupervised learning, and reinforcement learning.

[0211] In the past few years, a breakthrough solution to ray / path tracing for real-time applications has emerged in the form of "denoising" - a process that uses image processing techniques to generate high-quality, filtered / denoised images from noisy, low sample count inputs. The most effective denoising techniques rely on machine learning techniques where the machine learning engine learns what a noisy image looks like when it is computed with many more samples. In one particular implementation, the machine learning is performed by a Convolutional Neural Network (CNN). However, the underlying principles of the invention are not limited to CNN implementations. In such implementations, training data is generated using low sample count inputs and ground truth. The CNN is trained to predict a convergence pixel from a neighborhood of noisy pixel inputs around the pixel of interest.

[0212] Though not perfect, this AI-based denoising technique has proven surprisingly effective. However, it should be noted that suitable training data is required, as the network may predict incorrect results. For example, if an animation studio trains a denoising CNN on past movies on scenes on land, and then attempts to use the trained CNN to denoise frames from a new movie set on water, the denoising operation will perform sub-optimally.

[0213] To address this issue, training data may be dynamically collected while rendering, and a machine learning engine such as a CNN may be continuously trained based on currently running data, thereby continually improving the machine learning engine for the task at hand. Thus, a training phase may still be performed before runtime, but during runtime, the machine learning weights continue to be adjusted as needed. This avoids the high cost of computing reference data required for training by restricting the generation of training data to a sub-region of the image every frame or every N frames. In particular, a noisy input of a frame is generated to denoise the complete frame with the current network. Additionally, a small region of reference pixels may be generated and used for continued training, as described below.

[0214] Although a CNN implementation is described herein, any type of machine learning engine may be used, including, but not limited to, systems that perform supervised learning (e.g., building a mathematical model of a dataset that includes both an input and a desired output), unsupervised learning (e.g., evaluating input data for a particular type of structure), and / or a combination of supervised and unsupervised learning.

[0215] Existing denoising implementations operate in a training phase and a runtime phase. During the training phase, a network topology is defined which receives an NxN region of pixels with various per-pixel data channels such as pixel color, depth, normal, standard deviation, primitive ID and albedo to generate the final pixel color. A set of "representative" training data is generated using a frame's worth of low sample count inputs and with reference to the "desired" pixel color calculated at a very high sample count. The network is trained on these inputs to generate an "ideal" set of weights for the network. In these implementations, the reference data is used to train the network weights that most closely match the network's output for the desired result.

[0216] At runtime, given pre-computed ideal network weights are loaded and the network is initialized. For each frame, a denoised input of a low sample count image (i.e., the same one used for training) is generated. For each pixel, given inputs of nearby pixels are run through the network to predict the "denoised" pixel color, thus generating the denoised frame.

[0217] Figure 15 shows an implementation of initial training. A machine learning engine 1500 (e.g., a CNN) receives high sample count image data 1702 for an NxN pixel region with various per-pixel data channels such as pixel color, depth, normal, standard deviation, primitive ID, and albedo to generate the final pixel color. Representative training data is generated using one frame's worth of low sample count inputs 1501. A network is trained on these inputs to generate a set of "ideal" weights 1505 that are then used by the machine learning engine 1500 at runtime to denoise the low sample count images.

[0218] To improve upon the above technique, the denoising phase is augmented to generate new training data every frame or every subset of frames (e.g., every N frames, where N=2, 3, 4, 10, 25, etc.). In particular, as shown in Figure 16, one or more regions in each frame are selected, referred to herein as "new reference regions" 1602, that are rendered with high sample counts into a separate high sample count buffer 1604. A low sample count buffer 1603 stores the low sample count input frames 1601 (including a low sample region 1604 that corresponds to the new reference regions 1602).

[0219] The position of the new reference region 1602 may be selected randomly, or alternatively, the position of the new reference region 1602 may be adjusted in a predefined manner for each new frame (e.g., restricted to a designated region in the center of the frame, with a predefined movement of the region between frames, etc.).

[0220] Regardless of how a new reference region is selected, it is used by the machine learning engine 1600 to continually improve and update the trained weights 1605 used for denoising. In particular, the inputs of the reference pixel color from each new reference region 1602 and the noisy reference pixel from the corresponding low sample count region 1607 are rendered. Then, supplemental training is performed on the machine learning engine 1600 using the high sample count reference region 1602 and the corresponding low sample count region 1607. In contrast to the initial training, this training is performed continuously during runtime for each new reference region 1602, thereby ensuring that the machine learning engine 1600 is trained accurately. For example, per-pixel data channels (e.g., pixel color, depth, normal, standard deviation, etc.) may be evaluated. The machine learning engine 1600 uses this to adjust the trained weights 1605. As in the training case (FIG. 15), the machine learning engine 1600 is trained on a set of ideal weights 1605 to denoise low sample count input frames 1601 and generate denoised frames 1620. However, the trained weights 1605 are continually updated based on new image characteristics of new types of low sample count input frames 1601.

[0221] The retraining operations performed by the machine learning engine 1600 may run simultaneously in a background process on a graphics processor unit (GPU) or a host processor. A rendering loop, which may be implemented as a driver component and / or a GPU hardware component, may continually generate new training data (e.g., in the form of new reference regions 1602) that it places in a queue. The background training process running on the GPU or host processor may continually read the new training data from this queue to retrain the machine learning engine 1600 and update it with new weights 1605 at appropriate intervals.

[0222] 17 shows an example of one such implementation in which a background training process 1700 is implemented by a host CPU 1710. In particular, the background training process 1700 updates the machine learning engine 1600 by continually updating the trained weights 1605 with new reference regions 1602 of high sample counts and corresponding low sample regions 1604.

[0223] As shown in FIG. 18A, in a non-limiting example of a multiplayer online game, different host machines 1820-1822 individually generate reference regions that background training process 1700A-C transmits to server 1800 (e.g., a game server, etc.). Server 1800 then performs training on machine learning engine 1810 using the new reference regions received from each of hosts 1821-1822 and updates weights 1805 as previously described. These weights 1805 are transmitted to host machine 1820, which stores weights 1605A-C, thereby updating each individual machine learning engine (not shown). Because server 1800 can be provided with a large number of reference regions in a short period of time, it can efficiently and accurately update weights for any given application (e.g., an online game) run by a user.

[0224] As shown in FIG. 18B, different host machines may generate newly trained weights (e.g., based on training / reference domains 1602 as previously described) and share the newly trained weights with a server 1800 (e.g., a game server, etc.), or alternatively, may use a peer-to-peer sharing protocol. A machine learning management component 1810 on the server generates a set of combined weights 1805 using the new weights received from each of the host machines. The combined weights 1805 may be, for example, an average generated from the new weights as described herein and may be continually updated. Once generated, copies of the combined weights 1605A-C may then be transmitted to and stored in each of the host machines 1820-1821, which may then perform denoising operations using the combined weights as described herein.

[0225] This semi-closed loop update mechanism can be used by hardware manufacturers. For example, the reference network may be included as part of a driver distributed by the hardware manufacturer. The driver uses the techniques described herein to generate new training data and continually presents these back to the hardware manufacturer, so that the hardware manufacturer can use this information to continue improving its machine learning implementation for the next driver update.

[0226] In an exemplary implementation (e.g., in batch movie rendering on a render farm), the renderer transmits newly generated training regions to a dedicated server or database (within the studio's render farm) that aggregates this data from multiple rendering nodes over time. Separate processing on separate machines continuously improves the studio's dedicated denoising network, and new rendering jobs always use the most recent training network.

[0227] The machine learning method is illustrated in Figure 19. The method may be implemented in the architectures described herein, but is not limited to any particular system or graphics processing architecture.

[0228] At 1901, as part of an initial training phase, low and high sample count image data are generated for multiple image frames. At 1902, a machine learning denoising engine is trained using the high / low sample count image data. For example, a set of convolutional neural network weights associated with pixel features may be updated following the training. However, any machine learning architecture may be used.

[0229] At runtime, at 1903, image frames with low sample counts are generated along with at least one reference region with a high sample count. At 1904, the reference regions with high sample counts are used by the machine learning engine and / or separate training logic (e.g., background training module 1700) to continually improve the training of the machine learning engine. For example, the reference regions with high sample counts may be used in combination with corresponding portions of the image with low sample counts to continue to teach the machine learning engine 1904 how to most effectively perform noise removal. In a CNN implementation, for example, this may include updating weights associated with the CNN.

[0230] The above variations may be implemented in the manner in which the feedback loop to the machine learning engine is configured, the entity that generates the training data, the manner in which the training data is fed back to the training engine, and the manner in which the improved network is provided to the rendering engine, etc. Furthermore, while the above example performs continuous training using a single reference region, any number of reference regions may be used. Furthermore, as previously mentioned, the reference regions may be of different sizes, may be used for different numbers of image frames, and may be placed at different locations within the image frames using different techniques (e.g., randomly, following a predefined pattern, etc.).

[0231] Additionally, although a Convolutional Neural Network (CNN) is described as an example of a machine learning engine 1600, the underlying principles of the present invention may be implemented using any type of machine learning engine capable of continually improving its results with new training data. By way of example, but not by way of limitation, other machine learning implementations include Group Method of Data Handling (GMDH), long-short-term memory, deep reservoir computation, deep belief networks, tensor deep stacked networks, and deep predictive coding networks, to name a few. [Apparatus and method for efficient distributed noise reduction]

[0232] As mentioned above, denoising is becoming a key feature for real-time ray tracing with smooth and noise-free images. Rendering can be done across a distributed system on multiple devices, but so far, all existing denoising frameworks operate on a single instance on a single machine. When rendering is done across multiple devices, they may not be able to render all accessible pixels to compute the denoised portion of the image.

[0233] A distributed denoising algorithm is presented that works with both artificial intelligence (AI) and non-AI based denoising techniques. Regions of an image are either already distributed across nodes from distributed rendering operations or are split and distributed from a single frame buffer. When necessary, ghost regions of neighboring regions needed to compute sufficient denoising are collected from neighboring nodes and the resulting tiles are composited into the final image. [Distributed processing]

[0234] 20 shows multiple nodes 2021-2023 performing rendering. Although only three nodes are shown for purposes of simplicity, the underlying principles of the invention are not limited to any particular number of nodes, i.e., a single node may be used to implement a particular embodiment of the invention.

[0235] Each node 2021-2023 renders a portion of the image, resulting in regions 2011-2013 in this example. Although rectangular regions 2011-2013 are shown in FIG. 20, regions of any shape may be used and any device may process any number of regions. The regions required by a node to perform a sufficiently smooth denoising operation are referred to as ghost regions 2011-2013. In other words, ghost regions 2001-2003 represent the total data required to perform denoising at a specified level of quality. Reducing the quality level reduces the size of the ghost regions and therefore the amount of data required, while increasing the quality level increases the ghost regions and corresponding data required.

[0236] When a node such as node 2021 makes a local copy of the portion of ghost region 2001 required to denoise that region 2011 at a particular quality level, the node retrieves the requested data from one or more "neighboring" nodes such as node 2022 that owns the portion of ghost region 2001 as shown. Similarly, if node 2022 does not have a local copy of the portion of ghost region 2002 required to denoise region 2012 at the specified quality level, node 2022 retrieves the requested ghost region data 2032 from node 2021. The retrieval may be performed over a bus, an interconnect, a high-speed memory fabric, a network (e.g., high-speed Ethernet), or even an on-chip interconnect in a multi-core chip that can distribute rendering operations among multiple cores (e.g., used for rendering large images at very high resolution or for time-varying). Each node 2021-2023 may have individual execution units or a particular set of execution units within a graphics processor.

[0237] The specific amount of data transmitted depends on the denoising technique used. Additionally, the data from the ghost regions may include any data needed to improve the denoising of each respective region. For example, the ghost region data may include image color / wavelength, intensity / alpha data, and / or normals. However, the underlying principles of the present invention are not limited to any particular set of ghost region data. [More details]

[0238] For slower networks or interconnects, compression of this data can be utilized using existing general purpose lossless or lossy compression. Examples include, but are not limited to, zlib, gzip, and the Lempel-Ziv-Markov chain algorithm (LZMA). Further content-specific compression can be used by noting that the difference in ray hit information between frames can be very sparse, and if a node already has a difference collected from the previous frame, then only samples that contribute to that difference need to be sent. These can be selectively pushed to the node that collected these samples i, or node i can request samples from other nodes. Lossless compression is used for certain types of data and program code, while lossy compression is used for other types of data.

[0239] 21 shows further details of the interactions between the nodes 2021-2022. Each node 2021-2022 includes ray tracing rendering circuitry 2081-2082 for rendering the respective image regions 2011-2012 and ghost regions 2001-2002. The denoisers 2100-2111 perform denoising operations for each of the regions 2011-2012, with each node 2021-2022 responsible for rendering and denoising. The denoisers 2021-2022 may, for example, comprise circuitry, software or any combination thereof to generate the denoised regions 2121-2122, respectively. As already mentioned, when generating the denoised regions, the denoisers 2021-2022 may need to rely on data in ghost regions owned by different nodes (e.g., the denoiser 2100 may require data from the ghost region 2002 owned by node 2022).

[0240] Thus, the denoisers 2100-2111 may generate denoised regions 2121-2122 using data from each of the regions 2011-2012 and the ghost regions 2001-2002, at least some of which may be received from another node. The region data managers 2101-2102 may manage data transfers from the ghost regions 2001-2002 as described herein. The compressor / decompressor units 2131-2132 may perform compression and decompression, respectively, of the ghost region data exchanged between the nodes 2021-2022.

[0241] For example, the region data manager 2101 of node 2021 may send data from the ghost region 2001 to a compressor / decompressor 2131 upon request from node 2022, which compresses the data to generate compressed data 2106 that is transmitted to node 2022, thereby reducing bandwidth on an interconnect, network, bus, or other data communication link. The compressor / decompressor 2132 of node 2022 then decompresses the compressed data 2106, and the denoiser 2111 uses the decompressed ghost data to generate a denoised region 2012 with higher quality than would be possible with only the data from region 2012. The region data manager 2102 may store the data from the decompressed ghost region 2001 in a cache, memory, register file, or other storage, thereby making them available to the denoiser 2111 when generating the denoised region 2122. A similar set of operations may be performed to provide data from ghost region 2002 to denoiser 2100 at node 2021, which uses the data in combination with data from region 2011 to generate higher quality denoised region 2121. [GRAB data or rendering]

[0242] If the connections between devices such as nodes 2021-2022 are slow (i.e., below a threshold latency and / or threshold bandwidth), it may be faster to render the ghost region locally rather than requesting results from other devices. This may be determined at runtime by tracking network transaction rates and linear extrapolated rendering times with respect to ghost region size. In those cases where it would be faster to render the entire ghost region, multiple devices may end up rendering the same portion of the image. The resolution of the rendered portion of the ghost region may be adjusted based on the variance of the base region and the determined degree of blurring. [Load balancing]

[0243] Static and / or dynamic load balancing schemes may be used to distribute the processing load among the various nodes 2021-2023. For dynamic load balancing, the variance determined by the denoising filter may drive the amount of samples used to render a particular region of the scene, where low variance and blurry regions of the image require fewer samples, although both may require more time for denoising. The particular regions assigned to a particular node may be dynamically adjusted based on data from the previous frame, or dynamically communicated across devices so that they are rendered such that all devices have the same amount of work.

[0244] FIG. 22 shows how the monitoring 2201-2202 running on each of the nodes 2021-2022 collects performance metrics data, including but not limited to the time taken to transmit data over the network interfaces 2211-2212, the time taken to denoise the regions (with or without ghost region data), and the time taken to render each region / ghost region. The monitoring 2201-2202 reports these performance metrics back to the manager or load balancing node 2201, which analyzes the data to identify the current workload on each node 2021-2022 and potentially determine a more efficient mode of processing the various denoised regions 2121-2122. The manager node 2201 then distributes new workload for new regions to the nodes 2021-2022 according to the detected load. For example, the manager node 2201 may transmit more work to those nodes that are not heavily loaded and / or may reallocate work from those nodes that are overloaded. Additionally, the load balancing node 2201 may transmit reconfiguration commands to adjust the particular manner in which rendering and / or denoising is performed by each of the nodes (some examples of which are described above). [Determining the ghost area]

[0245] The size and shape of the ghost regions 2001-2002 may be determined based on the denoising algorithm implemented by the denoisers 2100-2111. Their respective sizes may then be dynamically modified based on the detected variance of the samples to be denoised. The learning algorithm used for the AI ​​denoising itself is used to determine the appropriate region size. Or, in other cases, such as bilateral blur, a predefined filter width may be used to determine the size of the ghost regions 2001-2002. In an exemplary implementation using a learning algorithm, the machine learning engine may run on the manager node 2201 and / or parts of the machine learning may run on each of the individual nodes 2021-2023 (see, e.g., Figures 18A-B and related text above). [Collecting final images]

[0246] The final image may be generated by collecting the rendered denoised regions from each of the nodes 2021-2023 without the need for ghost regions or normals. In FIG. 22, for example, the denoised regions 2121-2122 are transmitted to a region processor 2280 of the manager node 2201 which combines the regions to generate a final denoised image 2290, which is then displayed on the display 2290. The region processor 2280 may combine the regions using various 2D compositing techniques. Although illustrated as separate components, the region processor 2280 and the denoised image 2290 may be integral to the display 2290. The various nodes 2021-2022 may transmit the denoised regions 2121-2122 using direct transmission techniques, potentially using various lossy or lossless compression of the region data.

[0247] AI denoising remains an expensive operation as games move to the cloud. As such, distributed processing of denoising across multiple nodes 2021-2022 may become required to achieve real-time frame rates for traditional games or virtual reality (VR) that require higher frame rates. Movie studios will also frequently render on large render farms that can be utilized for faster denoising.

[0248] An exemplary method for performing distributed rendering and denoising is illustrated in Figure 23. The method may be implemented within the context of the system architectures described above, but is not limited to any particular system architecture.

[0249] At 2301, graphics work is dispatched to multiple nodes that perform ray tracing operations to render regions of an image frame. Each node may already have in memory the data needed to perform the operations. For example, two or more of the multiple nodes may share a common memory, or the local memory of the nodes may have the data already stored prior to the ray tracing operations. Alternatively or in addition, specific data may be transmitted to each node.

[0250] At 2302, a "ghost region" required for a particular noise reduction level (i.e., an acceptable level of performance) is determined. The ghost region comprises any data required to perform a particular noise reduction level, including data owned by one or more other nodes.

[0251] Data relating to the ghost regions (or portions thereof) are exchanged between the nodes at 2303. At 2304, each node performs denoising on each of its regions (e.g., using the exchanged data), and at 2305 the results are combined to generate a final denoised image frame.

[0252] For example, a manager node or primary node as shown in Figure 22 may dispatch work to the nodes, which then combine the work performed by the nodes to generate the final image frame. A peer-based architecture may be used, where the nodes are peers that exchange data to render and denoise the final image frame.

[0253] The nodes described herein (e.g., nodes 2021-2023) may be graphics processing computing systems interconnected via a high-speed network. Alternatively, the nodes may be individual processing elements coupled to a high-speed memory fabric. All of the nodes may share a common virtual memory space and / or a common physical memory. Alternatively, the nodes may be a combination of CPUs and GPUs. For example, the manager node 2201 described above may be a CPU and / or software running on a CPU, and the nodes 2021-2022 may be a GPU and / or software running on a GPU. A variety of different types of nodes may be used while still adhering to the basic principles of the present invention. [Example Neural Network Implementation]

[0254] There are many types of neural networks, and a simple type of neural network is the feedforward network. A feedforward network may be implemented as an acyclic graph with nodes arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer converts the inputs received by the input layer into a representation that is useful for generating outputs at the output layer. The network nodes are fully connected via edges to the nodes of adjacent layers, but there are no edges between the nodes within each layer. Data received at the nodes in the input layer of a feedforward network is propagated (i.e., "feeded forward") to the nodes in the output layer via activation functions that calculate the state of the nodes in each successive layer in the network, respectively, based on the coefficients ("weights") associated with each of the edges connecting the layers. Depending on the particular model represented by the algorithm being executed, the output from a neural network algorithm can take a variety of forms.

[0255] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training dataset. Training a neural network involves selecting a network topology using a set of training data representative of the problem being modeled by the network, and adjusting weights until the network model runs with minimal error for all instances of the training dataset. For example, during a supervised learning training process for a neural network, outputs generated by the network in response to inputs representing instances in the training dataset are compared with outputs classified as "correct" for that instance, an error signal representing the difference between the output and the classified output is calculated, and weights associated with the connections are adjusted to minimize the error as the error signal propagates backwards through the layers of the network. The network is considered "trained" if the error is minimized for each output generated from an instance of the training dataset.

[0256] The accuracy of machine learning algorithms can be greatly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can require a significant amount of time on conventional general-purpose processors. Thus, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, since the calculations performed in adjusting the coefficients in the neural network inherently lend themselves to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to take advantage of parallel processing hardware in general-purpose graphics processing devices.

[0257] 24 is a generalized diagram of a machine learning software stack 2400. Machine learning applications 2402 can be configured to train neural networks using a training dataset or to implement machine intelligence using a trained deep neural network. Machine learning applications 2402 can include training and inference functions for neural networks and / or specialized software that can be used to train neural networks prior to deployment. Machine learning applications 2402 can implement any type of machine intelligence, including, but not limited to, image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0258] Hardware acceleration of the machine learning application 2402 can be enabled through the machine learning framework 2404. The machine learning framework 2404 can be implemented in hardware as described herein, such as the processing system 100 including the processors and components described herein. Elements described in FIG. 24 that have the same or similar names as elements in any other figures herein can describe the same elements in the other figures, can operate or function in a similar manner, can have the same components, and can be linked to other entities as described elsewhere herein, including but not limited to. The machine learning framework 2404 can provide a library of machine learning primitives. Machine learning primitives are basic operations that are typically performed by machine learning algorithms. Without the machine learning framework 2404, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then reoptimize the computational logic when new parallel processors are developed. Instead, machine learning applications can be configured to perform the necessary computations using primitives provided by the machine learning framework 2404. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed during the training of a convolutional neural network (CNN). The machine learning framework 2404 can also provide primitives for implementing basic linear algebra subprograms performed by many machine learning algorithms, such as matrix and vector operations.

[0259] The machine learning framework 2404 can process input data received from the machine learning application 2402 and generate appropriate inputs to the compute framework 2406. The compute framework 2406 can abstract the underlying instructions provided to the GPGPU driver 2408 to enable the machine learning framework 2404 to leverage hardware acceleration via the GPGPU hardware 2410 without requiring the machine learning framework 2404 to have detailed knowledge of the architecture of the GPGPU hardware 2410. Furthermore, the compute framework 2406 can enable hardware acceleration of the machine learning framework 2404 across different types and generations of GPGPU hardware 2410.

[0260] GPGPU Machine Learning Acceleration

[0261] FIG. 25 illustrates a multi-GPU computing system 2500, which may be a variation of the processing system 100. Thus, the disclosure of any feature in combination with the processing system 100 herein also discloses, but is not limited to, the corresponding combination with the multi-GPU computing system 2500. Elements described in FIG. 25 that have the same or similar names as elements in any other figures herein may describe, operate or function in a similar manner as, have the same components as, and be linked to other entities as described elsewhere herein, but are not limited to such. The multi-GPU computing system 2500 may include a processor 2502 coupled to a number of GPGPUs 2506A-2506D via a host interface switch 2504. The host interface switch 2504 may be, for example, a PCI Express switching device that couples the processor 2502 to a PCI Express bus to enable the processor 2502 to communicate with the set of GPGPUs 2506A-D. Each of the multiple GPGPUs 2506A-D may be an instance of a GPGPU as described above. The GPGPUs 2506A-2506D may be interconnected via a set of high-speed point-to-point GPU-GPU links 2516. The high-speed GPU-GPU links may be connected to each of the GPGPUs 2506A-2506D via dedicated GPU links. The P2P GPU links 2516 allow direct communication between each of the GPGPUs 2506A-2506D without requiring communication via a host interface bus to which the processor 2502 is connected. Inter-GPU traffic on the P2P GPU links allows the host interface bus to remain available for system memory access or for communication with other instances of the multi-GPU computing system 2500, for example, via one or more network devices.Instead of connecting the GPGPUs 2506A-D to the processor 2502 via a host interface switch 2504, the processor 2502 may include direct support for P2P GPU links 2516 and therefore may connect directly to the GPGPUs 2506A-D.

[0262] Machine learning neural network implementation

[0263] The computing architecture described herein may be configured to perform a type of parallel processing suitable for training and deploying neural networks for machine learning in particular. A neural network can be generalized as a network of functions with graph relationships. As is known in the art, there are various types of neural network implementations used for machine learning. One exemplary type of neural network is a feedforward network, as previously described.

[0264] A second exemplary type of neural network is a convolutional neural network (CNN). A CNN is a feed-forward neural network dedicated to processing data with a known grid-like topology, such as image data. Thus, while CNNs are commonly used in vision computing or image recognition applications, they may also be used for other types of pattern recognition, such as speech and language processing. The nodes of a CNN input layer are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each filter set is propagated to nodes in successive layers of the network. Computation for a CNN involves applying a convolution mathematical operation to each filter to generate the output of that filter. Convolution is a special mathematical operation performed by two functions to generate a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function for the convolution may be referred to as the input, while the second function may be referred to as the convolution kernel. The output may be referred to as a feature map. For example, the input to a convolutional layer may be a multidimensional array of data that defines the various color components of the input image. The convolution kernel can be a multidimensional array of parameters, which are adapted by the neural network training process.

[0265] Recurrent neural networks (RNNs) are a family of feed-forward neural networks that contain feedback connections between layers. RNNs allow for the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes cycles. A cycle represents the effect of a variable's current value on its own value at a future time point, such that at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in turn. This feature is particularly useful for RNNs in language processing due to the variability in which language data can be constructed.

[0266] The figures described below present exemplary feedforward, CNN and RNN networks and explain the respective general processes for training and deploying each of these types of networks. It will be understood that these descriptions are exemplary and not limiting, and that the illustrated concepts may be generally applied to deep neural networks and machine learning techniques in general.

[0267] The above exemplary neural network can be used to perform deep learning. Deep learning is machine learning using deep neural networks. Deep neural networks used in deep learning are artificial neural networks that are composed of multiple hidden layers, as opposed to shallow neural networks that contain only a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network allow for multi-step pattern recognition, which results in reduced output errors compared to shallow machine learning techniques.

[0268] Deep neural networks used in deep learning typically include a front-end network that performs feature recognition coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on feature representations provided to the mathematical model. Deep learning allows machine learning to be performed without requiring hand-crafted feature engineering to be performed on the model. Instead, deep neural networks can learn features based on statistical structures or correlations in the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is generally dedicated to the particular task being performed, and different models are used to perform different tasks.

[0269] Once a neural network is constructed, a learning model can be applied to the network to train it to perform a specific task. The learning model describes how to adjust the weights in the model to reduce the network's output error. Backpropagation is a common method used to train neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each of the neurons in the output layer. The error values ​​are then propagated backwards until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from these errors using an algorithm such as, for example, a stochastic gradient descent algorithm to update the neural network weights.

[0270] 26 and 27 show an example convolutional neural network. FIG. 26 shows various layers in a CNN. As shown in FIG. 26, an example CNN used to model image processing can receive an input 2602 describing the red, green, and blue (RGB) components of an input image. The input 2602 can be processed by multiple convolutional layers (e.g., convolutional layer 2604, convolutional layer 2606). The output from the multiple convolutional layers can optionally be processed by a set of fully connected layers 2608. The neurons in the fully connected layer fully connect to all activations of the previous layer, as previously described in the feedforward network. The output from the fully connected layer 2608 can be used to generate an output result from the network. The activations in the fully connected layer 2608 can be calculated using matrix multiplication instead of convolution. Not all CNN implementations utilize fully connected layers. For example, in some implementations, the convolutional layer 2606 can generate the output of the CNN.

[0271] Convolutional layers are sparsely connected and differ from traditional neural network configurations found in the fully connected layer 2608. Traditional neural network layers are fully connected, so every output unit interacts with every input unit. However, as shown, convolutional layers are sparsely connected because the output of the convolution of the field (instead of the respective state values ​​of each node in the field) is input to the nodes of the subsequent layer. The kernels associated with the convolutional layers perform the convolution operation, and the output is sent to the next layer. The dimensionality reduction performed within the convolutional layers is one aspect that allows CNNs to scale and process large images.

[0272] 27 shows exemplary computational stages within a convolutional layer of a CNN. An input to the convolutional layer 2712 of a CNN can be processed in three stages of the convolutional layer 2714. The three stages can include a convolution stage 2716, a detection stage 2718, and a pooling stage 2720. The convolutional layer 2714 can then output data to successive convolutional layers. The final convolutional layer of the network can generate output feature map data, for example to generate a classification value for the input to the CNN, or can provide input to a fully connected layer.

[0273] The convolution stage 2716 performs several convolutions in parallel to generate a set of linear activations. The convolution stage 2716 can include an affine transformation, which is any transformation that can be specified as a linear transformation plus translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) that is connected to a particular region in the input, which can be determined as the local region associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the weight of the region in the local input to which the neuron is connected. The output from the convolution stage 2716 defines a set of linear activations that are processed by successive stages of the convolution layer 2714.

[0274] The linear activations may be processed by a detection stage 2718. In the detection stage 2718, each linear activation is processed by a nonlinear activation function. The nonlinear activation function enhances the nonlinear nature of the entire network without affecting the receptive fields of the convolutional layers. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x)=max(0,x) such that activations are thresholded to zero.

[0275] The pooling stage 2720 uses a pooling function that replaces the output of the convolutional layer 2706 with summary statistics of nearby outputs. Pooling functions can be used to introduce translation invariance into the neural network, so that small translations to the inputs do not change the pooled output. Invariance to local translations can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 2720, including max pooling, average pooling, and L2-norm pooling. Furthermore, some CNN implementations do not include a pooling stage. Instead, such implementations are alternative and additional convolutional stages with increased strides compared to the previous convolutional stage.

[0276] The output from the convolutional layer 2714 may then be processed by a next layer 2722, which may be an additional convolutional layer or one of the fully connected layers 2708. For example, FIG. 27 shows that the first convolutional layer 2704 may output to a second convolutional layer 2706, which in turn may output to the first layer of a fully connected layer 2808.

[0277] FIG. 28 illustrates an exemplary recurrent neural network 2800. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be constructed in various ways with various functions. The use of RNNs generally revolves around predicting the future based on a previous series of inputs using mathematical models. For example, RNNs can be used to perform statistical language modeling to predict the next word given a previous series of words. The illustrated RNN 2800 that can be described has an input layer 2802 that receives input vectors, a hidden layer 2804 that implements a recurrent function, a feedback mechanism 2805 that enables a "memory" of the previous state, and an output layer 2806 that outputs the results. The RNN 2800 operates based on time steps. The state of the RNN at a given time step is influenced based on the previous time step via the feedback mechanism 2805. For a given time step, the state of the hidden layer 2804 is defined by the previous state and the input at the current time step. An initial input (x1) for a first time step may be processed by the hidden layer 2804. A second input (x2) may be processed by the hidden layer 2804 using state information determined during the processing of the initial input (x1). A given state may be calculated as s_t=f(Ux_t+Ws_(t-1)), where U and W are parameter matrices. The function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or the normalization function f(x)=max(0,x). However, the particular mathematical function used in the hidden layer 2804 may vary depending on the particular implementation details for the RNN 2800.

[0278] In addition to the basic CNN and RNN networks described, variations on these networks may be enabled. One exemplary RNN variation is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs allow for the learning of long-term dependencies that may be required to process longer sequences of language. A variation on CNN is the Convolutional Deep Belief Network, which has a similar structure to CNNs and is trained in a similar manner to deep belief networks. Deep Belief Networks (DBNs) are generative neural networks composed of multiple layers of random (random) variables. DBNs may be trained layer-by-layer using greedy unsupervised learning. The learned weights of the DBN may then be used to provide a pre-trained neural network by determining an optimal initial set of weights for the neural network.

[0279] 29 illustrates the training and deployment of deep neural networks. Once a network is constructed for a given task, the neural network is trained using a training dataset 2902. To enable hardware acceleration of the training process, various training frameworks 2904 have been developed. For example, the machine learning frameworks described above may be configured as training frameworks. The training frameworks 2904 may connect to an untrained neural network 2906 and allow the untrained neural net to be trained using parallel processing resources as described herein to generate a trained neural net 2908.

[0280] To begin the training process, initial weights may be selected randomly or by pre-training with a deep belief network. Training cycles are then performed in either a supervised or unsupervised manner.

[0281] Supervised learning is a learning method in which training is performed as an intermediary operation, for example, when a training data set 2902 includes inputs that are combined with desired outputs for the inputs, or when a training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs to a set of expected or desired outputs. Errors are then propagated throughout the system. The training framework 2904 can be adjusted to adjust the weights that control the untrained neural network 2906. The training framework 2904 can provide tools to monitor how well the untrained neural network 2906 is converging towards a model suitable for generating correct answers based on known input data. The training process is iterative, such that the network weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural net 2908. The trained neural network 2908 can then be deployed to implement any number of machine learning operations.

[0282] Unsupervised learning is a learning method in which a network attempts to train itself using unclassified data. Thus, for unsupervised learning, a training data set 2902 includes input data without any associated output data. An untrained neural network 2906 can learn groupings within the unclassified inputs and determine how individual inputs relate to the entire data set. Unsupervised training can be used to generate self-organizing maps, and certain types of trained neural networks 2907 can perform operations useful for reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, allowing for the identification of data points within an input data set that deviate from normal patterns in the data.

[0283] Variations on supervised and unsupervised training may be employed. Semi-supervised learning is a technique in which the training data set 2902 contains a mixture of labeled and unlabeled data of the same variance. Incremental learning is a variation of supervised learning in which input data is continually used to further train the model. Incremental learning allows the trained neural network 2908 to apply knowledge imparted into the network during initial training to new data 2912 without forgetting it.

[0284] The training process, especially of deep neural networks, whether supervised or unsupervised, can be quite computationally intensive for a single compute node. Instead of using a single compute node, a distributed network of compute nodes can be used to accelerate the training process.

[0285] 30A is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes, such as those described above, to perform supervised or unsupervised training of a neural network. Each distributed computing node may include one or more host processors and one or more general-purpose processing nodes, such as highly parallel general-purpose graphics processing units. As shown, distributed learning may perform model parallelism 3002, data parallelism 3004, or a combination of model and data parallelism.

[0286] In model parallelism 3002, different computational nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Advantages of model parallelism include the ability to scale to particularly large models. Splitting up the computations associated with different layers of a neural network allows for the training of very large neural networks where all the layer weights do not fit into the memory of a single computational node. In some examples, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0287] In data parallelism 3004, different nodes of the distributed network have a complete instance of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Different approaches to data parallelism are possible, but all data parallel training approaches require techniques to combine the results and synchronize the model parameters between each node. Exemplary approaches to data combining include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transferring parameters from the nodes to the parameter server, model updates are transferred. Additionally, update-based data parallelism can be performed in a distributed manner, with updates being compressed and transferred between nodes.

[0288] The combined model and data parallelism 3006 may be implemented, for example, in a distributed system where each compute node contains multiple GPUs. Each node may have a complete instance of the model with separate GPUs in each node used to train different parts of the model.

[0289] Distributed training incurs increased overhead compared to training on a single machine, however, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques that enable high-bandwidth inter-GPU data transfers and accelerated remote data synchronization. [Example machine learning application]

[0290] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has been one of the most active research areas for machine learning applications to date. Applications of computer vision range from reproducing human visual capabilities, such as recognizing faces, to creating new categories of visual capabilities. For example, a computer vision application may be configured to recognize sound waves from vibrations caused in a visible object in a video. Parallel processor-accelerated machine learning allows computer vision applications to be trained with vast training datasets than previously feasible, and allows inference systems to be deployed using low-power parallel processors.

[0291] Parallel processor accelerated machine learning has automated driving applications including lane and road sign recognition, obstacle avoidance, navigation and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks used in automated driving solutions and enable the deployment of low power inference processors on mobile platforms suitable for integration into autonomous vehicles.

[0292] Parallel processor accelerated deep neural networks have enabled a machine learning approach to automatic speech recognition (ASR). ASR involves creating a function that calculates the most likely linguistic sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled the replacement of the Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) previously used for ASR.

[0293] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning procedures can utilize statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0294] Parallel processing platforms used for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations for accelerating multi-GPU single node training and multi-node, multi-GPU training. Exemplary parallel processors suitable for training include highly parallel general-purpose graphics processing units and / or multi-GPU computing systems described herein. Instead, deployed machine learning platforms generally include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0295] FIG. 30B illustrates an exemplary inference system-on-chip (SoC) 3100 suitable for performing inference using the trained model. Elements described in FIG. 30B that have the same or similar names as elements in any other figures herein may describe the same elements in the other figures, may operate or function in a similar manner, may have the same components, and may be linked to other entities as described elsewhere herein, including, but not limited to, the like. The SOC 3100 may integrate processing components including a media processor 3102, a vision processor 3104, a GPGPU 3106, and a multi-core processor 3108. The SOC 3100 may further include an on-chip memory 3105 that may enable a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power computing to enable deployment in a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, an implementation of the SoC 3100 may be used as part of a master control system for an autonomous vehicle. When the SoC3100 is configured for use in an autonomous vehicle, the SoC will be designed and configured to comply with the relevant functional safety standards for the deployment authority.

[0296] During operation, the media processor 3102 and the vision processor 3104 can operate simultaneously to accelerate computer vision operations. The media processor 3102 can enable low latency decoding of multiple high resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 3105. The vision processor 3104 can then analyze the decoded video and perform pre-processing operations on frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the vision processor 3104 can accelerate the convolution operations of a CNN used to perform image recognition on high resolution video data, while back-end model computations are performed by the GPGPU 3106.

[0297] The multi-core processor 3108 may include control logic that assists in sequencing and synchronization of data transfer and shared memory operations performed by the media processor 3102 and the vision processor 3104. The multi-core processor 3108 may also function as an application processor for executing software applications that may utilize the inference computation capabilities of the GPGPU 3106. For example, at least a portion of the navigation and driving logic may be implemented in software that runs on the multi-core processor 3108. Such software may issue computational workloads directly to the GPGPU 3106, or computational workloads may be issued to the multi-core processor 3108, which may offload at least a portion of these operations to the GPGPU 3106.

[0298] The GPGPU3106 may include a processing cluster, such as a low-power configuration of the processing clusters DPLAB06A-DPLAB06H in the highly parallel general-purpose graphics processing unit DPLAB00. The processing clusters in the GPGPU3106 may support instructions specifically optimized for performing inference calculations on trained neural networks. For example, the GPGPU3106 may support instructions that perform low-precision calculations, such as 8-bit and 4-bit integer vector operations. [Ray Tracing Architecture]

[0299] In one implementation, a graphics processor includes circuitry and / or program code for performing real-time ray tracing. A set of ray tracing cores dedicated to performing various ray tracing operations described herein, including ray traversal and / or ray intersection operations, may be included in the graphics processor. In addition to the ray tracing cores, sets of graphics processing cores for performing programmable shading operations and sets of tensor cores for performing matrix operations on tensor data may be included.

[0300] FIG. 31 illustrates an example portion of one such graphics processing unit (GPU) 3105 including a set of dedicated graphics processing resources arranged in multi-core groups 3100A-N. The graphics processing unit (GPU) 3105 may be a variation of the graphics processor 300, the GPGPU 1340, and / or any other graphics processor described herein. Thus, the disclosure of any feature of the graphics processor also discloses, but is not limited to, the corresponding combination with the GPU 3105. Furthermore, elements described in FIG. 31 that have the same or similar names as elements in any other figures herein may describe, operate or function in a similar manner as, have the same components as, and be linked to other entities as described elsewhere herein, but are not limited to such. Although only details of a single multi-core group 3100A are provided, it will be understood that the other multi-core groups 3100B-N may include the same or similar sets of graphics processing resources.

[0301] As shown, multi-core group 3100A may include a set of graphics cores 3130, a set of tensor cores 3140, and a set of ray tracing cores 3150. A scheduler / dispatcher 3110 schedules and dispatches graphics threads for execution on the various cores 3130, 3140, 3150. A set of register files 3120 store operand values ​​used by the cores 3130, 3140, 3150 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. The tile registers may be implemented as a combined set of multiple vector registers.

[0302] One or more level 1 (L1) caches and texture units 3160 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., local to each multicore group 3100A. A level 2 (L2) cache 3180, shared by all or a subset of the multicore groups 3100A-N, stores graphics data and / or instructions for multiple concurrent graphics threads. As shown, the L2 cache 3180 may be shared across multiple multicore groups 3100A-N. One or more memory controllers 3170 couple the GPU 3105 to memory 3198, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0303] An input / output (IO) circuit 3195 couples the GPU 3105 to one or more IO devices 3190, such as a digital signal processor (DSP), a network controller, or a user input device. An on-chip interconnect may be used to couple the I / O devices 3190 to the GPU 3105 and memory 3198. One or more IO memory management units (IOMMUs) 3170 of the IO circuit 3195 directly couple the IO devices 3190 to the system memory 3198. The IOMMUs 3170 may manage multiple sets of page tables for mapping virtual addresses to physical addresses in the system memory 3198. Furthermore, the IO devices 3190, the CPU 3199, and the GPU 3105 may share the same virtual address space.

[0304] The IOMMU 3170 may also support virtualization. In this case, the IOMMU 3170 may manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., in system memory 3198). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out upon context switch (e.g., so that a new context is provided with access to the relevant set of page tables). Although not shown in FIG. 31, each of the cores 3130, 3140, 3150 and / or multicore groups 3100A-N may include a translation lookaside buffer (TLB) for caching guest virtual to guest physical, guest physical to host physical, and guest virtual to host physical translations.

[0305] The CPU 3199, GPU 3105, and IO devices 3190 may be integrated into a single semiconductor chip and / or chip package. The illustrated memory 3198 may be integrated into the same chip or may be coupled to the memory controller 3170 via an off-chip interface. In one implementation, the memory 3198 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0306] Tensor cores 3140 may include multiple execution units specifically designed to perform matrix operations, which are fundamental compute operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for training and inference of neural networks. Tensor cores 3140 may perform matrix operations using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half-bytes (4 bits). Neural network implementations may also extract feature points for each rendered scene, potentially combining details from multiple frames, to construct a high-quality final image.

[0307] In a deep learning implementation, parallel matrix multiplication operations may be scheduled for execution on the tensor cores 3140. Training neural networks, in particular, requires a significant number of matrix dot product operations. To process the inner product formulation of N×N×N matrix multiplication, the tensor cores 3140 may include at least N dot product processing elements. Before starting the matrix multiplication, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded every N cycles. In each cycle, there are N dot products processed.

[0308] Matrix elements may be stored in different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4), depending on the particular implementation. Different precision modes may be specified for tensor cores 3140 to ensure that the most efficient precision is used for different workloads (e.g., inference workloads that can tolerate quantization to bytes and half-bytes).

[0309] The ray tracing core 3150 may also be used to accelerate ray tracing operations for both real-time and non-real-time ray tracing implementations. In particular, the ray tracing core 3150 may include ray traversal / intersection circuitry for performing ray traversal using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 3150 may also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar mechanism). In one implementation, the ray tracing core 3150 performs traversal and intersection operations in conjunction with the image denoising techniques described herein, at least some of which may be performed by the tensor core 3140. For example, the tensor core 3140 may implement a deep learning neural network to denoise frames generated by the ray tracing core 3150. However, the CPU 3199, the graphics core 3130, and / or the ray tracing core 3150 may also implement all or part of the denoising algorithm and / or the deep learning algorithm.

[0310] Additionally, as mentioned above, a distributed approach to denoising may be utilized in which the GPU 3105 resides in a computing device that is linked to other computing devices via a network or high speed interconnect. The interconnected computing devices may further share neural network learning / training data, improving the speed at which the overall system learns to perform denoising for different types of image frames and / or different graphics applications.

[0311] The ray tracing core 3150 may handle all BVH traversal and ray-primitive intersection, preventing the graphics core 3130 from being overloaded with thousands of instructions per ray. Each ray tracing core 3150 may include a first set of dedicated circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of dedicated circuitry for performing ray-triangle intersection tests (e.g., intersecting traversed rays). Thus, the multi-core group 3100A only needs to initiate ray probes, and the ray tracing core 3150 independently performs ray traversal and intersection and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 3130, 3140 may be freed to perform other graphics or compute work, and the ray tracing core 3150 performs the traversal and intersection operations.

[0312] Each ray tracing core 3150 may include a traversal unit for performing BVH test operations and an intersection unit for performing ray-primitive intersection tests. The intersection unit may then generate a "hit", "no hit", or "multiple hit" response and provide it to the appropriate thread. During traversal and intersection operations, the execution resources of other cores (e.g., graphics core 3130 and tensor core 3140) may be freed up to perform other forms of graphics work.

[0313] A hybrid rasterization / ray tracing approach may be used, in which work is distributed between the graphics core 3130 and the ray tracing core 3150.

[0314] The ray tracing core 3150 (and / or other cores 3130, 3140) may include hardware support for a ray tracing instruction set, such as Microsoft's DirectX Raytracing (DXR). DXR includes a DispatchRays command, as well as ray-generation, closest-hit, any-hit, and miss shaders, which allow for a unique set of shaders and textures to be assigned per object. Another ray tracing platform that may be supported by the ray tracing core 3150, graphics core 3130, and tensor core 3140 is Vulkan 1.1.85. However, it should be noted that the underlying principles of the present invention are not limited to any particular ray tracing ISA.

[0315] In general, the various cores 3150, 3140, 3130 may support a ray tracing instruction set that includes instructions / functions for ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions. More specifically, ray tracing instructions may be included to perform the following functions:

[0316] ray generation: The ray generation command may be executed per pixel, per sample, or other user-defined work allocation.

[0317] closest hit: The closest hit command may be executed to find the closest intersection point between a ray and a primitive in a scene.

[0318] any hit: The any hit command identifies multiple intersections between rays and primitives in the scene, and in some cases identifies a new closest intersection point.

[0319] The intersection:intersection command performs a ray-primitive intersection test and outputs the result.

[0320] per-primitive bounding box construction: This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0321] miss: indicates that the ray misses all geometry in the scene or in a specified area of ​​the scene.

[0322] visit: indicates the child volume that the ray will traverse.

[0323] exceptions: Contains different kinds of exception handlers (e.g., called for various error conditions).

[0324] The media processing circuit 3197 includes fixed function circuitry for encoding, decoding, or encoding media into or between one or more media encoding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and Joint Photographic Experts Group (JPEG) formats such as Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, JPEG, and Motion JPEG (MJPEG) formats. To process these formats, one embodiment of the media processing circuit includes logic for performing scaling / quantization, intra-frame prediction, inter-frame prediction, motion compensation, and motion estimation.

[0325] The display processor 3193 may include a 2D display engine and a display controller. The display processor 3193 may also include dedicated logic capable of operating independently from other circuitry of the GPU 3105. The display controller includes an interface for coupling to a display device (not shown). The display device may be a system integrated display device such as found in a laptop computer, or an external display device attached via a display device connector. [Hierarchical beam tracing]

[0326] Bounding volume hierarchies are commonly used to improve efficiency when operations are performed on graphics primitives and other graphics objects. A BVH is a hierarchical tree structure built on a set of geometric objects. At the top of the tree structure is a root node that contains all of the geometric objects in a given scene. Individual geometric objects are enveloped in bounding volumes that form the leaf nodes of the tree. These nodes are then grouped into smaller sets and contained within larger bounding volumes. These are also grouped and contained within other larger bounding volumes in a recursive manner, ultimately resulting in a tree structure with a single bounding volume represented by the root node at the top of the tree. Bounding volume hierarchies are used to efficiently support various operations on sets of geometric objects, such as collision detection, primitive culling, and ray traversal / intersection operations used in ray tracing.

[0327] In a ray tracing architecture, rays are traversed across the BVH to determine ray-primitive intersections. For example, if a ray does not pass through the root node of the BVH, it does not intersect with any of the primitives contained in the BVH, and no further processing for the ray is required for this set of primitives. If a ray passes through the first child node of the BVH but not the second child node, the ray does not need to be tested against any primitives contained by the second child node. In this manner, the BVH provides an efficient mechanism for testing ray-primitive intersections.

[0328] Rather than individual rays, a group of consecutive rays, referred to as a "beam," may be tested against the BVH. FIG. 32 shows an example beam 3201 that is outlined by four different rays. Any ray that intersects with a patch 3200 defined by the four rays is considered to be in the same beam. Although the beam 3201 in FIG. 32 is defined by a rectangular arrangement of rays, the beam may be defined in a variety of other ways (e.g., a circle, an ellipse, etc.) while still adhering to the basic principles of the invention.

[0329] FIG. 33 illustrates how the ray tracing engine 3310 of the GPU 3320 implements the beam tracing techniques described herein. In particular, the ray generation circuit 3304 generates multiple rays, for which traversal and intersection operations are performed. However, rather than performing the traversal and intersection operations on individual rays, the traversal and intersection operations are performed using a hierarchy of beams 3307 generated by the beam hierarchy construction circuit 3305. A beam hierarchy is similar to a bounding volume hierarchy (BVH). For example, FIG. 34 provides an example of a primary beam 3400 that may be subdivided into multiple different components. In particular, the primary beam 3400 may be divided into quadrants 3401-3404, each of which may itself be divided into child quadrants, such as child quadrants A-D within the quadrant 3404. The primary beam may be subdivided in various manners. For example, the primary beam may be divided into halves (rather than quadrants), each of the halves may be divided into halves, and so on. Regardless of how the subdivision is done, a hierarchical structure is created in a similar manner to a BVH, e.g., a root node representing the primary beam 3400, first level child nodes each represented by quadrants 3401-3404, second level child nodes for each child quadrant A-D, and so on.

[0330] Once the beam hierarchy 3307 is constructed, the traversal / intersection circuitry 3306 may perform traversal / intersection operations using the beam hierarchy 3307 and the BVH 3308. In particular, it may test the beam against the BVH and cull portions of the beam that do not intersect with any portion of the BVH. Using the data shown in FIG. 34, for example, if the sub-beams associated with sub-regions 3402 and 3403 do not intersect with the BVH or a particular branch of the BVH, they may be culled with respect to the BVH or branch. The remaining portions 3401, 3404 may be tested against the BVH by performing a depth-first search or other search algorithm.

[0331] A method for ray tracing is illustrated in Figure 35. The method may be implemented in the context of the graphics processing architectures described above, but is not limited to any particular architecture.

[0332] In 3500, a primary beam is constructed containing multiple rays, and in 3501, the beam is subdivided and a hierarchical data structure is generated to create the beam hierarchy. Operations 3500-3501 may be performed as a single, integrated operation to build the beam hierarchy from multiple rays. In 3502, the beam hierarchy is used with the BVH to cull rays (from the beam hierarchy) and / or nodes / primitives from the BVH. In 3503, ray-primitive intersections are determined for the remaining rays and primitives. [Lossy and lossless packet compression for distributed ray tracing systems]

[0333] Ray tracing computations may be distributed across multiple computational nodes coupled together via a network. Figure 36, for example, shows a ray tracing cluster 3600 including multiple ray tracing nodes 3610-3613 that perform ray tracing computations in parallel, possibly combining the results of one of the nodes. In the architecture shown, the ray tracing nodes 3610-3613 are communicatively coupled to a client-side ray tracing application 3630 via a gateway.

[0334] One of the drawbacks of a distributed architecture is the large amount of packetized data that must be transmitted between each of the ray tracing nodes 3610-3613. Both lossless and lossy compression techniques can be used to reduce the data transmitted between the ray tracing nodes 3610-3613.

[0335] To implement lossless compression, rather than sending packets filled with the results of a particular type of operation, data or commands are sent that allow the receiving node to reconstruct the results. For example, the light of the stochastically sampled region and the ambient occlusion (AO) operation do not necessarily require a direction. As a result, the transmitting node only sends a random seed, which the receiving node can then use to perform the random sampling. For example, if the scene is distributed throughout the nodes 3610-3612, to sample light 1 at points p1-p3, only the light ID and the origin need to be sent to the nodes 3610-3612. Each of these nodes may then independently sample the light probabilistically. The random seed may be generated by the receiving node. Similarly, at the hit point of the primary ray, the ambient occlusion (AO) and soft shadow sampling may be calculated at the nodes 3610-3612 without waiting for the origin of the successive frames. Furthermore, if it is known that a set of rays travel to the same point light source, an instruction identifying the light source may be sent to the receiving node that applies the light source to the set of rays. As another example, if there are N ambient occlusion rays transmitted to a single point, a command may be sent to generate N samples from this point.

[0336] Various additional techniques may be applied to the lossy compression. For example, a quantization factor may be utilized to quantize all coordinate values ​​associated with the BVH, primitives, and rays. Additionally, 32-bit floating point values ​​used for data such as BVH nodes and primitives may be converted to 8-bit integer values. In an exemplary implementation, ray packet boundaries are stored in full precision, but individual ray points P1-P3 are transmitted to these boundaries as index offsets. Similarly, multiple local coordinate systems may be generated that use 8-bit integer values ​​as local coordinates. The location of the origin of each of these local coordinate systems may be encoded using full precision (e.g., 32-bit floating point) values, effectively connecting the global and local coordinate systems.

[0337] Below is an example of lossless compression: Below is an example of a ray data format used internally in ray tracing programs: struct Ray { uint32 pixId; uint32 materialID; uint32 instanceID; uint64 primitiveID; uint32 geometryID; uint32 lightID; float origin[3]; float direction[3]; float t0; float t; float time; float normal[3]; / / Used for geometry intersections float u; float v; float wavelength; float phase; / / Interferometry float refractedOffset; / / Schlieren formula float amplitude; float weight; };

[0338] Instead of sending the raw data for every single generated node, this data can be compressed by grouping values ​​and creating absolute rays with applicable metadata if possible.

[0339] Bundling and Grouping Ray Data Flags can be used for common data or masks with modifiers. struct RayPacket { uint32 size; uint32 flags; list <ray>rays; } Example: RayPacket.rays = ray_1 to ray_256 [The origin is all shared]

[0340] All ray data is packed except that only a single origin is stored for every ray. RayPacket.flags is set to RAYPACKET_COMMON_ORIGIN. When a RayPacket is received and unpacked, multiple origins are written from a single origin value. [The origin is shared between only some rays]

[0341] All ray data is packed, except for rays that share an origin. For each group of unique shared origins, an operator is packed that identifies the operation (shared origin), stores the origin, and masks which rays share information. Such operations can be done on any value that is shared between nodes, e.g. material IDs, primitive IDs, origins, directions, normals, etc. struct RayOperation { uint8 operationID; void* value; uint64 mask; } [Absolute Ray Sending]

[0342] In many cases, ray data can be obtained at the receiver with minimal meta-information used to generate the ray data. A very common example is generating multiple secondary rays to stochastically sample an area. Instead of the transmitter generating secondary rays, sending them, and the receiver processing them, the transmitter can send commands to generate rays along with any dependency information, which are generated at the receiver. Rays need to be generated first by the transmitter, and when deciding which receiver to send them to, a ray can be generated and a random seed can be sent to regenerate the exact same ray.

[0343] For example, to sample hit points with 64 shadow rays sampling an area light source, all 64 rays intersect with the same area of ​​compute N4. A RayPacket with a common origin and normal is created. More data could be sent if we want the receiver to shade the resulting pixel contribution, but for this example we assume we only want to return if the ray hits another node data. A RayOperation is created to generate the shadow ray operation and is assigned the value of the lightID to be sampled and a random seed. When N4 receives the ray packet, it generates fully filled ray data by writing the shared origin data to all rays and setting the direction based on the lightID stochastically sampled with the random seed, generating the same rays that the original sender generated. When the results are returned, only the binary result per ray needs to be returned, and this binary result can be passed through a mask over the rays.

[0344] In this example, if we were to send the original 64 rays, we would have used 104 bytes x 64 rays = 6656 bytes. If the returning rays were also sent in raw form, this would also double to 13312 bytes. Using lossless compression, which only sends the ray generation operations with the common ray origin, normal, and seed and id, only 29 bytes are sent, and 8 bytes are returned for the intersected mask. This results in roughly a 360:1 compression rate of the data that needs to be sent over the network. This does not include the overhead of processing the message itself, which needs to be identified in some way, but that is left to the implementation. Other operations may be done to recalculate the ray origin and direction from the pixelID of the primary ray, and recalculate pixelD based on the raypacket range and many other possible implementations of value recalculation. Similar operations may be used for any single or group of rays sent, including shadows, reflections, refractions, ambient occlusion, intersections, volume intersections, shading, bounce reflections in path tracing, etc.

[0345] FIG. 37 shows further details of two ray tracing nodes 3710-3711 for compressing and decompressing ray tracing packets. Specifically, when the first ray tracing engine 3730 is ready to transmit data to the second ray tracing engine 3731, the ray compression circuit 3720 performs lossy and / or lossless compression of the ray tracing data as described herein (e.g., converting 32-bit values ​​to 8-bit values, using raw data instead of instructions to reconstruct the data, etc.). The compressed ray packet 3701 is transmitted from the network interface 3725 to the network interface 3726 over a local network (e.g., a 10 Gb / s, 100 Gb / s Ethernet network). The ray decompression circuit then decompresses the ray packet as appropriate. For example, the ray decompression circuit may execute commands to reconstruct the ray tracing data (e.g., using a random seed to perform random sampling for lighting calculations). The ray tracing engine 3731 then performs ray tracing calculations using the received data.

[0346] In the reverse direction, ray compression circuitry 3741 compresses the ray data, the network interface 3726 transmits the compressed ray data over the network (e.g., using techniques described herein), the ray decompression circuitry 3740 decompresses the ray data as necessary, and the ray tracing engine 3730 uses the data for ray tracing calculations. Although shown as separate units in Figure 37, the ray decompression circuits 3740-3741 may be integrated into the ray tracing engines 3730-3731, respectively. For example, to the extent that the compressed ray data includes commands to reconstruct the ray data, these commands may be executed by the respective ray tracing engines 3730-3731.

[0347] As shown in Fig. 38, the ray compression circuit 3720 may include a lossy compression circuit 3801 for performing the lossy compression techniques described herein (e.g., converting 32-bit floating point coordinates to 8-bit integer coordinates) and a lossless compression circuit 3803 for performing the lossless compression techniques (e.g., transmitting commands and data to enable the ray recompression circuit 3821 to reconstruct the data). The ray decompression circuit 3721 includes a lossy decompression circuit 3802 and a lossless decompression circuit 3804 for performing lossless decompression.

[0348] Another exemplary method is illustrated in Figure 39. The method may be implemented in a ray tracing architecture or other architectures described herein, but is not limited to any particular architecture.

[0349] At 3900, ray data is received from a first ray tracing node to be transmitted to a second ray tracing node. At 3901, a lossy compression circuit performs lossy compression on the first ray tracing data, and at 3902, a lossless compression circuit performs lossless compression on the second ray tracing data. At 3903, the compressed ray tracing data is transmitted to the second ray tracing node. At 3904, a lossy / lossless decompression circuit performs lossy / lossless decompression of the ray tracing data, and at 3905, the second ray tracing node performs ray tracing operations on the decompressed data. [Hardware-accelerated hybrid ray tracing graphics processor]

[0350] A hybrid rendering pipeline with rasterization in the graphics core 3130 and ray tracing computation in the ray tracing core 3150, graphics core 3130, and / or CPU core 3199 is presented next. For example, rasterization and depth testing may be performed in the graphics core 3130 instead of the primary ray casting stage. The ray tracing core 3150 may then generate secondary rays for reflection, refraction, and shadowing of rays. Furthermore, certain areas of the scene may be selected (e.g., based on material property thresholds such as high reflectance levels) for which the ray tracing core 3150 will perform ray tracing computations, while other areas of the scene will be rendered with rasterization in the graphics core 3130. This hybrid implementation may be used for real-time ray tracing applications where latency is a critical issue.

[0351] The ray traversal architecture described below may perform programmable shading and control of ray traversal using, for example, existing single instruction multiple data (SIMD) and / or single instruction multiple thread (SIMT) graphics processors, while accelerating key functions such as BVH traversal and / or intersection using dedicated hardware. SIMD occupancy of incoherent paths may be improved by regrouping generated shaders at specific points during traversal and before shading. This is achieved using dedicated hardware that dynamically sorts shaders on-chip. Recursion is managed by splitting functions into continuations that execute when the continuations return and regroup before execution for improved SIMD occupancy.

[0352] Programmable control of ray traversal / intersection is achieved by decomposing traversal functionality into inner traversal, which may be implemented as fixed-function hardware, and outer traversal, which runs on the GPU processor and allows programmable control by user-defined traversal shaders. The cost of transferring traversal contexts between hardware and software is reduced by conservatively pruning the inner traversal state when transitioning between inner and outer traversal.

[0353] Programmable control of ray tracing can be represented by different shader types, listed below in Table A. There can be multiple shaders per type. For example, each material can have a different hit shader. Table A [Table 1]

[0354] Recursive ray tracing can be initiated by an API function that instructs the graphics processor to invoke a primary set of shaders or an intersection circuit that can generate ray-scene intersections for the primary rays. This then generates other shaders, such as traversal shaders, hit shaders, or miss shaders. A shader that generates child shaders can also receive return values ​​from the child shaders. A callable shader is a generic function that can be generated directly by another shader and can also return these values ​​to the calling shader.

[0355] 40 illustrates a graphics processing architecture including shader execution circuitry 4000 and fixed function circuitry 4010. The general purpose execution hardware subsystem includes multiple single instruction multiple data (SIMD) and / or single instruction multiple thread (SIMT) cores / execution units (EUs) 4001 (i.e., each core may include multiple execution units), one or more samplers 4002, and a level 1 (L1) cache 4003 or other form of local memory. The fixed function hardware subsystem 4010 includes a message unit 4004, a scheduler 4007, a ray-to-BVH traversal / intersection circuitry 4005, a sorting circuit 4008, and a local L1 cache 4006.

[0356] At operation time, the primary dispatcher 4009 dispatches a set of primary rays to the scheduler 4007, which schedules work to shaders to be executed by the SIMD / SIMT core / EU 4001. The SIMD core / EU 4001 may be the ray tracing core 3150 and / or the graphics core 3130 described above. Execution of the primary shader generates additional work to be executed (e.g., by one or more child shaders and / or fixed function hardware). The message unit 4004 distributes the work generated by the SIMD core / EU 4001 to the scheduler 4007, accessing the free stack pool, the sorting circuit 4008, or the ray-BVH intersection circuit 4005 as needed. If the additional work is not sent to the scheduler 4007, the additional work is scheduled for processing by the SIMD / SIMT core / EU 4001. Prior to scheduling, the sorting circuit 4008 may sort the rays into groups or bins as described herein (e.g., grouping rays with similar characteristics). The ray-BVH intersection circuit 4005 performs intersection testing of the rays with the BVH volumes. For example, the ray-BVH intersection circuit 4005 may compare ray coordinates with the BVHs at each level to identify volumes that the rays intersect.

[0357] Shaders may be referenced using a shader record, a user-allocated structure that contains a pointer to an entry function, vendor-specific metadata, and global arguments for the shader to be executed by the SIMD core / EU 4001. Each execution instance of a shader is associated with a call stack that may be used to store arguments passed between parent and child shaders. The call stack may also store a reference to a continuing function that is executed when the call returns.

[0358] Figure 41 shows an example of a set of allocation stacks 4101 including a primary shader stack, a hit shader stack, a traversal shader stack, a continuation function stack, and a ray-BVH intersection stack (which may be implemented by fixed function hardware 4010 as described). A new shader invocation may implement a new stack from a free stack pool 4102. Call stacks, e.g., stacks consisting of the set of allocated stacks, may be cached in local L1 caches 4003, 4006 to reduce access latency.

[0359] There may be a finite number of call stacks, each of which is allocated a fixed maximum size "Sstack" in a contiguous region of memory. Thus, the base address of a stack may be calculated directly from the stack index (SID) as Base Address = SID x Sstack. Stack IDs may be allocated and deallocated by the scheduler 4007 when scheduling work to a SIMD core / EU 4001.

[0360] The primary dispatcher 4009 may include a graphics processor command processor that dispatches primary shaders in response to dispatch commands from a host (e.g., a CPU). The scheduler 4007 may receive these dispatch requests and launches the primary shaders on SIMD processor threads if it can allocate stack IDs per SIMD lane. The stack IDs may be allocated from a free stack pool 4102 that is initialized at the beginning of a dispatch command.

[0361] An executing shader can spawn child shaders by sending a spawn message to the messaging unit 4004. This command contains the stack ID associated with the shader and also contains a pointer to a child shader record for each active SIMD lane. A parent shader can only issue this message once for an active lane. After sending spawn messages for all relevant lanes, the parent shader can exit.

[0362] Shaders executing on SIMD cores / EUs 4001 can also generate fixed function tasks such as ray-BVH intersection using generate messages with shader record pointers reserved for fixed function hardware. As mentioned above, messaging unit 4004 sends generated ray-BVH intersection work to fixed function ray-BVH intersection circuit 4005 and also sends callable shaders directly to sorting circuit 4008. Sorting circuit 4008 can group shaders by shader record pointer to obtain SIMD batches with similar characteristics. Thus, stack IDs from different parent shaders can be grouped into the same batch by sorting circuit 4008. Sorting circuit 4008 sends grouped batches to scheduler 4007, which accesses shader records from graphics memory 2511 or last level cache (LLC) 4020 and launches shaders on processor threads.

[0363] Continuations may be treated as callable shaders and may also be referenced by a shader record. When a child shader is created and returns a value to a parent shader, a pointer to the continuation shader record may be pushed onto the call stack 4101. When the child shader returns, the continuation shader record may be popped from the call stack 4101 and a continuation shader may be created. Optionally, the created continuation may go through a sort unit similar to a callable shader and run on a processor thread.

[0364] As shown in FIG. 42, the sorting circuit 4008 groups the generated tasks by shader record pointers 4201A, 4201B, 4201n to create SIMD batches for shading. The stack IDs or context IDs of the sorted batches may be grouped from different dispatches and different input SIMD lanes. The grouping circuit 4210 may perform the sorting using a content addressable memory (CAM) structure 4201 that includes multiple entries, each entry identified by a tag 4201. As previously mentioned, the tag 4201 may be a corresponding shader record pointer 4201A, 4201B, 4201n. The CAM structure 4201 may store a limited number of tags (e.g., 32, 64, 128, etc.), each associated with an incomplete SIMD batch corresponding to a shader record pointer.

[0365] For an incoming generate command, each SIMD lane has a corresponding stack ID (shown as 16 context IDs 0-15 in each CAM entry) and a shader record pointer 4201A,B,...n (which serves as a tag value). The grouping circuit 4210 may compare the shader record pointer to tags 4201 in the CAM structure 4201 for each lane to find a matching batch. If a matching batch is found, the stack ID / context ID may be added to the batch. If not, a new entry with a new shader record pointer tag may be created, possibly evicting the old entry with the incomplete batch.

[0366] A running shader can deallocate its call stack when it becomes empty by sending a deallocate message to the message unit, which is relayed to the scheduler which returns the stack id / context id of the active SIMD lane to the free pool.

[0367] A hybrid approach for ray traversal computation is presented using a combination of fixed-function and software ray traversal. As a result, the hybrid approach provides the flexibility of software traversal while maintaining the efficiency of fixed-function traversal. Figure 43 shows an acceleration structure that can be used for hybrid traversal. The hybrid traversal is a two-level tree with a single top-level BVH 4300 and several lower-level BVHs 4301 and 4302. Graphical elements are shown on the right, showing an inner traversal path 4303, an outer traversal path 4304, a traversal node 4305, a leaf node with a triangle 4306, and a leaf node with a custom primitive 4307.

[0368] Leaf nodes 4306 with triangles in the higher level BVH 4300 can reference triangles, custom primitive intersection shader records, or traversal shader records. Leaf nodes 4306 with triangles in the lower level BVHs 4301-4302 can only reference triangle and custom primitive intersection shader records. The type of reference is encoded in the leaf node 4306. Internal traversal 4303 refers to traversals within each BVH 4300-4302. Internal traversal operations include ray-BVH intersection computations, while traversals throughout the BVH structures 4300-4302 are known as external traversals. Internal traversal operations may be implemented efficiently in fixed function hardware, and external traversal operations may be performed with acceptable performance using programmable shaders. As a result, internal traversal operations may be performed using fixed function circuitry 4010, and external traversal operations may be performed using shader execution circuitry 4000, which includes a SIMD / SIMT core / EU 4001, to execute programmable shaders.

[0369] Note that for simplicity, SIMD / SIMT core / EU 4001 may be referred to herein simply as a "core," "SIMD core," "EU," or "SIMD processor." Similarly, ray-to-BVH traversal / intersection circuitry 4005 may be referred to simply as a "traversal unit," "traversal / intersection unit," or "traversal / intersection circuitry." Even when alternative terminology is used, the particular names used to designate the respective circuitry / logic do not change the underlying functions that the circuitry / logic performs as described herein.

[0370] Further, although illustrated as a single component in FIG. 40 for purposes of explanation, the traversal / intersection unit 4005 may include a separate traversal unit and a separate intersection unit, each of which may be implemented in circuitry and / or logic as described herein.

[0371] When a ray intersects a traversal node during an inner traversal, a traversal shader may be generated. The sorting circuit 4008 may group these shaders by shader record pointers 4201A,B,...n and create SIMD batches that are launched by the scheduler 4007 for SIMD execution on the graphics SIMD core / EU 4001. The traversal shader may modify the traversal in several ways, allowing a wide range of applications. For example, the traversal shader may select a BVH at a coarse level of detail (LOD) or transform the ray to allow rigid body transformations. The traversal shader may then generate an inner traversal for the selected BVH.

[0372] Inner traversals compute ray-BVH intersections by traversing the BVH and computing ray-box and ray-triangle intersections. Inner traversals are generated in the same manner as shaders by sending messages to a messaging circuit 4004. The messaging circuit 4004 relays the corresponding generated messages to a ray-BVH intersection circuit 4005, which computes the ray-BVH intersections.

[0373] The stack for the inner traversal may be stored locally in the fixed function circuitry 4010 (e.g., in the L1 cache 4006). When a ray intersects with a leaf node corresponding to a traversal or intersection shader, the inner traversal may be terminated and the inner stack may be truncated. The truncated stack, along with pointers to the ray and BVH, may be written to memory at a location specified by the calling shader, and then the corresponding traversal or intersection shader may be generated. If the ray intersects with any triangle during the inner traversal, the corresponding hit information may be provided as an input argument to these shaders as shown in the code below. These generated shaders may be grouped by the sorting circuitry 4008 to create a SIMD batch for execution. struct HitInfo { float barycentrics[2]; float tmax; bool innerTravComplete; uint primID; uint geomID; ShaderRecord* leafShaderRecord; }

[0374] By pruning the inner traversal stack, the cost of spilling the inner traversal stack to memory is reduced. To prune the stack to a small number of entries, i.e. a 42-bit restart trail and a 6-bit depth value at the top of the stack, the approach described in "Restart Trail for Stackless BVH Traversal" (High Performance Graphics (2010), pp. 107-111) can be applied. The restart trail indicates the branches already taken inside the BVH, and the depth value indicates the depth of the traversal corresponding to the last stack entry. This is enough information to resume the inner traversal later.

[0375] The inner traversal is complete when the inner stack is empty and there are no more BVH nodes to test, in which case an outer stack handler is spawned which pops the top of the outer stack and resumes the traversal if the outer stack is not empty.

[0376] The external traversal may execute a main traversal state machine, which may be implemented in program code executed by the shader execution circuitry 4000. It may generate internal traversal queries under the following conditions: (1) when a new ray is generated by a hit shader or a primary shader, (2) when a traversal shader selects a BVH for traversal, and (3) when an external stack handler resumes an internal traversal of a BVH.

[0377] As shown in Figure 44, before an inner traversal is created, space is allocated in the call stack 4405 of the fixed function circuit 4010 to store a truncated inner stack 4410. Offsets 4403-4404 to the top of the call stack and inner stack are maintained in a traversal state 4400 which is also stored in memory 2511. The traversal state 4400 includes rays in world space 4401 and object space 4402, as well as hit information for the nearest intersecting primitive.

[0378] The traversal shaders, intersection shaders, and external stack handlers are all generated by the ray-to-BVH intersection circuit 4005. The traversal shaders allocate on the call stack 4405 before starting a new internal traversal of the second level BVH. The external stack handler is the shader responsible for updating the hit information and resuming any pending internal traversal tasks. The external stack handler is also responsible for generating a hit shader or a miss shader when the traversal is complete. A traversal is complete when there are no pending internal traversal queries to generate. When the traversal is complete and an intersection is found, a hit shader is generated, otherwise a miss shader is generated.

[0379] Although the hybrid traversal scheme described above uses a two-level BVH hierarchy, any number of BVH levels may be implemented, with corresponding changes in the outer traversal implementation.

[0380] Additionally, although the fixed function circuitry 4010 is described above as performing ray-to-BVH intersection, other system components may also be implemented in the fixed function circuitry. For example, the external stack handlers described above may potentially be internal (user invisible) shaders that may be implemented in the fixed function BVH traversal / intersection circuitry 4005. This implementation may be used to reduce the number of dispatch shader stages and round trips between the fixed function intersection hardware 4005 and the processor.

[0381] The examples described herein enable programmable shading and ray traversal control with user-defined functions that can run with high SIMD efficiency on existing and future GPU processors. Programmable control of ray traversal enables several key features, such as procedural instancing, probability level detail selection, custom primitive intersection, and lazy BVH updates.

[0382] A programmable multiple instruction multiple data (MIMD) ray tracing architecture that supports speculative execution of hit and intersection shaders is also provided. In particular, the architecture focuses on reducing the scheduling and communication overhead between the programmable SIMD / SIMT core / execution unit 4001 described above in connection with FIG. 40 and the fixed function MIMD traversal / intersection unit 4005 in the hybrid ray tracing architecture. Described below are multiple speculative execution schemes for hit and intersection shaders that can be dispatched in a single batch from the traversal hardware, avoiding multiple traversal and shading round trips. Dedicated circuitry for implementing these techniques may be used.

[0383] Embodiments of the present invention are particularly beneficial in use cases where execution of multiple hit or intersection shaders is desired from a ray traversal query that would impose significant overhead when implemented without dedicated hardware support. These include, but are not limited to, nearest k hit queries (invoking the hit shader of the kth closest intersection) and multiple programmable intersection shaders.

[0384] The techniques described herein may be implemented as an extension to the architecture illustrated in Figure 40 (and described in conjunction with Figures 40-44). In particular, the present embodiment of the invention builds on this architecture with enhancements to improve performance for the use cases described above.

[0385] The performance limitation of the hybrid ray tracing traversal architecture is the overhead of launching traversal queries from the execution units and invoking programmable shaders from the ray tracing hardware. If multiple hit or intersection shaders are invoked during the traversal of the same ray, this overhead generates "execution round trips" between the programmable cores 4001 and the traversal / intersection unit 4005. This also puts additional pressure on the sort unit 4008, which must extract SIMD / SIMT coherence from the individual shader invocations.

[0386] Some aspects of ray tracing require programmable control that can be expressed across different shader types listed in Table A above (i.e., Primary, Hit, Any Hit, Miss, Intersection, Traversal, and Callable). There can be multiple shaders of each type. For example, each material can have a different hit shader. Some of these shader types are defined in the current Microsoft® Ray Tracing API.

[0387] Briefly summarized, recursive ray tracing begins with an API function that instructs the GPU to invoke a set of primary shaders (implemented by hardware and / or software) that can generate ray-scene intersections for a primary ray. This in turn may generate other shaders, such as traversal shaders, hit shaders, or miss shaders. A shader that generates child shaders can also receive return values ​​from the child shaders. Callable shaders are generic functions that can be directly generated by another shader, and can also return these values ​​to the calling shader.

[0388] Ray traversal computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH). Recent research has shown that the efficiency of computing ray-scene intersections can be improved by an order of magnitude or more using techniques that are better suited for fixed-function hardware, such as reduced-precision arithmetic, BVH compression, per-ray state machines, dedicated intersection pipelines, and custom caches.

[0389] The architecture shown in Figure 40 includes a system in which an array of SIMD / SIMT cores / execution units 4001 interact with a fixed function ray tracing / intersection unit 4005 to perform programmable ray tracing. Programmable shaders are mapped to SIMD / SIMT threads on the execution units / cores 4001, where SIMD / SIMT utilization, execution, and data coherence are important for optimal performance. Ray queries often break coherence for a variety of reasons, such as: Traversal divergence: The duration of BVH traversal varies greatly between rays, which is good for asynchronous ray processing. Execution divergence: Rays generated from different lanes of the same SIMD / SIMT thread may result in different shader invocations. Data access divergence: For example, rays hitting different surfaces and primitives sample different BVH nodes, shaders access different textures, and a variety of other scenarios can cause data access divergence.

[0390] The SIMD / SIMT core / execution unit 4001 may be a variation of a core / execution unit described herein, including the graphics cores 415A-415B, the shader cores 1355A-N, the graphics core 3130, the graphics execution unit 608, the execution units 852A-B, or any other core / execution unit described herein. The SIMD / SIMT core / execution unit 4001 may be used in place of the graphics cores 415A-415B, the shader cores 1355A-N, the graphics core 3130, the graphics execution unit 608, the execution units 852A-B, or any other core / execution unit described herein. Thus, disclosure of any feature in combination with graphics cores 415A-415B, shader cores 1355A-N, graphics core 3130, graphics execution unit 608, execution units 852A-B, or any other core / execution unit described herein also discloses a corresponding combination with SIMD / SIMT core / execution unit 4001 of FIG. 40, but is not limited to such.

[0391] The fixed-function ray tracing / intersection unit 4005 may overcome the first two challenges by processing each ray individually and out of order. However, this breaks the SIMD / SIMT groups. The sort unit 4008 is therefore responsible for forming new coherent SIMD / SIMT groups of shader invocations that are then dispatched to the execution units again.

[0392] It is easy to see the advantages of such an architecture compared to a purely software-based ray tracing implementation directly on a SIMD / SIMT processor. However, there is overhead associated with messaging between the SIMD / SIMT core / execution units 4001 (sometimes referred to herein simply as SIMD / SIMT processors or cores / EUs) and the MIMD traversal / intersection unit 4005. Furthermore, the sort unit 4008 may not extract full SIMD / SIMT utilization from incoherent shader calls.

[0393] Use cases may be identified where shader invocations may be particularly frequent during traversal. Enhancements to the hybrid MIMD ray tracing processor are described to significantly reduce communication overhead between the cores / EUs 4001 and the traversal / intersection unit 4005. This may be particularly beneficial when finding the k-th nearest intersection and when implementing programmable intersection shaders. However, it should be noted that the techniques described herein are not limited to any particular processing scenario.

[0394] A summary of the high level cost of ray tracing context switches between the Core / EU 4001 and the fixed function Traversal / Intersection Unit 4005 is provided below. The majority of the performance overhead is caused by these two context switches every time a shader invocation is required during a single ray traversal.

[0395] Each SIMD / SIMT lane that launches a ray generates a generate message to the traversal / intersection unit 4005 associated with the BVH for traversal. The data (ray traversal context) is relayed to the traversal / intersection unit 4005 via the generate message and (cache) memory. When the traversal / intersection unit 4005 is ready to assign a new hardware thread to the generate message, it loads the traversal state and performs the traversal on the BVH. There is also a setup cost that needs to be performed before the first traversal stage on the BVH.

[0396] Figure 45 shows the operational flow of the programmable ray tracing pipeline. The shaded elements, including traversal 4502 and intersection 4503, may be implemented in fixed function circuits, while the remaining elements may be implemented in programmable cores / execution units.

[0397] The primary ray shader 4501 sends work to a traversal circuit at 4502 which traverses the current ray through the BVH (or other acceleration structure). When a leaf node is reached, the traversal circuit calls an intersection circuit at 4503 which, upon identifying a ray-triangle intersection, invokes an any hit shader at 4504 (which may provide results back to the traversal circuit, as shown).

[0398] Alternatively, the traversal may terminate before reaching a leaf node and calling the closest hit shader at 4507 (if a hit is recorded) or the miss shader at 4506 (in the event of a miss).

[0399] The intersection shader may be invoked when the traversal circuitry reaches a custom primitive leaf node, as shown at 4505. The custom primitive may be any non-triangular primitive, such as a polygon or polyhedron (e.g., a pyramid, voxel, hexahedron, wedge, pyramid, or other "unstructured" volume). The intersection shader 4505 identifies any intersections between the ray and the custom primitive to the any hit shader 4504, which implements the any hit processing.

[0400] When the hardware traversal 4502 reaches a programmable stage, the traversal / intersection unit 4005 may generate a shader dispatch message for the associated shader 4505-4507, corresponding to a single SIMD lane of the execution unit used to execute the shader. Because dispatches occur in any order of rays, and they are divergent in the called program, the sort unit 4008 may accumulate multiple dispatch calls to extract a coherent SIMD batch. The updated traversal state and optional shader arguments may be written to memory 2511 by the traversal / intersection unit 4005.

[0401] In the k-th closest intersection problem, the closest hit shader 4507 is executed for the first k intersections. In a traditional approach, this means finding the closest intersection, invoking the hit shader, and terminating the ray traversal when a new ray is generated from the hit shader to find the next closest intersection (the ray origin is offset so that the same intersection does not occur again). It is easy to see that this implementation requires the generation of k rays for a single ray. An alternative implementation works with an any-hit shader 4504 being called for every intersection, and maintains a global list of closest intersections using an insertion sort operation. The main problem with this approach is that there is no upper limit on the any-hit shader invocations.

[0402] As mentioned above, the intersection shader 4505 may be invoked on non-triangle (custom) primitives. Depending on the outcome of the intersection test and the traversal state (pending node and primitive intersections), traversal of the same ray may continue after execution of the intersection shader 4505. Thus, finding the closest hit may require multiple round trips to the execution unit.

[0403] There may also be a focus on reducing SIMD-MIMD context switches for intersection shaders 4505 and hit shaders 4504, 4507 through modifications to the traversal hardware and shader scheduling model. First, the ray traversal circuitry 4005 defers shader invocations by accumulating multiple potential invocations and dispatching them in larger batches. Additionally, certain invocations that are found to be unnecessary may be culled at this stage. Additionally, the shader scheduler 4007 may aggregate multiple shader invocations from the same traversal context into a single SIMD batch, which results in a single ray generation message. In one exemplary implementation, the traversal hardware 4005 parks the traversal thread and waits for the results of multiple shader invocations. This mode of operation is referred to herein as "speculative" shader execution because it allows for the dispatch of multiple shaders, some of which may not be called when using sequential invocations.

[0404] FIG. 46A shows an example where a traversal operation encounters multiple custom primitives 4650 in a subtree, and FIG. 46B shows how this can be resolved in three intersection dispatch cycles C1-C3. In particular, scheduler 4007 may require three cycles to present work to SIMD processor 4001, and traversal circuitry 4005 requires three cycles to provide results to sort unit 4008. The traversal state 4601 required by traversal circuitry 4005 may be stored in a memory, such as a local cache (e.g., an L1 cache and / or an L2 cache). [A. Deferred ray tracing shader invocation]

[0405] The manner in which the hardware traversal state 4601 is managed can also be modified to allow multiple potential intersection or hit invocations to be accumulated in the list. At a given time during the traversal, each entry in the list can be used to generate a shader invocation. For example, the kth closest intersection points can be accumulated in the traversal hardware 4005 and / or in the traversal state 4601 in memory, and when the traversal is complete, a hit shader can be invoked for each element. In the case of a hit shader, multiple potential intersections can be accumulated for a subtree in the BVH.

[0406] For the k-nearest use case, the advantage of this approach is that all hit shaders are called from the same traversal thread during a single traversal operation on the traversal circuitry 4005, instead of k-1 round trips to the SIMD core / EU 4001 and k-1 new ray generation messages. A potential implementation challenge is that it is not easy to guarantee the order of execution of hit shaders (a standard "round trip" approach guarantees that the hit shader of the closest intersection is executed first, etc.). This can be addressed by either synchronization of hit shaders or relaxing the ordering.

[0407] For the intersection shader use case, the traversal circuitry 4005 does not know in advance whether a given shader will return a positive intersection test. However, multiple intersection shaders can be speculatively executed, and if at least one returns a positive hit result, they are merged into a global nearest neighbor hit. A particular implementation needs to find an optimal number of delayed intersection tests to reduce the number of dispatch calls, but avoid calling too many redundant intersection shaders. [B. Aggregated Shader Invocation from the Traversal Circuitry]

[0408] When dispatching multiple shaders from the same ray generated on the traversal circuitry 4005, a branch in the flow of the ray traversal algorithm can be created. This can be problematic for intersection shaders because the remainder of the BVH traversal depends on the results of all of the dispatched intersection tests. This means that synchronous operations must wait for the results of shader invocations, which can be difficult for asynchronous hardware.

[0409] The two points for merging the results of shader calls can be the SIMD processor 4001 and the traversal circuitry 4005. With respect to the SIMD processor 4001, multiple shaders can synchronize and aggregate their results using a standard programming model. One relatively simple way to do this is to use global atomics and aggregate results in a shared data structure in memory where the intersection results of multiple shaders can be stored. The last shader can then resolve the data structure and call back to the traversal circuitry 4005, thereby continuing the traversal.

[0410] A more efficient approach may also be implemented that restricts execution of multiple shader invocations to lanes of the same SIMD thread on the SIMD processor 4001. The intersection tests are then reduced locally using SIMD / SIMT reduction operations (rather than relying on global atomics). This implementation may rely on new circuitry in the sort unit 4008 to ensure that small batches of shader invocations stay in the same SIMD batch.

[0411] Execution of the traversal thread may further be suspended on the traversal circuitry 4005. With a traditional execution model, if a shader is dispatched during traversal, the traversal thread is terminated and the ray traversal state is saved to memory, allowing execution units 4001 to process the shader while other ray generation commands are executed. If the traversal thread is simply suspended, the traversal state can wait for each shader result separately without having to be stored. This implementation may include circuitry to avoid deadlocks and provide sufficient hardware utilization.

[0412] 47 and 48 show an example of a delay model for invoking a single shader invocation on a SIMD core / execution unit 4001 with three shaders 4701. When pooled, all intersection tests are evaluated within the same SIMD / SIMT group. As a result, nearest neighbor intersections can also be calculated on the programmable core / execution unit 4001.

[0413] As described above, all or part of the shader aggregation and / or deferral may be performed by the traversal / intersection circuit 4005 and / or the core / EU scheduler 4007. Figure 47 shows how the shader delay / aggregator circuit 4706 in the scheduler 4007 can delay scheduling of shaders associated with a particular SIMD / SIMT thread / lane until a particular trigger event occurs. Upon detecting the trigger event, the scheduler 4007 dispatches multiple aggregated shaders in a single SIMD / SIMT batch to the core / EU 4001.

[0414] Figure 48 shows how a shader delay / aggregator circuit 4805 in the traversal / intersection circuit 4005 can delay scheduling of shaders associated with a particular SIMD thread / lane until a particular trigger event occurs. Upon detecting the trigger event, the traversal / intersection circuit 4005 provides the aggregate shaders to the sort unit 4008 in a single SIMD / SIMT batch.

[0415] However, it should be noted that the shader deferral and aggregation techniques may be implemented within various other components, such as sort unit 4008, or may be distributed across multiple components. For example, traversal / intersection circuitry 4005 may perform a first set of shader-intensive operations, and scheduler 4007 may perform a second set of shader-intensive operations, ensuring that shaders of a SIMD thread are efficiently scheduled on cores / EUs 4001.

[0416] The "trigger event" that causes a core / EU to dispatch an aggregate shader may be a processing event, such as a particular number of accumulated shaders, or a minimum latency associated with a particular thread. Alternatively, or in addition, the trigger event may be a temporal event, such as a particular period of time from the delay of a first shader, or a particular number of processor cycles. Other variables, such as the current workload on the core / EU 4001 and traversal / intersection unit 4005, may also be evaluated by the scheduler 4007 to determine when to dispatch a SIMD / SIMT batch of shaders.

[0417] Different embodiments of the invention may be implemented using different combinations of the above approaches, depending on the particular system architecture used and the requirements of the application. [Raytracing instructions]

[0418] The ray tracing instructions described below are included in an instruction set architecture (ISA) that supports the CPU 3199 and / or GPU 3105. When executed by the CPU, the single instruction multiple data (SIMD) instructions may utilize vector / packed source and destination registers to perform the described operations and may be decoded and executed by the CPU core. When executed by the GPU 3105, the instructions may be executed by the graphics core 3130. For example, any of the execution units (EUs) 4001 described above may execute the instructions. Alternatively, or in addition, the instructions may be executed by execution circuitry on the ray tracing core 3150 and / or the tensor core 3140.

[0419] Figure 49 shows an architecture for executing ray tracing instructions described below. The illustrated architecture may be integrated in one or more of the cores 3130, 3140, 3150 described above (see, for example, Figure 31 and associated text) or may be included in a different processor architecture.

[0420] During operation, the instruction fetch unit 4903 fetches the ray tracing instructions 4900 from the memory 3198 and the decoder 4995 decodes the instructions. In one implementation, the decoder 4995 decodes the instructions and generates executable operations (e.g., micro-operations or uops in a microcoded core). Alternatively, some or all of the ray tracing instructions 4900 may be executed without decoding, and thus the decoder 4904 is not required.

[0421] In either implementation, scheduler / dispatcher 4905 schedules and dispatches instructions (or operations) across a set of functional units (FUs) 4910-4912. The illustrated implementation includes a vector FU 4910 for executing single instruction, multiple data (SIMD) instructions that operate simultaneously on multiple packed data elements stored in vector registers 4915, and a scalar FU 4911 for operating on scalar values ​​stored in one or more scalar registers 4916. An optional ray tracing FU 4912 may operate on packed data values ​​stored in vector registers 4915 and / or scalar values ​​stored in scalar registers 4916. In implementations without a dedicated FU 4912, the vector FU 4910 and possibly the scalar FU 4911 may execute ray tracing instructions, described below.

[0422] The various FUs 4910-4912 access ray tracing data 4902 (e.g., traversal / intersection data) necessary to execute the ray tracing instructions 4900 from vector registers 4915, scalar registers 4916, and / or a local cache subsystem 4908 (e.g., an L1 cache). The FUs 4910-4912 may also perform accesses to memory 3198 via load and store operations, and the cache subsystem 4908 may operate independently to cache data locally.

[0423] Ray tracing instructions can be used to improve the performance of ray traversal / intersection and BVH builds, but they may also be applicable in other areas, such as high performance computing (HPC) and general purpose GPU (GPGPU) implementations.

[0424] In the following description, the term doubleword may be abbreviated as dw and unsigned byte may be abbreviated as ub. Additionally, the source and destination registers referenced below (e.g., src0, src1, dest, etc.) may refer to vector registers 4915, or in some cases, a combination of vector registers 4915 and scalar registers 4916. Typically, vector registers 4915 are used when a source or destination value used by an instruction includes packed data elements (e.g., the source or destination stores N data elements). Other values ​​may use scalar registers 4916 or vector registers 4915. [Dequantization]

[0425] An example of a dequantize instruction "dequantizes" a previously quantized value. For purposes of illustration, in a ray tracing implementation, a particular BVH subtree may be quantized to reduce storage and bandwidth requirements. The dequantize instruction may take the form dequantize dest src0 src1 src2, where source register src0 stores N unsigned bytes, source register src1 stores one unsigned byte, source register src2 stores one floating point value, and destination register dest stores N floating point values. All of these registers may be vector registers 4915. Alternatively, src0 and dest may be vector registers 4915 and src1 and src2 may be scalar registers 4916.

[0426] The following code sequence defines one particular implementation of the inverse quantization instruction. for (int i = 0; i < SIMD_WIDTH) { if (execMask[i]) { dst[i] = src2[i] + ldexp(convert_to_float(src0[i]),src1); } } In this example, ldexp multiplies a double-precision floating-point value by the specified power of 2 (that is, ldexp(x, exp) = x * 2 exp In the code above, if the execution mask value (execMask[i]) associated with the current SIMD data element is set to 1, then the SIMD data element at position i in src0 is converted to a floating-point value and multiplied by 2 src1 value ) and this value is added to the corresponding SIMD data element in src2. [Select Min or Max]

[0427] The selective min or max instruction may perform either a min or max operation (i.e., return the minimum or maximum of a set of values) per lane, as indicated by a bit in a bit mask. The bit mask may utilize a vector register 4915, a scalar register 4916, or a separate set of mask registers (not shown). The following code sequence defines one particular implementation of the min / max instruction, sel_min_max dest src0 src1 src2, where src0 stores N doublewords, src1 stores N doublewords, src2 stores one doubleword, and the destination register stores N doublewords.

[0428] The following code sequence defines one particular implementation of the selective min / max instruction. for (int i = 0; i < SIMD_WIDTH) { if (execMask[i]) { dst[i] = (1 << i) & src2 ? min(src0[i],src1[i]) : max(src0[i],src1[i]); } } In this example, the value of (1 < < i) & src2 (1 shifted left by i and ANDed with src2) is used to select either the minimum of the i-th data element in src0 and src1, or the maximum of the i-th data element in src0 and src1. This operation is performed for the i-th data element only if the execution mask value (execMask[i]) associated with the current SIMD data element is set to 1. [Shuffle index command]

[0429] The shuffle index instruction can copy any set of input lanes to the output lanes. For a SIMD width of 32, this instruction can run at a lower throughput. This instruction is shuffle_index dest src0 src1<optional flag> where src0 contains N doublewords, src1 contains N unsigned bytes (i.e. index values), and dest contains N doublewords.

[0430] The following code sequence defines one particular implementation of the shuffle index instruction. for (int i = 0; i < SIMD_WIDTH) { uint8_t srcLane = src1.index[i]; if (execMask[i]) { bool invalidLane = srcLane < 0 || srcLane >= SIMD_WIDTH || !execMask[srcLaneMod]; if (FLAG) { invalidLane |= flag[srcLaneMod]; } if (invalidLane) { dst[i] = src0[i]; } else { dst[i] = src0[srcLane]; } } }

[0431] In the code above, the index in src1 identifies the current lane. If the i-th value in the execution mask is set to 1, a check is performed to ensure that the source lane is in the range 0 to SIMD width. If so, a flag is set (srcLaneMod) and data element i of the destination is set equal to data element i of src0. If the lane is in range (i.e., valid), the index value from src1 (srcLane0) is used as the index into src0 (dst[i] = src0[srcLane]). [Immediate Shuffle Up / Dn / XOR Instructions]

[0432] The immediate shuffle instruction may shuffle the input data elements / lanes based on an immediate value of the instruction. The immediate value may specify to shift the input lanes by 1, 2, 4, 8, or 16 positions based on the value of the immediate value. Optionally, an additional scalar source register may be specified as a fill value. If the source lane index is invalid, the fill value (if provided) is stored in the data element position in the destination. If a fill value is not provided, the data element position is set to all zeros.

[0433] The flags register may be used as a source mask: if the flag bit for a source lane is set to 1, the source lane may be marked as invalid and the instruction may proceed.

[0434] Below are examples of different implementations of the immediate shuffle instruction. shuffle_ <up dn xor>_<1 / 2 / 4 / 8 / 16> dest src0 <optional src1> <optional flag> shuffle_ <up dn xor>_<1 / 2 / 4 / 8 / 16> dest src0<optional src1><optional flag> In this implementation, src0 contains N doublewords, src1 contains one doubleword for the fill value (if there is one), and dest contains N doublewords containing the result.

[0435] The following code sequence defines one particular implementation of the immediate shuffle instruction. for (int i = 0; i < SIMD_WIDTH) { int8_t srcLane; switch(SHUFFLE_TYPE) { case UP: srcLane = i - SHIFT; case DN: srcLane = i + SHIFT; case XOR: srcLane = i^SHIFT; } if (execMask[i]) { bool invalidLane = srcLane < 0 || srcLane >= SIMD_WIDTH || !execMask[srcLane]; if (FLAG) { invalidLane |= flag[srcLane]; } if (invalidLane) { if (SRC1) dst[i] = src1; else dst[i] = 0; } else { dst[i] = src0[srcLane]; } } }

[0436] Here, the input data element / lane is shifted by 1, 2, 4, 8 or 16 positions based on the value of the immediate. Register src1 is an additional scalar source register used as a fill value that is stored into a data element position in the destination if the source lane index is invalid. If no fill value is provided and the source lane index is invalid, the data element position in the destination is set to 0. The flag register (FLAG) is used as a source mask. If the flag bit for a source lane is set to 1, the source lane is marked as invalid and the instruction proceeds as above. [Indirect Shuffle Up / Dn / XOR Instructions]

[0437] The indirect shuffle instruction has a source operand (src1) that controls the mapping from the source lane to the destination lane. <up dn xor>dest src0 src1<optional flag> where src0 contains N doublewords, src1 contains 1 doubleword, and dest contains N doublewords.

[0438] The following code sequence defines one particular implementation of the immediate shuffle instruction. for (int i = 0; i < SIMD_WIDTH) { int8_t srcLane; switch(SHUFFLE_TYPE) { case UP: srcLane = i - src1; case DN: srcLane = i + src1; case XOR: srcLane = i^src1; } if (execMask[i]) { bool invalidLane = srcLane < 0 || srcLane >= SIMD_WIDTH || !execMask[srcLane]; if (FLAG) { invalidLane |= flag[srcLane]; } if (invalidLane) { dst[i] = 0; } else { dst[i] = src0[srcLane]; } } }

[0439] The indirect shuffle instruction therefore operates in a similar manner to the immediate shuffle instruction described above, except that the mapping of source lanes to destination lanes is controlled by the source register src1 rather than an immediate value. [Crosslane min / max command]

[0440] Cross lane minimum / max instructions may be supported for float and integer data types. Cross lane minimum instructions may take the form lane_min dest src0 and cross lane maximum instructions may take the form lane_max dest src0, where src0 stores N doublewords and dest stores 1 doubleword.

[0441] For illustrative purposes, the following code sequence defines one particular implementation of the cross lane minimum: dst = src[0]; for (int i = 1; i < SIMD_WIDTH) { if (execMask[i]) { dst = min(dst, src[i]); } } In this example, the double word value in data element position i of the source register is compared to the data element in the destination register and the minimum of the two values ​​is copied to the destination register. The cross lane max instruction operates in substantially the same manner, the only difference being that the maximum value of the data element in position i and the destination value are selected. [Crosslane Min / Max Index Command]

[0442] A cross lane minimum index instruction may take the form lane_min_index dest src0, and a cross lane maximum index instruction may take the form lane_max_index dest src0, where src0 stores N doublewords and dest stores 1 doubleword.

[0443] For illustrative purposes, the following code sequence defines one particular implementation of a cross lane minimum index instruction: dst_index = 0; tmp = src[0] for (int i = 1; i < SIMD_WIDTH) { if (src[i] < tmp && execMask[i]) { tmp = src[i]; dst_index = i; } } In this example, the destination index is incremented from 0 to the SIMD width and spans the destination register. If the execution mask bit is set, the data element at position i in the source register is copied to a temporary storage location (tmp) and the destination index is set to data element position i. [Cross Lane Sort Network Command]

[0444] A cross lane sort network instruction may sort all N input elements using an N-wide (stable) sorting network in either ascending (sortnet_min) or descending (sortnet_max) order. The min / max versions of the instruction may take the form sortnet_min dest src0 and sortnet_max dest src0, respectively. In one implementation, src0 and dest store N double words. A min / max sort is performed on the N double words of src0, and the ascending elements (for min) or descending elements (for max) are stored in dest in their respective sorted order. An example of a code sequence defining the instruction is as follows: dst =apply_N_wide_sorting_network_min / max(src0) [Crosslane sorting network index command]

[0445] The cross lane sorting network index instruction sorts all N input elements using an N-wide (stable) sorting network, either in ascending (sortnet_min) or descending (sortnet_max) order, and returns a permutation index. The min / max versions of the instruction may take the form sortnet_min_index dest src0 and sortnet_max_index dest src0, where src0 and dest each store N double words. An example of a code sequence that defines the instruction is dst = apply_N_wide_sorting_network_min / max_index(src0).

[0446] A method for executing any of the above instructions is illustrated in Figure 50. The method may be implemented in the specific processor architectures mentioned above, but is not limited to any particular processor or system architecture.

[0447] In 5001, instructions of a primary graphics thread are executed on a processor core, which may include, for example, any of the cores described above (e.g., graphics core 3130). When ray tracing work arrives in the primary graphics thread, as determined in 5002, the ray tracing instructions are offloaded to a ray tracing execution circuit, which may be in the form of a functional unit (FU) as described above in connection with FIG. 49, or may be in a dedicated ray tracing core 3150 described in connection with FIG. 31.

[0448] In 5003, the ray tracing instructions are decoded and fetched from memory, and in 5005, the instructions are decoded into executable operations (e.g., in embodiments requiring a decoder). In 5004, the ray tracing instructions are scheduled and dispatched for execution by the ray tracing circuitry. In 5005, the ray tracing instructions are executed by the ray tracing circuitry. For example, the instructions may be dispatched and executed on the FUs described above (e.g., the vector FU 4910, the ray tracing FU 4912, etc.) and / or the graphics core 3130 or the ray tracing core 3150.

[0449] When execution is completed for a ray tracing instruction, the results are stored (e.g., stored again in memory 3198) at 5006 and the primary graphics thread is notified at 5007. At 5008, the ray tracing results are processed (e.g., read from memory and integrated into the graphics rendering results) in the context of the primary thread.

[0450] In embodiments, the terms "engine" or "module" or "logic" may refer to, be a part of, or include one or more application specific integrated circuits (ASICs), electronic circuitry, processors (shared, dedicated or groups) executing software or firmware programs, and / or memory (shared, dedicated or groups), combinatorial logic circuitry, and / or other suitable components that provide the described functionality. In embodiments, the engine, module or logic may be implemented in firmware, hardware, software or any combination of firmware, hardware and software. [Apparatus and method for asynchronous ray tracing]

[0451] An embodiment of the present invention includes a combination of fixed-function acceleration circuitry and general-purpose processing circuitry to perform ray tracing. For example, certain operations related to ray traversal and intersection testing of bounding volume hierarchies (BVHs) may be performed by the fixed-function acceleration circuitry, while multiple execution circuits may be performed by various types of ray tracing shaders (e.g., any hit shader, intersection shader, miss shader, etc.). One embodiment includes dual high-bandwidth storage banks containing multiple entries for storing rays and corresponding dual stacks for storing BVH nodes. In this embodiment, the traversal circuitry switches between the dual ray banks and stacks to process rays at each clock cycle. Additionally, one embodiment includes priority selection circuitry / logic that distinguishes between interior nodes, non-internal nodes, and primitives and uses this information to intelligently prioritize processing of BVH nodes and primitives enclosed by BVH nodes.

[0452] A particular embodiment reduces the high-speed memory required for traversal by using a short stack to store a limited number of BVH nodes during a traversal operation. This embodiment includes stack management circuitry / logic to efficiently push and pop entries to and from the short stack to ensure that required BVH nodes are available. Additionally, the traversal operation is tracked by performing updates to a tracking data structure. When the traversal circuitry / logic is stopped, it can refer to the tracking data structure to start the traversal operation at the same location in the BVH where it left off. The tracking data maintained in the tracking data structure is then executed so that the traversal circuitry / logic can resume.

[0453] FIG. 51 illustrates an embodiment including a shader execution circuitry 4000 for executing shader program code and processing associated ray tracing data 4902 (e.g., BVH node data and ray data), a ray tracing acceleration circuitry 5110 for performing traversal and intersection operations, and a memory 3198 for storing program code and associated data processed by the RT acceleration circuitry 5110 and the shader execution circuitry 4000.

[0454] In one embodiment, the shader execution circuitry 4000 includes multiple cores / execution units 4001 that execute shader program code to perform various forms of data parallel operations. For example, in one embodiment, the cores / execution units 4001 can execute a single instruction across multiple lanes, where each instance of the instruction operates on data stored in a different lane. In a SIMT implementation, for example, each instance of the instruction is associated with a different thread. During execution, the L1 cache stores certain ray tracing data (e.g., recently or frequently accessed data) for efficient access.

[0455] The set of primary rays may be dispatched to a scheduler 4007 that schedules work for shaders executed by the core / EU 4001. The core / EU 4001 may be a ray tracing core 3150, a graphics core 3130, a CPU core 3199, or other type of circuitry capable of executing shader program code. One or more primary ray shaders 5101 process the primary rays and generate additional work (e.g., performed by one or more child shaders) that are executed by the ray tracing acceleration circuitry 5110 and / or the core / EU 4001. New work generated by the primary ray shader 5101 or other shaders executed by the core / EU 4001 may be distributed to a sorting circuitry 4008 that sorts the rays into groups or bins (e.g., grouping rays with similar characteristics) as described herein. The scheduler 4007 then schedules the new work on the core / EU 4001.

[0456] Other shaders that may be executed may include any hit shader 4514 and closest hit shader 4507, which handle hit results as described above (e.g., for a given ray, identify any hit or closest hit, respectively). Miss shader 4506 handles ray misses (e.g., a ray does not intersect with a node / primitive). As described above, various shaders may be referenced using a shader record, which may include one or more pointers, vendor specific metadata, and global arguments. In one embodiment, the shader record is identified by a shader record identifier (SRI). In one embodiment, each execution instance of a shader is associated with a call stack 5203, which may be used to store arguments passed between parent and child shaders. The call stack 5121 may also store a reference to a continuing function that is executed when the call returns.

[0457] The ray traversal circuitry 5102 traverses each ray through the nodes of the BVH, descending the hierarchy of the BVH (e.g., through parent, child, and leaf nodes) to identify the nodes / primitives traversed by the ray. The ray-BVH intersection circuitry 5103 performs intersection tests of rays, determines hit points on primitives, and generates results depending on the hits. The traversal circuitry 5102 and intersection circuitry 5103 may take work from one or more call stacks 5121. Within the ray tracing acceleration circuitry 5110, the call stacks 5121 and associated ray tracing data 4902 may be stored in a local ray tracing cache (RTC) 5107 or other local storage device for efficient access by the traversal circuitry 5102 and intersection circuitry 5103. One particular embodiment described below includes a high bandwidth ray bank (see, e.g., FIG. 52[[A]]).

[0458] The ray tracing acceleration circuitry 5110 may be a variation of the various traversal / intersection circuitry described herein, including the ray-BVH traversal / intersection circuitry 4005, the traversal circuitry 4502 and the intersection circuitry 4503, and the ray tracing core 3150. The ray tracing acceleration circuitry 5110 may be used in place of the ray-BVH traversal / intersection circuitry 4005, the traversal circuitry 4502 and the intersection circuitry 4503, and the ray tracing core 3150, or any other circuitry / logic for processing the BVH stack and / or performing traversal / intersection. Thus, disclosure of the ray-BVH traversal / intersection circuit 4005, traversal circuit 4502, and intersection circuit 4503 described herein, and any features in combination with the ray tracing core 3150, also discloses, but is not limited to, the corresponding combination with the ray tracing acceleration circuit 5110.

[0459] Referring to FIG. 52, one embodiment of the ray traversal circuit 5102 includes a first ray storage bank 5201 and a second ray storage bank 5202, each bank including a number of entries for storing a corresponding number of input rays 5206 loaded from memory. The corresponding first stack 5203 and second stack 5204 include selected BVH node data that is read from memory and stored locally for processing. As described herein, in one embodiment, the stacks 5203-5204 are "short" stacks including a limited number of entries (e.g., in one embodiment, six entries) for storing BVH node data. Although illustrated separately from the ray banks 5201-5202, the stacks 5203-5204 may also be maintained within the corresponding ray banks 5201-5202. Alternatively, the stacks 5203-5204 may be stored in separate local memories or caches.

[0460] One embodiment of the traversal processing circuit 5210 switches (e.g., in a ping-pong fashion) between the two banks 5201-5202 and stacks 5203-5204 when selecting the next ray and node to process. For example, the traversal processing circuit 5210 may select a new ray / BVH node from the switching ray bank / stack at each clock cycle. This ensures very efficient operation. However, it should be noted that this particular arrangement is not required to follow the basic principles of the present invention.

[0461] In one embodiment, the ray allocator 5205 balances the entries of incoming rays 5206 in the first memory bank 5201 and the second memory bank 5202, respectively, based on the current relative values ​​of a set of bank allocation counters 5220. In one embodiment, the bank allocation counters 5220 maintain a count of the number of untraversed rays in each of the first memory bank 5201 and the second memory bank 5202. For example, the first bank allocation counter may be incremented when the ray allocator 5205 adds a new ray to the first bank 5201, and may be decremented when a ray is processed from the first bank 5201. Similarly, the second bank allocation counter may be incremented when the ray allocator 5205 adds a new ray to the second bank 5201, and may be decremented when a ray is processed from the second bank 5201.

[0462] In one embodiment, the ray allocator 5205 allocates the current ray to the bank associated with the smaller counter value. If the two counters are equal, the ray allocator 5205 may select either bank, or may select a different bank from the one selected the last time the counters were equal. In one embodiment, each ray is stored in one entry in one of the banks 5201-5202, with each bank containing 32 entries for storing up to 32 rays. However, the underlying principles of the invention are not limited to these details. [Apparatus and method for non-local means filtering]

[0463] "Non-local means" is an image processing technique for performing noise removal. Unlike "local" means filters, which smooth an image by determining the average value of a block of pixels surrounding a target pixel, non-local means filters determine the average value of all pixels in an image, weighted by how similar these pixels are to the target pixel, resulting in improved clarity after filtering and reduced loss of detail in the image compared to local means algorithms.

[0464] In existing implementations, the non-local means calculation is performed in software. As a result, these implementations are not suitable for real-time rendering environments.

[0465] One embodiment of the present invention uses existing motion estimation hardware blocks in a media processor pipeline to perform non-local means filtering. Since the existing motion estimation circuitry is reused, only a small amount of additional circuitry is required. Using this hardware, embodiments of the present invention can perform non-local means filtering much more efficiently than using current software implementations.

[0466] Furthermore, since the motion estimation circuitry is inherently configured to estimate motion across image frames, an embodiment of the present invention utilizes this feature to perform inter-frame non-local means filtering (rather than limiting the operation within the current frame). Thus, in one implementation, efficient and accurate temporal denoising may be performed using non-local means filtering within and / or across image frames.

[0467] One embodiment of the present invention includes new interfaces, including hardware and / or software components (e.g., programming interfaces) for making the motion estimation block of a media processor accessible to other processor components and applications. By way of example and not limitation, these may include depth estimation operations in 3D graphics pipelines, video deinterlacing, and viewpoint interpolation for virtual reality implementations.

[0468] Many of the processor architectures described herein include media processors (sometimes referred to as "media engines" or "media pipelines") that have dedicated circuitry for encoding and decoding video content (e.g., H.264 video, etc.). These media processors include media pipeline 234 (FIG. 2B), media pipeline 316 (FIG. 3A, FIG. 4), media engine 837 (FIG. 8), and media processing engine 3197 (FIG. 31). Each such media processor includes circuitry for performing motion estimation for video processing. In one embodiment, instead of implementing a machine learning approach for denoising, an embodiment of the present invention performs non-local means filtering using motion estimation hardware in the media processor.

[0469] FIG. 53 illustrates one embodiment of the present invention in which the motion estimation circuitry 5320 of the media processing engine 3197 performs non-local means filtering on a rendered image frame 5330 to generate a denoised frame 5340. In particular, in one embodiment, the media API 5302 (i.e., a set of commands / instructions executable by the media processing engine 3197) is supplemented with non-local means commands 5305 for implementing the techniques described herein. The non-local means commands 5305 access various architectural features of the motion estimation circuitry 5320, including the additional capability provided by the motion estimation circuitry 5320 to perform non-local means filtering across multiple image frames 5330, rather than simply within the current frame as in the current implementation. For example, one of the primary functions of the motion estimation circuitry 5320 when performing video encoding is to identify movement of pixel blocks (e.g., macroblocks, slices, etc.) across successive frames. Thus, instead of performing non-local means filtering for a target pixel by determining the average of all pixels in a single image frame (weighted based on their similarity to the target pixel), the motion estimation circuit 5320 is used to determine the average of all pixels distributed across multiple image frames.

[0470] Non-local means filtering may be performed at the pixel or pixel block (e.g., macroblock) level. Pixel blocks may have any arrangement of pixels supported by the motion estimation circuit 5320, including blocks with the same number of pixels in each dimension (e.g., 16×16, 8×8, or 4×4), and blocks with different numbers of pixels in each dimension (e.g., 16×8, 16×4, 8×4, etc.). Furthermore, an image frame may be encoded with an asymmetric arrangement of pixel blocks, whereby a central region of the image frame is encoded with higher precision (e.g., using 4×4 pixel blocks) while the periphery of the image frame is encoded with less precision (e.g., using 16×16 pixel blocks).

[0471] Regardless of the type of encoding used, in one embodiment, the non-local means commands 5305 control the motion estimation circuitry 5320 to distinguish actual pixel data from "noise" in the image frame 5330 and generate a denoised image frame 5340. In particular, in one implementation, the motion estimation circuitry 5320 is used to perform efficient and accurate temporal denoising using non-local means filtering within and / or across image frames.

[0472] In operation, the command streamer 5310 streams image rendering commands to the ray tracing circuitry 5110 (i.e., for traversal and intersection) and the shader execution circuitry 4000 (i.e., for shader execution) to generate image frames 5330 using the various techniques described herein. Subsequently, or simultaneously, the command streamer 5310 streams non-local means commands 5305 to the media processing engine 3197 which executes the commands using the motion estimation circuitry 5320 to evaluate successive image frames 5330 to perform denoising and generate denoised image frames 5340.

[0473] In one embodiment, the media API 5302 comprises additional commands to make the motion estimation block 5320 accessible to other applications. By way of example and not limitation, these may include depth estimation operations in a 3D graphics pipeline, video deinterlacing, and / or viewpoint interpolation (e.g., for virtual reality implementations).

[0474] A method according to one embodiment is illustrated in Figure 54. The method may be implemented in the context of the architectures described herein, but is not limited to any particular processor or system architecture.

[0475] At 5401, a command streamer streams commands to a ray tracing circuit and a shader execution circuit. At 5402, the ray tracing circuit and the shader execution circuit execute the commands to render an image frame. At 5403, the command streamer streams non-local means (NLM) commands to a media processing circuit, and at 5404, the commands are executed using a motion estimation circuit to perform noise removal by evaluating inter-frame pixel blocks.

[0476] example

[0477] Below are exemplary implementations of different embodiments of the present invention.

[0478] Example 1 A processor comprising: a ray tracing circuit that executes a first set of one or more commands to traverse a ray through a bounding volume hierarchy (BVH) and identify BVH nodes and / or primitives that intersect with the ray; a shader execution circuit that executes one or more shaders in response to a second set of one or more commands to render a series of image frames based on the BVH nodes and / or primitives that intersect with the ray; and a motion estimation circuit that executes a third set of one or more commands to perform non-local means filtering to remove noise from the series of image frames based on average pixel values ​​collected over the series of image frames.

[0479] Example 2 2. The processor of example 1, further comprising a command streamer configured to stream the first set of commands to the ray tracing circuitry, the second set of commands to the shader execution circuitry, and the third set of commands to the media processing block.

[0480] Example 3 3. The processor of example 2, wherein the third set of commands comprises an extension of an application programming interface (API) associated with the media processing block.

[0481] Example 4 2. The processor of example 1, wherein the non-local means filtering of the target pixel includes determining an average value associated with all pixels across the set of images weighted by their similarity to the target pixel.

[0482] Example 5 2. The processor of claim 1, wherein the shader execution circuitry includes a plurality of execution units (EUs) for executing a plurality of different shaders to render the sequence of image frames.

[0483] Example 6 2. The processor of example 1, wherein the average pixel value is determined based on evaluation of blocks of pixels distributed across the sequence of image frames.

[0484] Example 7 7. The processor of example 6, wherein the block of pixels comprises a macroblock.

[0485] Example 8 8. The processor of example 7, wherein the macroblock comprises one or more of a 16x16 pixel block, an 8x8 pixel block, a 4x4 pixel block, a 16x8 pixel block, an 8x4 pixel block, or a 16x4 pixel block.

[0486] Example 9 1. A method comprising: executing a first set of one or more commands on a ray tracing circuit to traverse a ray through a bounding volume hierarchy (BVH) and identify BVH nodes and / or primitives that intersect with the ray; executing one or more shaders in response to a second set of one or more commands to render a series of image frames based on the BVH nodes and / or primitives that intersect with the ray; and executing a third set of one or more commands on a media processor including a motion estimation circuit to perform non-local means filtering to remove noise from the series of image frames based on average pixel values ​​collected across the series of image frames.

[0487] Example 10 10. The method of example 9, further comprising streaming the first set of commands to the ray tracing circuitry, the second set of commands to the shader execution circuitry, and the third set of commands to the media processing block.

[0488] Example 11 11. The method of example 10, wherein the third set of commands comprises an extension of an application programming interface (API) associated with the media processing block.

[0489] Example 12 10. The method of example 9, wherein the non-local means filtering of the target pixel comprises determining a mean value associated with all pixels across the set of images, weighted by similarity to the target pixel.

[0490] Example 13 10. The method of example 9, wherein the one or more shaders execute on multiple execution units (EUs) to render the sequence of image frames.

[0491] Example 14 10. The method of example 9, wherein the average pixel value is determined based on evaluation of blocks of pixels distributed across the sequence of image frames.

[0492] Example 15 15. The method of example 14, wherein the block of pixels comprises a macroblock.

[0493] Example 16. The method of example 15, wherein the macroblock comprises one or more of a 16x16 pixel block, an 8x8 pixel block, a 4x4 pixel block, a 16x8 pixel block, an 8x4 pixel block, or a 16x4 pixel block.

[0494] Example 17 A machine-readable medium storing program code that, when executed by a machine, causes the machine to perform operations of executing a first set of one or more commands on a ray tracing circuit to traverse a ray through a bounding volume hierarchy (BVH) and identify BVH nodes and / or primitives that intersect with the ray, executing one or more shaders in response to a second set of one or more commands to render a series of image frames based on the BVH nodes and / or primitives that intersect with the ray, and executing a third set of one or more commands on a media processor including a motion estimation circuit to perform non-local means filtering to remove noise from the series of image frames based on average pixel values ​​collected over the series of image frames.

[0495] Example 18 20. The machine-readable medium of example 17, wherein the operation further includes streaming the first set of commands to the ray tracing circuitry, the second set of commands to the shader execution circuitry, and the third set of commands to the media processing block.

[0496] Example 19 20. The machine-readable medium of example 18, wherein the third set of commands comprises an extension of an application programming interface (API) associated with the media processing block.

[0497] Example 20 20. The machine-readable medium of example 17, wherein the non-local means filtering of the target pixel includes determining an average value associated with all pixels across the set of images weighted by their similarity to the target pixel.

[0498] Example 21 20. The machine-readable medium of example 17, wherein the one or more shaders execute on multiple execution units (EUs) to render the sequence of image frames.

[0499] Example 22 20. The machine-readable medium of example 17, wherein the average pixel value is determined based on evaluation of blocks of pixels distributed across the sequence of image frames.

[0500] Example 23 23. The machine-readable medium of example 22, wherein the block of pixels comprises a macroblock.

[0501] Example 24 24. The machine-readable medium of example 23, wherein the macroblock comprises one or more of a 16x16 pixel block, an 8x8 pixel block, a 4x4 pixel block, a 16x8 pixel block, an 8x4 pixel block, or a 16x4 pixel block.

[0502] An embodiment of the present invention may include various steps described above. The steps may be embodied in machine-executable instructions that may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, the steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

[0503] As described herein, instructions may refer to a particular configuration of hardware, such as an application specific integrated circuit (ASIC) configured to perform a particular operation or having a predetermined functionality, or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques illustrated in the figures may be implemented using stored code and data and executed in one or more electronic devices (e.g., end stations, network elements, etc.). Such electronic devices store and communicate (internally and / or with other electronic devices over a network) code and data using computer machine readable media, such as non-transitory computer machine readable storage media (e.g., magnetic disks, optical disks, random access memory, read only memory, flash memory devices, phase change memory), and transitory computer machine readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc.).

[0504] Further, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens and / or displays), and network connections. The coupling of the processors and the set of other components is typically through one or more buses and bridges (also referred to as bus controllers). The signals carrying the storage devices and network traffic represent one or more machine-readable storage media and machine-r...

Claims

1. 1. A processor comprising: a ray tracing circuit that executes a first set of one or more commands to traverse a ray through a bounding volume hierarchy (BVH) and identify BVH nodes and / or primitives that intersect with the ray; a shader execution circuit that executes one or more shaders in response to a second set of one or more commands to render a sequence of image frames based on the BVH nodes and / or the primitives intersected by the ray; a media processor having a motion estimation circuit that executes a third set of one or more commands to perform non-local means filtering to remove noise from the sequence of image frames based on average pixel values ​​collected across the sequence of image frames; Equipped with the motion estimation circuitry performs the non-local means filtering between the image frames of the sequence by estimating motion across the image frames of the sequence. Processor.

2. 2. The processor of claim 1, further comprising a command streamer that streams the first set of commands to the ray tracing circuitry, the second set of commands to the shader execution circuitry, and the third set of commands to the media processor.

3. The processor of claim 2 , wherein the third set of commands comprises an extension of an application programming interface (API) associated with the media processor.

4. 4. The processor of claim 1, wherein the non-local means filtering of a target pixel comprises determining an average value associated with all pixels across the sequence of image frames, weighted by their similarity to the target pixel.

5. The processor of claim 1 , wherein the shader execution circuitry comprises a plurality of execution units (EUs) for executing a plurality of different shaders to render the sequence of image frames.

6. A processor according to claim 1 , wherein the average pixel value is determined based on evaluation of blocks of pixels distributed across the sequence of image frames.

7. The processor of claim 6 , wherein the blocks of pixels comprise macroblocks.

8. 8. The processor of claim 7, wherein a macroblock comprises one or more of a 16x16 pixel block, an 8x8 pixel block, a 4x4 pixel block, a 16x8 pixel block, an 8x4 pixel block, or a 16x4 pixel block.

9. executing a first set of one or more commands on a ray tracing circuit to traverse a ray through a bounding volume hierarchy (BVH) and identify BVH nodes and / or primitives that intersect with the ray; executing one or more shaders in response to a second set of one or more commands to render a series of image frames based on the BVH nodes and / or the primitives intersected by the ray; executing a third set of one or more commands on a media processor having a motion estimation circuit to perform non-local means filtering to remove noise from the sequence of image frames based on average pixel values ​​collected across the sequence of image frames; Equipped with the motion estimation circuitry performs the non-local means filtering between the image frames of the sequence by estimating motion across the image frames of the sequence. method.

10. 10. The method of claim 9, further comprising streaming the first set of commands to the ray tracing circuitry, the second set of commands to shader execution circuitry, and the third set of commands to the media processor.

11. The method of claim 10 , wherein the third set of commands comprises an extension of an application programming interface (API) associated with the media processor.

12. 12. The method of claim 9, wherein the non-local means filtering of a target pixel comprises determining an average value associated with all pixels across the sequence of image frames, weighted by their similarity to the target pixel.

13. The method of claim 9 , wherein the one or more shaders execute on multiple execution units (EUs) to render the sequence of image frames.

14. 12. A method according to any one of claims 9 to 11, wherein the average pixel value is determined based on evaluation of blocks of pixels distributed across the sequence of image frames.

15. The method of claim 14 , wherein the blocks of pixels comprise macroblocks.

16. 16. The method of claim 15, wherein a macroblock comprises one or more of a 16x16 pixel block, an 8x8 pixel block, a 4x4 pixel block, a 16x8 pixel block, an 8x4 pixel block, or a 16x4 pixel block.

17. A program for a computer, executing a first set of one or more commands on a ray tracing circuit to traverse a ray through a bounding volume hierarchy (BVH) and identify BVH nodes and / or primitives that intersect with the ray; executing one or more shaders in response to a second set of one or more commands to render a series of image frames based on the BVH nodes and / or the primitives intersected by the ray; executing a third set of one or more commands on a media processor having a motion estimation circuit to perform non-local means filtering to remove noise from the series of image frames based on average pixel values ​​collected across the series of image frames. Executing a procedure comprising: the motion estimation circuitry performs the non-local means filtering between the image frames of the sequence by estimating motion across the image frames of the sequence. program.

18. 20. The computer-implemented program of claim 17, wherein the steps further comprise streaming the first set of commands to the ray tracing circuitry, the second set of commands to shader execution circuitry, and the third set of commands to the media processor.

19. 20. The program product of claim 18, wherein the third set of commands comprises an extension of an application programming interface (API) associated with the media processor.

20. 20. The program of claim 17, wherein the non-local means filtering of a target pixel comprises determining an average value associated with all pixels across the sequence of image frames, weighted by their similarity to the target pixel.

21. 21. The program of claim 17, wherein the one or more shaders execute on multiple execution units (EUs) to render the sequence of image frames.

22. 22. A program as claimed in any one of claims 17 to 21, wherein the average pixel value is determined based on evaluation of blocks of pixels distributed across the sequence of image frames.

23. 23. The program of claim 22, wherein the block of pixels comprises a macroblock.

24. 24. The program of claim 23, wherein the macroblock comprises one or more of a 16x16 pixel block, an 8x8 pixel block, a 4x4 pixel block, a 16x8 pixel block, an 8x4 pixel block, or a 16x4 pixel block.

25. An apparatus comprising: means for executing a first set of one or more commands on a ray tracing circuit to traverse a ray through a bounding volume hierarchy (BVH) and identify BVH nodes and / or primitives that intersect with the ray; means for executing one or more shaders in response to a second set of one or more commands to render a series of image frames based on the BVH nodes and / or the primitives intersected by the ray; means for executing a third set of one or more commands on a media processor having a motion estimation circuit to perform non-local means filtering to remove noise from the sequence of image frames based on average pixel values ​​collected across the sequence of image frames; Equipped with the motion estimation circuitry performs the non-local means filtering between the image frames of the sequence by estimating motion across the image frames of the sequence. Device.

26. A machine-readable medium storing a program according to any one of claims 17 to 24.

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