Semiconductor light emitting device and method for manufacturing the same

Abstract

To suppress heat generation on an emission end surface while enhancing an output of a semiconductor light-emitting element.SOLUTION: A semiconductor light-emitting element comprises: a first conductive type semiconductor layer; an active layer that is positioned on the first conductive type semiconductor layer, and includes parallel end surfaces; a second conductive type semiconductor layer that is positioned on the active layer; a contact layer that is positioned on the second conductive type semiconductor layer, and can perform an ohmic-junction with an electrode; an intermediate layer that is positioned between the second conductive type semiconductor layer and the contact layer, and in which an impurity concentration is higher than that of the second conductive type semiconductor layer; and a resistance layer that is provided on the second conductive type semiconductor layer in the neighbor of at least one end surface of the end surfaces, and has a resistance higher than that of the intermediate layer.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to a semiconductor light-emitting device and a method for manufacturing the same. [Background technology]

[0002] As the output of semiconductor laser elements increases, COD (Catastrophic Optical Damage) can occur. COD is a phenomenon in which the emission facet of a semiconductor laser element is destroyed by heat generation due to light absorption, etc., and laser oscillation stops. The cause of COD is thought to be non-radiative recombination caused by deep interface states formed on the emission facet side, which generates heat near the facet, and this heat generation causes the band gap to shrink, promoting non-radiative recombination, resulting in positive feedback that dissolves the semiconductor crystal near the facet.

[0003] Patent Document 1 discloses a method of adopting a structure called a window region to suppress COD at the facets. This method involves diffusing impurities such as Zn near the laser facets to intermix the quantum well structure of the active layer and suppress light absorption. Patent Document 2 discloses a semiconductor laser element having a window region in which Zn is diffused as an impurity, in which an intermediate layer for reducing the band energy difference between the cladding layer and the contact layer is formed so as to be sandwiched between the cladding layer and the contact layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2018 / 105015 [Patent Document 2] JP 2014-110250 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the configuration disclosed in Patent Document 1, since there is no intermediate layer, discontinuity in the energy bands (energy difference in the conduction band level resulting from the difference in band gap energy between the materials) occurs between the upper cladding layer and the contact layer, resulting in high resistance of the element. Furthermore, in the configuration disclosed in Patent Document 2, the contact layer and intermediate layer are formed up to the emission end face, so that the current flowing through the emission end face increases, and the heat generated at the emission end face by the current increases.

[0006] SUMMARY OF THE PRESENT DISCLOSURE An object of the present invention is to provide a semiconductor light emitting device that is capable of suppressing heat generation at the light emitting end face while achieving high output, and a method for manufacturing the semiconductor light emitting device. [Means for solving the problem]

[0007] A semiconductor light-emitting element according to one aspect of the present invention includes a first conductivity type semiconductor layer, an active layer located on the first conductivity type semiconductor layer and having end faces parallel to each other, a second conductivity type semiconductor layer located on the active layer, a contact layer located on the second conductivity type semiconductor layer and capable of forming an ohmic junction with an electrode, an intermediate layer located between the second conductivity type semiconductor layer and the contact layer and having a higher impurity concentration than the second conductivity type semiconductor layer, and a resistive layer provided on the second conductivity type semiconductor layer near at least one of the end faces and having a higher resistance than the intermediate layer.

[0008] This makes it possible to reduce the band energy difference between the contact layer and the second conductive type semiconductor layer while suppressing an increase in resistance between the contact layer and the active layer. Furthermore, it is possible to suppress the current flowing to the light emitting end side via the intermediate layer. Therefore, even when an intermediate layer is provided between the second conductive type semiconductor layer and the contact layer, it is possible to suppress heat generation on the light emitting end side, and it is possible to suppress COD while achieving high output.

[0009] Furthermore, in a semiconductor light-emitting device according to one aspect of the present invention, a window region is provided in a position corresponding to the vicinity of an end face of the active layer, in a region where the contact layer is recessed from the end face in a resonator direction, and the active layer includes a mixed crystal region that is mixed based on impurities diffused through the window region.

[0010] This makes it possible to suppress heat generation due to current flowing to the light-emitting end side. Furthermore, the band gap of the active layer on the light-emitting end side can be widened, and the band gap on the light-emitting end side can be suppressed from shrinking. This makes it possible to suppress heat generation due to absorption of laser light on the light-emitting end side. Therefore, not only can the temperature rise due to current flowing to the light-emitting end side be suppressed, but also the temperature rise due to absorption of laser light on the light-emitting end side can be suppressed, making it possible to suppress COD while achieving high output.

[0011] In addition, in the semiconductor light emitting device according to one aspect of the present invention, the resistive layer is located in the window region.

[0012] This makes it possible to provide the intermediate layer between the second conductive type semiconductor layer and the contact layer, and to provide the resistive layer at the position of the intermediate layer on the light emitting end side.

[0013] In addition, in the semiconductor light emitting device according to one aspect of the present invention, the resistance layer has a concave-convex structure formed on the intermediate layer.

[0014] This makes it possible to increase the resistance of the intermediate layer on the light-emitting end side in a structure in which an intermediate layer is provided between the second conductive type semiconductor layer and the contact layer, and to suppress heat generation due to current flowing to the light-emitting end side. At this time, it is possible to provide a concave-convex structure in the intermediate layer on the light-emitting end side based on a heat treatment that diffuses impurities into the active layer through the window region. This makes it possible to suppress an increase in the number of steps.

[0015] In the semiconductor light emitting device according to one aspect of the present invention, at least a portion of the recesses of the recess-projection structure reaches the second conductive type semiconductor layer.

[0016] This allows the uneven structure of the intermediate layer on the light emitting end side to have a high resistance, making it possible to suppress heat generation due to a current flowing on the light emitting end side.

[0017] In the semiconductor light emitting device according to one aspect of the present invention, the resistance layer includes an oxide formed by oxidizing a portion of the intermediate layer.

[0018] This makes it possible to increase the resistance of the intermediate layer on the light-emitting end side in a structure in which an intermediate layer is provided between the second conductive type semiconductor layer and the contact layer, and to suppress heat generation due to current flowing on the light-emitting end side. At this time, a part of the intermediate layer on the light-emitting end side can be oxidized to form an oxide based on a heat treatment that diffuses impurities into the active layer through the window region. This makes it possible to suppress an increase in the number of steps.

[0019] In addition, in the semiconductor light emitting element according to one aspect of the present invention, the resistive layer is an insulating layer provided on the second conductive type semiconductor layer.

[0020] As a result, in a structure in which an intermediate layer is provided between the second conductive type semiconductor layer and the contact layer, it is possible to block current flowing through the intermediate layer on the light emitting end side, and it is possible to suppress heat generation due to current flowing on the light emitting end side. In this case, in order to form an insulating layer, it is only necessary to remove the intermediate layer on the light emitting end side, and the insulating layer can be formed simultaneously in a subsequent insulating layer formation process on the contact layer, thereby suppressing an increase in the number of processes.

[0021] Furthermore, a method for manufacturing a semiconductor light-emitting element according to one aspect of the present invention includes the steps of sequentially forming a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a semiconductor substrate, sequentially forming an intermediate layer and a contact layer on the second conductivity type semiconductor layer, forming a window region in which a portion of the contact layer is removed at a position corresponding to an end face side of the active layer, and forming a resistive layer having a higher resistance than the intermediate layer at the position of the window region.

[0022] As a result, with an intermediate layer provided between the second conductivity type semiconductor layer and the contact layer, the current flowing to the light emitting end side through this intermediate layer can be suppressed, and heat generation on the light emitting end side can be suppressed.

[0023] Furthermore, in accordance with a method for manufacturing a semiconductor light-emitting element according to one aspect of the present invention, the step of forming the resistive layer includes a step of performing a heat treatment while bringing an impurity diffusion source into contact with the intermediate layer at the position of the window region.

[0024] This makes it possible to increase the resistance of the intermediate layer on the light-emitting end side and to mix the active layer on the light-emitting end side based on a heat treatment that diffuses impurities into the active layer through the window region. This makes it possible to suppress not only the temperature rise caused by the current flowing through the light-emitting end side, but also the temperature rise caused by the absorption of laser light at the light-emitting end side while suppressing an increase in the number of processes. This makes it possible to suppress COD while achieving high output, and also to suppress an increase in the cost of the semiconductor light-emitting device.

[0025] Furthermore, in a method for manufacturing a semiconductor light-emitting element according to one aspect of the present invention, the step of forming the resistive layer includes a step of removing an intermediate layer located in the window region, and a step of forming an insulating layer or an oxidized intermediate layer in the portion from which the intermediate layer has been removed.

[0026] The step of forming the insulating layer or the oxidized intermediate layer can be carried out as part of a later manufacturing step of forming an insulating layer on the contact layer or a heat treatment step, so that an increase in the number of steps can be suppressed. Effect of the Invention

[0027] According to one aspect of the present invention, it is possible to suppress heat generation at the light emitting end surface while increasing the output of the semiconductor light emitting device. [Brief description of the drawings]

[0028] [Figure 1A] 1 is a cross-sectional view showing a configuration of a semiconductor light emitting element according to a first embodiment taken along an optical waveguide direction. [Figure 1B] FIG. 2 is an explanatory top view of the semiconductor light emitting element according to the first embodiment, as viewed from above. [Diagram 2] 5 is a cross-sectional view showing a configuration of a semiconductor light emitting element according to a second embodiment, cut along the optical waveguide direction. FIG. [Diagram 3] 11 is a cross-sectional view showing a configuration of a semiconductor light emitting element according to a third embodiment, cut along the optical waveguide direction. FIG. [Figure 4A] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. [Figure 4B] 10A to 10C are cross-sectional views illustrating an example of a manufacturing method for the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. [Figure 4C] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. [Figure 4D] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. [Figure 4E] 10A to 10C are cross-sectional views illustrating an example of a manufacturing method for the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. [Figure 4F] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. [Figure 4G] 10A to 10C are cross-sectional views illustrating an example of a manufacturing method for the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. [Figure 4H] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. [Figure 5A] 13A to 13C are cross-sectional views illustrating an example of a manufacturing method for the semiconductor light emitting device according to the fifth embodiment, taken along the optical waveguide direction. [Figure 5B] 13A to 13C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fifth embodiment, taken along the optical waveguide direction. [Figure 5C] 13A to 13C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fifth embodiment, taken along the optical waveguide direction. [Figure 5D] 13A to 13C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fifth embodiment, taken along the optical waveguide direction. [Figure 5E] 13A to 13C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fifth embodiment, taken along the optical waveguide direction. [Figure 5F] 13A to 13C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fifth embodiment, taken along the optical waveguide direction. [Figure 5G] 13A to 13C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fifth embodiment, taken along the optical waveguide direction. [Figure 6] FIG. 13 is a diagram showing results of a light-accelerated current test according to an embodiment, together with a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the present invention, and not all of the combinations of features described in the embodiments are necessarily essential to the configuration of the present invention. The configuration of the embodiments may be appropriately modified or changed depending on the specifications of the device to which the present invention is applied and various conditions (conditions of use, environment of use, etc.). The technical scope of the present invention is determined by the claims, and is not limited by the individual embodiments below. Also, the drawings used in the following description may differ in scale and shape from the actual structure in order to make each configuration easier to understand.

[0030] FIG. 1A is a cross-sectional view showing a configuration of a semiconductor light emitting element according to a first embodiment, cut along the optical waveguide direction. In the following description, an edge-emitting semiconductor laser element is taken as an example of the semiconductor light-emitting element. This semiconductor laser element may be an AlGaAs-based semiconductor laser element capable of emitting an infrared laser with a wavelength of 780 nm, or an AlGaInP-based semiconductor laser element capable of emitting a red laser with a wavelength of 650 nm. Furthermore, it may be an AlGaInN-based semiconductor laser element capable of emitting a blue laser with a wavelength of 405 nm. The edge-emitting semiconductor laser element may be a gain-guided semiconductor laser element or a refractive index-guided semiconductor laser element.

[0031] 1A, the semiconductor laser element Z1 includes an n-type semiconductor layer 2, an active layer 3, a p-type semiconductor layer 4, an intermediate layer 5, a contact layer 6, and a resistive layer R1 in a region corresponding to a window region WD. The n-type semiconductor layer 2, the active layer 3, the p-type semiconductor layer 4, the intermediate layer 5, and the contact layer 6 are sequentially stacked on an n-type semiconductor substrate 1. The resistive layer R1 is formed on the p-type semiconductor layer 4 so as to be adjacent to the intermediate layer 5 in the optical waveguide direction (also referred to as the resonator direction). The resistive layer R1 will be described in detail later, but it can be formed by, for example, making the intermediate layer 5 itself rough in a process of diffusing impurities into the semiconductor layer subsequent to the lower layer, in the intermediate layer 5 located in the window region WD.

[0032] The n-type semiconductor substrate 1 may comprise, for example, an n-type GaAs substrate. The n-type semiconductor layer 2 may comprise, for example, an n-type AlGaInP cladding layer. The active layer 3 may comprise, for example, an AlGaInP multi-quantum well (MQW) active layer in which barrier layers and well layers are alternately stacked. The p-type semiconductor layer 4 may comprise, for example, a p-type AlGaInP cladding layer. The intermediate layer 5 may comprise, for example, a p-type AlGaInP intermediate layer. The contact layer 6 may comprise, for example, a p-type GaAs contact layer.

[0033] The n-type semiconductor layer 2 may include an n-type buffer layer or an n-type guide layer in addition to the n-type cladding layer. Si (silicon) can be used as the n-type impurity. The p-type semiconductor layer 4 may include a p-type etch stop layer, a p-type carrier block layer, or a p-type guide layer in addition to the p-type cladding layer.

[0034] The active layer 3 has a front end face EA and a rear end face EB that are parallel to each other. In this case, the semiconductor laser element Z1 can form a resonator between the front end face EA and the rear end face EB of the active layer 3. The front end face EA can be used as a light emission face for emitting laser light from the semiconductor laser element Z1. In this case, the optical reflectance on the front end face EA side can be made lower than that on the rear end face EB side. The optical reflectance on the front end face EA side and the optical reflectance on the rear end face EB side can be adjusted by end face coating.

[0035] An intermediate layer 5 and a resistive layer R1 are formed on the p-type semiconductor layer 4. A contact layer 6 is formed on the intermediate layer 5. The contact layer 6 can form an ohmic junction with an electrode 8. In the contact layer 6, Zn (zinc) or C (carbon) can be used as a p-type impurity. In this case, the impurity concentration of the contact layer 6 is 1×10 18 ~1×10 21 (atoms / cm 3 The contact layer 6 has window regions WD recessed in the cavity direction from the front end face EA and the rear end face EB, respectively.

[0036] The intermediate layer 5 serves to reduce the band energy difference between the p-type semiconductor layer 4 and the contact layer 6. The intermediate layer 5 can have a lower resistance than the p-type semiconductor layer 4 by having a higher impurity concentration than the p-type semiconductor layer 4. In this case, the impurity concentration of the p-type semiconductor layer 4 is 1×10 17 ~5×10 18 (atoms / cm 3 ), and the impurity concentration of the intermediate layer 5 is set to 1×10 18 ~1×10 20 (atoms / cm 3As the p-type impurity for p-type semiconductor layer 4 and intermediate layer 5, Mg (magnesium) or Zn can be used.

[0037] The resistive layer R1 is provided on the p-type semiconductor layer 4 on the front end face EA side and the rear end face EB side, and has a higher resistance than the intermediate layer 5. In this case, the resistive layer R1 may have a roughened structure obtained by roughening the surface of the intermediate layer 5 located in the window region WD, or may have an uneven structure formed on the intermediate layer 5 located in the window region WD. At least a part of the concave portion of the uneven structure provided on the intermediate layer 5 may reach the p-type semiconductor layer 4. In the example of FIG. 1A, an example in which the resistive layer R1 is provided on the front end face EA and the rear end face EB is shown, but the resistive layer R1 may be provided on at least one of the front end face EA and the rear end face EB, and for example, the resistive layer R1 may be provided only on the front end face EA side. The roughened structure or uneven structure provided on the intermediate layer 5 can be confirmed by observing a cross section of the resistive layer R1 cut in a direction perpendicular to the resonator direction with a SEM (scanning electron microscope).

[0038] Moreover, the window region WD is provided with a mixed crystal region DF in which the active layer 3 is mixed. The mixed crystal region DF may extend from the p-type semiconductor layer 4 to the active layer 3 and further to the n-type semiconductor layer 2. By providing the mixed crystal region DF in which the active layer 3 is mixed in the window region WD, the band gap of the active layer 3 in the mixed crystal region DF can be expanded. This makes it possible to reduce the absorption of laser light on the front end facet EA side and the rear end facet EB side, and to suppress heat generation at the end facets on the front end facet EA side and the rear end facet EB side. As a result, COD can be suppressed.

[0039] The mixed crystal region DF can be formed based on the impurity diffused through the window region WD. For example, Zn (zinc) can be used as the impurity. Here, the contact layer 6 using GaAs has a slower diffusion rate of the impurity than the p-type semiconductor layer 4 and the intermediate layer 5 using AlGaInP. Therefore, by removing a part of the contact layer 6 and providing the window region WD, it is possible to suppress an increase in the time required for the diffusion of the impurity to form the mixed crystal region DF. Therefore, it is possible to suppress the progress of the destruction of the crystal of the active layer 3 during the diffusion of the impurity to form the mixed crystal region DF, and it is possible to suppress the deterioration of characteristics such as an increase in the threshold current. At this time, by adjusting the conditions of the heat treatment for diffusing the impurity through the window region WD, it is possible to provide an uneven structure in the intermediate layer 5 located in the window region WD.

[0040] In FIG. 1A, an insulating layer 7 is formed on the resistive layer R1. The insulating layer 7 is, for example, a silicon oxide film or a silicon nitride film. In this case, the insulating layer 7 can be formed so as to be embedded in the uneven structure of the intermediate layer 5 located in the window region WD. Also, as shown in FIG. 1B, an opening 7A that becomes a current injection region RN is formed in the insulating layer 7 (FIG. 1B is a drawing in which the electrode 8 is omitted for the sake of explanation). At this time, a current non-injection region RU into which a current is not injected through the interface with the electrode 8 is formed around the opening 7A. In FIG. 1B, a resistive layer R1 made of the uneven structure of the intermediate layer 5 is formed near both ends (near the left and right ends in the drawing) of the ridge portion OG that forms the optical waveguide.

[0041] 1A, the electrode 8 is formed on the insulating layer 7, but in the region of the opening 7A, it is formed on the contact layer 6. The electrode 8 may be formed of a single metal film such as Au (gold) or may be formed of a laminated structure of metals such as Ti (titanium) / Pt (platinum) / Au.

[0042] An end face protective film 9A is formed on the front end face EA side of the active layer 3, and an end face protective film 9B is formed on the rear end face EB side of the active layer 3. The end face protective film 9A can have a lower optical reflectance than the end face protective film 9B. The end face protective films 9A and 9B can be made of, for example, aluminum nitride, silicon nitride, aluminum oxide, silicon oxide, or a laminate structure thereof.

[0043] Here, by providing the intermediate layer 5 between the p-type semiconductor layer 4 and the contact layer 6, and then providing the resistive layer R1 located in the window region WD on the p-type semiconductor layer 4, it is possible to reduce the energy difference in the conduction band level caused by the difference in band gap energy of each material between the contact layer 6 and the p-type semiconductor layer 4, thereby reducing resistance. In addition, it is possible to suppress the current flowing to the front end facet EA side and the rear end facet EB side via the intermediate layer 5. This makes it possible to suppress heat generation due to the current on the front end facet EA side and the rear end facet EB side, thereby suppressing COD while achieving high output.

[0044] Furthermore, by providing a resistive layer R1 on the p-type semiconductor layer 4 at the position of the window region WD and providing a mixed crystal region DF in the active layer 3, it is possible to suppress heat generation due to current flowing on the front end facet EA side and the rear end facet EB side. Furthermore, by widening the band gap of the active layer 3 on the front end facet EA side and the rear end facet EB side, it is possible to suppress heat generation due to absorption of laser light on the front end facet EA side and the rear end facet EB side. Therefore, it is possible to suppress not only the temperature rise due to the current flowing on the front end facet EA side and the rear end facet EB side, but also the temperature rise due to absorption of laser light on the front end facet EA side and the rear end facet EB side. As a result, it is possible to suppress COD while achieving high output.

[0045] At the cavity end faces (front end face EA and rear end face EB) of the semiconductor laser element Z1, adsorption of oxygen on the semiconductor surface and oxidation of the surface occur. As a result, a specific level occurs near the cavity end face, and the forbidden band width of the semiconductor near the cavity end face is substantially narrowed. As a result, the vicinity of the cavity end face of the semiconductor laser element Z1 becomes an absorption region for the light generated inside the cavity, causing COD. Non-radiative recombination via the surface state present near the cavity end face causes a temperature rise, so that the forbidden band width near the cavity end face is further reduced. As a result, a positive feedback occurs in which light absorption becomes more likely to occur. Here, by providing the mixed crystal region DF at the position of the window region WD, it is possible to widen the band gap near the cavity end face and suppress light absorption, and it is possible to reduce heat generation due to light absorption near the cavity end face.

[0046] On the other hand, heat generation near the resonator end face is caused not only by light absorption but also by the current flowing near the resonator end face. In order to reduce the resistance of the element, the p-type impurity concentration of the intermediate layer 5 and the contact layer 6 is increased to reduce the resistance. In this state, the leakage current flowing near the resonator end face through the intermediate layer 5 increases. As a result, the current flowing near the resonator end face increases, and the heat generation due to the current near the resonator end face increases. Here, by providing a current non-injection region RU and a resistive layer R1 on the p-type semiconductor layer 4 near the resonator end face, it is possible to suppress the leakage current near the resonator end face through the contact layer 6 and the intermediate layer 5. This makes it possible to reduce the heat generation near the resonator end face due to the current flowing near the resonator end face.

[0047] Furthermore, by providing a concave-convex structure in intermediate layer 5 located in window region WD, it is possible to increase the resistance of intermediate layer 5 on the front end facet EA side and the rear end facet EB side. This makes it possible to suppress heat generation due to current flowing to the front end facet EA side and the rear end facet EB side. At this time, by adjusting the heat treatment temperature for diffusing impurities into active layer 3 through window region WD, it is possible to provide a concave-convex structure in intermediate layer 5 on the front end facet EA side and the rear end facet EB side. The heat treatment step for impurity diffusion also serves as a step for forming the concave-convex structure, thereby suppressing an increase in the number of steps.

[0048] Fig. 2 is a cross-sectional view showing the configuration of the semiconductor light emitting device according to the second embodiment cut along the optical waveguide direction. In the following description, parts different from the configuration in Fig. 1A will be described, and parts that are the same as those in Fig. 1A will be denoted by the same reference numerals and description thereof will be omitted.

[0049] In FIG. 2, the semiconductor laser element Z2 includes a resistive layer R2 instead of the resistive layer R1 of the semiconductor laser element Z1 of FIG. 1A. The resistive layer R2 is a layer including an oxide obtained by oxidizing a part of the intermediate layer 5. The oxide is, for example, gallium oxide (Ga2O3). In this case, the resistive layer R2 may include an uneven structure obtained by roughening the surface of the intermediate layer 5 together with the oxide obtained by oxidizing a part of the intermediate layer 5. At least a part of the oxide obtained by oxidizing a part of the intermediate layer 5 may reach the p-type semiconductor layer 4. The oxide obtained by oxidizing a part of the intermediate layer 5 can be formed by adjusting the heat treatment temperature during impurity diffusion for forming the mixed crystal region DF. In this case, there is no need to provide an oxidation step for oxidizing a part of the intermediate layer 5 separately from the impurity diffusion step for forming the mixed crystal region DF, and an increase in the number of steps can be suppressed.

[0050] Here, by providing resistive layer R2 located in window region WD on p-type semiconductor layer 4, it is possible to suppress current flowing to the front end facet EA side and the rear end facet EB side through intermediate layer 5. This makes it possible to suppress heat generation on the front end facet EA side and the rear end facet EB side, thereby suppressing COD while achieving high output.

[0051] FIG. 3 is a cross-sectional view showing a configuration of the semiconductor light emitting element according to the third embodiment taken along the optical waveguide direction.

[0052] In FIG. 3, the semiconductor laser element Z3 includes a resistive layer R3 instead of the resistive layer R1 of the semiconductor laser element Z1 of FIG. 1A. The resistive layer R3 can be made of an insulator. The resistive layer R3 can be made of, for example, a silicon oxide film or a silicon nitride film. The intermediate layer 5 is removed at the position of the resistive layer R3. The resistive layer R3 can be formed on the p-type semiconductor layer 4 by embedding an insulating layer in the position where the intermediate layer 5 is removed. The material of the insulator used for the resistive layer R3 may be different from the material of the insulating layer 7 or may be the same as the material of the insulating layer 7. Here, if the material of the insulator used for the resistive layer R3 is the same as the material of the insulating layer 7, the resistive layer R3 can be formed in the process of forming the insulating layer 7. Therefore, it is not necessary to provide a process of forming the resistive layer R3 separately from the process of forming the insulating layer 7, and an increase in the number of processes can be suppressed.

[0053] Here, by providing resistive layer R3 located in window region WD on p-type semiconductor layer 4, it is possible to suppress current flowing to the front end facet EA side and the rear end facet EB side through intermediate layer 5. This makes it possible to suppress heat generation on the front end facet EA side and the rear end facet EB side, thereby suppressing COD while achieving high output.

[0054] Furthermore, in this embodiment, since the resistive layer R3 is provided on the p-type semiconductor layer 4 in addition to the process of forming the insulating layer 7, the heat treatment time and heat treatment temperature in the impurity diffusion process for forming the mixed crystal region DF can be appropriately set, and the conditions for forming the mixed crystal region DF can be optimized.

[0055] 4A to 4H are cross-sectional views showing an example of a method for manufacturing the semiconductor light emitting device according to the fourth embodiment, taken along the optical waveguide direction. Note that the fourth embodiment shows an example of a method for manufacturing the semiconductor laser device Z1 of FIG. 1A.

[0056] 4A, an n-type semiconductor layer 2, an active layer 3, a p-type semiconductor layer 4, an intermediate layer 5, and a contact layer 6 are sequentially stacked on an n-type semiconductor substrate 1 by epitaxial growth. At this time, the impurity concentration of the intermediate layer 5 is made higher than the impurity concentration of the p-type semiconductor layer 4, and the impurity concentration of the contact layer 6 is made higher than the impurity concentration of the intermediate layer 5. The epitaxial growth may be performed by MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), or HVPE (Hydride Vapor Phase Epitaxy).

[0057] 4B, the contact layer 6 is patterned by using photolithography and etching techniques to form a window region WD in the contact layer 6. The window region WD may also be formed in the contact layer 6 by using photolithography and lift-off techniques.

[0058] Next, as shown in FIG. 4C, a protective film 9 is formed on the contact layer 6 by a method such as plasma CVD or sputtering. The protective film 9 is a film for preventing the diffusion of impurities such as Zn. The protective film 9 is, for example, a silicon oxide film or a silicon nitride film. Then, the protective film 9 is patterned by using photolithography and etching techniques, and the protective film 9 in the window region WD is removed.

[0059] Next, as shown in FIG. 4D, impurities are deposited by plasma CVD or sputtering so as to cover the window region WD. diffusion The source 10 is formed on the protective film 9. diffusion The material of the source 10 may be, for example, ZnO.

[0060] Next, as shown in FIG. 4E, the impurity diffusion The n-type semiconductor substrate 1 with the window region WD covered is heat-treated by the source 10, so that the impurity diffusionImpurities are diffused from the source 10 to the crystal side (semiconductor substrate 1 side) to mix the active layer 3. This heat treatment is performed in a nitrogen atmosphere environment at a temperature and time that are capable of preventing crystal destruction that would cause deterioration of the characteristics of the semiconductor laser element Z1.

[0061] At this time, the impurities are diffused into the p-type semiconductor layer 4, the active layer 3, and the n-type semiconductor layer 2 through the intermediate layer 5 located in the window region WD. In this process, a part of the intermediate layer 5 located in the window region WD is lost, and a rough state can be obtained. As a result, the intermediate layer 5 located in the window region WD is made highly resistive, and a resistive layer R1 located in the window region WD can be formed on the p-type semiconductor layer 4. Note that the impurities diffusion When the impurities are diffused from the source 10 to the crystal side, the impurities diffusion A part of the intermediate layer 5 located in the window region WD is oxidized by the oxygen contained in the source 10, and an oxide can be formed in the part of the intermediate layer 5 located in the window region WD. This allows not only the roughening of the intermediate layer 5 but also the oxidation to contribute to increasing the resistance of the intermediate layer 5 located in the window region WD, and the resistance of the intermediate layer 5 located in the window region WD can be efficiently increased while suppressing an increase in the number of steps. Note that in this description, in order to increase the resistance of the intermediate layer 5 located in the window region WD, an impurity is added. diffusion A heat treatment was used to diffuse impurities from the source 10 to the crystal side. diffusion A heat treatment other than that which diffuses impurities from source 10 into the crystal may also be used.

[0062] Next, as shown in FIG. 4F, impurities are removed from the contact layer 6 and the resistive layer R1 by a method such as etching. diffusion The source 10 and the protective film 9 are removed.

[0063] Next, as shown in Fig. 4G, an insulating layer 7 made of a silicon oxide film, a silicon nitride film, or the like is formed on the contact layer 6 and the resistive layer R1 by a method such as plasma CVD. Then, the insulating layer 7 is patterned by using photolithography and etching techniques to form an opening 7A in the insulating layer 7 that will become the current injection region RN in Fig. 1A (see Fig. 1B).

[0064] 4H, an electrode 8 connected to the contact layer 6 through the opening 7A is formed on the insulating layer 7 by using a method such as sputtering or vapor deposition. Furthermore, the n-type semiconductor substrate 1 on which the electrode 8 connected to the contact layer 6 has been formed is cleaved into a bar shape. Then, an end face protective film 9A is formed on the front end face EA side of the active layer 3 by a method such as sputtering, and an end face protective film 9B is formed on the rear end face EB side of the active layer 3.

[0065] In the above-described embodiment, a method for increasing the resistance of the intermediate layer 5 located in the window region WD based on a heat treatment of the intermediate layer 5 has been described, but the resistance of the intermediate layer 5 located in the window region WD may also be increased by implanting ions into the intermediate layer 5 through the window region WD. For example, by implanting hydrogen ions or helium ions into the intermediate layer 5 located in the window region WD, the intermediate layer 5 can be made amorphous and increased in resistance.

[0066] 5A to 5G are cross-sectional views taken along the optical waveguide direction illustrating an example of a method for manufacturing the semiconductor light emitting device according to the fifth embodiment. Note that the fifth embodiment illustrates an example of a method for manufacturing the semiconductor laser device Z3 of FIG.

[0067] In FIG. 5A, impurities are removed so that the window region WD is covered by the same process as in FIG. 4A to FIG. 4D. diffusion The source 10 is formed on the protective film 9 .

[0068] Next, as shown in FIG. 5B, the impurity diffusion The n-type semiconductor substrate 1 with the window region WD covered is heat-treated by the source 10, so that the impurity diffusion Impurities are diffused from the source 10 into the crystal side to mix the active layer 3. This heat treatment is performed in a nitrogen atmosphere environment at a temperature and time that can prevent crystal destruction that would cause deterioration of the characteristics of the semiconductor laser element Z1. In this embodiment, since a separate insulating layer is provided in a process to be described later (FIGS. 5D, 5E, and 5F), it is not necessary to increase the resistance of the intermediate layer 5 located in the window region WD in this heat treatment process. Therefore, the conditions for forming the mixed crystal region DF can be optimized.

[0069] Next, as shown in FIG. 5C, the impurities are removed from the contact layer 6 and the window region WD by a method such as etching. diffusion The source 10 and the protective film 9 are removed.

[0070] Next, as shown in FIG. 5D, the intermediate layer 5 is patterned by using photolithography and etching techniques, and the intermediate layer 5 in the window region WD is removed.

[0071] 5E, an insulating layer such as a silicon oxide film or a silicon nitride film is deposited on the contact layer 6 and the p-type semiconductor layer 4 by a method such as plasma CVD. Then, the insulating layer on the contact layer 6 is removed by using a photolithography technique and a dry etching technique, and a resistive layer R3 made of the insulating layer is formed in the position of the window region WD.

[0072] Next, as shown in Fig. 5F, an insulating layer 7 made of a silicon oxide film or the like is formed on the contact layer 6 and the resistive layer R3 by a method such as plasma CVD. Then, the insulating layer 7 is patterned by using photolithography and etching techniques to form an opening 7A in the insulating layer 7, which will become the current injection region RN in Fig. 1A.

[0073] Next, as shown in FIG. 5G, an electrode 8 is formed on insulating layer 7 in a process similar to that shown in FIG. 4H, an end face protective film 9A is formed on the front end face EA side of active layer 3, and an end face protective film 9B is formed on the rear end face EB side of active layer 3.

[0074] In the above-described fifth embodiment, an example was shown in which the step of forming the resistive layer R3 in Fig. 5E was provided separately from the step of forming the insulating layer 7 in Fig. 5F, but the resistive layer R3 may be formed in the step of forming the insulating layer 7 in Fig. 5F. In this case, it is not necessary to provide the step of Fig. 5E, and the number of steps can be reduced.

[0075] 6 is a diagram showing the results of a light-accelerated current test according to the embodiment together with a comparative example. In this light-accelerated current test, the mean time to failure (MTTF) leading to COD breakdown and the threshold current were examined for the comparative example and examples 1 to 3 in which the heat treatment time in the step of FIG. 4E was changed.

[0076] 6, when the heat treatment time was short (Example 1), the improvement in mean time to failure was smaller than that of the comparative example. This is presumably because when the heat treatment time is short, the resistance of intermediate layer 5 located in window region WD is not sufficiently increased, and the effect of suppressing the current flowing on the front end facet EA side and the rear end facet EB side is small.

[0077] When the heat treatment time was increased (Example 2), the mean time to failure was improved by more than three times compared to the comparative example, and there was no deterioration in characteristics such as an increase in threshold current. This is presumably because increasing the heat treatment time increases the resistance of intermediate layer 5 located in window region WD, which increases the effect of suppressing the current flowing on the front end facet EA side and the rear end facet EB side.

[0078] When the heat treatment time was too long (Example 3), the mean time to failure was improved by more than five times compared to the comparative example, but deterioration of characteristics such as an increase in threshold current was observed. It is presumed that when the heat treatment time is too long, not only does the resistance of the intermediate layer 5 located in the window region WD increase, but also crystal destruction progresses, resulting in deterioration of characteristics.

[0079] In the above-described embodiment, an example has been shown in which an n-type semiconductor layer is used as the first conductive type semiconductor layer and a p-type semiconductor layer is used as the second conductive type semiconductor layer, but a p-type semiconductor layer may be used as the first conductive type semiconductor layer and an n-type semiconductor layer may be used as the second conductive type semiconductor layer. [Explanation of symbols]

[0080] 1 n-type semiconductor substrate 2 n-type semiconductor layer 3 Active layer 4 p-type semiconductor layer 5. Middle Tier 6 Contact layer 7 Insulating layer 8 electrodes 9A, 9B end face protective films R1~R3 resistance layers RN current injection region RU non-current injection region

Claims

1. A first conductivity type semiconductor layer; an active layer located on the first conductive type semiconductor layer and having end faces parallel to each other; a second conductive type semiconductor layer located on the active layer; a contact layer located on the second conductive type semiconductor layer and capable of making an ohmic contact with an electrode; an intermediate layer located between the second conductive type semiconductor layer and the contact layer and having an impurity concentration higher than that of the second conductive type semiconductor layer; a resistive layer provided on the second conductive type semiconductor layer in the vicinity of at least one of the end faces, the resistive layer having a higher resistance than the intermediate layer; The semiconductor light-emitting element, wherein the resistive layer has a concave-convex structure formed on the intermediate layer.

2. A first conductivity type semiconductor layer; an active layer located on the first conductive type semiconductor layer and having end faces parallel to each other; a second conductive type semiconductor layer located on the active layer; a contact layer located on the second conductive type semiconductor layer and capable of making an ohmic contact with an electrode; an intermediate layer located between the second conductive type semiconductor layer and the contact layer and having an impurity concentration higher than that of the second conductive type semiconductor layer; a resistive layer provided on the second conductive type semiconductor layer in the vicinity of at least one of the end faces, the resistive layer having a higher resistance than the intermediate layer; The semiconductor light-emitting element, wherein the resistive layer comprises an oxide formed by oxidizing a portion of the intermediate layer.

3. a window region is provided at a position corresponding to the vicinity of an end face of the active layer, the window region being located in a region recessed from the end face toward the cavity; 3. The semiconductor light emitting device according to claim 1, wherein the active layer comprises a mixed crystal region which is mixed with impurities diffused through the window region.

4. The semiconductor light emitting device according to claim 3 , wherein the resistive layer is located in the window region.

5. The semiconductor light-emitting element according to claim 1 , wherein at least a portion of the recess of the uneven structure reaches the second conductive type semiconductor layer.

6. The semiconductor light-emitting device according to claim 1 , wherein the resistive layer is an insulating layer provided on the second conductive type semiconductor layer.

7. A step of sequentially forming a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on a semiconductor substrate; forming an intermediate layer and a contact layer in sequence on the second conductive type semiconductor layer; forming a window region by removing a portion of the contact layer at a position corresponding to the vicinity of an end face of the active layer; forming a resistive layer having a resistance higher than that of the intermediate layer at the position of the window region; The step of forming the resistive layer includes: removing the intermediate layer located in the window area; A method for manufacturing a semiconductor light-emitting device, comprising the step of forming an insulating layer or an oxidized intermediate layer in the portion from which the intermediate layer has been removed.

8. 8. The method for manufacturing a semiconductor light emitting device according to claim 7, wherein the step of forming the resistive layer comprises a step of performing a heat treatment in a state where an impurity diffusion source is in contact with the intermediate layer at the position of the window region.

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