Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing damage to a semiconductor substrate and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor substrate; a first metal layer provided on the semiconductor substrate; a second metal layer provided on the first metal layer and made from a material containing Ni; and a third metal layer provided on the second metal layer and made from a material containing Cu or Ni. Vickers hardness of the second metal layer is 400Hv or more and harder than the third metal layer. The third metal layer is harder than the first metal layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses the structure of a surface electrode of a power semiconductor device. This surface electrode is provided with a first Cu layer formed by electroless plating mainly composed of Cu with a Vickers hardness of 200 to 350 Hv. A second Cu layer formed by electroless plating mainly composed of Cu with a Vickers hardness of 70 to 150 Hv, which is softer than the first Cu layer, is provided on the first Cu layer. A Cu wire is wire-bonded to the second Cu layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-37684 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, two electroless Cu plating layers are laminated as a surface electrode in order to suppress damage to the semiconductor chip during wire bonding. In general, in electroless Cu plating, it is necessary to increase the impurity concentration in order to increase the Vickers hardness. However, increasing the impurity concentration may cause voids due to the impurities, which may make it difficult to increase the Vickers hardness. For this reason, it may not be possible to sufficiently suppress damage to the semiconductor chip.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress damage to a semiconductor substrate. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a semiconductor substrate, a first metal layer provided on the semiconductor substrate, a second metal layer provided on the first metal layer and containing Ni as a material, and a third metal layer provided on the second metal layer and containing Cu or Ni as a material, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer. The second metal layer is an electroless NiP plating layer, and the third metal layer is an electrolytic Cu plating layer. . The semiconductor device according to the present disclosure comprises a semiconductor substrate, a first metal layer provided on the semiconductor substrate, a second metal layer provided on the first metal layer and containing Ni as a material, a third metal layer provided on the second metal layer and containing Cu or Ni as a material, and an insulating film provided between the semiconductor substrate and the first metal layer and having an opening for exposing the semiconductor substrate, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, the third metal layer is harder than the first metal layer, the first metal layer is electrically connected to the semiconductor substrate through the opening, the insulating film has a plurality of the openings formed in a dot shape in a planar view, and an uneven surface is formed on the third metal layer. The semiconductor device according to the present disclosure comprises a semiconductor substrate, a first metal layer provided on the semiconductor substrate, a second metal layer provided on the first metal layer and containing Ni as a material, a third metal layer provided on the second metal layer and containing Cu or Ni as a material, and a resin layer provided on a portion of an upper surface of the first metal layer and covered by the second metal layer, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer.

[0007] The method for manufacturing a semiconductor device according to the present disclosure includes forming a first metal layer on a semiconductor substrate, and forming a Ni P A second metal layer including electroless The second metal layer is formed by plating. u A third metal layer including With electrolytic plating The second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer. Effect of the Invention

[0008] In the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure, the hard second metal layer can suppress damage to the semiconductor substrate caused by wire bonding or the like. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Diagram 3] FIG. 11 is a cross-sectional view of a semiconductor device according to a modified example of the second embodiment. [Figure 4] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Diagram 5] FIG. 13 is a cross-sectional view of a semiconductor device according to a modified example of the third embodiment. [Figure 6]FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 8] FIG. 13 is a plan view of a semiconductor device according to a modification of the fifth embodiment. [Figure 9] FIG. 13 is a perspective view of a semiconductor device according to a sixth embodiment. [Figure 10] 10 is a cross-sectional view obtained by cutting FIG. 9 along line AB. [Figure 11] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh embodiment. [Figure 12] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth embodiment. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A semiconductor device and a method of manufacturing the semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0011] Embodiment 1 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 is a power semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 100 includes a semiconductor substrate. The semiconductor substrate ranges from a base layer 3 to a collector layer 8 in FIG. 1.

[0012] The semiconductor substrate has a drift layer 1 of a first conductivity type between an upper surface and a rear surface opposite to the upper surface. A carrier accumulation layer 2 of a first conductivity type is provided on the upper surface side of the drift layer 1. A base layer 3 of a second conductivity type is provided on the upper surface side of the carrier accumulation layer 2. An emitter layer 5 of a first conductivity type and a contact layer 6 of a second conductivity type are provided on the upper surface side of the base layer 3. An active trench 10 and a dummy trench 13 are formed in the semiconductor substrate. The active trench 10 penetrates from the upper surface of the semiconductor substrate through the emitter layer 5, the base layer 3, and the carrier accumulation layer 2 to reach the drift layer 1. A gate electrode 11 is formed on the inner wall of the active trench 10 via a gate insulating film 12.

[0013] A buffer layer 7 is provided on the back surface side of the drift layer 1. A collector layer 8 of the second conductivity type is provided on the back surface side of the buffer layer 7. A collector electrode 9 is provided on the back surface of the semiconductor substrate.

[0014] A first metal layer 20 is provided on the upper surface of the semiconductor substrate. An interlayer insulating film 4 having an opening for exposing the semiconductor substrate is provided between the semiconductor substrate and the first metal layer 20. The first metal layer 20 is electrically connected to the semiconductor substrate through the opening of the interlayer insulating film 4. The first metal layer 20 is an emitter electrode. A second metal layer 21 is provided on the first metal layer 20. The second metal layer 21 contains Ni as a material. The second metal layer 21 may be mainly composed of Ni. A third metal layer 22 containing Cu or Ni as a material is provided on the second metal layer. The third metal layer 22 may be mainly composed of Cu. The second metal layer 21 is harder than the third metal layer 22. The third metal layer 22 is harder than the first metal layer 20.

[0015] A method for manufacturing the semiconductor device 100 according to the present embodiment will be described. First, each semiconductor layer shown in FIG. 1 is formed on a semiconductor substrate. Next, a first metal layer 20 is formed on the semiconductor substrate. Next, a second metal layer 21 is formed on the first metal layer 20 by plating. The second metal layer 21 is formed, for example, by electroless NiP plating. Next, a third metal layer 22 containing Cu or Ni as a material is formed on the second metal layer 21. The third metal layer 22 is formed, for example, by electrolytic Cu plating. Next, a collector electrode 9 is formed on the back surface of the semiconductor substrate. This is not limited to this, and the collector electrode 9 may be formed before the formation of the third metal layer 22. For example, the collector electrode 9 may be formed after the formation of the first metal layer 20, and then the second metal layer 21 may be formed.

[0016] A wire or solder is bonded to the third metal layer 22. The semiconductor device 100 is electrically connected to the outside via the wire or solder. In this embodiment, a hard second metal layer 21 is disposed under the third metal layer 22. This makes it possible to suppress damage to the semiconductor substrate during wire bonding or solder bonding. Furthermore, a soft first metal layer 20 is disposed under the second metal layer 21. This makes the first metal layer 20 a buffer material, making it possible to further suppress damage to the semiconductor substrate. The Vickers hardness of the second metal layer 21 is preferably 400 Hv or more.

[0017] The second metal layer 21 may contain P as an impurity. That is, the second metal layer 21 may be an electroless NiP plating layer. In this case, the Vickers hardness of the second metal layer 21 is, for example, 600 to 1300 Hv. With electroless NiP plating, the Vickers hardness of the second metal layer 21 can be 600 Hv or more even considering the variation. It has been confirmed that when P is added to Ni as an impurity, the voids do not increase even if the proportion of P is increased. Furthermore, by forming the second metal layer 21 by electroless plating, it is possible to easily inject impurities. Therefore, it is possible to easily increase the Vickers hardness.

[0018] As long as the Vickers hardness can be made 400 Hv or more, the second metal layer 21 may be formed by a method other than electroless NiP plating. For example, the second metal layer 21 may be formed by electrolytic Ni plating. In general, electrolytic Ni plating can achieve a Vickers hardness of 200 to 500 Hv.

[0019] When the second metal layer 21 is a plating layer, the Vickers hardness can be made higher than when the second metal layer 21 is a sputtered electrode mainly composed of Ni. The Vickers hardness of a Ni electrode formed by sputtering is generally 100 Hv or less.

[0020] The third metal layer 22 is, for example, an electrolytic Cu plating layer. The Vickers hardness of the third metal layer 22 is, for example, 100 to 300 Hv. In general, impurities are easily mixed into electroless Cu plating. Therefore, there is a possibility that voids due to impurities may occur. In contrast, electrolytic Cu plating can suppress the mixing of impurities, so that voids in the Cu plating can be suppressed. By suppressing voids in the electrode, reliability against heat cycles, power cycles, and the like can be improved. The Vickers hardness of the outermost third metal layer 22 does not need to be high. Therefore, it is not necessary to inject a large amount of impurities into the third metal layer 22 by electroless Cu plating. If the amount of impurities can be adjusted, the third metal layer 22 may be formed by electroless Cu plating.

[0021] Furthermore, if the second metal layer 21 is harder than the third metal layer 22, the third metal layer 22 may be mainly composed of Ni. By forming the second metal layer 21 as a plating layer mainly composed of Ni, which has a high Vickers hardness, it is possible to easily satisfy the relationship that the second metal layer 21 is harder than the third metal layer 22. Therefore, damage to the semiconductor device 100 during wire bonding can be easily suppressed.

[0022] The structure of the front surface electrode of this embodiment can be applied to semiconductor devices other than IGBTs. The semiconductor device 100 may be, for example, a diode, a reverse-conducting (RC) IGBT, or a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0023] The semiconductor substrate may be made of a wide band gap semiconductor. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride material, or diamond. According to this embodiment, the voids in the electrode can be suppressed. Therefore, even when the semiconductor substrate is made of a wide band gap semiconductor and operates at high temperatures, the reliability against heat cycles can be improved.

[0024] These modifications can be appropriately applied to the semiconductor devices and semiconductor device manufacturing methods according to the following embodiments. Note that the semiconductor devices and semiconductor device manufacturing methods according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0025] Embodiment 2 2 is a cross-sectional view of a semiconductor device 101 according to a second embodiment. The semiconductor device 101 differs from the semiconductor device 100 in the structure of the surface electrode. The other structures are similar to those of the semiconductor device 100. The semiconductor device 101 includes a barrier metal layer 23 provided between the semiconductor substrate and the first metal layer 20. The barrier metal layer 23 is electrically connected to the semiconductor substrate through an opening in the interlayer insulating film 4. The barrier metal layer 23 is harder than the first metal layer 20.

[0026] This configuration allows for good contact between the semiconductor substrate and the surface electrode, stabilizing electrical characteristics, and further suppressing damage to the semiconductor substrate even if the first metal layer 20 is crushed during wire bonding.

[0027] 3 is a cross-sectional view of a semiconductor device 102 according to a modification of the second embodiment. In the semiconductor device 101, a barrier metal layer 23 is provided on the entire surface of the IGBT cell. However, as shown in FIG. 3, a fourth metal layer 24, which is an embedded electrode layer, may be provided in an opening of the interlayer insulating film 4. The fourth metal layer 24 electrically connects the semiconductor substrate and the first metal layer 20. The fourth metal layer 24 is formed of, for example, tungsten.

[0028] Embodiment 3 4 is a cross-sectional view of a semiconductor device 103 according to a third embodiment. The semiconductor device 103 differs from the semiconductor device 100 in that it includes an oxidation prevention film 25 provided on the third metal layer 22. The other structures are similar to those of the semiconductor device 100. For example, a benzotriazole-based component is used for the oxidation prevention film 25. When performing wire bonding or solder bonding, it is desirable to remove the oxidation prevention film 25 by formic acid reflow or the like.

[0029] The surface of the third metal layer 22, which is mainly composed of Cu, is easily oxidized. According to the present embodiment, the oxidation of the third metal layer 22 can be suppressed, and the wire bondability and the solder bondability can be improved. This allows the wire or solder to be bonded without applying excessive energy to the semiconductor device 103. This makes it possible to mitigate damage to the semiconductor substrate.

[0030] 5 is a cross-sectional view of a semiconductor device 104 according to a modification of the third embodiment. In the semiconductor device 104, the wire 26 penetrates the oxidation-resistant film 25 and is electrically connected to the third metal layer 22. The wire 26 may contain, for example, Cu as a material. When the oxidation-resistant film 25 is a thin film, the wire bonding may be performed by breaking through the oxidation-resistant film 25 without removing the oxidation-resistant film 25. This eliminates the need for a step of reducing the chip, such as formic acid reflow, and reduces process costs.

[0031] Embodiment 4 6 is a cross-sectional view of a semiconductor device 105 according to a fourth embodiment. The semiconductor device 105 includes an adhesion layer 27 between the second metal layer 21 and the third metal layer 22, which adheres the second metal layer 21 and the third metal layer 22 to each other. The other structures are similar to those of the semiconductor device 100. The adhesion layer 27 is made of, for example, Ti, TiW, W, Ta, TaN, or Mo. The adhesion layer 27 is formed by, for example, PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition).

[0032] According to this embodiment, the second metal layer 21 and the third metal layer 22 are in close contact with each other, so that the energy of wire bonding can be transmitted efficiently. Therefore, bonding can be performed without applying excessive energy to the semiconductor substrate, and damage to the semiconductor substrate can be reduced.

[0033] Instead of the adhesion layer 27, an Au layer may be provided between the second metal layer 21 and the third metal layer 22. The second metal layer 21 is mainly composed of Ni and is therefore easily oxidized during the manufacturing process. The Au layer can suppress the oxidation of the second metal layer 21. Therefore, the variation in the electrical characteristics of the surface electrodes can be suppressed.

[0034] Embodiment 5. 7 is a cross-sectional view of a semiconductor device 106 according to a fifth embodiment. The semiconductor device 106 includes a well region 14 of a second conductivity type at the boundary between the cell region and the termination region. A resurf region 15 is provided on the upper surface side of the termination region. A gate wiring 17 is provided on the well region 14. A field oxide film 16 is provided on the resurf region 15. A first protective film 18 is formed so as to cover the field oxide film 16 and the gate wiring 17. A second protective film 19 is formed on the upper surface of the first protective film 18.

[0035] The second protective film 19 is provided on a part of the upper surface of the first metal layer 20 in the cell region, and is covered with the second metal layer 21. The second protective film 19 is, for example, a resin layer. The heat insulating effect of the second protective film 19 can suppress the transfer of heat during wire bonding to the first metal layer 20. Therefore, the first metal layer 20 can be suppressed from being crushed.

[0036] The second protective film 19 is disposed, for example, over the entire cell region. The arrangement of the second protective film 19 is not limited thereto. Fig. 8 is a plan view of a semiconductor device 106a according to a modification of the fifth embodiment. The second protective film 19 may be disposed only directly below the region to be wire-bonded.

[0037] Embodiment 6 FIG. 9 is a perspective view of a semiconductor device 107 according to a sixth embodiment. FIG. 10 is a cross-sectional view obtained by cutting FIG. 9 along line AB. In FIG. 9, the first metal layer, the second metal layer, and the third metal layer are omitted. The semiconductor device 107 is a MOSFET. In the semiconductor device 107, an epitaxial layer 28 of a first conductivity type is provided on the upper surface side of a semiconductor substrate 33 of a first conductivity type. A well layer 29 of a second conductivity type is provided on the upper surface side of the epitaxial layer 28. A source layer 30 of the first conductivity type is partially disposed in the well layer 29.

[0038] An interlayer insulating film 31 having a portion thereof opened is provided on the upper surface of the epitaxial layer 28. A gate electrode 32 and a gate insulating film 34 disposed between the gate electrode 32 and the upper surface of the epitaxial layer 28 are provided in the interlayer insulating film 31.

[0039] A plurality of openings are formed in the interlayer insulating film 31 in a dot shape in plan view. The first metal layer 35 is electrically connected to the source layer 30 through the plurality of openings in the interlayer insulating film 31. The first metal layer 35 is a source electrode. A second metal layer 21, which is a plating layer mainly composed of Ni, is provided on the upper surface of the first metal layer 35. A third metal layer 22, which is a plating layer mainly composed of Cu, is disposed on the upper surface of the second metal layer 21. As in the first embodiment, the order of hardness is the second metal layer 21, the third metal layer 22, and the first metal layer 35.

[0040] The upper surface of the third metal layer 22 is formed with projections and recesses so as to correspond to the openings in the interlayer insulating film 31. These minute projections and recesses can improve the bonding properties of the wire or solder. This allows bonding to be performed without applying excessive energy to the semiconductor device 107, and reduces damage to the semiconductor substrate.

[0041] The openings in the interlayer insulating film 31 are not limited to a dot shape, but may be in a lattice shape.

[0042] Embodiment 7 11 is a cross-sectional view of a semiconductor device 108 according to the seventh embodiment. The semiconductor device 108 includes a base plate 37. A ceramic substrate 38 having electrode pads 40 is bonded to the upper surface of the base plate 37 with solder 39. A semiconductor chip 41 is bonded to the upper surface of the ceramic substrate 38 with solder 39. The semiconductor chip 41 has a collector pad 43 on its back surface, and a gate pad 42 and an emitter pad 44 on its upper surface.

[0043] Each of the gate pad 42 and the emitter pad 44 is formed from the first metal layer, the second metal layer, and the third metal layer described in the first to sixth embodiments. The wire 26 is electrically connected to the third metal layer. The wire 26 contains, for example, Cu as a material. The wire 26 may be mainly composed of Cu. The electrode pad 40 is mainly composed of, for example, Cu. The gate pad 42 and the emitter pad 44 are connected to the electrode pad 40 via the wire 26.

[0044] Generally, Cu bonding is stronger than Al bonding. Therefore, by using Cu bonding, it is possible to improve the resistance to power cycles. Note that the ceramic substrate 38 and the semiconductor chip 41 may be bonded not only with the solder 39 but also with an Ag sintered material or a Cu sintered material.

[0045] Embodiment 8 12 is a cross-sectional view of a semiconductor device 109 according to the eighth embodiment. The semiconductor device 109 is, for example, an IGBT module. The semiconductor device 109 includes an insulating sheet 47, a heat spreader 46 provided on the upper surface of the insulating sheet 47, and a semiconductor chip 41 joined to the upper surface of the heat spreader with solder 39. The semiconductor chip 41 has a collector pad 43 on its lower surface, and a gate pad 42 and an emitter pad 44 on its upper surface.

[0046] Each of the gate pad 42 and the emitter pad 44 is formed from the first metal layer, the second metal layer, and the third metal layer described in the first to sixth embodiments. In this embodiment, solder 39 is provided on the third metal layer. A lead frame 48 serving as a main terminal is joined to the emitter pad 44 by the solder 39. A lead frame 49 serving as a control terminal is joined to the gate pad 42 by the solder 39. A molding resin 45 is provided so as to cover the semiconductor chip 41, leaving parts of the lead frames 48 and 49 exposed.

[0047] Soldering can reduce damage to the semiconductor chip 41 more than wire bonding. It can also improve the heat dissipation of the semiconductor chip 41, and increase the current density. Therefore, the semiconductor device 109 can be made smaller.

[0048] Embodiment 9 FIG. 13 is a cross-sectional view of a semiconductor device 110 according to a ninth embodiment. The semiconductor device 110 is different from the semiconductor device 100 in that three metal layers are also formed on the back side of the semiconductor substrate. The other structures are similar to those of the semiconductor device 100. The semiconductor device 110 includes a fifth metal layer 50 provided under the semiconductor substrate, a sixth metal layer 51 provided under the fifth metal layer 50 and containing Ni as a material, and a seventh metal layer 52 provided under the sixth metal layer 51 and containing Cu or Ni as a material. The Vickers hardness of the sixth metal layer 51 is 400 Hv or more. The sixth metal layer 51 is harder than the seventh metal layer 52, and the seventh metal layer 52 is harder than the fifth metal layer 50.

[0049] The fifth metal layer 50 is a collector electrode. The sixth metal layer 51 is a plating layer. The sixth metal layer 51 may be mainly composed of Ni. The seventh metal layer 52 is, for example, a plating layer. The seventh metal layer 52 may be mainly composed of Cu.

[0050] This back electrode structure can improve heat dissipation and current density, thereby enabling the device to be made smaller. In addition, the stresses of multiple metal layers are offset, suppressing chip warpage and reducing backside void defects.

[0051] The technical features described in each embodiment may be used in appropriate combination. [Explanation of symbols]

[0052] 1 drift layer, 2 carrier accumulation layer, 3 base layer, 4 interlayer insulating film, 5 emitter layer, 6 contact layer, 7 buffer layer, 8 collector layer, 9 collector electrode, 10 active trench, 11 gate electrode, 12 gate insulating film, 14 well region, 15 resurf region, 16 field oxide film, 17 gate wiring, 18 first protective film, 19 second protective film, 20 first metal layer, 21 second metal layer, 22 third metal layer, 23 barrier metal layer, 24 fourth metal layer, 25 oxidation prevention film, 26 wire, 27 adhesion layer, 28 epitaxial layer, 29 well layer, 30 source layer, 31 interlayer insulating film, 32 gate electrode, 33 semiconductor substrate, 34 gate insulating film, 35 first metal layer, 37 base plate, 38 ceramic substrate, 39 solder, 40 electrode pad, 41 semiconductor chip, 42 Gate pad, 43 collector pad, 44 emitter pad, 45 molding resin, 46 heat spreader, 47 insulating sheet, 48 lead frame, 49 lead frame, 50 fifth metal layer, 51 sixth metal layer, 52 seventh metal layer, 100 to 110 semiconductor device

Claims

1. A semiconductor substrate; a first metal layer disposed on the semiconductor substrate; a second metal layer provided on the first metal layer, the second metal layer including Ni as a material; a third metal layer provided on the second metal layer and including Cu or Ni as a material; Equipped with The second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer; the third metal layer being harder than the first metal layer; The semiconductor device according to claim 1, wherein the second metal layer is an electroless NiP plating layer, and the third metal layer is an electrolytic Cu plating layer.

2. 2. The semiconductor device according to claim 1, wherein the second metal layer contains P as an impurity.

3. a barrier metal layer provided between the semiconductor substrate and the first metal layer; 3. The semiconductor device according to claim 1, wherein the barrier metal layer is harder than the first metal layer.

4. an insulating film provided between the semiconductor substrate and the first metal layer, the insulating film having an opening for exposing the semiconductor substrate; 4. The semiconductor device according to claim 1, wherein the first metal layer is electrically connected to the semiconductor substrate through the opening.

5. 5. The semiconductor device according to claim 4, further comprising a fourth metal layer provided in the opening and electrically connecting the semiconductor substrate and the first metal layer.

6. 6. The semiconductor device according to claim 4, wherein the insulating film has a plurality of the openings formed in a dot shape in a plan view.

7. A semiconductor substrate; a first metal layer disposed on the semiconductor substrate; a second metal layer provided on the first metal layer, the second metal layer including Ni as a material; a third metal layer provided on the second metal layer and including Cu or Ni as a material; an insulating film provided between the semiconductor substrate and the first metal layer, the insulating film having an opening for exposing the semiconductor substrate; Equipped with The second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer; the third metal layer being harder than the first metal layer; the first metal layer is electrically connected to the semiconductor substrate through the opening; The insulating film has a plurality of openings formed in a dot shape in a plan view, The semiconductor device according to claim 1, wherein the third metal layer has an upper surface formed with projections and recesses.

8. 8. The semiconductor device according to claim 1, further comprising an adhesion layer for adhering the second metal layer and the third metal layer to each other.

9. 8. The semiconductor device according to claim 1, further comprising an Au layer provided between the second metal layer and the third metal layer.

10. A semiconductor substrate; a first metal layer disposed on the semiconductor substrate; a second metal layer provided on the first metal layer, the second metal layer including Ni as a material; a third metal layer provided on the second metal layer and including Cu or Ni as a material; a resin layer provided on a portion of an upper surface of the first metal layer and covered by the second metal layer; Equipped with The second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer; The semiconductor device according to claim 1, wherein the third metal layer is harder than the first metal layer.

11. 11. The semiconductor device according to claim 10, wherein the resin layer is provided immediately below a region where wire bonding is performed.

12. 12. The semiconductor device according to claim 1, further comprising an oxidation prevention film provided on the third metal layer.

13. 13. The semiconductor device according to claim 12, further comprising a wire that penetrates the oxidation prevention film and is electrically connected to the third metal layer.

14. 14. The semiconductor device according to claim 13, wherein the wire contains Cu as a material.

15. 13. The semiconductor device according to claim 1, further comprising a wire electrically connected to the third metal layer, the wire including Cu as a material.

16. 13. The semiconductor device according to claim 1, further comprising a solder layer provided on the third metal layer.

17. a fifth metal layer disposed beneath the semiconductor substrate; a sixth metal layer provided under the fifth metal layer and including Ni as a material; a seventh metal layer provided under the sixth metal layer and containing Cu or Ni as a material; Equipped with The sixth metal layer has a Vickers hardness of 400 Hv or more and is harder than the seventh metal layer; 17. The semiconductor device according to claim 1, wherein the seventh metal layer is harder than the fifth metal layer.

18. 18. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a wide band gap semiconductor.

19. 20. The semiconductor device according to claim 18, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material or diamond.

20. forming a first metal layer over a semiconductor substrate; forming a second metal layer containing NiP on the first metal layer by electroless plating; forming a third metal layer containing Cu on the second metal layer by electrolytic plating; The second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer; 4. A method for manufacturing a semiconductor device, comprising the steps of: forming a first metal layer on a first insulating film;

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