Semiconductor Device

Abstract

To provide a semiconductor device which reduces a stress generated in a semiconductor element, suppresses an increase of heat resistance and improves reliability.SOLUTION: A semiconductor device comprises: a semiconductor element 1a including a first drain electrode D on a surface at the side of a lower electrode 1g and including a source electrode S and a gate electrode on a surface at the side of an upper electrode 1d; the lower electrode 1g connected through a conductive joint material 1p to the surface of the semiconductor element 1a at the side of the drain electrode D; and the upper electrode 1d connected through a conductive joint material 1q to the surface of the semiconductor chip at the side of the source electrode S. The lower electrode 1g is a tabular electrode and includes a groove T in a region overlapped with the semiconductor element 1a, and the groove T has a configuration penetrating in a thickness direction of the lower electrode 1g and is formed in a shape reaching an end of the lower electrode 1g in a planar view.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Power semiconductors are becoming more widespread worldwide, and for semiconductor devices used in switching circuits and rectifier circuits, mounting technologies are being developed to meet a variety of requirements, such as higher current, higher heat dissipation, and higher reliability.

[0003] A known mounting technology for power semiconductors is a double-sided mounting structure in which electrodes are provided on the top and bottom surfaces of a semiconductor element, and at least one electrode on each of the top and bottom surfaces is connected to an external electrode. Examples of semiconductor elements having electrodes on the top and bottom surfaces include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors).

[0004] A MOSFET has a source electrode and a gate electrode on one side, and a drain electrode on the other side.

[0005] An IGBT has an emitter electrode and a gate electrode on one surface, and a collector electrode on the other surface. Power semiconductor elements usually have a surface protection film formed on the outer periphery of one of their surfaces. In a MOSFET, the surface protection film is formed on the source electrode side, and in an IGBT, the surface protection film is formed on the emitter electrode side. In the case of an IGBT, if it has a diode, the surface protection film is formed on either the P pole or N pole side.

[0006] As an example of such a semiconductor device with a double-sided mounting structure, Patent Document 1 discloses a semiconductor module having a semiconductor chip with electrodes on both electrode surfaces, and a pair of module substrates each having a surface wiring layer with an electrode disposed on each electrode surface of the semiconductor chip, the surface wiring layer having an electrode, in which grooves are formed in the electrodes of the surface wiring layer of the module substrate. Patent Document 1 also discloses an example in which lattice-shaped grooves are formed in the back wiring layer of the module substrate. Patent Document 1 also describes the effect of mitigating thermal stress caused by differences in the thermal expansion coefficients of materials constituting the module substrate.

[0007] Patent Document 2 discloses a semiconductor device including a pair of heat-dissipating metal electrodes arranged so that their inner surfaces face each other, a semiconductor element sandwiched between the two metal electrodes and electrically connected to the inner surfaces of the two metal electrodes, and a ceramic insulating substrate having heat dissipation arranged on the outer surface of each metal electrode, in which at least one of the pair of metal electrodes has a layered structure in which a plurality of layers are layered from the outer surface side to the inner surface side in order of decreasing thermal expansion coefficient. Patent Document 2 also discloses an example in which at least one of the pair of metal electrodes is provided with a slit. Patent Document 2 also describes the effect of alleviating thermal stress generated in the metal electrode by the slit. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2014-107506 A [Patent Document 2] JP 2007-173680 A Summary of the Invention [Problem to be solved by the invention]

[0009] Since Pb has a low melting point and low elasticity, solders containing Pb as the main component have been widely used as bonding materials for semiconductor devices. However, in recent years, restrictions on the use of Pb have been tightened due to environmental considerations, and Pb-free materials are being developed. Common Pb-free materials include solders containing Sn as the main component, such as Sn-Sb and Sn-Ag-Cu, and bonding materials that use Cu or Ag and are sintered at high temperatures.

[0010] These Pb-free materials have a higher elasticity than Pb-containing solders, and there is a problem that the stress on the semiconductor element increases due to heating and cooling during the joining process.

[0011] Reducing stress is important to prevent the occurrence of cracks in semiconductor elements. In particular, in the double-sided mounting structure that is often used for power semiconductors, the bonding area needs to be as large as possible to allow a large current to flow, and this tends to increase stress.

[0012] To reduce stress, the shape of the electrodes bonded to the semiconductor element is devised so as to reduce thermal deformation of the semiconductor element during solder connection. In general, the thermal deformation of the semiconductor element can be reduced by reducing the area of ​​the electrodes bonded to the semiconductor element. However, this reduces the heat transfer area between the semiconductor element and the electrodes, increasing the thermal resistance during product use and reducing heat dissipation performance. Therefore, the challenge is to suppress the increase in thermal resistance while reducing the stress on the semiconductor element during the bonding process.

[0013] In the semiconductor module described in Patent Document 1, as shown in Figures 4 and 9 of Patent Document 1, a groove (55) that is thinner than other parts is formed in the substrate electrode (52) bonded to the gate electrode (30), and a lattice-shaped groove (80) is formed in the back wiring layer (70, 71). However, the grooves (55, 80) are not formed in the substrate electrodes (51, 61) bonded to the source electrode (31) and drain electrode (32) that have a large bonding area. For this reason, it is believed that the effect of mitigating thermal stress is not sufficiently obtained.

[0014] In the semiconductor device described in Patent Document 2, as shown in FIGS. 7 and 8 of Patent Document 2, the slits (16) do not reach the ends of the metal electrodes. Therefore, when a semiconductor element is bonded to an end portion where there is no slit, it is considered that the thermal stress transmitted to the semiconductor element cannot be reduced in the vicinity of the end portion.

[0015] An object of the present invention is to provide a semiconductor device which reduces stress generated in a semiconductor element and suppresses an increase in thermal resistance, thereby providing a highly reliable semiconductor device. [Means for solving the problem]

[0016] The present invention relates to a semiconductor device having a semiconductor chip having a first main electrode on one surface and a second main electrode and a gate electrode on the other surface, a first electrode connected to the one surface of the semiconductor chip via a first bonding material, and a second electrode connected to the other surface of the semiconductor chip via a second bonding material, wherein the first electrode is a plate-shaped electrode and has a groove in an area overlapping with the semiconductor chip, the groove having a configuration penetrating the first electrode in a thickness direction, and when viewed in a plan view , in the vicinity of an end portion of the semiconductor chip, in a shape that follows the end portion of the semiconductor chip, The shape reaches the end of the first electrode. When a region closer to the center of the semiconductor chip than the groove is defined as a first region, and a region closer to an end of the semiconductor chip than the groove is defined as a second region, the semiconductor chip and the first electrode are connected by the first bonding material in each of the first region and the second region, and the first bonding material bonding the first region and the first bonding material bonding the second region are separated by the groove. do. Effect of the Invention

[0017] According to the present invention, it is possible to provide a highly reliable semiconductor device by reducing the stress generated in the semiconductor element and suppressing an increase in thermal resistance. [Brief description of the drawings]

[0018] [Figure 1] 1 is a schematic vertical cross-sectional view showing a semiconductor device according to a first embodiment of the present invention; [Diagram 2] 2 is an enlarged vertical cross-sectional view showing the semiconductor element 1a of FIG. 1 and components located above and below it. [Diagram 3] FIG. 2 is a plan view partially showing the electronic circuit body 100 of FIG. [Figure 4] FIG. 1 is a partial vertical cross-sectional view showing a semiconductor device having a conventional structure. [Diagram 5]1 is a partial vertical cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 6] 6 is a longitudinal sectional view geometrically illustrating the same portion of the semiconductor device as shown in FIG. 5. [Figure 7] 4 is a graph showing an example of the results of estimating thermal stress occurring in the semiconductor element of Example 1 by finite element analysis. [Figure 8] 7 is a graph showing an example of the results of estimating the thermal resistance of the semiconductor device 200 shown in FIG. 6 by finite element analysis. [Figure 9] 11 is a vertical cross-sectional view partially showing a semiconductor device in which the position of a groove T has been changed. [Figure 10] FIG. 13 is a plan view partially showing an electronic circuit body of a comparative example. [Figure 11] 11 is a graph showing the results of a thermal stress analysis comparing the embodiment shown in FIG. 3 with the comparative example shown in FIG. 10. [Figure 12] FIG. 11 is a plan view partially showing an electronic circuit body according to a second embodiment. [Figure 13] 13 is a cross-sectional view taken along the line BB' of FIG. 12. [Figure 14] FIG. 11 is a vertical cross-sectional view showing the vicinity of an end portion of a semiconductor element according to a second embodiment. [Figure 15] FIG. 11 is a plan view partially showing an electronic circuit body according to a third embodiment. [Figure 16] 16 is a graph showing the effect of the configuration of FIG. 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The present disclosure relates to a structure of a semiconductor device, and in particular to a technique that is effective when applied to a mounting structure of a power semiconductor for power control. The present technique is particularly effective for a semiconductor device having a double-sided mounting structure.

[0020] Hereinafter, examples of the semiconductor device according to the present disclosure will be described in detail with reference to the drawings. Note that the contents of the present disclosure are not limited to the examples. EXAMPLES

[0021] FIG. 1 is a schematic vertical cross-sectional view showing a semiconductor device according to a first embodiment.

[0022] The semiconductor device 200 shown in the figure is used as a rectifying element in an on-vehicle alternator.

[0023] In this figure, the semiconductor device 200 includes an electronic circuit body 100, a base 2 having a pedestal 2a on top, and leads 3 having a lead header 3a on the bottom. The electronic circuit body 100 has a rectifying function. The area occupied by the electronic circuit body 100 is indicated by a dotted line. The base 2 and the leads 3 serve as terminals for electrically connecting the electronic circuit body 100 to an external circuit. The pedestal 2a and a portion located at the top of the base 2, the lead header 3a and a portion located at the bottom of the leads 3, and the electronic circuit body 100 are covered and sealed with a molded resin 5.

[0024] The electronic circuit body 100 includes a semiconductor element 1a (semiconductor chip), a capacitor 1b, and a control circuit chip 1c. The electronic circuit body 100 also includes a lower electrode 1g, an upper electrode 1d (source block), and a lead frame 1i.

[0025] The base 2a and the lower electrode 1g of the electronic circuit body 100 are connected via a conductive bonding material 4a. The lead header 3a and the upper electrode 1d of the electronic circuit body 100 are connected via a conductive bonding material 4b. In this specification, the lower electrode 1g is also called the "first electrode" and the upper electrode 1d is also called the "second electrode."

[0026] In this embodiment, the semiconductor element 1a is a MOSFET. The MOSFET has a drain electrode D and a source electrode S. In this figure, the drain electrode D is provided on the lower surface, and the source electrode S is provided on the upper surface. In other words, the semiconductor element 1a has a double-sided mounting structure. The surface on which the drain electrode D is provided is referred to as the "first main surface" of the semiconductor element 1a, and the surface on which the source electrode S is provided is referred to as the "second main surface" of the semiconductor element 1a.

[0027] The drain electrode D is connected to the upper surface of the lower electrode 1g, which is the first internal electrode, via a conductive bonding material 1p. However, if the conductive bonding material 1p is not used, the connection may be made by ultrasonic bonding or the like.

[0028] The source electrode S is connected to the lower surface of the upper electrode 1d, which is the second internal electrode, via a conductive bonding material 1q. However, if the conductive bonding material 1q is not used, the connection may be made by ultrasonic bonding or the like.

[0029] The control circuit chip 1c is connected via a conductive adhesive to the upper surface of a lead frame 1i, which serves as a support.

[0030] The capacitor 1b that supplies power to the control circuit chip 1c is also connected to the upper surface of the lead frame 1i via a conductive bonding material. The capacitor 1b may be, for example, a ceramic capacitor.

[0031] The lower surface of the lower electrode 1g is not covered with the molding resin 5 and is exposed from the lower surface of the electronic circuit body 100. The lower surface of the lower electrode 1g is connected to the base 2a via a conductive bonding material 4a.

[0032] The upper surface of the upper electrode 1d is exposed from the upper surface of the electronic circuit body 100. The upper surface of the upper electrode 1d is connected to the lead header 3a via a conductive bonding material 4b.

[0033] The materials of the conductive bonding materials 1p, 1q, 4a, 4b, etc. are generally used solders, alloys containing Au, Ag or Cu, conductive adhesives, etc. In addition, as the solder, general high-lead solders, eutectic solders, lead-free solders, etc. are used. In addition, as the conductive adhesive, a mixture of a metal filler such as Ag, Cu, Ni, etc. with a resin, or a material composed only of metal is used. In addition, the materials of the conductive bonding materials 1p, 1q, 4a, 4b, etc. may be the same material or different materials. In addition, the conductive bonding materials 1p and 1q may be the same material or different materials above and below the semiconductor element 1a. In addition, the materials of the conductive bonding materials 4a and 4b may be the same material or different materials above and below the electronic circuit body 100.

[0034] The base 2 and the leads 3, as well as the lower electrode 1g, the upper electrode 1d, and the lead frame 1i inside the electronic circuit 100, are mainly made of Cu, which has high thermal conductivity and excellent electrical conductivity, but CuMo, 42 alloy, Al, Au, Ag, etc. may also be used. In this case, it is desirable to plate the connection parts with the conductive bonding material with Au, Pd, Ag, Ni, etc. in order to improve connection stability.

[0035] The control circuit chip 1c is electrically connected to the semiconductor element 1a via wires 1f. For example, if the semiconductor element 1a is a power MOSFET, the gate electrode formed on the semiconductor element 1a is connected to the control circuit chip 1c via wires 1f, and the control circuit chip 1c controls the gate voltage of the power MOSFET. This allows a large current to flow through the semiconductor element 1a, which has a switching function.

[0036] The capacitor 1b is electrically connected to the semiconductor element 1a and the control circuit chip 1c by a lead frame 1i and a wire 1f. The capacitor 1b has a function of supplying power necessary to drive the control circuit chip 1c.

[0037] The semiconductor element 1a has a function of switching a large current. Examples of such a semiconductor element 1a include switching circuit chips such as IGBTs, GTOs (Gate Turn-Off thyristors), and power MOSFETs. The semiconductor element 1a may also be a thyristor or the like that controls the on / off of a large current and may be made of Si, SiC, SiN, GaAs, or the like.

[0038] The control circuit chip 1c is a semiconductor element that controls the semiconductor element 1a that switches a large current. The control circuit chip 1c itself is a semiconductor element that does not include a semiconductor element that switches a large current. In other words, the control circuit chip 1c is a semiconductor element that includes, for example, a logic circuit, an analog circuit, a driver circuit, etc., and is formed with a microprocessor, etc., as necessary. The control circuit chip 1c may also have a function of controlling the large current flowing through the semiconductor element 1a.

[0039] The semiconductor element 1a, the control circuit chip 1c, the capacitor 1b, the lower electrode 1g, the upper electrode 1d, and the conductive bonding materials 1p and 1q are all covered and sealed with a resin 1h.

[0040] The lower surface of the lower electrode 1g and the upper surface of the upper electrode 1d are not covered with the resin 1h of the electronic circuit body 100 and are exposed to the outside of the electronic circuit body 100.

[0041] Therefore, the upper surface of the upper electrode 1d of the electronic circuit body 100 can be electrically connected to the lead header 3a via the conductive bonding material 4b. Also, the lower surface of the lower electrode 1g of the electronic circuit body 100 can be electrically connected to the base 2a via the conductive bonding material 4a.

[0042] As described above, the electronic circuit body 100 is sealed with resin 1h and constructed as an integral unit. The exposed portion of the lower electrode 1g is electrically connected to the seat 2a of the base 2 by a conductive bonding material 4a. The exposed portion of the upper electrode 1d is electrically connected to the lead header 3a of the lead 3 by a conductive bonding material 4b. The entire electronic circuit body 100 and parts of the base 2 and the lead 3 are covered with mold resin 5 to construct a semiconductor device 200.

[0043] Furthermore, the P and N polarities of the semiconductor device 200 can be switched by turning the electronic circuit 100 upside down during manufacturing.

[0044] As shown in the figure, it is desirable to make the upper electrode 1d connected to the source electrode S of the semiconductor element 1a thicker than the lower electrode 1g. Here, making it thicker means making it longer in the direction from the base 2a toward the lead header 3a.

[0045] By thickening the upper electrode 1d in this way, the heat capacity of the upper electrode 1d increases, so that the upper electrode 1d can absorb the heat generated by the loss caused when a current flows through the source electrode S. This makes it possible to suppress a temperature rise in the semiconductor element 1a.

[0046] Furthermore, by making the upper electrode 1d thicker, the upper electrode 1d can be made higher than the height of the capacitor 1b, and the upper electrode 1d can be connected as a terminal of the electronic circuit body 100 to the lead header 3a.

[0047] FIG. 2 is an enlarged vertical cross-sectional view showing the semiconductor element 1a of FIG. 1 and components located above and below it.

[0048] 2, the semiconductor element 1a (semiconductor chip) has a drain electrode D (first main electrode) on the surface (one surface) on the lower electrode 1g side, and has a gate electrode C (not shown, see FIG. 3) and a source electrode S (second main electrode) on the surface (the other surface) on the upper electrode 1d side. The semiconductor element 1a also has a surface protective film L (guard ring) on ​​the outer periphery of the surface on the gate electrode C side.

[0049] The lower electrode 1g is a plate-shaped electrode.

[0050] The surface of the semiconductor element 1a on the source electrode S side is connected to the lower surface of the upper electrode 1d via a conductive bonding material 1q. The surface of the semiconductor element 1a on the drain electrode D side is connected to the upper surface of the lower electrode 1g via a conductive bonding material 1p. The conductive bonding materials 1p and 1q are also simply called "bonding materials." The conductive bonding material 1p may be called the "first bonding material" and the conductive bonding material 1q may be called the "second bonding material" to distinguish them from each other.

[0051] The length of the upper electrode 1d is shorter than that of the semiconductor element 1a. The end of the upper electrode 1d and the end of the connection between the upper electrode 1d and the semiconductor element 1a are both located inside the semiconductor element 1a. The end of the lower electrode 1g connected to the semiconductor element 1a is located outside the end of the semiconductor element 1a. The lower electrode 1g is provided with a groove T. The groove T penetrates the lower electrode 1g in the thickness direction. At least a portion of the groove T of the lower electrode 1g overlaps with the semiconductor element 1a. The groove T can be formed by pressing or etching.

[0052] In summary, the lower electrode 1g is a plate-shaped electrode and has a groove T in the region overlapping with the semiconductor element 1a.

[0053] Fig. 3 is a plan view partially showing the electronic circuit body 100 of Fig. 1. The cross section taken along line AA' in Fig. 3 corresponds to Fig. 2.

[0054] As shown in FIG. 3, the semiconductor element 1a (semiconductor chip) has a gate electrode C on the surface (other surface) on the upper electrode 1d side.

[0055] Four grooves T are provided along the longitudinal direction of the lower electrode 1g, and reach the end of the lower electrode 1g. In other words, the grooves T penetrate the first electrode in the thickness direction, and reach the end of the first electrode when viewed in a plan view.

[0056] The groove T provided in the lower electrode 1g reaches the outer periphery G of the lower electrode 1g (highlighted by a dashed line in the figure). If the groove T reaches the end of the lower electrode 1g, deformation of the semiconductor element 1a due to thermal stress can be suppressed, as described later.

[0057] Next, a method for manufacturing the electronic circuit 100 which is a component of the semiconductor device 200 will be described.

[0058] First, the lower electrode 1g, the conductive adhesive, the semiconductor element 1a, the conductive adhesive, and the upper electrode 1d are laminated in this order. This is heated to melt the conductive adhesive, forming layers of the conductive adhesives 1p and 1q. Then, it is cooled to room temperature.

[0059] In the cooling process, thermal strain occurs in all of the upper electrode 1d, the lower electrode 1g, and the semiconductor element 1a. When the upper electrode 1d and the lower electrode 1g are made of Cu and the semiconductor element 1a is made of Si, the thermal expansion coefficients of each are 16.8×10 -6 [K -1 ], 2.4×10 -6 [K -1 ], the upper electrode 1d and the lower electrode 1g shrink more than the semiconductor element 1a, which causes bending deformation in the upper electrode 1d, the lower electrode 1g, and the semiconductor element 1a, generating thermal stress in each member.

[0060] FIG. 4 is a partial vertical cross-sectional view showing a semiconductor device having a conventional structure.

[0061] In this figure, a portion corresponding to region Y in FIG. 2 is shown in an enlarged scale.

[0062] 4, in the conventional structure, the length of the lower electrode 1g is longer than that of the semiconductor element 1a. The length of the upper electrode 1d is shorter than that of the semiconductor element 1a. Therefore, the length of the conductive bonding material 1p provided between the lower electrode 1g and the semiconductor element 1a is longer than the conductive bonding material 1q provided between the upper electrode 1d and the semiconductor element 1a.

[0063] Because the lower electrode 1g and the upper electrode 1d contract more than the semiconductor element 1a during cooling, the force that the semiconductor element 1a receives from the conductive bonding material 1p is greater than that from the conductive bonding material 1q. Therefore, the shape of the semiconductor element 1a after cooling becomes upwardly convex.

[0064] At point p1 shown in the figure, bending deformation of the semiconductor element 1a generates a tensile stress indicated by an arrow Tb, and simultaneously, a tensile stress indicated by an arrow Tj is generated from the conductive bonding material 1p, so that stress is concentrated at point p1. If a bonding material with high rigidity such as lead-free solder or a sintered material is used for the conductive bonding materials 1p and 1q, the stress at point p1 becomes even larger, increasing the risk of cracks occurring in the semiconductor element 1a.

[0065] FIG. 5 is a partial vertical cross-sectional view showing the semiconductor device of this embodiment.

[0066] In this figure, too, a portion corresponding to region Y in FIG. 2 is shown in an enlarged scale.

[0067] In FIG. 5, a groove T is provided in the lower electrode 1g. The groove T penetrates the lower electrode 1g in the thickness direction. The groove T causes stresses to occur separately in the regions D1 and D2 of the semiconductor element 1a. Therefore, the stress is smaller than that in the conventional structure. This allows the stress at point p1 to be significantly reduced.

[0068] If the groove T does not penetrate all the way through, the effect of reducing the stress occurring in the regions D1 and D2 cannot be obtained sufficiently because the influence of the continuous portion of the lower electrode 1g remains.

[0069] Moreover, it is desirable that the width U of the groove T is wider than the thickness of the conductive bonding material 1p. If the width U of the groove T is narrow, the conductive bonding material 1p will spread during manufacturing, filling the groove T with the conductive bonding material 1p, and the lower electrode 1g will be bonded between the regions D1 and D2, so that stress will be transmitted through the bonded portion. This is undesirable because the stress reduction effect will be lost.

[0070] By providing the groove T in the lower electrode 1g, a highly reliable semiconductor device can be manufactured even when a highly rigid lead-free bonding material such as lead-free solder or a sintered material is used as the conductive bonding material 1p.

[0071] Furthermore, by adjusting the position of the groove T, for example by vertically aligning it with the end of the upper electrode 1d, a heat dissipation path for the semiconductor element 1a can be secured and an increase in thermal resistance can be suppressed. In other words, it is desirable that the groove T is provided at a position overlapping the upper electrode 1d. In this case, it is desirable that the groove T and the semiconductor element 1a overlap, and that the upper electrode 1d overlap above that.

[0072] Next, the effect of reducing thermal stress and the change in thermal resistance will be quantitatively described with reference to FIGS.

[0073] FIG. 6 is a vertical cross-sectional view showing the geometry of the same portion of the semiconductor device as shown in FIG.

[0074] FIG. 6 shows the definitions of coordinates and parameters used when examining the thermal stress and thermal resistance occurring in the manufactured semiconductor element 1a.

[0075] In this figure, the x-axis is parallel to the top surface of the semiconductor element 1a and perpendicular to the longitudinal direction of the groove T. The distance from the end E-E' (the right end of the upper electrode 1d in the figure) of the connection surface of the upper electrode 1d with the semiconductor element 1a to the end of the semiconductor element 1a is defined as W. The distance from the end E-E' to the center line F-F' of the groove T (the symmetrical axis of the width in the short direction of the groove T) is defined as J. J is a parameter to consider the case where the position of the groove T is changed. Note that when the center line F-F' of the groove T is closer to the center of the semiconductor element 1a (to the left in the figure) than the end E-E' of the upper electrode 1d, J takes a negative value. Here, the parameter normalized by dividing J by W is defined as X.

[0076] In the example shown in this figure, X=-0.4.

[0077] 7 is a graph showing an example of the results of estimating the thermal stress occurring in the semiconductor element 1a by finite element analysis, in which the horizontal axis represents X and the vertical axis represents normalized stress σ.

[0078] The material of the upper electrode 1d and the lower electrode 1g is Cu, and the material of the semiconductor element 1a is Si. The material of the conductive bonding material 1p is solder mainly composed of Sn, which is a common lead-free bonding material. X is changed in the range from -2 to 2. In addition, σ on the vertical axis is a standardized value with the thermal stress generated at point p1 (stress concentration point) of the semiconductor element 1a in FIG. 6 as the numerator and the stress generated at point p1 when soft lead solder is used for the conductive bonding material 1p in the conventional structure shown in FIG. 4 as the denominator. For this reason, σ=1 is indicated by the symbol Pb in the figure. Note that the solder mainly composed of Sn has a higher Sn content than the other metal elements contained in the solder.

[0079] 7, the stress is minimum when X is -0.4 and increases as X moves away from -0.4. In addition, when X is 0.3 and -1.2, the stress increases to the same level as the stress in the conventional structure.

[0080] In summary, when the distance from the end of the connection surface of the second electrode with the semiconductor chip to the end of the semiconductor chip is defined as W, the distance from the end of the connection surface of the second electrode with the semiconductor chip to the center line of the groove T is defined as J, and J / W is defined as X, the position of the center line of the groove T satisfies the following formula (1).

[0081] -1.2 <X<0.3 …(1) FIG. 8 is a graph showing an example of the result of estimating thermal resistance by finite element analysis. The horizontal axis is X, and the vertical axis is the normalized thermal resistance θ. X is changed in the range from -2 to 1. The vertical axis θ is a value obtained by normalizing the thermal resistance of the semiconductor device 200 shown in FIG. 6 with the thermal resistance of the semiconductor device 200 having the conventional electronic circuit body 100 shown in FIG. 4 as the denominator. Therefore, in the figure, θ=1 is indicated by the symbol CS. Here, the thermal resistance is defined as the increment from the initial state of the heat quantity calculated from the temperature distribution of the semiconductor device 200 in the steady state in which the semiconductor element 1a operates and generates a predetermined amount of heat. This is because it is considered that the larger this increment is, the smaller the heat dissipation to the outside.

[0082] From Fig. 8, we can see that the larger X is, that is, the closer the position of groove T is to the end of bottom electrode 1g, the larger the thermal resistance is. Therefore, within the range of X shown in this figure, it is preferable to position groove T on the inside of bottom electrode 1g, as this keeps the thermal resistance low.

[0083] Considering the thermal stress shown in FIG. 7 and the thermal resistance shown in FIG. 8, it can be seen that when X is −0.4, the thermal stress is at a minimum and the thermal resistance is also kept low.

[0084] 6, by providing the groove T at the position of X=-0.4, it is possible to suppress the concentration of stress at the point p1 and minimize the amount of deformation. Furthermore, since the upper electrode 1d is provided directly above the groove T, it is possible to ensure a heat dissipation path from the semiconductor element 1a to the upward direction and suppress the thermal resistance from the semiconductor element 1a.

[0085] In this embodiment, solder mainly composed of Sn is used as the conductive bonding material 1p. Since solder mainly composed of Sn has a higher elastic modulus and a higher thermal conductivity than solder mainly composed of Pb, it is considered that when applied to the conventional structure as shown in FIG. 4, the stress generated in the semiconductor element 1a increases and the thermal resistance decreases. Here, the problem is the stress, but by providing the groove T as in this embodiment, the stress generated in the semiconductor element 1a can be suppressed to the same level or less than that of the conventional structure using solder mainly composed of Pb. In this embodiment, the thermal resistance increases by providing the groove T, but since solder mainly composed of Sn is used, the thermal resistance can also be suppressed. Even when other Pb-free bonding materials such as sintered metals using Cu or Ag are used, if the elastic modulus and thermal conductivity are higher than Pb, it is expected that a qualitatively similar tendency can be obtained.

[0086] The effect of this embodiment is not limited to X=-0.4.

[0087] FIG. 9 is a vertical sectional view partially showing a semiconductor device in which the position of the groove T is changed.

[0088] In this figure, the groove T is arranged so that the center line F-F' of the groove T is located outside the end E-E'. In other words, this is an example where X=0.25. In this example as well, the groove T can be said to be provided at a position that overlaps with the second electrode.

[0089] In this figure, the area directly above the groove T where the upper electrode 1d overlaps is small, so the heat dissipation path from the semiconductor element 1a upward is smaller than X=-0.4 shown in FIG. 6, but the increase in thermal resistance is small, as shown in FIG. 8.

[0090] It can be seen from Fig. 7 that the stress can be made equivalent to that in the case of the conventional structure even when X = 0.25 as in the example of Fig. 9. Therefore, even when X = -0.4 cannot be realized due to the constraints of the electronic circuit body 100, the stress reduction effect can be obtained.

[0091] Next, the necessity for the groove T to reach the end of the lower electrode 1g will be described.

[0092] FIG. 10 is a plan view partially showing an electronic circuit body of a comparative example.

[0093] In this figure, the groove T does not reach the outer periphery G of the lower electrode 1g. The configuration other than the groove T is the same as in FIG. 3. The lower electrode 1g is connected by an outer periphery region H (a rectangle indicated by a dashed line in the figure that touches the end of the lower electrode 1g). For this reason, the stress generated on both sides of the outer periphery region H is transmitted without being separated, and the effect of reducing the stress applied to the semiconductor element 1a is not obtained. For this reason, the thermal deformation of the semiconductor element 1a is likely to become large.

[0094] Fig. 11 is a graph showing the results of thermal stress analysis comparing the embodiment shown in Fig. 3 with the comparative example shown in Fig. 10. Both the embodiment and the comparative example show the case where solder containing Sn as a main component, which is a lead-free bonding material, is used. The vertical axis shows normalized stress σ as in Fig. 7. Note that the denominator used for normalizing the stress is the stress when lead solder is used for the conductive bonding material 1p.

[0095] 11, the comparative example Cm has a high value of 1.48 compared to 1.22 for the embodiment Ex. From this result, it is understood that it is desirable for the groove T to reach the end of the lower electrode 1g. EXAMPLES

[0096] Second Embodiment Next, a semiconductor device according to a second embodiment will be described with reference to FIGS.

[0097] FIG. 12 is a plan view partially showing the electronic circuit body of this embodiment.

[0098] In this figure, the width of the lower electrode 1g is narrowed, and the end Te is configured to be located inside the semiconductor element 1a. A groove T is provided in the lower electrode 1g.

[0099] FIG. 13 is a cross-sectional view taken along line BB' of FIG.

[0100] In FIG. 13, the end of the lower electrode 1g is located inside the semiconductor element 1a.

[0101] FIG. 14 is a vertical cross-sectional view showing the vicinity of an end portion of the semiconductor element of this embodiment.

[0102] As shown in the figure, the lower electrode 1g is not bonded to the region D2 located at the edge of the semiconductor element 1a. Therefore, for example, when the lower electrode 1g thermally shrinks during the cooling process of the reflow process or flow process, the edge of the semiconductor element 1a does not receive stress from the lower electrode 1g. This makes it possible to reduce the stress at point p1.

[0103] The configuration in which the end of the lower electrode 1g is located inside the end of the semiconductor element 1a can also be applied to a configuration in which the groove T is provided. Moreover, compared to a configuration in which the groove T is simply provided in the lower electrode 1g, the stress at the point p1 can be further reduced. EXAMPLES

[0104] FIG. 15 is a plan view partially showing the electronic circuit body of the third embodiment.

[0105] In this figure, grooves T are provided along the longitudinal direction of lower electrode 1g, reaching the ends, and grooves T2 are provided in two of the four grooves T. Groove T2 is provided along the lateral direction of lower electrode 1g. Groove T2 is provided midway along groove T so as to communicate with groove T. In other words, groove T has a branched groove T2.

[0106] The configuration of this embodiment is obtained by adding a groove T2 to the configuration of the first embodiment shown in FIG.

[0107] With this configuration, it is possible to suppress thermal deformation of the semiconductor element 1a in both the longitudinal and lateral directions of the lower electrode 1g, and it is possible to further reduce the stress generated in the semiconductor element 1a.

[0108] Fig. 16 is a graph showing the effect of the configuration of Fig. 15. The conditions are the same as those of Fig. 11.

[0109] 16, the thermal stress σ in this embodiment (Ex3) is 1.17, which is lower than that in Example 1 (Ex1). Therefore, by adding the groove T2 to the groove T, the effect of further reducing the thermal stress can be obtained.

[0110] The effects obtained by the semiconductor device of the present disclosure will be summarized below.

[0111] According to the semiconductor device of the present disclosure, it is possible to reduce the stress generated in the semiconductor element, suppress an increase in thermal resistance, and improve reliability.

[0112] Since the stress can be reduced, damage to the semiconductor element can be prevented.

[0113] Since an increase in thermal resistance can be suppressed, failure of the semiconductor element can be prevented.

[0114] Furthermore, not only in a single-sided mounting structure but also in a double-sided mounting structure, temperature rise can be suppressed, and failure can be prevented even if a large current is applied during use. [Explanation of symbols]

[0115] 1a: semiconductor element, 1b: capacitor, 1c: control circuit chip, 1d: upper electrode, 1p, 1q: conductive bonding material, 1f: wire, 1g: lower electrode, 1h: resin, 1i: lead frame, 2: base, 2a: pedestal, 3: lead, 3a: lead header, 4a, 4b: conductive bonding material, 5: molded resin, 100: electronic circuit body, 200: semiconductor device, L: surface protective film, T, T2: groove, S: source electrode, C: gate electrode, D: drain electrode.

Claims

1. a semiconductor chip having a first main electrode on one surface and a second main electrode and a gate electrode on the other surface; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; a second electrode connected to the other surface of the semiconductor chip via a second bonding material, the first electrode is a plate-like electrode and has a groove in an area overlapping the semiconductor chip; the groove has a configuration penetrating the first electrode in a thickness direction, and has a shape that, when viewed in a plan view, is in the vicinity of an end of the semiconductor chip, is along the end of the semiconductor chip, and reaches an end of the first electrode; A semiconductor device, wherein when a region closer to the center of the semiconductor chip than the groove is defined as a first region, and a region closer to the end of the semiconductor chip than the groove is defined as a second region, in each of the first region and the second region, the semiconductor chip and the first electrode are connected by the first bonding material, and the first bonding material bonding the first region and the first bonding material bonding the second region are separated by the groove.

2. The semiconductor device according to claim 1 , wherein the groove has a width greater than a thickness of the first bonding material.

3. The semiconductor device according to claim 1 , wherein said groove is provided at a position overlapping said second electrode.

4. When the distance from an end of the connection surface of the second electrode with the semiconductor chip to the end of the semiconductor chip is defined as W, and the distance from the end of the connection surface of the second electrode with the semiconductor chip to the center line of the groove is defined as J, and when the center line of the groove is closer to the center of the semiconductor chip than the end of the second electrode, J takes a negative value, and J / W is defined as X, The semiconductor device according to claim 1 , wherein the position of the center line of the groove satisfies the following formula (1): -1.2<X<0.3...(1)

5. 2. The semiconductor device according to claim 1, wherein the first bonding material and the second bonding material are solders containing Sn as a main component.

6. 2. The semiconductor device according to claim 1, wherein an end of said second electrode is located inside said semiconductor chip when viewed in a plan view, and said end of said first electrode is located outside said semiconductor chip when viewed in a plan view.

7. 2. The semiconductor device according to claim 1, wherein an end of said second electrode is located inside said semiconductor chip when viewed in a plan view, and said end of said first electrode is located inside said semiconductor chip when viewed in a plan view.

8. 2. The semiconductor device according to claim 1, wherein said groove further comprises a groove branched off from said groove and communicating with said groove.

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