Semiconductor structure, memory and method of operation thereof

Abstract

The present invention provides a semiconductor structure, a memory and a method of operating the same, the semiconductor structure comprising: a substrate; a first gate structure and a second gate structure located on a surface of the substrate, the second gate structure and the first gate structure having the same thickness, the second gate structure being smaller than a predetermined thickness; and a first doped region and a second doped region located in the substrate and respectively on either side of the first gate structure, the first gate structure forming a select transistor together with the first doped region and the second doped region, an orthogonal projection of the second gate structure on the substrate at least partially overlaps with the second doped region, the second gate structure and the second doped region form an anti-fuse bit structure, and a breakdown state and a non-breakdown state of the anti-fuse bit structure are used to represent different stored data.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on July 8, 2022, bearing application number 202210806749.X and entitled "Semiconductor structure, memory and method of operation thereof," the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of semiconductor technology, and in particular, but not exclusively, to semiconductor structures, memories and methods of operation thereof. [Background technology]

[0003] With the current development of science and technology, the performance of semiconductor memory devices is getting higher and higher, while the feature size is getting smaller and smaller. Here, one-time programmable (OTP) memory is a non-volatile memory (NVM) that can retain stored data even when the power is turned off. OTP memory can only perform one-time write programming and cannot be electrically erased. It can be applied to program code memory, serial configuration memory, and system-on-chip (SOC), and plays roles such as ID recognition and memory repair.

[0004] At present, OTP memory mainly adopts a structure similar to that of dynamic random access memory (DRAM), which includes one selection transistor and one destructible capacitor (1T1C), and since the destruction of the dielectric layer of the capacitor is irreversible, the solidified stored data can be obtained by reading the destruction state of the capacitor. However, OTP memory faces problems such as a large memory cell area, low integration, complicated manufacturing process, and high manufacturing cost. Summary of the Invention

[0005] In view of the above, embodiments of the present invention provide a semiconductor structure and method for fabricating the same, a memory and method for operating the same.

[0006] In a first aspect, an embodiment of the present invention provides a semiconductor structure, the semiconductor structure comprising: a substrate; a first gate structure and a second gate structure located on a surface of the substrate, the second gate structure and the first gate structure having the same thickness less than a predetermined thickness; and a first doped region and a second doped region located within the substrate and respectively on either side of the first gate structure, the first gate structure forming a select transistor together with the first doped region and the second doped region, an orthogonal projection of the second gate structure on the substrate at least partially overlaps with the second doped region, the second gate structure and the second doped region form an anti-fuse bit structure, and a breakdown state and a non-breakdown state of the anti-fuse bit structure are used to represent different stored data.

[0007] In some embodiments, the first gate structure includes a first gate electrode and a first gate dielectric layer underlying the first gate electrode, the second gate structure includes a second gate electrode and a second gate dielectric layer underlying the second gate electrode, the first gate dielectric layer and the second gate dielectric layer have the same thickness, and the first gate dielectric layer and the second gate dielectric layer have a predetermined thin gate oxide structure.

[0008] In some embodiments, the semiconductor structure further includes a first metal line overlying the first gate structure and the second gate structure, the first metal line being connected to the first doped region via a first connecting structure.

[0009] In some embodiments, the semiconductor structure further includes a second metal line located between the first gate structure and the first metal line, the second metal line being connected to the substrate via a second connection structure.

[0010] In some embodiments, the semiconductor structure further includes an isolation structure located in the substrate between two adjacent anti-fuse bit structures, and at least a portion of the second connection structure is located on the isolation structure.

[0011] In some embodiments, the semiconductor structure further includes a third doped region located in the substrate on either side of the isolation structure, and the second connection structure is connected to the substrate via the third doped region.

[0012] In some embodiments, the semiconductor structure further includes a word line located on the first gate structure, the word line connecting a plurality of first gate structures located in an extension direction of the word line, and a third metal line located on the second gate structure, the extension direction of the third metal line being parallel to the extension direction of the word line, and the third metal line connecting a plurality of second gate structures located in the extension direction of the third metal line.

[0013] In some embodiments, two adjacent select transistors are arranged symmetrically and share the same first doped region.

[0014] In a second aspect, an embodiment of the present invention provides a method of operating a memory, the memory comprising a semiconductor structure according to any one of the above embodiments, the method comprising: performing a write operation on the memory based on data to be written, the write operation comprising destroying a target antifuse bit structure of one of the antifuse bit structures of the memory to switch the target antifuse bit structure from a non-destructive state to a destructive state, and maintaining the non-destructive state of non-target antifuse bit structures, the non-target antifuse bit structures being antifuse bit structures other than the target antifuse bit structure.

[0015] In some embodiments, the write operation further comprises applying a first voltage to the substrate to maintain the select transistor in a non-destructive state.

[0016] In some embodiments, rupturing a target antifuse bit structure of one of the antifuse bit structures of the memory to switch the target antifuse bit structure from a non-ruptured state to a ruptured state includes applying a second voltage to a first gate electrode of the select transistor connected to the target antifuse bit structure to cause the select transistor to conduct and applying a third voltage to a first metal line connected to the select transistor, where a difference between the third voltage and the second voltage is less than a breakdown voltage of a first gate dielectric layer; and applying a fourth voltage to a second gate electrode of the target antifuse bit structure to switch the target antifuse bit structure from a non-ruptured state to a ruptured state, where a voltage difference between the third voltage and the fourth voltage is greater than or equal to a breakdown voltage of a second gate dielectric layer.

[0017] In some embodiments, maintaining the non-targeted anti-fuse bit structure in a non-disrupted state includes applying a second voltage to a first gate electrode of the select transistor connected to the non-targeted anti-fuse bit structure to cause the select transistor to conduct and applying a first voltage to a first metal line connected to the select transistor, where a difference between the first voltage and the second voltage is less than or equal to a breakdown voltage of a first gate dielectric layer; and applying a fourth voltage to a second gate electrode of the non-targeted anti-fuse bit structure to maintain the non-targeted anti-fuse bit structure in a non-disrupted state, where a voltage difference between the first voltage and the fourth voltage is less than a breakdown voltage of a second gate dielectric layer.

[0018] In some embodiments, maintaining the non-targeted anti-fuse bit structure in a non-disrupted state includes applying a blocking voltage to a first gate electrode of the select transistor connected to the non-targeted anti-fuse bit structure to block the select transistor and applying a third voltage to a first metal line connected to the select transistor, where a difference between the third voltage and the blocking voltage is less than a breakdown voltage of a first gate dielectric layer; and applying a first voltage to a second gate electrode of the non-targeted anti-fuse bit structure to maintain the non-targeted anti-fuse bit structure in a non-disrupted state, where a voltage difference between the third voltage and the first voltage is less than a breakdown voltage of a second gate dielectric layer.

[0019] In some embodiments, the method of operating the memory further includes performing a read operation on the memory, the read operation including grounding the substrate; applying a first read voltage to a first gate electrode of the select transistor connected to the anti-fuse bit structure to cause the select transistor to conduct; applying a second read voltage to a first metal line connected to the select transistor; and detecting a current on the first metal line.

[0020] In a third aspect, an embodiment of the present invention provides a memory, the memory including a memory array including a semiconductor structure according to any one of the above embodiments, and a peripheral circuit coupled to the memory array.

[0021] In the semiconductor structure provided by the embodiment of the present invention, the first gate structure and the second gate structure have the same thickness, which is smaller than a predetermined thickness, and the orthogonal projection of the second gate structure on the substrate at least partially overlaps with the second doped region. In this way, on the one hand, the first gate structure and the second gate structure can have thin gate oxide structures with the same thickness, so that the channel width of the select transistor is smaller and the occupied area of ​​the semiconductor structure is reduced, and the thin gate oxide structures of the first gate structure and the second gate structure can be formed simultaneously, so that the manufacturing process is simplified; on the other hand, the overlapping portion between the second gate structure and the second doped region can reduce the horizontal length of the anti-fuse bit structure, and further reduce the occupied area of ​​the semiconductor structure, so that the integration degree of the memory can be improved. [Brief description of the drawings]

[0022] [Figure 1] 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention; [Diagram 2] 2 is a schematic diagram of another semiconductor structure according to an embodiment of the present invention. [Diagram 3] 2 is a schematic diagram of yet another semiconductor structure according to an embodiment of the present invention. [Figure 4] 2 is a schematic diagram of yet another semiconductor structure according to an embodiment of the present invention. [Diagram 5] 2 is a schematic diagram of yet another semiconductor structure according to an embodiment of the present invention. [Figure 6] 1 is a top view of a semiconductor structure according to an embodiment of the present invention. [Figure 7] 1 is a schematic diagram of a memory according to an embodiment of the present invention; [Figure 8] 2 is a schematic diagram of a memory array in a memory according to an embodiment of the present invention; [Figure 9] 3A-3D are diagrams illustrating steps of a method of operating a memory according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] In order to facilitate understanding of the embodiments of the present invention, the following describes in more detail exemplary embodiments of the present invention with reference to the associated drawings. Although exemplary embodiments of the present invention are illustrated in the drawings, it should be understood that the present invention can be realized in various forms and should not be limited by the specific embodiments described herein. The embodiments provided herein are intended to provide a more complete understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0024] In the following, many specific details are shown to allow the present invention to be more fully understood. However, it is clear to those skilled in the art that the present invention can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present invention, some technical features that are well known in the art are not described, that is, all the features of the actual embodiment are not described in this specification, and well-known functions and configurations are not described in detail.

[0025] Generally, a term can be understood, at least in part, from its use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used in a singular sense to describe any feature, structure, or characteristic, or can be used in a plural sense to describe a combination of features, structures, or characteristics. Similarly, terms such as "a" or "said" can be understood as conveying a singular use or as conveying a plural use, depending at least in part on the context. Also, the application of "based on" is not necessarily intended to convey an exclusive set of factors, but instead can allow for the existence of additional factors not necessarily explicitly recited, also depending at least in part on the context.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "one" and "the" can include the plural unless the context clearly indicates otherwise. Additionally, the terms "comprising" and / or "comprising" as used herein determine the presence of said features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0027] In order to make the present invention fully understandable, detailed steps and detailed structures are presented in the following description to describe the technical solutions of the present invention. The preferred embodiments of the present invention are described in detail below, but the present invention can have other embodiments in addition to these detailed descriptions.

[0028] As shown in FIG. 1, an embodiment of the present invention provides a semiconductor structure 10, the semiconductor structure 10 including: a substrate 100; a first gate structure 110 and a second gate structure 120 located on a surface of the substrate 100 and having the same thickness less than a predetermined thickness; and a first doped region 101 and a second doped region 102 located in the substrate 100 and respectively located on both sides of the first gate structure 110, the first gate structure 110 together with the first doped region 101 and the second doped region 102 forming a select transistor 130, an orthogonal projection of the second gate structure 120 on the substrate 100 at least partially overlaps with the second doped region 102, the second gate structure 120 and the second doped region 102 forming an anti-fuse bit structure 140, and a destruction state and a non-destruction state of the anti-fuse bit structure 140 are used to represent different stored data.

[0029] In addition, in order to clearly show each structure in the drawings, the scale of each structure may not match the actual structure.

[0030] In an embodiment of the present invention, the semiconductor structure 10 may be used for a one-time programmable (OTP) memory, where the material of the substrate 100 may include elemental semiconductor materials such as silicon (Si), germanium (Ge), or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP). In some embodiments, the substrate 100 may further include a well region, such as a P-well and a deep N-well located below the P-well, where the P-well may be used to form a channel of the select transistor 130, and the deep N-well may be used to isolate the P-well and reduce noise interference to devices formed in the P-well.

[0031] The semiconductor structure 10 may further include a plurality of first doped regions 101 and second doped regions 102 as the source and drain of the selection transistor 130, the first doped regions 101 and the second doped regions 102 being located in the substrate 100. The first doped regions 101 and the second doped regions 102 may have the same doping type, where the impurity ions doped in the P-type doped regions may be trivalent elements such as boron, and the impurity ions doped in the N-type doped regions may be pentavalent elements such as phosphorus, arsenic, etc. In some embodiments, the first doped regions 101 and the second doped regions 102 may be high concentration N-type doped regions in a P-well, i.e., N+-type doped regions.

[0032] 1, there is a first gate structure 110 and a second gate structure 120 on the surface of a substrate 100, and the first gate structure 110 and the second gate structure 120 may be located in the same plane and have the same thickness. The first doped region 101 and the second doped region 102 are located on either side of the first gate structure 110, respectively, and the first doped region 101 together with the second doped region 102 and the first gate structure 110 form a select transistor 130. Also, the projection of the second gate structure 120 on the substrate 100 at least partially overlaps with the second doped region 102, and the second gate structure 120 and the second doped region 102 form an anti-fuse bit structure 140. The anti-fuse bit structure 140 may be a structure similar to a metal oxide semiconductor field effect transistor (MOSFET), where a breakdown state and a non-breakdown state of a gate dielectric layer of the anti-fuse bit structure 140 are used to represent different stored data, i.e., "0" or "1". Exemplarily, the first gate structure 110 may include a first gate electrode and a first gate dielectric layer, where the first gate electrode is located on the first gate dielectric layer, and the first gate electrode may be connected to a word line (WL) via a contact structure, and the second gate structure 120 may include a second gate electrode and a second gate dielectric layer, where the second gate electrode is located on the second gate dielectric layer, and the breakdown state and the non-breakdown state of the second gate dielectric layer are used to represent different stored data. The first gate electrode and the second gate electrode include, but are not limited to, conductive materials such as metals, doped semiconductors, and the first gate dielectric layer and the second gate dielectric layer may be materials such as silicon oxide, hafnium oxide, and the like.

[0033] In some embodiments, one select transistor 130 and one anti-fuse bit structure 140 form one memory cell of the OTP memory. By applying different voltages to the first gate electrode, the select transistor 130 can be controlled to be conductive or non-conductive. In some embodiments, the first doped region 101 in the select transistor 130 is also connected to a first metal line, which may be a bit line, and when the select transistor 130 is conductive, the voltage on the first metal line can be applied to the second doped region 102, and then, by applying a suitable voltage to the second gate electrode, the voltage difference between the second gate electrode and the second doped region 102 can be made equal to or greater than the breakdown voltage of the second gate dielectric layer, thereby permanently destroying the anti-fuse bit structure 140 and completing the one-time programming operation for the memory cell.

[0034] In some embodiments, the first gate dielectric layer in the first gate structure 110 has a thick gate oxide structure, and the thickness thereof can reach 6 nm. The thick gate oxide structure can enable the selection transistor 130 to withstand a higher gate voltage and reduce the possibility of the selection transistor 130 being accidentally destroyed. However, in order for the selection transistor 130 with the thick gate oxide structure to obtain a sufficient read current, the diffusion width, i.e., the channel width, of the selection transistor 130 needs to be increased, where the channel width refers to the width of the channel in the direction in which the source electrode and the drain electrode are connected. Therefore, the occupation area of ​​the selection transistor 130 is increased, which leads to a low integration degree of the OTP memory. In addition, since the anti-fuse bit structure 140 uses a thin gate oxide structure as the second gate dielectric layer, the thickness of the second gate dielectric layer is significantly different from that of the first gate dielectric layer, and in the manufacturing process, the distance between the first gate structure 110 and the second gate structure 120 needs to be relatively large to meet the requirements of the lithography process for the different gate oxide layer thicknesses, which leads to a large occupation area of ​​the semiconductor structure 10.

[0035] In the embodiment of the present invention, the first gate dielectric layer and the second gate dielectric layer may have a thin gate oxide structure with the same thickness, i.e., the first gate structure 110 and the second gate structure 120 may have the same thickness, which is smaller than a predetermined thickness. Exemplarily, the thickness of the thin gate oxide structure here may be less than 3 nm. Therefore, the thin gate oxide structure can reduce the channel width of the selection transistor 130 under the premise of having a sufficient read current, thereby reducing the area occupied by the selection transistor 130 and improving the integration degree of the memory. In addition, the first gate dielectric layer and the second gate dielectric layer have the same thickness and can be formed simultaneously during the manufacturing process, which simplifies the manufacturing process and shortens the distance between the first gate structure 110 and the second gate structure 120. Furthermore, since the projection of the second gate structure 120 on the substrate 100 at least partially overlaps with the second doped region 102, there is no need to form an additional doped region next to the second doped region 102 as a bottom electrode corresponding to the second gate electrode, which simplifies the manufacturing process and further reduces the occupied area of ​​the semiconductor structure 10. In some embodiments, the voltages applied to the first doped region 101 and the first gate electrode can be adjusted to make the voltage difference between them less than the breakdown voltage of the thin gate oxide structure, thereby reducing the possibility of accidental breakdown of the select transistor 130.

[0036] In some embodiments, as shown in FIG. 2 , the first gate structure 110 includes a first gate electrode 111 and a first gate dielectric layer 112 located below the first gate electrode 111, the second gate structure 120 includes a second gate electrode 121 and a second gate dielectric layer 122 located below the second gate electrode 121, the first gate dielectric layer 112 has the same thickness as the second gate dielectric layer 122, and the first gate dielectric layer 112 and the second gate dielectric layer 122 have a predetermined thin gate oxide structure.

[0037] In an embodiment of the present invention, the first gate structure 110 may include a first gate electrode 111 and a first gate dielectric layer 112, and the first gate dielectric layer 112 may be located at least between the first gate electrode 111 and the substrate 100, and the second gate structure 120 may include a second gate electrode 121 and a second gate dielectric layer 122, and the second gate dielectric layer 122 may be located at least between the second gate electrode 121 and the second doped region 102. Exemplarily, the first gate electrode 111 and the second gate electrode 121 may include a conductive material such as, but not limited to, tungsten (W), doped polysilicon, and the first gate dielectric layer 112 and the second gate dielectric layer 122 may be a material such as silicon oxide, hafnium oxide, and the like. The first gate dielectric layer 112 and the second gate dielectric layer 122 have the same thickness and both have a thin gate oxide structure, where the predetermined thin gate oxide structure can be a gate oxide layer with a thickness of less than 3 nm, where the thickness refers to the thickness in the direction perpendicular to the surface of the substrate 100. The first gate dielectric layer 112 with the thin gate oxide structure can make the channel width of the selection transistor 130 smaller, thereby reducing the occupation area of ​​the selection transistor 130, and can simplify the manufacturing process because the first gate dielectric layer 112 and the second gate dielectric layer 122 with the same thickness can be formed simultaneously. In this way, when the voltage difference between the second gate electrode 121 and the second doped region 102 is greater than or equal to the breakdown voltage of the second gate dielectric layer 122, the second gate dielectric layer 122 is broken down, i.e., the anti-fuse bit structure 140 is permanently broken down, thereby completing the one-time programming operation for the memory cell.

[0038] In some embodiments, the first gate dielectric layer 112 and the second gate dielectric layer 122 may be the same continuous layer of a thin gate oxide structure, where the part of the thin gate oxide structure located between the first gate electrode 111 and the substrate 100 is the first gate dielectric layer 112 and the part of the thin gate oxide structure located between the second gate electrode 121 and the second doped region 102 is the second gate dielectric layer 122.

[0039] In some embodiments, as shown in Figures 3 to 6, the first gate structure 110 may be connected to a word line 113 via a contact structure, and the second gate structure 120 may be connected to a third metal line 123 via a contact structure, and the extension direction of the word line 113 may be parallel to the extension direction of the third metal line 123.

[0040] In some embodiments, as shown in FIG. 3, the semiconductor structure 10 further includes a first metal line 150. A first metal line 150 is located over the first gate structure 110 and the second gate structure 120 , and the first metal line 150 is connected to the first doped region 101 via a first connection structure 160 .

[0041] In an embodiment of the present invention, the first metal line 150 can be a bit line (BL) in the memory. When the select transistor 130 is conductive, a voltage on the first metal line 150 can be applied to the second doped region 102 of the anti-fuse bit structure 140 through the select transistor 130, and then, by applying an appropriate voltage to the second gate electrode 121, the voltage difference between the second doped region 102 and the second gate electrode 121 can be made equal to or greater than the breakdown voltage of the second gate dielectric layer 122, thereby permanently destroying the anti-fuse bit structure 140 and completing the one-time programming operation for the memory cell. The extension direction of the first metal line 150 can be perpendicular to the extension direction of the word lines 113 in the memory, so that a memory cell array can be formed by providing memory cells at the intersections of the extension directions of the bit lines and the word lines 113. In another embodiment, the extension direction of the first metal line 150 crosses but is not perpendicular to the extension direction of the word lines 113. The first metal line 150 is connected to the first doped region 101 via a first connecting structure 160, where the first connecting structure 160 may be a conductive material such as a metal, a doped semiconductor, or the like.

[0042] In some embodiments, as shown in FIG. 3, the substrate 100 includes a first well 104 and a second well 105 having opposite doping types, the second well 105 being located below the first well 104, the first doped region 101 and the second doped region 102 being located within the first well 104, and the doping type of the first doped region 101 and the second doped region 102 being the same as the doping type of the second well 105.

[0043] In an embodiment of the present invention, the substrate 100 further includes a second well 105 and a first well 104 located above the second well 105, where the first well 104 is used to form a channel of the selection transistor 130, and the doping types of the first well 104 and the second well 105 are opposite, so that the second well 105 has the same doping type as the first doped region 101 and the second doped region 102, and the second well 105 can effectively isolate the first well 104. In some embodiments, the substrate 100 may further include a base 106 located below the second well 105, where the doping type of the base 106 may be the same as the doping type of the first well 104. Exemplarily, the first well 104 is a P well, the second well 105 is a deep N well, the base 106 is a P-type doped semiconductor material, and the first doped region 101 and the second doped region 102 are N-type doped regions, thus forming reverse-biased PN junctions between the first well 104 and the second well 105 and between the second well 105 and the base 106, thereby reducing noise interference to devices formed in the first well 104. In some embodiments, the second well 105 can surround the bottom and side surfaces of the first well 104 to improve isolation effect.

[0044] In some embodiments, as shown in FIG. 4, the semiconductor structure 10 further includes a second metal line 190. A second metal line 190 is located between the first gate structure 110 and the first metal line 150 , and the second metal line 190 is connected to the substrate 100 via a second connection structure 170 .

[0045] In the embodiment of the present invention, the second metal line 190 can apply a voltage to the substrate 100 through the second connection structure 170. The second metal line 190 is located above the first gate structure 110 and below the first metal line 150, thereby reducing problems such as shorting between the second metal line 190 and the first gate structure 110 and the first metal line 150. Here, the second connection structure 170 may be a conductive material such as a metal, a doped semiconductor, etc. The second metal line 190 is used to apply a voltage to the substrate 100, thereby ensuring that the PN junction formed between the first doped region 101, the second doped region 102, and the substrate 100 in each selection transistor 130 is not broken down in the reverse direction (such as avalanche breakdown of the source electrode and the drain electrode in a MOS transistor). In some embodiments, in the memory cell array of the OTP memory, the second metal lines 190 are laid out in a matrix and respectively connected to the substrates of the multiple selection transistors 130 via multiple second connection structures 170, thereby ensuring that the PN junctions in the multiple selection transistors 130 are not reversely broken down when a voltage is applied to the substrates of the multiple memory cells simultaneously.

[0046] In some embodiments, as shown in FIG. 4, the semiconductor structure 10 further includes an isolation structure 180. An isolation structure 180 is located in the substrate 100 between two adjacent anti-fuse bit structures 140 , where at least a portion of the second connecting structure 170 is located above the isolation structure 180 .

[0047] In the embodiment of the present invention, the anti-fuse bit structures 140 of two memory cells that are adjacent to each other and do not share the same first doped region 101 are located close to each other. Thus, by providing an isolation structure 180 between the two adjacent anti-fuse bit structures 140, problems such as electrical leakage between the active regions of the two memory cells that are adjacent to each other and do not share the first doped region 101 can be prevented. Here, the depth of the isolation structure 180 is greater than the depth of the first doped region 101 and the depth of the second doped region 102. Exemplarily, the isolation structure 180 may be a shallow trench isolation (STI) having a good isolation effect at low cost, and the material of the isolation structure 180 includes, but is not limited to, silicon oxide. At least a portion of the second connection structure 170 is located on the isolation structure 180, and the width of the bottom of the second connection structure 170 can be larger than the width of the top of the isolation structure 180, so that the bottom of the second connection structure 170 can be in contact with the substrate 100 to realize an electrical connection between the second connection structure 170 and the substrate 100.

[0048] In some embodiments, as shown in FIG. 4, the semiconductor structure 10 further comprises a third doped region 103; A third doped region 103 is located in the substrate 100 on either side of the isolation structure 180 , and the second connection structure 170 is connected to the substrate 100 through the third doped region 103 .

[0049] In the embodiment of the present invention, the substrate 100 on both sides of the isolation structure 180 further includes a third doped region 103, and the second connecting structure 170 is connected to the substrate 100 through the third doped region 103, so that a voltage can be applied to the substrate 100. The doping type of the third doped region 103 is opposite to that of the first doped region 101 and the second doped region 102, and the third doped region 103 is used to reduce the contact resistance between the second connecting structure 170 and the substrate 100. Exemplarily, the third doped region 103 can be a P+ type doped region.

[0050] It can be understood that the distance between the second connecting structure 170 and the first connecting structure 160 in Fig. 4 is large, i.e., one first gate structure 110 and one second gate structure 120 can be provided between the second connecting structure 170 and the first connecting structure 160, thus effectively reducing the signal interference occurring during the operation of the memory. In addition, the second gate structures 120 located on both sides of the second connecting structure 170 can play a role of self-alignment in forming the third doped region 103, where the second gate structure 120 can store data as a part of the memory cell. In some embodiments, as shown in Fig. 5, the second connection structure 170 can be located close to the first connection structure 160, i.e., only one first gate structure 110 is provided between the second connection structure 170 and the first connection structure 160, thereby saving the occupied area of ​​the semiconductor structure 10, but the first gate structure 110 provided alone here cannot form a memory cell, and only plays a role of self-alignment when forming the third doped region 103. In the case of Fig. 5, the second connection structure 170 and the first connection structure 160 are offset by a certain distance in the word line extending direction, thereby reducing signal interference.

[0051] In some embodiments, as shown in FIG. 6, FIG. 6 is a partial top view of the semiconductor structure 10, and the semiconductor structure 10 further includes a word line 113 and a third metal line 123, where the word line 113 is located on the first gate structure 110, and the word line 113 connects multiple first gate structures 110 located in the extension direction of the word line 113, and the third metal line 123 is located on the second gate structure 120, and the extension direction of the third metal line 123 is parallel to the extension direction of the word line 113, and the third metal line 123 connects multiple second gate structures 120 located in the extension direction of the third metal line 123.

[0052] In an embodiment of the present invention, one select transistor 130 and one anti-fuse bit structure 140 form one memory cell of the OTP memory. The first gate structure 110 may be connected to a word line 113 located above the first gate structure 110 through a contact structure. The word line 113 connects the first gate structures 110 of the memory cells located in its extension direction. The second gate structure 120 may be connected to a third metal line 123 located above the second gate structure 120 through a contact structure. The third metal line 123 connects the second gate structures 120 of the memory cells located in its extension direction. The extension direction of the word line 113 is parallel to the extension direction of the third metal line 123. In this way, one word line 113 can control the conduction or blocking of the select transistors 130 of the memory cells located in its extension direction, and one third metal line 123 can simultaneously apply a voltage to the second gate structures 120 of the memory cells located in its extension direction, which can simplify the operation of the memory. For example, the word lines 113 and the third metal lines 123 may be located in the same plane parallel to the surface of the substrate 100, and the word lines 113 and the third metal lines 123 may be formed simultaneously, thereby simplifying the manufacturing process.

[0053] In some embodiments, two adjacent selection transistors 130 are disposed symmetrically and share the same first doped region 101, as shown in FIGS.

[0054] In the embodiment of the present invention, any two adjacent selection transistors 130 are provided symmetrically and share the same first doped region 101. In this way, in the OTP memory, any two adjacent memory cells are provided symmetrically and share one first doped region 101, thereby reducing the area occupied by each memory cell, and one bit line (first metal line 150) is connected to two adjacent memory cells via one first connection structure 160, thereby allowing a voltage to be applied to the first doped regions 101 of the two memory cells, thereby improving the efficiency of the memory.

[0055] As shown in FIG. 7, an embodiment of the present invention further provides a memory 20, which includes a memory array 21 including a semiconductor structure 10 described in any one of the above embodiments, and a peripheral circuit 22 coupled to the memory array 21.

[0056] In an embodiment of the present invention, the memory 20 includes a memory array 21 and a peripheral circuit 22 coupled to the memory array 21. Here, the memory array 21 includes the semiconductor structure 10 according to any one of the above embodiments. The peripheral circuit 22 includes an address circuit for latching and decoding row / column address information, a sensing circuit for monitoring and determining information stored in the anti-fuse unit, and a switching control circuit for switching the operation mode. In this way, on the one hand, the first gate structure and the second gate structure can have thin gate oxide structures with the same thickness, so that the channel width of the selection transistor is smaller and the occupied area of ​​the anti-fuse bit structure is reduced, and the thin gate oxide structures of the first gate structure and the second gate structure can be formed simultaneously, so that the manufacturing process is simplified, and on the other hand, the overlapping portion between the second gate structure and the second doped region can reduce the horizontal length of the anti-fuse bit structure and further reduce the area of ​​the anti-fuse bit structure, so that the integration degree of the memory can be improved.

[0057] 8 is a schematic diagram of the memory array 21, in which one select transistor 240 and one anti-fuse bit structure 250 form one memory cell 210. Each word line 213 connects the first gate electrodes 211 in the memory cells 210 located in its extension direction, and each third metal line 223 connects the second gate electrodes 221 in the memory cells 210 located in its extension direction. One first metal line 260 (bit line) connects two memory cells 210 adjacent to each other and sharing a first doped region 201. The memory array 21 further includes a substrate 200 to which a voltage can be applied, thereby ensuring that the PN junctions in the select transistors 240 in the memory cells 210 are not reversely broken by simultaneously applying a voltage to the channels of the select transistors 240 in the memory cells 210.

[0058] As shown in FIG. 9, an embodiment of the present invention further provides a method for operating a memory, where the memory includes the semiconductor structure 10 according to any one of the above embodiments, and the method may include the following steps:

[0059] In step S10, a write operation is performed on the memory based on data to be written, the write operation including destroying one target antifuse bit structure among the antifuse bit structures of the memory to switch the target antifuse bit structure from a non-destructive state to a destructive state, and maintaining the non-destructive state of non-target antifuse bit structures, the non-target antifuse bit structures being antifuse bit structures other than the target antifuse bit structure.

[0060] 8, in an embodiment of the present invention, when a write operation is performed on a target memory cell 210a, the second gate dielectric layer of one target anti-fuse bit structure 250a in the memory array 21 is destroyed according to data to be written, thereby switching the target anti-fuse bit structure 250a from a non-destructive state to a destructive state, while maintaining the non-destructive states of the non-target anti-fuse bit structures 250b and 250c. It can be understood that by applying different voltages to the second doped region and the second gate electrode, and making the voltage difference between them equal to or greater than the destructive voltage HV, the destructive state of the anti-fuse bit structure is realized, and when the voltage difference between them is less than the destructive voltage HV, the non-destructive state of the anti-fuse bit structure is maintained.

[0061] In some embodiments, the voltages applied to the first metal line and the word line can be controlled so that the difference between the voltage of the first doped region and the voltage of the first gate electrode is less than the breakdown voltage HV of the first gate dielectric layer, so as to prevent the first gate dielectric layer adopting a thin gate oxide structure from being accidentally broken down. It can be understood that the first gate dielectric layer and the second gate dielectric layer have the same thickness in the thin gate oxide structure, so that the breakdown voltages of both are HV. In the following, the operation method of the memory 20 will be described based on the operating voltages shown in Table 1 and FIG. 8. Here, the non-target memory cell 210b and the target memory cell 210a are connected to the same word line 213 and the same third metal line 223, and the non-target memory cell 210c and the target memory cell 210a are connected to the same bit line, i.e., the first metal line 260.

[0062] [Table 1]

[0063] In some embodiments, the write operation comprises: The method further includes applying a first voltage V1 to the substrate 200 to maintain the select transistor in a non-destructive state.

[0064] In an embodiment of the present invention, a first voltage V1 may be applied to the substrate 200 to prevent a PN junction in the select transistor 240 from being reversely broken down by a large voltage (e.g., HV) applied to the first doped region 201 and the second doped region 202 via the first metal line 260. Here, the first voltage V1 may be HV / 2. It can be understood that by simultaneously applying the first voltage V1 to the substrates of the select transistors 240 in multiple memory cells 210, the operation of the memory 20 may be simplified.

[0065] In some embodiments, destroying a target antifuse bit structure 250a of one of the antifuse bit structures 250 of the memory to switch the target antifuse bit structure 250a from a non-destructive state to a destructive state includes: applying a second voltage V2 to a first gate electrode 211a of the select transistor 240a connected to the target anti-fuse bit structure 250a to cause the select transistor 240a to conduct, and applying a third voltage V3 to a first metal line 260 connected to the select transistor 240a, wherein a difference between the third voltage V3 and the second voltage V2 is less than a breakdown voltage HV of a first gate dielectric layer; applying a fourth voltage V4 to the second gate electrode 221a of the target anti-fuse bit structure 250a to switch the target anti-fuse bit structure 250a from a non-destructive state to a destruction state, where a voltage difference between the third voltage V3 and the fourth voltage V4 is greater than or equal to a destruction voltage HV of a second gate dielectric layer.

[0066] In the embodiment of the present invention, data can be written by destroying the target anti-fuse bit structure 250a in the target memory cell 210a. Specifically, as shown in FIG. 8, a second voltage V2 is applied to the first gate electrode 211a of the select transistor 240a connected to the target anti-fuse bit structure 250a, i.e., the second voltage V2 is applied to the word line 213 to make the select transistor 240a conductive. Optionally, the second voltage V2 here may be a destruction voltage HV. At the same time, a third voltage V3 is applied to the first metal line 260 connected to the select transistor 240a, and a fourth voltage V4 is applied to the second gate electrode 221a of the target anti-fuse bit structure 250a, i.e., the fourth voltage V4 is applied to the third metal line 223. In this way, the third voltage V3 is applied to the second doped region 202a of the target anti-fuse bit structure 250a by the conductive selection transistor 240a, and the voltage difference between the third voltage V3 and the fourth voltage V4 is greater than or equal to the breakdown voltage HV, thereby switching the target anti-fuse bit structure 250a from a non-destructive state to a destruction state. Optionally, the third voltage V3 here can be the breakdown voltage HV, and the fourth voltage V4 can be 0V. It can be understood that since the second voltage V2 is applied to the first gate electrode 211a and the third voltage V3 is applied to the first doped region 201a, the voltage difference between the first gate electrode 211a and the first doped region 201a is 0V, which is less than the breakdown voltage HV of the first gate dielectric layer, ensuring that the first gate dielectric layer is not destroyed by mistake.

[0067] In some embodiments, maintaining the non-destructive state of the non-targeted anti-fuse bit structure comprises: applying the second voltage V2 to a first gate electrode 211b of the select transistor 240b connected to the non-target anti-fuse bit structure 250b to cause the select transistor 240b to conduct, and applying the first voltage V1 to a first metal line 260b connected to the select transistor 240b, wherein a difference between the first voltage V1 and the second voltage V2 is less than a breakdown voltage HV of a first gate dielectric layer; applying a fourth voltage V4 to the second gate electrode 221b of the non-target anti-fuse bit structure 250b to maintain the non-target anti-fuse bit structure 250b in a non-destructive state, where a voltage difference between the first voltage V1 and the fourth voltage V4 is less than a breakdown voltage HV of a second gate dielectric layer.

[0068] In an embodiment of the present invention, when destroying the target anti-fuse bit structure 250a in the target memory cell 210a, it is also necessary to maintain the non-destruction state of the non-target anti-fuse bit structure 250b in the non-target memory cell 210b. Specifically, as shown in FIG. 8, for the non-target memory cell 210b connected to the same word line 213 and the same third metal line 223 as the target memory cell 210a, a second voltage V2 is applied to the first gate electrode 211b of the selection transistor 240b connected to the non-target anti-fuse bit structure 250b to make the selection transistor 240b conductive, so that it is necessary to ensure that the voltage difference between the second doped region 202b and the second gate electrode 221b of the non-target anti-fuse bit structure 250b is smaller than the destruction voltage HV. Therefore, a first voltage V1 is applied to the first metal line 260b connected to the select transistor 240b, and thus the first voltage V1 is applied to the second doped region 202b of the non-targeted anti-fuse bit structure 250b by the conductive select transistor 240b, and the voltage difference between the fourth voltage V4 on the second gate electrode 221b and the first voltage V1 on the second doped region 202b is less than the breakdown voltage HV, so that the non-targeted anti-fuse bit structure 250b remains in a non-breakdown state. Optionally, the second voltage V2 here can be the breakdown voltage HV, the first voltage V1 can be HV / 2, and the fourth voltage V4 can be 0V. It can be understood that since the second voltage V2 is applied to the first gate electrode 211b and the first voltage V1 is applied to the first doped region 201b, the voltage difference between the first gate electrode 211b and the first doped region 201b is HV / 2, which is smaller than the breakdown voltage HV of the first gate dielectric layer, thereby ensuring that the first gate dielectric layer is not broken down accidentally.

[0069] In some embodiments, maintaining the non-destructive state of the non-targeted anti-fuse bit structure comprises: applying a blocking voltage Voff to a first gate electrode 211c of the select transistor 240c connected to the non-target anti-fuse bit structure 250c to block the select transistor 240c, and applying a third voltage V3 to a first metal line 260 connected to the select transistor 240c, wherein a difference between the third voltage V3 and the blocking voltage Voff is less than a breakdown voltage HV of the first gate dielectric layer; applying a first voltage V1 to a second gate electrode 221c of the non-target anti-fuse bit structure 250c to maintain the non-target anti-fuse bit structure 250c in a non-destructive state, where a difference between the third voltage V3 and the first voltage V1 is less than a breakdown voltage HV of a second gate dielectric layer.

[0070] In the embodiment of the present invention, when the target antifuse bit structure 250a in the target memory cell 210a is destroyed, it is also necessary to maintain the non-destructed state of the non-target antifuse bit structure 250c in the non-target memory cell 210c. Specifically, as shown in FIG. 8, the non-target memory cell 210c is connected to the same first metal line 260 (i.e., bit line) as the target memory cell 210a. Since the third voltage V3 is applied to the first metal line 260 connected to the non-target antifuse bit structure 250c, the cut-off voltage Voff can be applied to the first gate electrode 211c of the selection transistor 240c connected to the non-target antifuse bit structure 250c, i.e., the cut-off voltage Voff can be applied to the word line 213c to cut off the selection transistor 240c, and at this time, the third voltage V3 is not transferred to the second doped region 202c through the selection transistor 240c. At the same time, the first voltage V1 can also be applied to the second gate electrode 221c of the non-target anti-fuse bit structure 250c, i.e., the first voltage V1 can also be applied to the third metal line 223c, and the difference between the third voltage V3 and the first voltage V1 is less than the breakdown voltage HV of the second gate dielectric layer, so as to further ensure that the non-target anti-fuse bit structure 250c is not destroyed. Optionally, the cut-off voltage Voff here can be HV / 2, the first voltage V1 can be HV / 2, and the third voltage V3 can be the breakdown voltage HV. It can be understood that, since the cut-off voltage Voff is applied to the first gate electrode 211c and the third voltage V3 is applied to the first doped region 201c, the voltage difference between the first gate electrode 211c and the first doped region 201c is HV / 2, which is less than the breakdown voltage HV of the first gate dielectric layer, so as to ensure that the first gate dielectric layer is not erroneously destroyed.

[0071] In some embodiments, the method further includes performing a read operation on the memory, the read operation including grounding the substrate 200, applying a first read voltage Vwlr to a first gate electrode 211 of the select transistor 240 connected to the anti-fuse bit structure 250 to cause the select transistor 240 to conduct, applying a second read voltage Vblr to a first metal line 260 connected to the select transistor 240, and detecting a current on the first metal line 260.

[0072] [Table 2]

[0073] In an embodiment of the present invention, the write and read operations for the memory 20 can also be performed based on the operating voltages shown in Table 2. Here, Vblr is the second read voltage Vblr of the first metal line 260, i.e., the bit line, and Vwlr is the first read voltage Vwlr of the word line 213. When Vwlr is applied to the word line 213, i.e., the first gate electrode 211, the selection transistor 240 is turned on, and at this time, the substrate 200 is grounded, i.e., the voltage on the substrate 200 is 0V, Vblr is applied to the first metal line 260, and 0V is applied to the third metal line 223, i.e., the second gate electrode 221, and thus, by detecting the current on the first metal line 260, it can be determined whether the anti-fuse bit structure 250 is in a destruction state or a non-destruction state, and thus a read operation can be realized.

[0074] In some embodiments, the voltage required for breakdown is small because the overlap area between the second doped region and the antifuse electrode is small, and therefore a relatively small voltage can be applied to the substrate, the word line structure, the antifuse electrode, and the first metal line in the memory, and the duration of the applied voltage is relatively short, thereby saving energy consumption.

[0075] It should be noted that the features disclosed in some method or device embodiments provided in the present invention can be arbitrarily combined without conflict to obtain new method or device embodiments. The above content is merely an embodiment of the present invention, and the protection scope of the present invention is not limited thereto. Any modifications or replacements that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. [Industrial Applicability]

[0076] In the semiconductor structure provided by the embodiment of the present invention, the first gate structure and the second gate structure have the same thickness, which is smaller than a predetermined thickness, and the orthogonal projection of the second gate structure on the substrate at least partially overlaps with the second doped region. In this way, on the one hand, the first gate structure and the second gate structure can have thin gate oxide structures with the same thickness, so that the channel width of the select transistor is smaller and the occupied area of ​​the semiconductor structure is reduced, and the thin gate oxide structures of the first gate structure and the second gate structure can be formed simultaneously, so that the manufacturing process is simplified, and on the other hand, the overlapping portion between the second gate structure and the second doped region reduces the horizontal length of the anti-fuse bit structure and further reduces the occupied area of ​​the semiconductor structure, so as to improve the integration density of the memory.

Claims

1. A semiconductor structure applied to a one-time programmable (OTP) memory, comprising: A substrate; a first gate structure and a second gate structure located on a surface of the substrate, the second gate structure and the first gate structure having the same thickness, which is less than a predetermined thickness, the first gate structure including a first gate electrode and a first gate dielectric layer located below the first gate electrode, the second gate structure including a second gate electrode and a second gate dielectric layer located below the second gate electrode, the first gate dielectric layer and the second gate dielectric layer having the same thickness, and the first gate dielectric layer and the second gate dielectric layer having a thin gate oxide structure, which is less than 3 nm; a first doped region and a second doped region respectively located in the substrate and on either side of the first gate structure, the first gate structure forming a select transistor together with the first doped region and the second doped region; an orthogonal projection of the second gate structure in a direction perpendicular to the substrate at least partially overlaps with the second doped region, the second gate structure and the second doped region forming an anti-fuse bit structure, a breakdown state and a non-breakdown state of the anti-fuse bit structure being used to represent different stored data; The semiconductor structure further comprises: a first metal line overlying the first gate structure and the second gate structure and connected to the first doped region via a first connection structure; a second metal line located between the first gate structure and the first metal line, the second metal line being connected to the substrate via a second connection structure.

2. The semiconductor structure further comprises: an isolation structure located in the substrate between two adjacent anti-fuse bit structures, and at least a portion of the second connection structure is located on the isolation structure; The semiconductor structure of claim 1 .

3. The semiconductor structure further comprises: a third doped region located in the substrate on either side of the isolation structure, the second connection structure being connected to the substrate via the third doped region; The semiconductor structure of claim 2 .

4. The semiconductor structure further comprises: a word line located above the first gate structure, the word line connecting a plurality of first gate structures located in an extension direction of the word line; a third metal line located on the second gate structure, the extension direction of the third metal line being parallel to the extension direction of the word line, the third metal line connecting a plurality of second gate structures located in the extension direction of the third metal line; The semiconductor structure of claim 1 .

5. The two adjacent select transistors are provided symmetrically and share the same first doped region. The semiconductor structure of claim 1 .

6. A method of operating a memory including a semiconductor structure according to any one of claims 1 to 5, comprising the steps of: and executing a write operation on the memory based on data to be written, the write operation comprising: destroying a target antifuse bit structure of one of the antifuse bit structures of the memory to switch the target antifuse bit structure from a non-destructive state to a destructive state; and maintaining a non-destructive state of non-target anti-fuse bit structures, the non-target anti-fuse bit structures being anti-fuse bit structures other than the target anti-fuse bit structure.

7. The write operation includes: and applying a first voltage to the substrate to maintain a non-destructive state of the select transistor. A method for operating the memory of claim 6.

8. Destroying a target antifuse bit structure of one of the antifuse bit structures of the memory to switch the target antifuse bit structure from a non-destructive state to a destructive state includes: applying a second voltage to a first gate electrode of the select transistor connected to the target anti-fuse bit structure to cause the select transistor to conduct, and applying a third voltage to a first metal line connected to the select transistor, a difference between the third voltage and the second voltage being less than a breakdown voltage of a first gate dielectric layer; applying a fourth voltage to a second gate electrode of the target anti-fuse bit structure to switch the target anti-fuse bit structure from a non-breakdown state to a breakdown state, wherein a voltage difference between the third voltage and the fourth voltage is greater than or equal to a breakdown voltage of a second gate dielectric layer. A method for operating the memory of claim 6.

9. maintaining the non-destructive state of the non-target anti-fuse bit structure; applying a second voltage to a first gate electrode of the select transistor connected to the non-target anti-fuse bit structure to cause the select transistor to conduct, and applying a first voltage to a first metal line connected to the select transistor, wherein a difference between the first voltage and the second voltage is less than or equal to a breakdown voltage of a first gate dielectric layer; applying a fourth voltage to a second gate electrode of the non-targeted anti-fuse bit structure to maintain the non-targeted anti-fuse bit structure in a non-breakdown state, wherein a voltage difference between the first voltage and the fourth voltage is less than a breakdown voltage of a second gate dielectric layer. A method for operating the memory of claim 6.

10. maintaining the non-destructive state of the non-target anti-fuse bit structure; applying a blocking voltage to a first gate electrode of the select transistor connected to the non-target anti-fuse bit structure to block the select transistor, and applying a third voltage to a first metal line connected to the select transistor, a difference between the third voltage and the blocking voltage being less than a breakdown voltage of a first gate dielectric layer; applying a first voltage to a second gate electrode of the non-targeted anti-fuse bit structure to maintain the non-targeted anti-fuse bit structure in a non-breakdown state, wherein a voltage difference between the third voltage and the first voltage is less than a breakdown voltage of a second gate dielectric layer. A method for operating the memory of claim 6.

11. The method of operating the memory includes: and performing a read operation on the memory, the read operation comprising: grounding the substrate; applying a first read voltage to a first gate electrode of the select transistor connected to the anti-fuse bit structure to cause the select transistor to be conductive; applying a second read voltage to a first metal line connected to the select transistor; and detecting a current on the first metal line. A method for operating the memory of claim 6.

12. A memory, A memory array comprising a semiconductor structure according to any one of claims 1 to 5; and peripheral circuitry coupled to the memory array.

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