Electronic component embedded package and electronic device

Abstract

To improve pad bonding reliability.SOLUTION: A package 10 with built-in electronic components to be soldered to an electronic circuit board has an insulating layer 11, an electronic component 12 provided on one side of the insulating layer 11, and a pad 13 where the apertures 13c1 to 13c5 reaching from the side 13a contacting with a solder bump 14 to the insulating layer 11, electrically connected to the electronic component 12 and having a larger aperture area on the side 13a of the apertures 13c1 to 13c5 than that on the side 13b, which is the side opposite to the side 13a and in contact with the insulating layer 11.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an electronic component built-in package and an electronic device. [Background technology]

[0002] Known electronic component built-in packages include chip size packages (CSPs) and fan out wafer level packages (FOWLPs), which enable high density mounting of electronic components (see, for example, Patent Documents 1 and 2).

[0003] Among these, FOWLP has a rewiring layer formed by a build-up wiring process on a pseudo wafer formed by embedding electronic components (e.g., semiconductor chips) in molding resin, and is capable of accommodating multi-terminal electronic components.

[0004] The FOWLP is soldered to a printed wiring board or the like when used. However, when heat is generated during the operation of electronic components, the stress generated by the difference in thermal expansion coefficient between the FOWLP and the printed wiring board or the like can cause destruction of the joint, resulting in disconnection of the redistribution layer. A method has been proposed in the past in which pads that are electrically insulated from the electronic components and have through holes are provided at the four corners of the FOWLP where thermal stress is likely to concentrate, and holes are formed in the solder bumps formed on the pads (see, for example, Patent Document 2). With this method, when thermal stress becomes excessive, cracks occur in the solder bumps with the holes formed therein before cracks occur in the insulating film of the redistribution layer, suppressing the occurrence of cracks in the insulating film. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2004-153249 A [Patent Document 2] JP 2020-88105 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, with conventional methods, there was a possibility that the pads of the FOWLP would peel off due to heat generated during soldering between the FOWLP and a printed wiring board, etc. As a result, sufficient joint reliability could not be obtained. This problem is not limited to FOWLPs, but can also occur with other electronic component embedded packages such as CSPs.

[0007] According to one aspect, the present invention has an object to provide an electronic component built-in package and an electronic device that can improve the bonding reliability of pads. [Means for solving the problem]

[0008] In one embodiment, an electronic component embedded package is provided that is solder-bonded to an electronic circuit board, the package having an insulating layer, an electronic component provided on one side of the insulating layer, and a pad having a plurality of openings formed from a first side that contacts a solder bump to the insulating layer and is electrically connected to the electronic component, and a second side of the plurality of openings that is opposite the first side and contacts the insulating layer and has an opening area smaller than the opening area on the first side.

[0009] Also provided in one embodiment is an electronic device. Effect of the Invention

[0010] In one aspect, the present invention can improve the bonding reliability of the pad. [Brief description of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing a portion of an electronic component built-in substrate according to a first embodiment. [Diagram 2] FIG. [Diagram 3] 11 is a cross-sectional view (part 1) of a process for manufacturing the electronic component built-in package according to the second embodiment. FIG. [Figure 4] 13 is a cross-sectional view (part 2) of a process for manufacturing the electronic component built-in package according to the second embodiment. FIG. [Diagram 5] 13 is a cross-sectional view (part 3) of a process for manufacturing the electronic component built-in package according to the second embodiment. FIG. [Figure 6] 13 is a cross-sectional view (part 4) of a process for manufacturing the electronic component built-in package according to the second embodiment. FIG. [Figure 7] 13 is a cross-sectional view (part 5) of a process for manufacturing the electronic component built-in package according to the second embodiment. FIG. [Figure 8] 13 is a cross-sectional view (part 6) of a process for manufacturing the electronic component built-in package according to the second embodiment. FIG. [Figure 9] FIG. 7 is a cross-sectional view (part 7) of a process for manufacturing the electronic component built-in package according to the second embodiment. [Figure 10] 8 is a cross-sectional view (part 8) of a process for manufacturing the electronic component built-in package according to the second embodiment. FIG. [Figure 11] FIG. 9 is a cross-sectional view of a process for manufacturing the electronic component built-in package according to the second embodiment (part 9). [Figure 12] FIG. 10 is a cross-sectional view of a process for manufacturing the electronic component built-in package according to the second embodiment (part 10). [Figure 13] 11 is a cross-sectional view of a process for manufacturing the electronic component built-in package according to the second embodiment; FIG. [Figure 14] FIG. 4 is a top view showing an example of a land. [Figure 15] 12 is a cross-sectional view of a process for manufacturing the electronic component built-in package according to the second embodiment (part 12). FIG. [Figure 16] 13 is a cross-sectional view (part 13) of a process for manufacturing the electronic component built-in package according to the second embodiment. FIG. [Figure 17] FIG. 14 is a cross-sectional view (part 14) of a process for manufacturing the electronic component built-in package according to the second embodiment. [Figure 18]FIG. 15 is a cross-sectional view (part 15) of a process for manufacturing the electronic component built-in package according to the second embodiment. [Figure 19] 16 is a cross-sectional view of a process for manufacturing the electronic component built-in package according to the second embodiment (part 16). FIG. [Figure 20] FIG. 17 is a cross-sectional view (part 17) of a process for manufacturing the electronic component built-in package according to the second embodiment. [Figure 21] FIG. 18 is a cross-sectional view (part 18) of a process for manufacturing the electronic component built-in package according to the second embodiment. [Figure 22] 1 is a cross-sectional view showing a portion of an electronic device including an electronic component built-in package and an electronic circuit board. [Diagram 23] FIG. 13 is a diagram showing the measurement results of the resistance change rate after a thermal shock test. [Figure 24] FIG. 11 is a cross-sectional view showing a first modified example of the electronic component built-in package. [Diagram 25] FIG. 11 is a cross-sectional view showing a second modified example of the electronic component built-in package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The inventors of the present application discovered that the cause of the pad peeling was that the main components of the insulating layer and contaminants in the insulating layer formed on the FOWLP were gasified by heating when soldering the FOWLP to the printed wiring board, and pressure was applied to the pads. In other words, it was found that there is another cause of the pad peeling besides the thermal stress generated by the difference in thermal expansion between the FOWLP and the printed wiring board.

[0013] The following embodiments prevent the pad from peeling off and improve the bonding reliability of the pad by efficiently exhausting the gas generated from the insulating layer during soldering. The following embodiments can be applied not only to FOWLP but also to other electronic component built-in packages such as CSPs that may generate the above-mentioned gas, and similar effects can be obtained.

[0014] Hereinafter, an embodiment of the invention will be described with reference to the drawings. (First embodiment) FIG. 1 is a cross-sectional view showing a part of an electronic component built-in substrate according to a first embodiment.

[0015] The electronic component built-in package 10 of the first embodiment is a package such as a FOWLP or CSP that is joined by soldering to an electronic circuit board such as a printed wiring board or a package substrate (also called a module substrate, etc.).

[0016] The electronic component embedded package 10 has an insulating layer 11, a pad 13 electrically connected to an electronic component 12 provided on one surface of the insulating layer, and a solder bump 14 disposed on the pad 13. In the example of Fig. 1, the pad 13 is connected to a terminal (not shown) of the electronic component 12 via a contact plug 15, a land electrode 16, and a contact via 17.

[0017] For the sake of simplicity, FIG. 1 shows one pad 13 electrically connected to one terminal (not shown) of electronic component 12; however, pads electrically connected to other terminals of electronic component 12 are provided in the same manner as pad 13.

[0018] Insulating layer 11 is, for example, an insulating film in a rewiring layer when electronic component built-in package 10 is a FOWLP, and is an insulating film in an interposer when electronic component built-in package 10 is a CSP.

[0019] The electronic component 12 is, for example, an LSI (Large Scale Integrated circuit) chip, a memory chip, etc. Although not shown in Fig. 1, the electronic component 12 is embedded in a resin material such as a molding resin.

[0020] The pad 13 is also called a BGA (Ball Grid Array) pad, and is an electrode pad on which a solder bump is disposed for soldering the electronic component built-in package 10 to an electronic circuit board. The pad 13 may include an electrode called an UBM (Under Bump Metal). The material of the pad 13 is not particularly limited as long as it is made of a material that can be electrically connected to a printed wiring board via the solder bump 14. The material of the pad 13 may be a single metal or an alloy such as copper (Cu), aluminum (Al), gold (Au), platinum (Pt), silver (Ag), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tin (Sn), or chromium (Cr).

[0021] The pad 13 may have a single structure or a laminated structure made of the above-mentioned metals or alloys. When a laminated structure is adopted, for example, in order to further enhance the effect of preventing the pad 13 from peeling off due to the configuration of the pad 13 described below, it is preferable to use a material having high adhesion strength to the insulating layer 11 for the part of the pad 13 that contacts the insulating layer 11 (for example, surface 13b). Examples of such materials include Ti, W, Ta, Sn, Cr, or alloys containing these metals. Note that, in order to prevent an increase in connection resistance or disconnection, it is preferable to use a material other than a metal that causes interdiffusion with the solder bump 14 for the part of the pad 13 that contacts the solder bump 14 (for example, surface 13a).

[0022] 1, pad 13 has openings 13c1, 13c2, 13c3, 13c4, and 13c5 formed from surface 13a in contact with the solder bump to insulating layer 11. The opening area of ​​openings 13c1-13c5 on surface 13b in contact with insulating layer 11 is smaller than the opening area on surface 13a. By providing such openings 13c1-13c5, gas generated from insulating layer 11 during solder bonding is exhausted to the outside of electronic component built-in package 10 through openings 13c1-13c5.

[0023] In addition, by making the opening area on the side of face 13b of openings 13c1 to 13c5 smaller than the opening area on the side of face 13a, gas is released more vigorously than when the opening area on the side of face 13b is equal to or larger than the opening area on the side of face 13a, allowing for efficient exhaust.

[0024] The ratio of the opening area on the surface 13b side to the opening area on the surface 13a side is appropriately determined so that the openings 13c1-13c5 are not completely blocked by solder during soldering. The openings 13c1-13c5 are created so that the opening area on the surface 13b side is in the range of, for example, 0.5 to 0.9 times the opening area on the surface 13a side.

[0025] In addition, the openings 13c1 to 13c5 also function to relieve thermal stress caused by the difference in thermal expansion between the electronic component built-in package 10 and the electronic circuit board. 1, the openings 13c1 to 13c5 are formed deeper than the surface (the surface in contact with the surface 13b) of the insulating layer 11. This makes it possible to more efficiently exhaust gas generated from the insulating layer 11.

[0026] 1, the openings 13c1-13c5 have two different opening areas in the depth direction, but may have three or more different opening areas. For example, the openings 13c1-13c5 may have a tapered shape in the depth direction (see FIG. 25 described later). However, in order to improve the adhesive strength with the solder bump 14, it is preferable that the openings 13c1-13c5 have a stepped structure in the depth direction as shown in FIG. 1 to increase the surface area.

[0027] FIG. 2 is a top view of the pad. A plurality of openings, including openings 13c1 to 13c5, are formed in pad 13. A plurality of such pads 13 are provided on one surface side (the surface side opposite to the surface on which electronic component 12 is provided) of insulating layer 11 of electronic component built-in package 10.

[0028] The shape of pad 13 as viewed from surface 13a is not particularly limited as long as it can be electrically connected to a printed wiring board via solder bump 14. However, the shape of pad 13 as viewed from surface 13a is preferably circular as shown in Fig. 2, because this can uniformly distribute thermal stress caused by the difference in thermal expansion coefficient between electronic component built-in package 10 and an electronic circuit board (not shown). If the shape of pad 13 as viewed from surface 13a is to be square, rectangular, or polygonal for some reason, it is preferable to make the corners of pad 13 rounded in order to prevent cracks or peeling in pad 13 due to stress.

[0029] For the same reason, the shape of the openings (openings 13c1 to 13c5, etc.) as viewed from above surface 13a is preferably circular as shown in Fig. 2, but is not limited thereto. The shape of the openings as viewed from above surface 13a may be, for example, a single or multiple shapes selected from an ellipse, a square, a rectangle, a polygon, or a slit shape. However, if the shape of the openings as viewed from above surface 13a is a square, rectangle, or polygon, it is preferable to make the corners of the openings round in order to prevent cracks and peeling from occurring at the corners of the openings due to thermal stress.

[0030] Taking into consideration the experimental results described later (see FIG. 23), the area ratio of the openings on the upper surface (surface 13b in FIG. 1) of pad 13 is preferably 3% or more and 30% or less. According to the electronic component built-in package 10 of the first embodiment as described above, the openings 13c1-13c5 having the above-mentioned shapes formed in the pad 13 allow gas generated from the insulating layer 11 during solder bonding to be efficiently exhausted. This prevents pressure from being applied to the pad 13 by the gas, and prevents the pad 13 from peeling off. This improves the bonding reliability of the pad 13.

[0031] (Second embodiment) An example of manufacturing a FOWLP incorporating a plurality of electronic components as the electronic component embedded package according to the second embodiment will be described below.

[0032] Each of FIGS. 3 to 13 and 15 to 21 is a cross-sectional view showing one step of the manufacturing process for the electronic component built-in package according to the second embodiment. First, a component-embedded substrate 23 is fabricated in which electronic components 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h, 21i, and 21j are embedded in molded resin 22 (FIG. 3). The electronic components 21a to 21j are, for example, LSI chips or memory chips. Although not shown in the figure, one or more terminals of each of the electronic components 21a to 21j are exposed on a surface 23a of the component-embedded substrate 23.

[0033] Thereafter, a positive-type photosensitive insulating film 24 is formed on the surface 23a of the component-embedded substrate 23 (FIG. 4). The insulating film 24 is, for example, a polyimide film or a phenol resin film. The insulating film 24 is formed, for example, by applying a resin material onto the surface 23a by a spin coat method, and then pre-baking. The pre-baking is performed, for example, under conditions of a temperature of 60° C. to 120° C. and a time of 1 minute to 30 minutes.

[0034] Next, the insulating film 24 is exposed and developed to form a plurality of contact holes (contact holes 24a, 24b, 24c, 24d, etc.) that penetrate the insulating film 24 and expose the terminals of the electronic components 21a to 21j (FIG. 5).

[0035] The contact holes are formed, for example, by using a broadband 1:1 stepper. The diameter of each contact hole is, for example, 10 μm to 20 μm. After the contact holes are formed, the substrate is cured, for example, in a nitrogen atmosphere at 150° C. to 250° C. for 30 minutes to 120 minutes.

[0036] The manufacturing process for the electronic component built-in package will be described below with a focus on a portion (portion 25) of Fig. 5. Similar processes are carried out for the other portions. After the process shown in Fig. 5, a seed layer 26 is formed on the insulating film 24 in which the contact holes 24a-24d have been formed (Fig. 6). The seed layer 26 can be formed by, for example, a sputtering method. The seed layer 26 is, for example, a laminated film in which a Ti layer and a Cu layer are laminated in this order. For example, the thickness of the Ti layer is 30 nm-200 nm, and the thickness of the Cu layer is 50 nm-500 nm.

[0037] Next, a positive resist film 27 is formed on the seed layer 26 (FIG. 7). The resist film 27 is formed, for example, by applying a resist onto the seed layer 26 by a spin coating method and pre-baking. The pre-baking is performed, for example, under conditions of a temperature of 60° C. to 120° C. and a time of 1 minute to 30 minutes.

[0038] Thereafter, the resist film 27 is exposed and developed to form opening patterns (opening patterns 27a, 27b, etc.) for land electrodes and vias and opening patterns (opening patterns 27c, 27d, etc.) for wiring, penetrating the resist film 27 (FIG. 8).

[0039] Each opening pattern is formed, for example, by using a broadband 1x stepper. The diameter of the opening pattern for the land electrode and the contact plug is, for example, 50 μm to 70 μm. The width of the opening pattern for the wiring is, for example, 5 μm to 15 μm.

[0040] Thereafter, the plating film 28 is formed by electrolytic plating using the resist film 27 having the above-mentioned opening patterns formed thereon as a mask (FIG. 9). The plating film 28 is, for example, a Cu plating film. The thickness of the plating film 28 is, for example, 1 μm to 20 μm.

[0041] Then, the resist film 27 is peeled off, and the seed layer 26 is etched using the plating film 28 as a mask. As a result, the first layer wiring (wires 29a, 29b, etc.) and lands (lands 30a, 30b, etc.) integrally molded with the contact plugs are formed (FIG. 10).

[0042] Next, the second layer of wiring and other components are formed. First, a positive-type photosensitive insulating film 31 is formed on a substrate on which a first layer of wiring and lands have been formed (FIG. 11). The insulating film 31 is, for example, a polyimide film or a phenol resin film. The insulating film 31 is formed, for example, by a spin coating method and pre-baking. The pre-baking is performed, for example, under conditions of a temperature of 60° C. to 120° C. and a time of 1 minute to 30 minutes.

[0043] Next, the insulating film 31 is exposed and developed to form a plurality of contact holes 31a, 31b, 31c, and 31d that penetrate the insulating film 31 and expose the lands (30a, 30b, etc.) (FIG. 12).

[0044] The contact holes 31a to 31d are formed, for example, using a broadband 1x stepper. The diameter of each contact hole is, for example, 15 μm to 23 μm. After the contact holes 31a to 31d are formed, they are cured, for example, in a nitrogen atmosphere at 150° C. to 250° C. for 30 minutes to 120 minutes.

[0045] 6 to 10, second-layer wirings 32a and 32b and lands 33a, 33b, 33c, and 33d integrally formed with contact vias are formed (FIG. 13). The lands 33a to 33d are electrically connected to the lands (lands 30a, 30b, etc.) of the first layer.

[0046] Here, at least one of the lands 33a to 33d has a plurality of through holes formed by etching. In the following description, it is assumed that the lands 33a and 33d have a plurality of through holes formed therein. The lands 33a and 33d become part of the pads on which the solder bumps are disposed.

[0047] FIG. 14 is a top view showing an example of a land. For example, a plurality of through holes (such as through hole 34) are formed in land 33a as shown in Fig. 14. The diameter of each through hole is, for example, 10 µm to 30 µm.

[0048] After the process shown in Fig. 13, a positive-type photosensitive insulating film 35 is formed on the substrate on which the second-layer wirings 32a, 32b and lands 33a-33d have been formed (Fig. 15). The insulating film 35 is, for example, a polyimide film or a phenol resin film. The insulating film 35 is formed, for example, by a spin coating method and pre-baking. The pre-baking is performed, for example, under conditions of a temperature of 60°C to 120°C and a time of 1 minute to 30 minutes.

[0049] The laminated structure of the insulating films 24, 31, and 35 formed in the steps up to FIG. 15 corresponds to the insulating layer 11 shown in FIG. Next, the insulating film 35 is exposed and developed to form opening patterns 35a and 35b that expose the portions of the lands 33a, 33d where the multiple through-holes are formed (FIG. 16).

[0050] The opening patterns 35a, 35b are formed, for example, using a broadband 1:1 stepper. The opening patterns 35a, 35b have a shape and size according to the shape and size of the pad to be formed. When the shape of the pad to be formed as viewed from above is circular, the diameter of the opening patterns 35a, 35b is, for example, 300 μm to 500 μm. After the opening patterns 35a, 35b are formed, they are cured, for example, in a nitrogen atmosphere at 150° C. to 250° C. for 30 minutes to 120 minutes.

[0051] The manufacturing process for the electronic component built-in package (particularly the pad manufacturing process) will be described below with reference to a portion (part P) of Fig. 16. Similar processes are carried out for the other portions. 16, the portions of the insulating film 35 that are filled in the through holes formed in the lands 33a are removed by, for example, oxygen plasma irradiation, and the through holes (for example, the through holes 34a) are formed again. At this time, the through holes are formed deeper (for example, about 0.1 μm to 2 μm deeper) than the surface of the insulating film 31 (FIG. 17).

[0052] Next, after the seed layer 36 as described above is formed on the insulating film 35 with the opening pattern 35a formed therein, a positive resist film 37 is formed on the seed layer 36 (FIG. 18). The resist film 37 is formed, for example, by applying a resist onto the seed layer 36 by spin coating and pre-baking. The pre-baking is performed, for example, under conditions of a temperature of 60° C. to 120° C. and a time of 1 minute to 30 minutes.

[0053] Thereafter, a resist pillar (for example, resist pillar 37a) having a diameter larger than the diameter of the through hole is formed on each through hole of land 33a (FIG. 19). The diameter of each resist pillar is, for example, 1.1 to 2 times the diameter of the through hole.

[0054] The resist pillars are formed, for example, using a broadband 1:1 stepper. Then, a plating film 38 is formed by electrolytic plating using the above-mentioned multiple resist pillars as a mask (FIG. 20). The plating film 38 is, for example, a Cu plating film.

[0055] Thereafter, the resist film 37 is peeled off, and the seed layer 36 is etched using the plating film 38 as a mask. As a result, a pad 39 including through holes having two different diameters in the depth direction is formed (FIG. 21). Such through holes correspond to one example of the openings 13c1-13c5 formed in the pad 13 shown in FIG.

[0056] Thereafter, although not shown, solder bumps are formed on the pads 39, completing the electronic component built-in package of the second embodiment. The electronic component built-in package 10 of the first embodiment shown in FIG. 1 can be manufactured by the same process.

[0057] Although the above describes an example of forming a pad including through holes with two different diameters, it is also possible to form through holes with three or more different diameters. In this case, the steps of Fig. 15 to Fig. 21 are repeated.

[0058] The electronic component built-in package manufactured by the above-mentioned process is soldered to an electronic circuit board such as a printed wiring board or a package substrate. FIG. 22 is a cross-sectional view showing a portion of an electronic device including an electronic component built-in package and an electronic circuit board.

[0059] The electronic component-embedded package 40 manufactured by the above-described process is solder-joined to an electronic circuit board 50, which is an example of an electronic circuit board, as shown in FIG. 22, by solder bumps 41 formed on pads 39, to manufacture electronic device 60.

[0060] The electronic circuit board 50 has a core layer 51, an insulating layer 52 provided on the surface of the core layer 51 facing the electronic component embedded package 40, and an insulating layer 53 provided on the surface of the core layer 51 opposite the electronic component embedded package 40.

[0061] A plurality of lands (e.g., lands 54 and 59), a plurality of vias (e.g., vias 55, 57, 60 and 62), and a plurality of wirings (e.g., wirings 56 and 61) are formed in the insulating layers 52 and 53. In addition, a plurality of pads (e.g., pads 58 and 63) are formed on the surfaces of the insulating layers 52 and 53.

[0062] Furthermore, a plurality of contact holes (for example, contact hole 64) are formed in core layer 51. In the example of Fig. 22, lands 54 and 59 are electrically connected by contact hole 64.

[0063] In the example of FIG. 22, a pad 58 of an electronic circuit board 50 is joined to a pad 39 of an electronic component built-in package 40 by a solder bump 41. In electronic component built-in package 40, gas generated from an insulating layer (e.g., insulating film 31) during solder bonding is efficiently exhausted by a plurality of openings (through holes) having two different diameters formed in a pad to be soldered (e.g., pad 39). This prevents pressure from being applied to the pad by the gas, and prevents the pad from peeling off. This improves the bonding reliability of the pad.

[0064] 21, the through holes are formed deeper than the surface of the insulating film 31. This makes it possible to more efficiently exhaust gas generated from the insulating layer. In addition, by suppressing the peeling of the pads as described above, it becomes easier to apply the present invention to large-area packages that are significantly affected by thermal stress. This makes it possible to ease restrictions on the number of electronic components (e.g., the number of chips) and the size of the electronic components (e.g., chip size) mounted in the electronic component-embedded package 40. This is expected to increase the bandwidth for signal transmission between electronic components (e.g., the bandwidth for communication between a CPU (Central Processing Unit) and memory) and suppress signal transmission loss.

[0065] Therefore, electronic component built-in package 40 is also suitable for, for example, high-frequency modules utilizing millimeter wave and terahertz wave bands, for which low signal transmission loss is required. (Experimental Example) A thermal shock test was carried out on an electronic device 60 in which an electronic component built-in package (FOWLP) 40 manufactured according to the above-mentioned process was soldered to an electronic circuit board 50.

[0066] The through holes formed in the pads were circular, had a diameter of 20 μm on the insulating layer side, and the area ratio of the through holes on the pad surface (surface on the solder bump side) was in the range of 0.3% to 30%. In addition, FR4 (Flame Retardant type 4) fabricated by a build-up method was used as the electronic circuit board 50.

[0067] For the thermal shock test, each sample was pretreated by three cycles of drying at 125°C for 24 hours, moisture absorption at 30°C and 60% relative humidity for 192 hours, and infrared reflow at 260°C for 1 minute.

[0068] In the thermal shock test, each sample was subjected to 100 cycles of cooling at -65°C for 5 minutes and heating at 150°C for 5 minutes. As comparative examples, thermal shock tests were also carried out under similar conditions on a number of samples in which the area ratio of the through holes on the pad surface ranged from 0% (no through holes provided) to 0.2% and from 31% to 45%.

[0069] 23 is a diagram showing the measurement results of the rate of resistance change after a thermal shock test, in which the horizontal axis represents the occupied area rate of the through holes, and the vertical axis represents the rate of resistance change. Fig. 23 shows the judgment reference value line when the resistance change rate for judging a product as non-defective is set to 10% or less. As shown in Fig. 23, when the occupation area rate of the through holes is set to 0.3% to 30%, the resistance change rate for all samples is 10% or less. In other words, it was found that there was almost no break in the current path caused by peeling of the pad or the like.

[0070] When the occupied area ratio is less than 3%, the resistance change rate increases rapidly because the effect of stress relaxation and exhausting generated gas is low. When the occupied area ratio is more than 30%, the resistance change rate increases rapidly because, although there is an effect of stress relaxation and exhausting generated gas, the adhesion strength decreases rapidly because the bonding area between the insulating layer and the pad is small. (Modification) Fig. 24 is a cross-sectional view showing a first modified example of the electronic component built-in package, in which the same elements as those shown in Fig. 1 are denoted by the same reference numerals.

[0071] A pad 71 of an electronic component built-in package 70 of a first modified example has openings 71c1, 71c2, 71c3, 71c4, and 71c5 whose opening areas on the surface 71b side are smaller than the opening areas on the surface 71a side.

[0072] The opening areas of the openings 71c1-71c5 change in multiple steps in the depth direction, unlike the openings 13c1-13c5 of the pad 13 in Fig. 1. For example, if the opening area on the surface 71a side is a first size and the opening area on the surface 71b side is a second size, the opening areas change in the depth direction from the first size, to the second size, to the first size, to the second size, as shown in Fig. 24.

[0073] Providing the openings 71c1-71c5 provides the effect of being able to exhaust gas efficiently, similar to the openings 13c1-13c5 of the pad 13 in Fig. 1. Although the number of manufacturing steps for the openings 71c1-71c5 is increased compared to the openings 13c1-13c5 of the pad 13 in Fig. 1, the openings 71c1-71c5 have a larger surface area, and therefore the adhesive strength with the solder bump 14 can be improved.

[0074] Fig. 25 is a cross-sectional view showing a second modified example of the electronic component built-in package, in which the same elements as those shown in Fig. 1 are denoted by the same reference numerals. A pad 81 of an electronic component built-in package 80 of a first modified example has openings 81c1, 81c2, 81c3, 81c4, and 81c5 whose opening area on the surface 81b side is smaller than the opening area on the surface 81a side.

[0075] The opening areas of the openings 81c1 to 81c5 are continuously reduced in the depth direction, unlike the openings 13c1 to 13c5 of the pad 13 in Fig. 1. That is, the openings 81c1 to 81c5 have a tapered shape.

[0076] Although the openings 81c1 to 81c5 have a shape such as that of the openings 81c1 to 81c5, which is inferior in adhesive strength with the solder bumps 14 compared to the openings 13c1 to 13c5 of the pads 13 in FIG. 1, they can still have the effect of allowing gas to be exhausted efficiently.

[0077] While one aspect of the electronic component built-in package and electronic device of the present invention has been described above based on the embodiment, it is to be understood that these are merely examples and the present invention is not limited to the above description. [Explanation of symbols]

[0078] 10 Electronic component embedded package 11 Insulating layer 12 Electronic Components 13 Pad 13a,13b side 13c1~13c5 opening 14 Solder Bumps 15 Contact plug 16 Land electrode 17 Contact Vias

Claims

1. In a package with built-in electronic components that is soldered to an electronic circuit board, An insulating layer; an electronic component provided on one surface of the insulating layer; a pad having a plurality of openings formed from a first surface in contact with a solder bump to the insulating layer, the pad being electrically connected to the electronic component, and the opening area of ​​a second surface side of the pad, which is a surface opposite to the first surface and in contact with the insulating layer, is smaller than the opening area of ​​the first surface side; A package with an embedded electronic component.

2. The electronic component built-in package according to claim 1 , wherein the plurality of openings have a stepped structure in a depth direction.

3. 3. The electronic component built-in package according to claim 1, wherein the plurality of openings are formed deeper than a surface of the insulating layer that contacts the second surface.

4. 4. The electronic component built-in package according to claim 1, wherein an area ratio of the plurality of openings in the first surface is equal to or greater than 3% and equal to or less than 30%.

5. The electronic component built-in package according to claim 1 , wherein the plurality of openings have a circular shape when viewed from above the first surface.

6. The electronic component built-in package according to claim 1 , wherein the plurality of openings have two or more different opening areas in a depth direction.

7. An electronic circuit board; an electronic component built-in package comprising: an insulating layer; an electronic component provided on one surface of the insulating layer; and a pad having a plurality of openings formed from a first surface contacting solder bumps to the insulating layer, the pad being electrically connected to the electronic component, the second surface being a surface opposite to the first surface and contacting the insulating layer, the second surface having an opening area smaller than the opening area on the first surface, the electronic component built-in package being joined to the electronic circuit board by the solder bumps; An electronic device having:

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