Cobalt-implanted ruthenium liner and cobalt cap interconnect structure

Abstract

The interconnect structure and method for forming the same include forming a recess in a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-implanted ruthenium liner is formed above the barrier layer, and the cobalt-containing ruthenium liner is formed by stacking a second liner over the first liner, the first liner being located above the barrier layer. The first liner comprises ruthenium, while the second liner comprises cobalt. Cobalt atoms migrate from the second liner into the first liner, forming the cobalt-implanted ruthenium liner. A conductive material is deposited over the cobalt-implanted ruthenium liner to fill the recess, and a capping layer is subsequently fabricated from cobalt.

Description

[Background technology]

[0001] The present invention relates generally to the field of complementary metal oxide semiconductor (CMOS) devices, and more specifically to fabricating copper interconnect structures with cobalt-implanted ruthenium liners and cobalt caps.

[0002] Typical components of an integrated circuit (IC) include transistors, capacitors, etc. In semiconductor chip manufacturing, these IC components are joined by interconnect structures that conduct electrical current through different circuit layers. These interconnect structures typically take the form of wires, trenches, or vias formed in a dielectric layer above the microelectronic devices or metallization levels of the IC. Interconnect structures are typically formed by depositing a dielectric layer, etching recesses in the dielectric layer, and filling the recesses with metal. Typically, interconnect structures are made from copper and can be formed using single damascene or dual damascene manufacturing processes. In a single damascene process, the interconnect structures are manufactured independently, whereas in a dual damascene process, they are manufactured simultaneously.

[0003] Generally, interconnect structures are lined with a barrier layer located at the interface between the dielectric layer and the metal level below. The presence of a barrier layer can reduce electromigration (EM) problems in ICs. Electromigration can be defined as the transport of material induced by the flow of electrons during operation under electric current, and the interface between the interconnect structure and the surrounding dielectric is the primary pathway for material transport in metal lines. In 7nm technology and beyond, ruthenium (Ru) liners are used for better copper (Cu) filling. However, cobalt (Co) from the cobalt cap used to encapsulate the copper filling can diffuse into the ruthenium liner causing EM degradation, thus representing a critical electromigration resistance (yield) issue for back-end-of-line (BEOL) technologies. Therefore, alternative designs and techniques for forming interconnect structures are desirable. Summary of the Invention

[0004] The shortcomings of the prior art are overcome and additional advantages are provided by providing a method of forming an interconnect structure that includes forming a recess in a dielectric layer, conformally depositing a barrier layer in the recess, and forming a cobalt-implanted ruthenium liner over the barrier layer. The cobalt-implanted ruthenium liner includes a first liner over the barrier layer and a second liner over the first liner. The first liner includes ruthenium, while the second liner includes cobalt. Cobalt atoms from the second liner migrate to the first liner to form the cobalt-implanted ruthenium liner. A conductive material is deposited over the cobalt-implanted ruthenium liner to fill the recess, and subsequently a capping layer including cobalt is formed over an upper surface of the conductive material. The formation of the cobalt-implanted ruthenium liner reduces the cobalt concentration gradient between the capping layer and the first liner, thereby preventing migration of cobalt from the capping layer.

[0005] Another embodiment of the present invention provides another method for forming an interconnect structure, comprising forming a recess in a dielectric layer, conformally depositing a barrier layer in the recess, followed by conformally depositing a first liner on the barrier layer and a second liner on the first liner. The first liner comprises ruthenium, while the second liner comprises cobalt. A third liner comprising ruthenium is then formed on the second liner. Migration of cobalt atoms from the second liner to the first and third liner forms a cobalt-implanted ruthenium liner. A conductive material is formed on the cobalt-implanted ruthenium liner to fill the recess, followed by deposition of a capping layer comprising cobalt on a top surface of the conductive material. Formation of the cobalt-implanted ruthenium liner reduces the cobalt concentration gradient between the capping layer and the first and third liners, thereby preventing migration of cobalt from the capping layer.

[0006] Another embodiment of the present invention provides a semiconductor structure including an interconnect structure in a dielectric layer, the interconnect structure including a barrier layer located on a bottom surface and sidewalls of the interconnect structure, a first liner located directly over the barrier layer and including ruthenium, a second liner located directly over the first liner and including cobalt, a conductive material on the second liner substantially filling the interconnect structure, and a capping layer located directly over the conductive material and including cobalt, wherein migration of cobalt atoms from the second liner to the first liner reduces the concentration gradient between the capping layer and the first liner, thereby preventing diffusion of cobalt atoms from the capping layer.

[0007] The following detailed description is given by way of example and is not intended to be limiting of the invention only, and is best understood in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0008] [Figure 1A] 1A-1C are cross-sectional views of simplified semiconductor structures illustrating forming a recess in a dielectric layer and depositing a barrier layer within the recess in accordance with one embodiment of the present invention. [Figure 1B] 1 is a cross-sectional view of a simplified semiconductor structure illustrating deposition of a first liner over a barrier layer in accordance with one embodiment of the present invention. [Figure 1C] 1 is a cross-sectional view of a simplified semiconductor structure illustrating deposition of a second liner over a first liner in accordance with one embodiment of the present invention. [Figure 1D] 2 is a cross-sectional view of a simplified semiconductor structure illustrating deposition of a first conductive material over a second liner in accordance with one embodiment of the present invention. [Figure 1E] 2 illustrates a cross-sectional view of a simplified semiconductor structure after planarization according to one embodiment of the present invention. [Figure 1F] 1 is a cross-sectional view of a simplified semiconductor structure illustrating a first interconnect structure including a first capping layer over a first conductive material in accordance with one embodiment of the present invention. [Figure 2A] 4 is a cross-sectional view of a simplified semiconductor structure illustrating forming a recess in a dielectric layer and depositing a barrier layer within the recess in accordance with another embodiment of the present invention. [Figure 2B] 4 is a cross-sectional view of a simplified semiconductor structure illustrating deposition of a first liner over a barrier layer and deposition of a second liner over the first liner in accordance with another embodiment of the present invention. [Figure 2C] 1 is a cross-sectional view of a simplified semiconductor structure illustrating deposition of a third liner over a second liner in accordance with another embodiment of the present invention. [Figure 2D] 4 is a cross-sectional view of a simplified semiconductor structure illustrating deposition of a second conductive material over a third liner in accordance with another embodiment of the present invention. [Figure 2E] 4 is a cross-sectional view of a simplified semiconductor structure after planarization according to another embodiment of the present invention. [Figure 2F] 4 is a cross-sectional view of a simplified semiconductor structure illustrating a second interconnect structure including a second capping layer over the second conductive material according to another embodiment of the present invention. [Figure 3A]4 is a cross-sectional view of a simplified semiconductor structure illustrating forming a recess in a dielectric layer and depositing a barrier layer within the recess in accordance with yet another embodiment of the present invention. [Figure 3B] 1 is a cross-sectional view of a simplified semiconductor structure illustrating deposition of a first liner, a second liner, and a third liner according to yet another embodiment of the present invention. [Figure 3C] 1 is a cross-sectional view of a simplified semiconductor structure illustrating the removal of horizontal portions of a first liner, a second liner, and a third liner in accordance with yet another embodiment of the present invention. [Figure 3D] 4 is a cross-sectional view of a simplified semiconductor structure illustrating deposition of a second conductive material over a third liner in accordance with another embodiment of the present invention. [Figure 3E] 4 is a cross-sectional view of a simplified semiconductor structure after planarization according to yet another embodiment of the present invention. [Figure 3F] 1 is a cross-sectional view of a simplified semiconductor structure illustrating a second interconnect structure including a second capping layer over a second conductive material according to yet another embodiment of the present invention.

[0009] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to illustrate only typical embodiments of the invention. In the drawings, like numbering represents like elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods that may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. In this description, details of well-known features and techniques may be omitted so as not to unnecessarily obscure the present embodiments.

[0011] In the following description, the terms "top", "bottom", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives are intended to relate to the disclosed structures and methods as oriented in the drawings. The terms "above", "overlying", "above", "on top", "located on" or "located on" mean that a first element, such as a first structure, is above a second element, such as a second structure, where there may be an intervening element, such as an interface structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating or semiconducting layer at the interface between the two elements.

[0012] It will be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element described below can be called a second element without departing from the scope of the inventive concept.

[0013] In order to avoid obscuring the presentation of the embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be grouped together for presentation and illustration purposes, and in some cases may not be described in detail. In addition, some process steps or operations known in the art may not be described at all. It should be noted that the following description instead focuses on the distinctive features or elements of various embodiments of the present invention.

[0014] Copper (Cu) has been used for many years in the manufacture of integrated circuit (IC) chips. Copper is a better electrical conductor than aluminum (Al) and can have a lower metal content. However, copper can cause problems if not properly contained within the interconnect structure. To properly contain copper, cobalt (Co) has been used in current 7nm (nanometer) interconnects as a cobalt liner and as a cobalt cap for copper encapsulation. Unfortunately, cobalt migration / diffusion has been linked to reduced electromigration lifetimes, especially when combined with ruthenium (Ru) liners typically used in 7nm technologies to enhance copper filling.

[0015] Accordingly, an embodiment of the present invention provides a method and associated structure for fabricating a copper interconnect structure having a cobalt-containing ruthenium liner and a cobalt cap. The proposed embodiment prevents the diffusion of cobalt atoms from the cobalt cap into the ruthenium liner, thereby improving electromigration performance. The method for preventing cobalt diffusion from the cobalt cap includes forming a tantalum nitride layer, followed by forming a ruthenium liner and a substantially thin cobalt liner, which can saturate the underlying ruthenium liner with cobalt atoms to form a cobalt-containing ruthenium liner, which can stop the driving force for cobalt diffusion from the cobalt cap. One embodiment in which a cobalt-containing ruthenium liner can be formed in a copper interconnect structure is described in detail below by referring to the accompanying drawings of Figures 1A-1F. An alternative embodiment in which a cobalt-containing ruthenium liner can be formed to prevent cobalt diffusion in copper interconnects is described in detail below with reference to the accompanying drawings of Figures 2A-3F.

[0016] 1A-1F, cross-sectional views of a highly simplified semiconductor structure 100 are shown during a series of processing steps in accordance with one embodiment of the present invention. The series of processing steps illustrated in Figures 1A-1F show the formation of an interconnect structure 160 in a highly simplified semiconductor structure 100 (hereinafter "semiconductor structure").

[0017] 1A, at this step in the fabrication process, semiconductor structure 100 includes a dielectric layer 106 in which recesses 108 have been formed using standard etching techniques. For illustrative purposes only and not intended to be limiting, only two recesses 108 are shown in dielectric layer 106. As known to those skilled in the art, any number of recesses 108 may be formed depending on the circuit design and / or requirements.

[0018] Dielectric layer 106 is typically formed over a device or metal level (not shown) of semiconductor structure 100. Specifically, as known to those skilled in the art, a layer of dielectric material, such as dielectric layer 106, is deposited over an active area (not shown) of semiconductor structure 100 and then etched to form openings or recesses that are later filled with a conductive material to form an interconnect structure.

[0019] The dielectric material forming the dielectric layer 106 may include, for example, a low-k dielectric material having a dielectric constant k in the range of about 2.4 to about 2.7. In some embodiments, the dielectric layer 106 may include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, a silicon-based low-k dielectric, or a porous dielectric. The dielectric layer 106 may be formed by any suitable deposition process, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0020] As described above, the dielectric layer 106 is etched to form the recesses 108. The recesses 108 may be formed using lithography and etching processing techniques typically used in single damascene and dual damascene processes. The recesses 108 may be formed to accommodate various interconnect structures (e.g., trenches, lines, or vias). Typically, the recesses 108 may extend through the dielectric layer 106 to expose an active area (not shown) of the semiconductor structure 100. The recesses 108 are then filled with a conductive metal, as described in more detail below.

[0021] As known to those skilled in the art, the recess 108 shown in Figure 1A is etched into the dielectric layer 106 having a predetermined aspect ratio (HID) between height (=H) and width (=D). In some embodiments, the aspect ratio range varies from about 0.5 to about 20, with aspect ratios between 1 and 10 being preferred. However, in practical devices, high aspect ratios (H / D) of over 20:1 may be present.

[0022] With continued reference to FIG. 1A, the barrier layer 110 is deposited on the horizontal and vertical surfaces of the dielectric layer 106. In other words, the barrier layer 110 is deposited on the bottom, sidewalls, and top surface of the dielectric layer 106 as shown. The barrier layer 110 may include any barrier material suitable for preventing the diffusion of a subsequently deposited metal layer (e.g., cobalt, ruthenium, or copper) into the dielectric layer 106. More specifically, the barrier layer 110 prevents the diffusion of atoms from the subsequently formed ruthenium and cobalt liner into the dielectric layer 106 and also acts as an adhesion promoter layer so that the ruthenium and cobalt liner is bonded to the dielectric layer 106. Experimental results indicate that depositing ruthenium directly on a dielectric material can result in poor adhesion and lead to reliability issues related to delamination.

[0023] According to one embodiment, the barrier layer 110 comprises tantalum nitride (TaN). In other embodiments, the barrier layer 110 may comprise alternative metal nitrides including, for example, titanium nitride (TiN), tungsten nitride (WN), or the like. Standard deposition processes may be used to form the barrier layer 110. For example, in some embodiments, the barrier layer 110 may be formed via a CVD, PVD, or atomic layer deposition (ALD) process.

[0024] The barrier layer 110 can have a thickness that varies from about 0.5 nm to about 5 nm, although thicknesses less than 0.5 nm and greater than 5 nm are also acceptable.

[0025] The process continues by conformally depositing a first liner 120 directly over the barrier layer 110, as shown in FIG. 1B. In a preferred embodiment, the first liner 120 is substantially, if not entirely, composed of ruthenium (Ru) and can be formed by standard deposition processes, such as PVD, CVD, electroless plating, evaporation, or any other deposition method that deposits a conformal thin film. As mentioned above, ruthenium-containing liners such as the first liner 120 are used in 7 nm technology and beyond to improve copper (Cu) fill. In particular, liners containing ruthenium can adhere better to copper seeds and allow for more conformal (i.e., eliminating voids) thinning.

[0026] The first liner 120 may have a thickness that varies from about 0.5 nm to about 5 nm, although thicknesses less than 0.5 nm and greater than 5 nm may also be acceptable. In one embodiment, the first liner 120 may have a thickness of about 10 nm.

[0027] Following the formation of the first liner 120, a second liner 130 is formed directly on the first liner 120, as shown in FIG. 1C. The second liner 130 may comprise a very thin layer of (metal) material conformally deposited on the first liner 120. In a preferred embodiment, the second liner 130 is substantially, if not entirely, composed of cobalt (Co). Standard deposition processes can be used to form the second liner 130, such as PVD, CVD, electroless plating, evaporation, or other deposition methods that deposit conformal thin films.

[0028] By forming the second liner 130 in direct contact with the first liner 120, cobalt atoms from the second liner 130 migrate to the first liner 120 (i.e., the ruthenium liner) and the first liner 120 becomes saturated with cobalt, such that there is no driving force for cobalt diffusion from the subsequently formed cobalt cap (e.g., the first capping layer 156 of FIG. 1F). Thus, depletion of the subsequently formed cobalt cap is prevented, which in turn may improve the electromigration performance of the (first) interconnect structure 160 (FIG. 1F).

[0029] It should be noted that cobalt diffusion into the ruthenium liner (e.g., first liner 120) typically occurs during thermal treatments performed on the semiconductor structure 100 during processing steps such as annealing or high temperature film deposition. Since the driving force for cobalt diffusion is the cobalt concentration gradient between the subsequently formed cobalt cap (e.g., first capping layer 156 in FIG. 1F) and the first liner 120 (i.e., the ruthenium liner), the incorporation of cobalt atoms from the second liner 130 into the first liner 120 reduces the cobalt concentration gradient between the cobalt cap and the first liner 120, thereby effectively suppressing or mitigating cobalt diffusion in the semiconductor structure 100.

[0030] The thickness of the second liner 130 may be less than the thickness of the first liner 120. According to one embodiment, the second liner 130 may have a thickness of less than about 5 nm. In other embodiments, the second liner 130 may have a thickness ranging from about 0.1 nm to about 5 nm. In yet other embodiments, the second barrier liner may be thicker than the first liner 120.

[0031] 1D, the first conductive material 142 may be conformally deposited directly on the top surface of the second liner 130. According to one embodiment, the first conductive material 142 includes copper (Cu). In some embodiments, the first conductive material 142 may further include a dopant, such as manganese, magnesium, copper, aluminum, or other known dopants. The first conductive material 142 may be formed by electroplating, electroless plating, PVD, CVD, or any combination thereof.

[0032] The thickness of the first conductive material 142 may be sufficient to completely fill the remaining space within the recess 108. However, in some cases, the thickness of the first conductive material 142 may exceed the depth of the recess 108, as shown in Figure 1D. In these cases, a planarization process may be performed on the semiconductor structure 100 to remove the areas of the first conductive material 142 that exceed the depth of the recess 108, as shown in Figure 1E.

[0033] 1E, excess portions of the first conductive material 142 may be removed from the semiconductor structure 100 by any planarization method known in the art, including, for example, chemical mechanical polishing (CMP). Additionally, during the planarization process, portions or regions of the barrier layer 110, the first liner 120, and the second liner 130 that are parallel to the dielectric layer 106 may also be removed.

[0034] The process continues with the formation of a first capping layer 156, illustrated in FIG. 1F. The first capping layer 156 is substantially, but not entirely, composed of cobalt (Co). The first capping layer 156 may be deposited by any suitable deposition process and may have a thickness of from about 0.5 nm to about 5 nm. As known to those skilled in the art, the first capping layer 156 is typically used in back-end-of-line (BEOL) technologies to encapsulate copper (Cu) in the first conductive material 142, reduce electromigration of Cu in the interconnect structure 160, and improve the overall reliability of the semiconductor structure 100.

[0035] Referring to FIG. 1F, the final step in the formation of the first interconnect structures 160 is shown. According to one embodiment, each of the resulting first interconnect structures 160 includes a first barrier liner 120 directly on the barrier layer (110), a (thin) second liner 130 directly on the first liner 120, a first conductive material 142 on the second liner 130 that substantially fills the first interconnect structure 160, and a first capping layer 156 on the top surface of the first conductive material 142. This can prevent the diffusion of cobalt from the first capping layer 156 into the first liner 120. By preventing the diffusion of cobalt atoms from the first capping layer 156, depletion of the first capping layer 156 can be avoided, which can improve electromigration performance. More specifically, the cobalt from the second liner 130 saturates the first liner 120 made of ruthenium, forming a cobalt-implanted ruthenium liner that can stop the driving force for cobalt diffusion from the first capping layer 156 due to the reduced (cobalt) concentration gradient.

[0036] 2A-2F, cross-sectional views of a semiconductor structure 100 are shown during an alternative processing sequence for forming an interconnect structure, according to another embodiment of the present invention. The sequence of processing steps shown in FIGS. 2A-2F illustrates an alternative method of forming a second interconnect structure 260 in the semiconductor structure 100. The second interconnect structure 260 is formed similarly to the first interconnect structure 160 described above with reference to FIGS. 1A-1F. However, in this embodiment, after forming the second barrier liner 130 (FIG. 2B), a third barrier liner 240 is formed directly over the second barrier liner 130, as shown in FIG. 2C.

[0037] As can be seen in FIG. 2C, in this embodiment, the second liner 130 is disposed between the first liner 120 and the third liner 240. According to one embodiment, the third liner 240 is made of substantially the same material as the first liner 120 (i.e., ruthenium) and can be formed using a similar deposition process. The third liner 240 can have a thickness ranging from about 0.5 nm to about 5 nm. As explained above, ruthenium-containing liners are typically used in advanced BEOL manufacturing to enhance copper filling. However, the combination of a ruthenium liner and a cobalt cap used to encapsulate the copper (e.g., the first capping layer 156 of FIG. 1F and the second capping layer 256 of FIG. 2F) leads to a degraded electromigration lifetime.

[0038] Thus, by interposing the second liner 130 between the first liner 120 and the third liner 240, saturation of the first liner 120 and the third liner 240 with cobalt atoms from the second liner 130 occurs, thereby preventing migration of cobalt from a subsequently formed cobalt cap layer (e.g., capping layer 256 in FIG. 2F). Furthermore, in this embodiment, the ruthenium (Ru) / copper (Cu) interface is maintained, enhancing copper fill performance for either copper plating or PVD copper reflow. Specifically, by depositing the third liner 240 on top of the second liner 130, a Ru / Cu interface remains after deposition of the second conductive material 242.

[0039] In some embodiments, after depositing the third liner 240, an etching process can be performed on the semiconductor structure 100 to selectively remove the horizontal portions of the first, second, and third liners 120, 130, and 240 from the dielectric layer 106, as illustrated in FIG. 3C. In other words, the portions of the first, second, and third liners 120, 130, and 240 that are parallel to the dielectric layer 106 are selectively removed by any suitable etching process. For example, an argon (Ar) plasma etch can be performed to remove the horizontal portions of the first, second, and third liners 120, 130, and 240 from the semiconductor structure 100.

[0040] Removal of these portions of the first, second, and third liners 120, 130, and 240 exposes the top (horizontal) surface of the barrier layer 110, as illustrated in FIG. 3C. In other words, after the etching step of FIG. 3C, the first, second, and third liners 120, 130, and 240 remain only on opposing sidewalls of the second interconnect structure 260, as illustrated in FIG. 3F. By performing this etching step (FIG. 3C), the resulting second interconnect structure 260 (FIG. 3F) may exhibit reduced via resistance due to the absence of the first, second, and third liners 120, 130, and 240 on the bottom of the second interconnect structure 260, in addition to reduced cobalt diffusion from the second capping layer 256.

[0041] 2D, the process continues with the deposition of a second conductive material 242, which is similar to the first conductive material 142 of FIG. 1D. The second conductive material 242 may be formed of a similar material and deposited in a manner similar to the first conductive material 142 of FIG. 1D. Note that the deposition of the second conductive material 242 continues with or without the etching step illustrated in FIG. 3C.

[0042] 2E, excess portions of the second conductive material 242 may be removed from the semiconductor structure 100 by any planarization method known in the art, including, for example, CMP. Additionally, during the planarization process, horizontally disposed portions or regions of the barrier layer 110, the first liner 120, the second liner 130, and the third liner 240 parallel to the dielectric layer 106 may also be removed from the semiconductor structure 100.

[0043] The process continues with the formation of a second capping layer 256, shown in Figure 2F. The second capping layer 256 is composed of a similar material and is deposited in a similar manner as the first capping layer 156 (Figure 1F).

[0044] 2F, the final step in the formation of the second interconnect structures 260 is shown. According to one embodiment, each of the resulting second interconnect structures 260 includes a first liner 120 directly on the barrier layer 110, a (thin) second liner 130 interposed between the first liner 120 and the third liner 240, a second conductive material 242 on the third liner 240 that substantially fills the interconnect structure 260, and a second capping layer 256 on the top surface of the second conductive material 242. As explained above, this configuration may prevent the diffusion of cobalt from the second capping layer 256 into the ruthenium-containing liners (i.e., the first liner 120 and the third liner 240). By preventing the diffusion of cobalt from the second capping layer 256, depletion of the second capping layer 256 may be avoided, and electromigration performance may be enhanced. More specifically, cobalt atoms from the second liner 130 saturate the first and third liners 120 , 240 of ruthenium which stops the driving force for cobalt diffusion from the second capping layer 256 .

[0045] Thus, embodiments of the present invention provide copper interconnect structures with enhanced electromigration performance. In one embodiment, improved electromigration performance is achieved by forming a (thin) cobalt liner in direct contact with the ruthenium liner to form a cobalt-injected ruthenium liner resulting from migration of cobalt atoms from the cobalt liner to the ruthenium liner, which in turn can reduce the driving force for cobalt diffusion from the cobalt cap. In another embodiment, a thin cobalt liner is formed within or inserted between the ruthenium liners, which in these embodiments can maintain the Ru / Cu interface and further enhance copper filling. In yet another embodiment, the cobalt / ruthenium liner is removed from the bottom surface of the interconnect structure reducing via resistance in addition to reducing cobalt diffusion from the cobalt cap, thereby further enhancing device performance and reliability.

[0046] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method of forming an interconnect structure, comprising: forming a recess in a dielectric layer; conformally depositing a barrier layer within the recess; forming a cobalt-implanted ruthenium liner over the barrier layer, the cobalt-implanted ruthenium liner comprising: a first liner overlying the barrier layer and comprising ruthenium; a second liner overlying the first liner and including cobalt; a cobalt-implanted ruthenium liner is formed by transfer of cobalt atoms from the second liner to the first liner; depositing a conductive material over the second liner to fill the recess; and forming a capping layer comprising cobalt over an upper surface of the conductive material; The method includes:

2. 1. A method of forming an interconnect structure, comprising: forming a recess in a dielectric layer; conformally depositing a barrier layer within the recess; forming a cobalt-implanted ruthenium liner over the barrier layer, the cobalt-implanted ruthenium liner comprising: a first liner overlying the barrier layer and comprising ruthenium; a second liner overlying the first liner and including cobalt; a cobalt-implanted ruthenium liner is formed by transfer of cobalt atoms from the second liner to the first liner; depositing a conductive material over the cobalt-implanted ruthenium liner to fill the recess; and forming a capping layer comprising cobalt over an upper surface of the conductive material; Including, forming the cobalt-implanted ruthenium liner over the barrier layer; conformally depositing the first liner comprising ruthenium over the barrier layer; conformally depositing the second liner over the first liner, the second liner comprising cobalt; and conformally depositing a third liner over the second liner, the third liner comprising ruthenium; wherein a cobalt-implanted ruthenium liner is formed by transfer of cobalt atoms from the second liner to the first liner and to the third liner.

3. 3. The method of claim 1 or claim 2, wherein the formation of the cobalt-implanted ruthenium liner reduces a concentration gradient between the capping layer and the cobalt-implanted ruthenium liner, thereby preventing diffusion of cobalt atoms from the capping layer.

4. The method of claim 1 or claim 2, wherein the thickness of the second liner is less than the thickness of the first liner.

5. The method of claim 1 or claim 2, wherein the thickness of the second liner is greater than the thickness of the first liner.

6. The method of claim 2 , wherein the thickness of the second liner is less than the thickness of the third liner.

7. The method of claim 1 or claim 2, wherein the conductive material comprises copper.

8. The method of claim 1 or claim 2, wherein the barrier layer comprises tantalum nitride.

9. The method of claim 1 or claim 2, further comprising performing a planarization process to remove excess conductive material from the interconnect structure.

10. 3. The method of claim 2, further comprising selectively removing portions of the first liner, the second liner, and the third liner parallel to the dielectric layer from a bottom region of the interconnect structure, wherein remaining portions of the first liner, the second liner, and the third liner remain on sidewalls of the interconnect structure.

11. 11. The method of claim 10, wherein via resistance is reduced by selectively removing portions of the first liner, the second liner, and the third liner parallel to the dielectric layer from the bottom region of the interconnect structure.

12. an interconnect structure in the dielectric layer, the interconnect structure comprising: a barrier layer located on a bottom surface and sidewalls of the interconnect structure; a first liner directly overlying the barrier layer and comprising ruthenium; a second liner immediately above the first liner, the second liner including cobalt; a conductive material on the second liner that substantially fills the interconnect structure; and a capping layer directly overlying the conductive material and comprising cobalt; wherein migration of cobalt atoms from the second liner to the first liner reduces a concentration gradient between the capping layer and the first liner, thereby preventing diffusion of cobalt atoms from the capping layer.

13. 13. The semiconductor structure of claim 12, further comprising a third liner comprising ruthenium on said second liner, wherein migration of cobalt atoms from said second liner interposed between said first liner and said third liner forms a cobalt-implanted ruthenium liner, said cobalt-implanted ruthenium liner reducing said concentration gradient between said capping layer and said cobalt-implanted ruthenium liner and preventing diffusion of cobalt atoms from said capping layer.

14. 14. The semiconductor structure of claim 13, wherein a portion of the first liner, a portion of the second liner, and a portion of the third liner remain on sidewalls of the interconnect structure, and a bottom of the interconnect structure is covered only by the barrier layer.

15. 15. The semiconductor structure of claim 14, wherein a thickness of the second liner is less than a thickness of the first liner and the third liner.

16. 13. The semiconductor structure of claim 12, wherein the conductive material comprises copper and the barrier layer comprises tantalum nitride.

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