Sensor chip and electronic device

Abstract

Provided are a sensor chip and an electronic device in which characteristics of SPAD pixels having avalanche photodiode elements are improved. This sensor chip is provided with: a pixel array part having a pixel region in which a plurality of pixels are arranged in a matrix shape; avalanche photodiode elements that respectively amplify carriers by high electric-field regions provided to the pixels; an inter-pixel separation part that insulates and separates a pixel from another pixel adjacent thereto in a semiconductor substrate in which the avalanche photodiode elements are formed; wires that are respectively provided to wiring layers stacked with respect to a surface on a side opposite to a light-receiving surface of the semiconductor substrate so as to cover at least the high electric-field regions. The pixel array part has a dummy pixel region located near the outer periphery of the pixel region. A cathode electric potential and an anode electric potential of each of the avalanche photodiode elements arranged in the dummy pixel region is equal to each other, or the cathode electric potential and / or the anode electric potential is floating.

Description

[Technical field]

[0001] The present disclosure relates to a sensor chip and an electronic device, and more particularly to a sensor chip and an electronic device that are capable of improving the characteristics of a SPAD pixel. [Background technology]

[0002] In recent years, distance image sensors that measure distance using the ToF (Time-of-Flight) method have been attracting attention. For example, a pixel array formed by using CMOS (Complementary Metal Oxide Semiconductor) semiconductor integrated circuit technology to arrange multiple SPAD (Single Photon Avalanche Diode) pixels with avalanche photodiode elements in a planar manner can be used for distance image sensors. In a SPAD pixel, avalanche amplification occurs when a single photon enters a PN junction region with a high electric field under the condition that a voltage much larger than the breakdown voltage is applied. By detecting the time when the current flows at that time, the distance can be measured with high accuracy.

[0003] For example, Patent Document 1 describes a sensor chip in which SPAD pixels are arranged in an array in a predetermined pixel region. In the sensor chip of Patent Document 1, a peripheral region is provided outside the image region, and a pad region is provided outside the peripheral region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2018 / 074530 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when SPAD pixels are arranged in an array on a sensor chip, the periodicity of the SPAD pixels tends to be lost in the peripheral region of the pixel area. When the periodicity of the SPAD pixels is lost, the SPAD device characteristics become abnormal, which may cause bias fluctuations or current increases that affect the characteristics of the entire sensor chip.

[0006] The present disclosure has been made in consideration of such problems, and provides a sensor chip and electronic device with improved characteristics of a SPAD pixel having an avalanche photodiode element. [Means for solving the problem]

[0007] In order to solve the above problems, a sensor chip according to one aspect of the present disclosure includes a pixel array section having a pixel region in which a plurality of pixels are arranged in a matrix, an avalanche photodiode element that amplifies carriers by a high electric field region provided for each pixel, an inter-pixel isolation section that insulates and isolates adjacent pixels on a semiconductor substrate in which the avalanche photodiode element is formed, and wiring provided in a wiring layer that is stacked on a surface opposite to the light-receiving surface of the semiconductor substrate so as to cover at least the high electric field region, wherein the pixel array section has a dummy pixel region located in the vicinity of the periphery of the pixel region, and the cathode potential and anode potential of the avalanche photodiode element arranged in the dummy pixel region are the same potential, or at least one of the cathode potential and the anode potential is floating.

[0008] Furthermore, an electronic device according to another aspect of the present disclosure includes a pixel array section having a pixel region in which a plurality of pixels are arranged in a matrix, an avalanche photodiode element that amplifies carriers by a high electric field region provided for each pixel, an inter-pixel isolation section that insulates and isolates adjacent pixels on a semiconductor substrate in which the avalanche photodiode element is formed, and wiring provided in a wiring layer that is stacked on a surface opposite to the light-receiving surface of the semiconductor substrate so as to cover at least the high electric field region, wherein the pixel array section has a dummy pixel region located near the periphery of the pixel region, and includes a sensor chip in which the cathode potential and anode potential of the avalanche photodiode element arranged in the dummy pixel region are the same potential, or at least one of the cathode potential and anode potential is floating. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram showing a configuration of a SPAD pixel formation surface of a sensor chip according to a first embodiment of the present disclosure. [Diagram 2] 1 is a block diagram showing a configuration example of a sensor chip according to a first embodiment of the present disclosure. [Diagram 3] 1 is a cross-sectional view showing a configuration example of a SPAD pixel of a sensor chip according to a first embodiment of the present disclosure. [Figure 4] 1 is a cross-sectional view showing a configuration example of a SPAD pixel of a sensor chip according to a first embodiment of the present disclosure. [Diagram 5] 11 is a cross-sectional view showing a configuration example of a SPAD pixel of a sensor chip according to a second embodiment of the present disclosure. FIG. [Figure 6] FIG. 11 is a circuit diagram showing a configuration example of a sensor chip according to a third embodiment of the present disclosure. [Figure 7] 11 is a cross-sectional view showing a configuration example of a SPAD pixel of a sensor chip according to a third embodiment of the present disclosure. FIG. [Figure 8] FIG. 13 is a block diagram showing a configuration example of a sensor chip according to a fourth embodiment of the present disclosure. [Figure 9] FIG. 13 is a circuit diagram showing a configuration example of a sensor chip according to a fifth embodiment of the present disclosure. [Figure 10] FIG. 13 is a cross-sectional view showing a configuration example of a SPAD pixel of a sensor chip according to a fifth embodiment of the present disclosure. [Figure 11] FIG. 13 is a circuit diagram showing a configuration example of a sensor chip according to a sixth embodiment of the present disclosure. [Figure 12] FIG. 13 is a cross-sectional view showing a configuration example of a SPAD pixel of a sensor chip according to a sixth embodiment of the present disclosure. [Figure 13] 1 is a block diagram showing an example of the configuration of a range image sensor, which is an electronic device that uses a sensor chip according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present disclosure will be described below through embodiments, but the following embodiments do not limit the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In addition, the drawings are schematic diagrams of the invention according to the claims, and the dimensions of the width, thickness, etc. of each part are different from the actual dimensions, and the ratios between these dimensions are also different from the actual dimensions. Hereinafter, each aspect of each embodiment of the present disclosure will be described with reference to the drawings.

[0011] 1. First embodiment The sensor chip according to the first embodiment will be described with reference to FIGS. 1 to 4. FIG.

[0012] <Example of sensor chip configuration> Fig. 1 is a schematic diagram showing the configuration of a SPAD pixel formation surface of a sensor chip 10. Fig. 2(A) is a block diagram showing one configuration example of a sensor chip 10 to which the present technology is applied. Fig. 2(B) and Fig. 2(C) are circuit diagrams showing the configurations of SPAD pixels 21 and 22 provided in the sensor chip 10, respectively.

[0013] As shown in FIG. 1, the pixel array section 11 has a pixel region A1, a peripheral region A2 provided outside the pixel region A1, and a pad region A3 formed outside the peripheral region A2. The pixel region A1 is a light receiving surface that receives light collected by an optical system (not shown). In the pixel region A1, a plurality of SPAD pixels 21 and 22 are arranged in a matrix.

[0014] The pad region A3 is provided with a plurality of wiring electrode pads (hereinafter referred to as electrode pads) 23. The electrode pads 23 are used, for example, to connect the sensor chip 10 to an external device (not shown). The peripheral area A2 is an area between the pixel area A1 and the pad area A3. The peripheral area A2 is composed of, for example, an n-type semiconductor area and a p-type semiconductor area, and the p-type semiconductor area is connected to the ground (GND).

[0015] As shown in FIG. 2A, the sensor chip 10 includes a pixel array section 11 and a bias voltage application section 12. The pixel array section 11 and the bias voltage application section 12 include a pixel array section 11 and a bias voltage application section 12. The bias voltage application section 12 applies a bias voltage to each of the multiple SPAD pixels 21 arranged in the pixel array section 11 .

[0016] The pixel region A1 of the pixel array section 11 has a reference pixel region RA located in the center of the pixel region A1, and a dummy pixel region DA located near the outer periphery of the pixel region A1 and surrounding the reference pixel region RA.

[0017] The SPAD pixels 21 are pixels arranged in a reference pixel area RA. The SPAD pixels 21 are valid SPAD pixels (hereinafter referred to as reference pixels) that output a light receiving signal (APD OUT) in which a pulse waveform is generated starting from the arrival time of one photon. Note that, although FIG. 2A shows 24 SPAD pixels 21 arranged in a 6×8 matrix, this arrangement is merely an example and is not limiting.

[0018] On the other hand, the SPAD pixels 22 are pixels arranged in the dummy pixel area DA. The dummy pixel area DA is located near the outer periphery of the pixel array section 11, and is an area where the process of forming the SPAD pixels 22 is likely to be unstable. The SPAD pixels 22 formed in the dummy pixel area DA are likely to lose their shape and lose their periodicity of arrangement. For this reason, the SPAD pixels 22 do not function as general SPAD pixels, that is, they are invalid SPAD pixels (hereinafter referred to as dummy pixels) that do not output the above-mentioned light receiving signal (APD OUT). Note that, although FIG. 2A shows a state in which 60 SPAD pixels 22 are arranged in the dummy pixel area DA, this arrangement is an example and is not limited thereto. In the actual sensor chip 10, the SPAD pixels 22 arranged in the dummy pixel area DA are arranged so that they are sufficiently fewer than the SPAD pixels 21 arranged in the reference pixel area RA.

[0019] The deformation of the shape of the SPAD pixels 22 and the deformation of the periodicity of the arrangement are caused by the peripheral region A2 and the pad region A3 being arranged around the pixel region A1 where the SPAD pixels 21 and 22 are arranged in a matrix. When forming the SPAD pixels 21 and 22, a resist having an opening is formed in the pixel region A1 in order to inject impurity ions into the SPAD pixel formation region. The resist formed in the peripheral region A2 and the pad region A3 has a larger amount of resist than the resist formed in the pixel region A1 because no openings corresponding to the formation positions of the SPAD pixels 21 and 22 are provided. Therefore, the resist formed in the peripheral region A2 and the pad region A3 is likely to be deformed by its own weight. The deformation of the resist that serves as a mask during the implantation of impurity ions makes it easy for process failures to occur. That is, process failures are likely to occur in the openings formed inside the peripheral region A2 and the pad region A3 (near the outer periphery of the pixel region A1). Therefore, the SPAD pixels 22 formed in the dummy pixel region DA are likely to be deformed and the periodicity of the arrangement is likely to be deformed.

[0020] Therefore, the sensor chip 10 that uses only the outputs of the SPAD pixels 21 formed in the central region of the pixel region A1 and uses the SPAD pixels 22 formed in the peripheral region of the pixel region A1 as dummy pixels can obtain good characteristics. The SPAD pixel 21, which is a reference pixel, and the SPAD pixel 22, which is a dummy pixel, will be described in detail below.

[0021] (Reference pixel circuit configuration) As shown in FIG. 2B, the SPAD pixel 21, which is a reference pixel, includes a SPAD element 31, a p-type metal-oxide-semiconductor field-effect transistor (MOSFET) 32, and an inverter 33.

[0022] The SPAD element 31 has an anode connected to the bias voltage application unit 12 and a cathode connected to a source terminal of a quenching resistor 32 described later. A bias voltage VB is applied to the anode of the SPAD element 31 from the bias voltage application unit 12. The SPAD element 31 is an avalanche photodiode element that forms an avalanche multiplication region by applying a large negative voltage to the cathode and can avalanche multiply electrons generated by the incidence of one photon.

[0023] The quenching resistor 32 is connected in series with the SPAD element 31, with its source terminal connected to the cathode of the SPAD element 31 and its drain terminal connected to a power supply (not shown). The quenching resistor 32 can be composed of a transistor or resistor, and for example, a p-type MOSFET can be used. An excitation voltage VE is applied to the drain terminal of the quenching resistor 32 from a power supply. When the voltage due to the electrons avalanche multiplied by the SPAD element 31 reaches a negative voltage VBD, the quenching resistor 32 performs quenching to return the voltage to the initial voltage. When the cathode voltage of the SPAD element 31 reaches the negative voltage VBD, the quenching resistor 32 performs quenching by emitting the electrons multiplied by the SPAD element 31.

[0024] The inverter 33 has an input terminal connected to the cathode of the SPAD element 31 and the source terminal of the quenching resistor 32, and an output terminal connected to a downstream arithmetic processing unit (not shown). The inverter 33 is, for example, a CMOS inverter. The inverter 33 outputs a light receiving signal based on the electrons multiplied by the SPAD element 31. More specifically, the inverter 33 shapes a voltage generated by the electrons multiplied by the SPAD element 31. The inverter 33 then outputs to the arithmetic processing unit a light receiving signal (APD OUT) that generates a pulse waveform, for example, as shown in FIG. 2B, with the arrival time of one photon as the starting point.

[0025] (Circuit configuration of dummy pixels) 2C, the SPAD pixel 22, which is a dummy pixel, includes a SPAD element 31, a p-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 32, and an inverter 33, similar to the SPAD pixel 21. The SPAD pixel 22 differs from the SPAD pixel 21 in that the wiring is different.

[0026] The anode of the SPAD element 31 is connected to the bias voltage application unit 12. On the other hand, the cathode of the SPAD element 31 is not connected to the source terminal of the quenching resistor 32 and is in a floating state. That is, the cathode potential of the SPAD element 31 of the SPAD pixel 22 formed in the dummy pixel area DA located in the vicinity of the outer periphery of the pixel area A1 is floating. Therefore, no large negative voltage is applied to the cathode of the SPAD element 31, and the SPAD element 31 is in a substantially non-functional state.

[0027] Specifically, it is possible to prevent bias fluctuations and current increases that would otherwise occur if breakdown continues to occur in the SPAD element 31 of the SPAD pixel 22 and affect the sensor chip 10 and an external device connected to the sensor chip 10. In the sensor chip 10, it is possible to suppress an increase in power consumption of the sensor chip 10 caused by a large current flowing in the SPAD element 31 of the SPAD pixel 22. In addition, in the sensor chip 10, it is possible to suppress a drop in the anode potential of the SPAD pixel 21 caused by a large current flowing in the SPAD element 31, thereby suppressing a decrease in sensing accuracy.

[0028] The quenching resistor 32 has a source terminal that is not connected to the cathode of the SPAD element 31 and is in a floating state. Therefore, the quenching resistor 32 is configured not to perform quenching. The input terminal of the inverter 33 is in a floating state without being connected to the cathode of the SPAD element 31 or the source terminal of the quenching resistor 32. For this reason, the inverter 33 is configured not to output a light reception signal (APD OUT).

[0029] In the sensor chip 10, as shown in an example in FIG. 2(A), the anodes of the SPAD pixels 21 and the anodes of the SPAD pixels 22 arranged in the row direction among the SPAD pixels 21 and 22 arranged in a matrix are each connected by a common wiring.

[0030] From the sensor chip 10 configured in this manner, a light reception signal is output for each SPAD pixel 21 and supplied to a downstream arithmetic processing unit. For example, the arithmetic processing unit performs arithmetic processing to calculate a distance for each light reception signal from the SPAD pixel 21 based on the timing of generation of a pulse indicating the arrival time of one photon, and calculates the distance to the subject for each SPAD pixel 21. Then, based on the calculated distances, a distance image is generated in which the distances to the subject detected by the multiple SPAD pixels 21 are arranged in a plane. At this time, since no light reception signal is output from the SPAD pixel 22, the SPAD pixel 22 does not contribute to the generation of the above-mentioned distance image.

[0031] (Reference pixel structure) 2B and 3, a configuration example of a SPAD pixel 21 that is a reference pixel formed on the sensor chip 10 will be described. FIG. 3 is a cross-sectional view showing a configuration example of a SPAD pixel 21.

[0032] As shown in FIG. 3, the reference pixel area RA of the sensor chip 10 has a layered structure in which a sensor substrate 41, a sensor side wiring layer 42, and a logic side wiring layer 43 are stacked, and a logic circuit substrate (not shown) is stacked on the logic side wiring layer 43. 2A, a bias voltage application unit 12, a quenching resistor 32, an inverter 33, and the like are formed on the logic circuit board. The sensor board 41 and the logic circuit board are electrically connected by a sensor-side wiring layer 42 and a logic-side wiring layer 43, which are wiring layers. For example, the sensor chip 10 can be manufactured by a manufacturing method in which the sensor-side wiring layer 42 is provided opposite the sensor board 41, the logic-side wiring layer 43 is provided opposite the logic circuit board, and then the sensor-side wiring layer 42 and the logic-side wiring layer 43 are bonded at their bonding surfaces (surfaces indicated by dashed lines in FIG. 3).

[0033] The sensor substrate 41 is, for example, a semiconductor substrate obtained by thinly slicing single crystal silicon. The concentration of p-type or n-type impurities in the sensor substrate 41 is controlled, and a SPAD element 31 is formed for each SPAD pixel 21. The surface of the sensor substrate 41 facing downward in Fig. 3 is a light receiving surface that receives light, and a sensor side wiring layer 42 is laminated on the surface opposite to the light receiving surface (the surface facing upward in Fig. 2).

[0034] The sensor side wiring layer 42 and the logic side wiring layer 43 are provided with wiring for supplying voltage to be applied from the bias voltage application unit 12 to the SPAD element 31, and wiring for extracting electrons generated in the SPAD element 31 from the sensor substrate 41.

[0035] The SPAD element 31 is composed of an N-well 51, a P-type diffusion layer 52, an N-type diffusion layer 53, a hole accumulation layer 54, a pinning layer 55, and a high-concentration P-type diffusion layer 56, which are formed on the sensor substrate 41. In the SPAD element 31, an avalanche multiplication region 57 is formed by a depletion layer formed in a region where the P-type diffusion layer 52 and the N-type diffusion layer 53 are connected.

[0036] The N well 51 is formed by controlling the impurity concentration of the sensor substrate 41 to be of n type, and forms an electric field that transfers electrons generated by photoelectric conversion in the SPAD element 31 to the avalanche multiplication region 57. Note that instead of the N well 51, a P well may be formed by controlling the impurity concentration of the sensor substrate 41 to be of p type.

[0037] The P-type diffusion layer 52 is a dense P-type diffusion layer (P+) formed near the surface of the sensor substrate 41 on the back side (lower side in Figure 3) of the N-type diffusion layer 53, and is formed over almost the entire surface of the SPAD element 31.

[0038] The N-type diffusion layer 53 is a dense N-type diffusion layer (N+) formed near the surface of the sensor substrate 41 on the surface side (upper side in FIG. 3) of the P-type diffusion layer 52, and is formed so as to cover almost the entire surface of the SPAD element 31. In addition, the N-type diffusion layer 53 has a convex shape such that a part of it is formed up to the surface of the sensor substrate 41 in order to connect to a contact electrode 71 for supplying a negative voltage for forming an avalanche multiplication region 57.

[0039] The hole accumulation layer 54 is a P-type diffusion layer (P) formed so as to surround the side and bottom surfaces of the N well 51, and accumulates holes. The hole accumulation layer 54 is also electrically connected to the anode of the SPAD element 31, allowing bias adjustment. This strengthens the hole concentration of the hole accumulation layer 54 and strengthens the pinning including the pinning layer 55, thereby making it possible to suppress, for example, the generation of dark current.

[0040] The pinning layer 55 is a dense P-type diffusion layer (P+) formed on the surface (the back surface of the sensor substrate 41 or the side surface in contact with the insulating film 62) outside the hole accumulation layer 54, and similar to the hole accumulation layer 54, for example, suppresses the generation of dark current.

[0041] The high-concentration P-type diffusion layer 56 is a high-concentration P-type diffusion layer (P++) formed in the vicinity of the surface of the sensor substrate 41 so as to surround the outer periphery of the N-well 51, and is used for connection to a contact electrode 72 for electrically connecting the hole accumulation layer 54 to the anode of the SPAD element 31.

[0042] The avalanche multiplication region 57 is a high electric field region formed at the boundary between the P-type diffusion layer 52 and the N-type diffusion layer 53 by a large negative voltage applied to the N-type diffusion layer 53, and multiplies electrons (e-) generated by one photon incident on the SPAD element 31.

[0043] The sensor chip 10 is provided with an inter-pixel isolation portion 63 formed between adjacent SPAD elements 31. The inter-pixel isolation portion 63 has a double structure formed of a metal film 61 and an insulating film 62. The inter-pixel isolation portion 63 is formed, for example, so as to penetrate from the rear surface to the front surface of the sensor substrate 41. The SPAD element 31 is electrically and optically isolated from the adjacent SPAD element 31 by the inter-pixel isolation portion 63.

[0044] The metal film 61 is a film made of a metal (such as tungsten) that reflects light. The insulating film 62 is a film having insulating properties, such as SiO2. The inter-pixel isolation portion 63 is formed, for example, by embedding the metal film 61 in the sensor substrate 41 so that the surface of the metal film 61 is covered with an insulating film 62 .

[0045] On the sensor side wiring layer 42, contact electrodes 71 to 73, metal wires 74 to 76, contact electrodes 77 to 79, and metal pads 80 to 82 are formed.

[0046] The contact electrode 71 connects the N-type diffusion layer 53 and a metal wiring 74. The contact electrode 72 connects the high-concentration P-type diffusion layer 56 and a metal wiring 75. The contact electrode 73 connects the metal film 61 and a metal wiring .

[0047] 3, the metal wiring 74 is formed wider than the avalanche multiplication region 57 so as to cover at least the avalanche multiplication region 57. The metal wiring 74 reflects light transmitted through the SPAD element 31 back to the SPAD element 31, as indicated by the hollow arrow in FIG.

[0048] 3, the metal wiring 75 is formed so as to surround the outer periphery of the metal wiring 74 and overlap with the high-concentration P-type diffusion layer 56. The metal wiring 76 is formed so as to connect to the metal film 61 at the four corners of the SPAD pixel 21, for example.

[0049] The contact electrode 77 connects the metal wiring 74 and the metal pad 80. The contact electrode 78 connects the metal wiring 75 and the metal pad 81. The contact electrode 79 connects the metal wiring 76 and the metal pad 82.

[0050] The metal pads 80 to 82 are used for electrically and mechanically joining to the metal pads 101 to 103 formed on the logic-side wiring layer 43 by the metal (Cu) forming each of them.

[0051] On the logic-side wiring layer 43, electrode pads 91 to 93, an insulating layer 94, contact electrodes 95 to 100, and metal pads 101 to 103 are formed.

[0052] The electrode pads 91 to 93 are each connected to a logic circuit board (not shown), and the insulating layer 94 insulates the electrode pads 91 to 93 from each other.

[0053] Contact electrodes 95 and 96 connect the electrode pad 91 to the metal pad 101 , contact electrodes 97 and 98 connect the electrode pad 92 to the metal pad 102 , and contact electrodes 99 and 100 connect the electrode pad 93 to the metal pad 103 .

[0054] Metal pad 101 is bonded to metal pad 80 , metal pad 102 is bonded to metal pad 81 , and metal pad 103 is bonded to metal pad 82 .

[0055] With such a wiring structure, for example, the electrode pad 91 is connected to the N-type diffusion layer 53 via the contact electrodes 95 and 96, the metal pad 101, the metal pad 80, the contact electrode 77, the metal wiring 74, and the contact electrode 71. Therefore, in the SPAD pixel 21, a large negative voltage applied to the N-type diffusion layer 53 can be supplied from the logic circuit board to the electrode pad 91.

[0056] Furthermore, the electrode pad 92 is connected to the high-concentration P-type diffusion layer 56 via the contact electrodes 97 and 98, the metal pad 102, the metal pad 81, the contact electrode 78, the metal wiring 75, and the contact electrode 72. Therefore, in the SPAD pixel 21, the anode of the SPAD element 31 electrically connected to the hole accumulation layer 54 is connected to the electrode pad 92, making it possible to adjust the bias for the hole accumulation layer 54 via the electrode pad 92.

[0057] Furthermore, the electrode pad 93 is connected to the metal film 61 via the contact electrodes 99 and 100, the metal pad 103, the metal pad 82, the contact electrode 79, the metal wiring 76, and the contact electrode 73. Therefore, in the SPAD pixel 21, a bias voltage supplied to the electrode pad 93 from the logic circuit board can be applied to the metal film 61.

[0058] As described above, in the SPAD pixel 21, the metal wiring 74 is formed wider than the avalanche multiplication region 57 so as to cover at least the avalanche multiplication region 57, and the metal film 61 is formed so as to penetrate the sensor substrate 41. That is, the SPAD pixel 21 is formed to have a reflective structure in which the metal wiring 74 and the metal film 61 surround all the SPAD element 31 except for the light incident surface. This makes it possible for the SPAD pixel 21 to prevent the occurrence of optical crosstalk by the effect of reflecting light by the metal wiring 74 and the metal film 61, and to improve the sensitivity of the SPAD element 31.

[0059] Moreover, the SPAD pixel 21 can adjust the bias voltage by surrounding the side and bottom surfaces of the N well 51 with a hole accumulation layer 54 and electrically connecting the hole accumulation layer 54 to the anode of the SPAD element 31. Furthermore, the SPAD pixel 21 can form an electric field that assists carriers to the avalanche multiplication region 57 by applying a bias voltage to the metal film 61 of the inter-pixel separator 63.

[0060] (Dummy pixel configuration) 2C and 4, a configuration example of the SPAD pixel 22, which is a dummy pixel formed on the sensor chip 10, will be described. FIG. 4 is a cross-sectional view showing a configuration example of the SPAD pixel 22.

[0061] As shown in FIG. 4, the dummy pixel area DA of the sensor chip 10 has a laminated structure in which a sensor substrate 41, a sensor side wiring layer 42, and a logic side wiring layer 43 are laminated, similarly to the reference pixel area RA.

[0062] Like the SPAD pixel 21 , the SPAD pixel 22 includes a SPAD element 31 , a quenching resistor 32 , and an inverter 33 . In addition, on the sensor-side wiring layer 42, contact electrodes 72 and 73, metal wires 74 to 76, contact electrodes 77 to 79, and metal pads 80 to 82 are formed. Furthermore, on the logic-side wiring layer 43, electrode pads 91 to 93, an insulating layer 94, contact electrodes 95 to 100, and metal pads 101 to 103 are formed.

[0063] As shown in FIG. 2C, the SPAD pixel 22 differs from the SPAD pixel 21 in that the cathode of the SPAD element 31 is not connected to the source terminal of the quenching resistor 32 and is in a floating state. 4, the SPAD pixel 22 differs from the SPAD pixel 21 in that the contact electrode 71 is not provided and the SPAD element 31 is not electrically connected to the metal wiring 74 in order to make the cathode potential of the SPAD element 31 floating. Other configurations are the same as those of the SPAD pixel 21.

[0064] In recent years, avalanche photodiodes, or SPAD elements, have come to be used as image sensors, and are required to have better characteristics than ever before. Avalanche photodiodes are larger in size than general photodiodes. For this reason, when forming the avalanche photodiodes of the SPAD pixels, the shape of the mask formed using the resist is easily distorted due to the large amount of resist used. For this reason, by using the configuration of the sensor chip disclosed herein, the effect of improving the characteristics of the sensor chip 10 is further enhanced by making the SPAD pixels formed on the outer periphery of the pixel array section, where formation abnormalities are likely to occur, invalid pixels.

[0065] <Advantages of the First Embodiment> The sensor chip 10 according to the first embodiment configured as above provides the following advantages. (1) In the sensor chip 10, the SPAD pixels 22, which are prone to deformation or loss of periodicity in their arrangement, are prevented from outputting light reception signals (APD OUT). As a result, the sensor chip 10 is able to output only light reception signals from the highly stable SPAD pixels 21. This makes it possible to calculate the distance to the subject based only on the light reception signals from the highly stable SPAD pixels 21, and generate a highly accurate distance image. (2) In the sensor chip 10, it is possible to suppress the generation of a large current in the SPAD pixels 22. This makes it possible to suppress an increase in the power consumption of the entire sensor chip 10 due to a large current flowing in the SPAD pixels 22.

[0066] (3) In the sensor chip 10, it is possible to suppress the generation of a large current in the SPAD pixel 22. This makes it possible to suppress a drop in the anode potential of the SPAD pixel 21 due to the generation of a large current in the SPAD pixel 22, thereby suppressing a decrease in the sensing accuracy of the SPAD pixel 21. (4) In the sensor chip 10, it is possible to suppress the generation of a large current in the SPAD pixels 22. This suppresses the generation of crosstalk between the SPAD pixels 21 in the reference pixel area RA, which is caused by the large current in the SPAD pixels 22, and improves the sensitivity of the SPAD elements 31 in the SPAD pixels 21.

[0067] 2. Second embodiment The sensor chip according to the second embodiment will be described using Fig. 5 while referring to Fig. 2 to Fig. 4. The sensor chip 10A according to the second embodiment differs from the sensor chip 10 according to the first embodiment in that it has a SPAD pixel 22A as a dummy pixel instead of the SPAD pixel 22. Other parts of the SPAD pixel 22B are formed in the same manner as the SPAD pixel 22 of the sensor chip 10 of the first embodiment.

[0068] (Circuit configuration of dummy pixels) The following describes the differences between the SPAD pixel 22B and the SPAD pixel 21. The anode of the SPAD element 31 of the SPAD pixel 22, which is a dummy pixel, is not connected to the bias voltage application unit 12 and is in a floating state. The cathode of the SPAD element 31 is not connected to the source terminal of the quenching resistor 32 and is in a floating state. That is, the cathode potential and the anode potential of the SPAD element 31 of the SPAD pixel 22B formed in the dummy pixel area DA located in the vicinity of the outer periphery of the pixel area A1 are floating. Therefore, no large negative voltage is applied to the cathode of the SPAD element 31, and the SPAD element 31 is in a substantially non-functional state.

[0069] (Dummy pixel configuration) An example of the configuration of the SPAD pixel 22A, which is a dummy pixel of the sensor chip 10A, will be described with reference to Fig. 5. Fig. 4 is a cross-sectional view showing an example of the configuration of the SPAD pixel 22A.

[0070] Like the SPAD pixels 21 and 22, the SPAD pixel 22A includes a SPAD element 31, a quenching resistor 32, and an inverter 33. In addition, on the sensor-side wiring layer 42, a contact electrode 73, metal wires 74 to 76, contact electrodes 77 to 79, and metal pads 80 to 82 are formed. The configuration of the logic-side wiring layer 43 is similar to that of the SPAD pixel 22 .

[0071] 5, in the SPAD pixel 22A, in order to float the cathode potential of the SPAD element 31, a contact electrode that electrically connects the SPAD element 31 to the metal wiring 74 is not provided. In addition, in the SPAD pixel 22A, in order to float the anode potential of the SPAD element 31, a contact electrode that electrically connects the SPAD element 31 to the metal wiring 75 is not provided.

[0072] <Effects of the second embodiment> The sensor chip 10A according to the second embodiment configured as above provides the same advantages as those (1) to (4) in the first embodiment.

[0073] (Modification) In order to use the SPAD pixels formed in the dummy pixel area DA as dummy pixels, at least one of the cathode potential and the anode potential of the sensor chip may be floating. In the first and second embodiments, a sensor chip 10 in which the cathode potential of the SPAD pixels 22 formed in the dummy pixel area DA is floating, and a sensor chip 10A in which the cathode potential and anode potential are floating were described, respectively, but this configuration is not limited to this. That is, the SPAD pixel of the sensor chip may be configured so that the cathode potential of the SPAD element 31 is floating. In this case, the SPAD pixel has the contact electrode 71 shown in the SPAD pixel 21 in FIG. 2, but does not have the contact electrode 72.

[0074] 3. Third embodiment The sensor chip according to the third embodiment will be described with reference to Fig. 2 to Fig. 4 and Fig. 6 and Fig. 7. The sensor chip 10B according to the third embodiment differs from the sensor chip 10 according to the first embodiment in that it has a SPAD pixel 22B as a dummy pixel instead of the SPAD pixel 22. In addition, the SPAD pixel 21, which is a reference pixel, is formed in the same manner as the SPAD pixel 21 of the sensor chip 10 of the first embodiment.

[0075] (Circuit configuration of dummy pixels) The following describes the differences between the SPAD pixel 22B and the SPAD pixel 21. 6, the anode of the SPAD element 31 of the dummy SPAD pixel 22B is connected to the bias voltage application unit 12, but the cathode of the SPAD element 31 is not connected to the source terminal of the quenching resistor 32. In addition, the cathode and anode of the SPAD element 31 are short-circuited. That is, the cathode potential and the anode potential of the SPAD element 31 formed in the dummy pixel area DA located near the outer periphery of the pixel area A1 are set to the same potential. Therefore, no large negative voltage is applied to the cathode of the SPAD element 31, and the SPAD element 31 is substantially in a non-functional state. Other parts of the SPAD pixel 22B are formed in the same manner as the SPAD pixel 22 of the sensor chip 10 of the first embodiment.

[0076] (Dummy pixel configuration) An example of the configuration of the SPAD pixel 22B, which is a dummy pixel of the sensor chip 10B, will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view showing an example of the configuration of the SPAD pixel 22B.

[0077] Like the SPAD pixels 21 and 22, the SPAD pixel 22B includes a SPAD element 31, a quenching resistor 32, and an inverter 33. In addition, on the sensor side wiring layer 42, contact electrodes 71 to 73, metal wires 74B and 76, contact electrodes 78 and 79, and metal pads 80 to 82 are formed. The configuration of the logic-side wiring layer 43 is similar to that of the SPAD pixel 22 .

[0078] 7, in the SPAD pixel 22B, in order to make the cathode potential and the anode potential of the SPAD element 31 the same potential, the contact electrodes 71 and 72 are connected to one metal wiring 74B. This shorts the cathode and the anode of the SPAD element 31. Furthermore, in the SPAD pixel 22B, a contact electrode that connects the metal wiring 74B and the metal pad 80 is not provided, and the SPAD element 31 is not electrically connected to the quenching resistor 32 and the inverter 33.

[0079] <Effects of the third embodiment> The sensor chip 10B according to the second embodiment configured as above provides the same advantages as those (1) to (4) of the first embodiment.

[0080] 4. Fourth embodiment The sensor chip according to the fourth embodiment will be described with reference to FIGS. 2 to 4 and with reference to FIGS. 8(A) to 8(C). The sensor chip 10C according to the fourth embodiment differs from the sensor chip 10 according to the first embodiment in that it has a SPAD pixel 21C as a reference pixel instead of the SPAD pixel 21, and has a SPAD pixel 22C as a dummy pixel instead of the SPAD pixel 22.

[0081] (Circuit configuration of dummy pixels) The following describes the differences between the SPAD pixel 21C and the SPAD pixel 22C and the SPAD pixel 21 and the SPAD pixel 22. The configurations of the SPAD pixel 21C and the SPAD pixel 22C are the same as those of the SPAD pixel 21 and the SPAD pixel 22B. In addition, as shown in Fig. 8B, the wiring of the SPAD element 31, the quenching resistor 32, and the inverter 33 in the SPAD pixel 22C is also the same as that in the SPAD pixel 22B.

[0082] 8A, the anodes of the multiple SPAD pixels 21C arranged in a matrix are connected to a common wiring, and the anodes of the multiple SPAD pixels 22C are connected to a common wiring. That is, the sensor chip 10C differs from the sensor chip 10 of the first embodiment in that the anodes of the multiple SPAD pixels 21C and the anodes of the multiple SPAD pixels 22C are separated.

[0083] <Effects of the Fourth Embodiment> The sensor chip 10C according to the fourth embodiment configured as above has the following advantages in addition to the advantages (1) to (4) of the first embodiment. (5) In the sensor chip 10C, the anode of the SPAD pixel 21C is separated from the anode of the SPAD pixel 22C. Therefore, even if a large current flows through the SPAD pixel 22C in the dummy pixel area DA, the large current does not affect the SPAD pixel 22C in the reference pixel area. This prevents a drop in the anode potential of the SPAD pixel 21C and prevents a decrease in the sensing accuracy of the sensor chip 10C.

[0084] 5. Fifth embodiment The sensor chip according to the fifth embodiment will be described with reference to Fig. 2 to Fig. 4 and Fig. 9 and Fig. 10. The sensor chip 10D according to the fifth embodiment differs from the sensor chip 10 according to the first embodiment in that it has, as a dummy pixel, a SPAD pixel 22D in which the anode and cathode of the SPAD element 31 are shorted in the logic-side wiring layer 43. In addition, the SPAD pixel 21, which is a reference pixel, is formed in the same manner as the SPAD pixel 21 of the sensor chip 10 of the first embodiment.

[0085] (Circuit configuration of dummy pixels) The following describes the differences between the SPAD pixel 22D and the SPAD pixel 21. As shown in Fig. 9, the anode of the SPAD element 31 of the SPAD pixel 22D, which is a dummy pixel, is connected to the bias voltage application unit 12. The cathode of the SPAD element 31 is connected to the source terminal of the quenching resistor 32, but is not connected to the inverter 33. The cathode and anode of the SPAD element 31 are short-circuited in the logic-side wiring layer 43. That is, the cathode potential and the anode potential of the SPAD element 31 formed in the dummy pixel area DA located in the vicinity of the outer periphery of the pixel area A1 in the pixel area A1 are set to the same potential. Therefore, no large negative voltage is applied to the cathode of the SPAD element 31, and the SPAD element 31 is substantially in a non-functioning state.

[0086] (Dummy pixel configuration) An example of the configuration of a SPAD pixel 22D, which is a dummy pixel of the sensor chip 10D, will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view showing an example of the configuration of the SPAD pixel 22D.

[0087] Like the SPAD pixels 21 and 22, the SPAD pixel 22D includes a SPAD element 31, a quenching resistor 32, and an inverter 33. The configuration of the sensor side wiring layer 42 is similar to that of the SPAD pixel 22 of the first embodiment. On the logic-side wiring layer 43, electrode pads 91D and 93, an insulating layer 94, contact electrodes 95-100, and metal pads 101-103 are formed.

[0088] 10, in the SPAD pixel 22D, in order to make the cathode potential and the anode potential of the SPAD element 31 the same potential, the contact electrodes 95 to 98 are connected to one electrode pad 91D. As a result, the cathode and anode of the SPAD element 31 are short-circuited in the logic-side wiring layer 43. Also, in the SPAD pixel 22D, the SPAD element 31 and the quenching resistor 32 are not electrically connected to the inverter 33 in the logic-side wiring layer 43.

[0089] <Effects of the Fifth Embodiment> The sensor chip 10D according to the fifth embodiment configured as above provides the same advantages as those (1) to (4) of the first embodiment.

[0090] 6. Sixth embodiment The sensor chip according to the sixth embodiment will be described with reference to Fig. 2 to Fig. 4 and with reference to Fig. 11 and Fig. 12. The sensor chip 10E according to the sixth embodiment differs from the sensor chip 10 according to the first embodiment in that it has a SPAD pixel 22E as a dummy pixel instead of the SPAD pixel 22. In addition, the SPAD pixel 21, which is a reference pixel, is formed in the same manner as the SPAD pixel 21 of the sensor chip 10 according to the first embodiment.

[0091] (Circuit configuration of dummy pixels) The following describes the differences between the SPAD pixel 22E and the SPAD pixel 21. As shown in FIG. 11, a SPAD pixel 22E, which is a dummy pixel, includes a SPAD element 31, but differs from the SPAD pixel 21 in that it does not include a quenching resistor 32 and an inverter 33. In addition, on the sensor side wiring layer 42, contact electrodes 71 to 73, metal wires 74B and 76, contact electrodes 78 and 79, and metal pads 80 to 82 are formed. The configuration of the logic-side wiring layer 43 is similar to that of the SPAD pixel 22 .

[0092] The anode of the SPAD element 31 is connected to the bias voltage application unit 12, and the cathode is connected to the anode without being connected to the source terminal of the quenching resistor 32. That is, the cathode potential and the anode potential of the SPAD element 31 formed in the dummy pixel area DA located in the vicinity of the outer periphery of the pixel area A1 are set to the same potential. Therefore, no large negative voltage is applied to the cathode of the SPAD element 31, and the SPAD element 31 is substantially in a non-functioning state.

[0093] Although the logic-side wiring layer 43 does not include the inverter 33, the anode and cathode of the SPAD element 31 are short-circuited to set the anode potential and the cathode potential to the same potential. This prevents current from flowing through the SPAD pixel 22E, and more reliably prevents the characteristics of the sensor chip 10E from deteriorating. The anode and cathode of the SPAD element 31 may be in a floating state.

[0094] (Dummy pixel configuration) An example of the configuration of a SPAD pixel 22E, which is a dummy pixel of the sensor chip 10E, will be described with reference to Fig. 12. Fig. 12 is a cross-sectional view showing an example of the configuration of a SPAD pixel 22E.

[0095] As described above, the SPAD pixel 22E has the SPAD element 31 formed on the sensor substrate 41. In addition, on the sensor side wiring layer 42, contact electrodes 71 to 73, metal wires 74E and 76, contact electrodes 78 and 79, and metal pads 80 to 82 are formed. On the logic-side wiring layer 43, electrode pads 92, 93, an insulating layer 94, contact electrodes 97 to 100, and metal pads 102, 103 are formed.

[0096] 7, in the SPAD pixel 22E, the contact electrodes 71 and 72 are connected to one metal wiring 74B in order to make the cathode potential and the anode potential of the SPAD element 31 the same potential. Moreover, in the SPAD pixel 22E, the wiring of the logic-side wiring layer 43 electrically connected to the cathode of the SPAD element 31 is not provided.

[0097] <Effects of the Sixth Embodiment> The sensor chip 10E according to the fifth embodiment configured as above provides the same advantages as those (1) to (4) in the first embodiment.

[0098] 7.Examples of electronic device configurations FIG. 13 is a block diagram showing an example of the configuration of a range image sensor, which is an electronic device that uses the sensor chip 10.

[0099] 13, the distance image sensor 201 is configured to include an optical system 202, a sensor chip 10, an image processing circuit 203, a monitor 204, and a memory 205. The distance image sensor 201 can obtain a distance image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected from a light source device 211 toward the subject and reflected by the surface of the subject.

[0100] The optical system 202 is configured to have one or more lenses, and guides image light (incident light) from a subject to the sensor chip 10, forming an image on the light receiving surface (sensor portion) of the sensor chip 10.

[0101] As the sensor chip 10, the sensor chip 10 according to each of the above-mentioned embodiments is applied, and a distance signal indicating a distance determined from a light reception signal (APD OUT) output from the sensor chip 10 is supplied to the image processing circuit 203.

[0102] The image processing circuit 203 performs image processing to construct a distance image based on the distance signal supplied from the sensor chip 10, and the distance image (image data) obtained by this image processing is supplied to a monitor 204 for display, or supplied to a memory 205 for storage (recording).

[0103] In the range image sensor 201 configured in this manner, by applying the above-mentioned sensor chip 10, it becomes possible to calculate the distance to the subject and generate a highly accurate range image based only on the light receiving signals from the highly stable SPAD pixels 21. In other words, the range image sensor 201 can obtain a more accurate range image.

[0104] 8.Examples of using image sensors The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.

[0105] ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as on-board sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving (such as automatic stopping) and for recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles, etc. A device used in home appliances such as televisions, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication - Cosmetic devices such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp - Devices used for sports, such as action cameras and wearable cameras for sports use Agricultural equipment such as cameras for monitoring fields and crop conditions

[0106] The present technology may be configured as follows. (1) a pixel array section having a pixel region in which a plurality of pixels are arranged in a matrix; an avalanche photodiode element that amplifies carriers by a high electric field region provided for each pixel; an inter-pixel isolation portion that insulates and isolates adjacent pixels on a semiconductor substrate on which the avalanche photodiode element is formed; a wiring provided in a wiring layer laminated on a surface of the semiconductor substrate opposite to the light receiving surface so as to cover at least the high electric field region; Equipped with the pixel array section has a dummy pixel region located near an outer periphery of the pixel region, The cathode voltage of the avalanche photodiode element disposed in the dummy pixel region The cathode potential and the anode potential are the same, or at least one of the cathode potential and the anode potential is floating. Sensor chip. (2) The cathode and the anode of the avalanche photodiode element arranged in the dummy pixel region are shorted. The sensor chip according to (1) above. (3) a sensor substrate on which the avalanche photodiode element is formed; a logic circuit board on which the quenching resistor and the inverter are formed; a wiring layer including a sensor side wiring layer provided opposite the sensor substrate and a logic side wiring layer provided opposite the logic circuit substrate, the wiring layer electrically connecting the sensor substrate and the logic circuit substrate; Equipped with The cathode and the anode of the avalanche photodiode element arranged in the dummy pixel region are short-circuited in the logic-side wiring layer. The sensor chip according to (1) or (2) above. (4) the pixel array section has a reference pixel region located at the center of the pixel region, anodes of the plurality of avalanche photodiode elements arranged in the reference pixel region are connected to a common wiring; anodes of the plurality of avalanche photodiode elements arranged in the dummy pixel region are connected to a common wiring, The anodes of the plurality of avalanche photodiode elements arranged in the reference pixel region and the anodes of the plurality of avalanche photodiode elements arranged in the dummy pixel region are separated from each other. The sensor chip according to any one of (1) to (3) above. (5) The pixels arranged in the reference pixel area include The avalanche photodiode element; a quenching resistor connected in series with the avalanche photodiode element; an inverter that outputs a light receiving signal based on the electrons multiplied by the avalanche photodiode element; The pixels arranged in the reference pixel area include The avalanche photodiode element is provided. The avalanche photodiode element does not include a quenching resistor connected in series with the avalanche photodiode element, and an inverter that outputs a light receiving signal based on the electrons multiplied by the avalanche photodiode element. The sensor chip according to any one of (1) to (4) above. (6) a pixel array section having a pixel region in which a plurality of pixels are arranged in a matrix; an avalanche photodiode element that amplifies carriers by a high electric field region provided for each pixel; an inter-pixel isolation portion that insulates and isolates adjacent pixels on a semiconductor substrate on which the avalanche photodiode element is formed; a wiring provided in a wiring layer laminated on a surface of the semiconductor substrate opposite to the light receiving surface so as to cover at least the high electric field region; Equipped with the pixel array section has a dummy pixel region located near an outer periphery of the pixel region, The cathode potential and the anode potential of the avalanche photodiode element disposed in the dummy pixel region are the same potential, or at least one of the cathode potential and the anode potential is floating. An electronic device equipped with a sensor chip.

[0107] The scope of the present disclosure is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those contemplated by the present disclosure. Furthermore, the scope of the present disclosure is not limited to the combination of inventive features defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features. [Explanation of symbols]

[0108] 10, 10A, 10B, 10C, 10D, 10E Sensor chip 11 Pixel array section 12 Bias voltage application section 21, 21C, 22, 22A, 22B, 22C, 22D, 22E SPAD pixels 23 Electrode Pads 31 SPAD element 32 Quenching resistor 33 Inverter 41 Sensor board 42 Sensor side wiring layer 43 Logic side wiring layer 51 N-well 52 P-type diffusion layer 53 N-type diffusion layer 54 Hole accumulation layer 55 Pinning Layer 56 High concentration P-type diffusion layer 57 Avalanche multiplication region 61 Metal Film 62 Insulating film 63 Inter-pixel separation section 71, 72, 73 Contact electrodes 74, 74B, 74E, 75, 76 Metal wiring 77,78,79 Contact electrodes 80,81,82,101,102,103 Metal pad 91, 91D, 92, 93 Electrode pads 94 Insulating Layer 95,96,97,78,99,100 Contact electrodes A1 Pixel area A2 Peripheral area A3 Pad Area DA Dummy pixel area RA Reference Pixel Area

Claims

1. a pixel array section having a pixel region in which a plurality of pixels are arranged in a matrix; an avalanche photodiode element that amplifies carriers by a high electric field region provided for each pixel; an inter-pixel isolation portion that insulates and isolates adjacent pixels on a semiconductor substrate on which the avalanche photodiode element is formed; a wiring provided in a wiring layer laminated on a surface of the semiconductor substrate opposite to the light receiving surface so as to cover at least the high electric field region; Equipped with the pixel array section has a reference pixel region located at a center of the pixel region and a dummy pixel region located near an outer periphery of the pixel region, a pixel arranged in the reference pixel region includes the avalanche photodiode element electrically connected to a bias voltage application unit, a quenching resistor electrically connected to a power supply to which an excitation voltage is applied and connected in series with the avalanche photodiode element, and an inverter having an input terminal electrically connected to the avalanche photodiode element and the quenching resistor and outputting a light receiving signal based on electrons multiplied by the avalanche photodiode element, The pixel arranged in the dummy pixel region includes the avalanche photodiode element electrically connected to the bias voltage application unit, a quenching resistor electrically connected to the power supply and not electrically connected to the avalanche photodiode element, and an inverter having an input terminal not electrically connected to the avalanche photodiode element and the quenching resistor. Sensor chip.

2. The cathode and the anode of the avalanche photodiode element arranged in the dummy pixel region are shorted. The sensor chip according to claim 1 .

3. A pixel array section having a pixel area in which a plurality of pixels are arranged in a matrix; an avalanche photodiode element that amplifies carriers by a high electric field region provided for each pixel; an inter-pixel isolation portion that insulates and isolates adjacent pixels on a semiconductor substrate on which the avalanche photodiode element is formed; a wiring provided in a wiring layer laminated on a surface of the semiconductor substrate opposite to the light receiving surface so as to cover at least the high electric field region; Equipped with the pixel array section has a reference pixel region located at a center of the pixel region and a dummy pixel region located near an outer periphery of the pixel region, a pixel arranged in the reference pixel region includes the avalanche photodiode element electrically connected to a bias voltage application unit, a quenching resistor electrically connected to a power supply to which an excitation voltage is applied and connected in series with the avalanche photodiode element, and an inverter having an input terminal electrically connected to the avalanche photodiode element and the quenching resistor and outputting a light receiving signal based on electrons multiplied by the avalanche photodiode element, a pixel disposed in the dummy pixel region has the avalanche photodiode element electrically connected to the bias voltage application unit, and a cathode and an anode of the avalanche photodiode element are short-circuited; The pixel arranged in the dummy pixel region further includes a quenching resistor electrically connected to the power supply and connected in series with the avalanche photodiode element, and an inverter having an input terminal that is not electrically connected to the avalanche photodiode element and the quenching resistor. Sensor chip.

4. a sensor substrate on which the avalanche photodiode element is formed; a logic circuit board on which the quenching resistor and the inverter are formed; a wiring layer including a sensor side wiring layer provided opposite the sensor substrate and a logic side wiring layer provided opposite the logic circuit substrate, the wiring layer electrically connecting the sensor substrate and the logic circuit substrate; Equipped with The cathode and the anode of the avalanche photodiode element arranged in the dummy pixel region are short-circuited in the logic-side wiring layer. The sensor chip according to claim 2 or 3.

5. the pixel array section has a reference pixel region located at the center of the pixel region, anodes of the plurality of avalanche photodiode elements arranged in the reference pixel region are connected to a common wiring; anodes of the plurality of avalanche photodiode elements arranged in the dummy pixel region are connected to a common wiring, The anodes of the plurality of avalanche photodiode elements arranged in the reference pixel region and the anodes of the plurality of avalanche photodiode elements arranged in the dummy pixel region are separated from each other. The sensor chip according to claim 1 .

6. a pixel array section having a pixel region in which a plurality of pixels are arranged in a matrix; an avalanche photodiode element that amplifies carriers by a high electric field region provided for each pixel; an inter-pixel isolation portion that insulates and isolates adjacent pixels on a semiconductor substrate on which the avalanche photodiode element is formed; a wiring provided in a wiring layer laminated on a surface of the semiconductor substrate opposite to the light receiving surface so as to cover at least the high electric field region; Equipped with the pixel array section has a reference pixel region located at the center of the pixel region and a dummy pixel region located near the outer periphery of the pixel region, a pixel arranged in the reference pixel region includes the avalanche photodiode element electrically connected to a bias voltage application unit, a quenching resistor electrically connected to a power supply to which an excitation voltage is applied and connected in series with the avalanche photodiode element, and an inverter having an input terminal electrically connected to the avalanche photodiode element and the quenching resistor and outputting a light receiving signal based on electrons multiplied by the avalanche photodiode element, The pixel arranged in the dummy pixel region includes the avalanche photodiode element electrically connected to the bias voltage application unit, a quenching resistor electrically connected to the power supply and not electrically connected to the avalanche photodiode element, and an inverter having an input terminal not electrically connected to the avalanche photodiode element and the quenching resistor. An electronic device equipped with a sensor chip.

7. a pixel array section having a pixel region in which a plurality of pixels are arranged in a matrix; an avalanche photodiode element that amplifies carriers by a high electric field region provided for each pixel; an inter-pixel isolation portion that insulates and isolates adjacent pixels on a semiconductor substrate on which the avalanche photodiode element is formed; a wiring provided in a wiring layer laminated on a surface of the semiconductor substrate opposite to the light receiving surface so as to cover at least the high electric field region; Equipped with the pixel array section has a reference pixel region located at a center of the pixel region and a dummy pixel region located near an outer periphery of the pixel region, a pixel arranged in the reference pixel region includes the avalanche photodiode element electrically connected to a bias voltage application unit, a quenching resistor electrically connected to a power supply to which an excitation voltage is applied and connected in series with the avalanche photodiode element, and an inverter having an input terminal electrically connected to the avalanche photodiode element and the quenching resistor and outputting a light receiving signal based on electrons multiplied by the avalanche photodiode element, The pixel arranged in the dummy pixel region includes the avalanche photodiode element electrically connected to the bias voltage application unit, a quenching resistor electrically connected to the power supply and connected in series with the avalanche photodiode element, and an inverter whose input terminal is not electrically connected to the avalanche photodiode element and the quenching resistor, and the cathode and anode of the avalanche photodiode element are short-circuited. An electronic device equipped with a sensor chip.

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