Staggered vertical crystalline semiconductor channel

Abstract

The semiconductor structure includes a first semiconductor channel having a plurality of vertical nanowires and a second semiconductor channel having a plurality of vertical nanowires, the first semiconductor channel and the second semiconductor channel being configured in a stacked configuration, with the plurality of vertical nanowires of the first semiconductor channel being configured to be interleaved with the plurality of vertical nanowires of the second semiconductor channel.

Description

[Technical field]

[0001] The present invention relates generally to semiconductor technology, and more particularly to structures and methods for forming vertical semiconductor channels. [Background technology]

[0002] Vertical stacking of field-effect transistors (FETs) provides an additional dimension for scaling complementary metal-oxide-semiconductor (CMOS) area. In a typical CMOS layout, 90 percent of the first transistors are connected to at least a second transistor. For example, the drain of an n-type transistor is connected to the drain of a p-type transistor to form an inverter. Other arrangements are possible, such as a connection between the drain of the first transistor connected to the source of the second transistor, the drain of the first transistor connected to the drain of the second transistor, or the source of the first transistor connected to the source of the second transistor, where the first and second transistors can be any combination of n-type or p-type transistors.

[0003] Vertical field effect transistors (VFETs) have a unique structure that can support stacking processes. In contrast to planar CMOS devices, VFETs are adapted with a vertical fin channel located at the bottom source / drain and the top source / drain located at the fin channel. The gate runs vertically parallel to the vertical fin channel. VFETs are being investigated as a potential device option for scaling CMOS to the 5 nanometer (nm) node and beyond. Summary of the Invention [Means for solving the problem]

[0004] Embodiments of the invention include structures and methods for forming staggered stacked vertical semiconductor channels. For example, one exemplary embodiment includes a semiconductor structure comprising a first semiconductor channel comprising a plurality of vertical nanowires and a second semiconductor channel comprising a plurality of vertical nanowires. The first semiconductor channel and the second semiconductor channel are configured in a stacked configuration. The plurality of vertical nanowires of the first semiconductor channel are configured to be staggered relative to the plurality of vertical nanowires of the second semiconductor channel.

[0005] In another exemplary embodiment, a logic device is included having one or more semiconductor structures, at least one of which comprises a first semiconductor channel comprising a plurality of vertical nanowires and a second semiconductor channel comprising a plurality of vertical nanowires, the first semiconductor channel and the second semiconductor channel being configured in a stacked configuration, the plurality of vertical nanowires of the first semiconductor channel being configured to be interleaved with respect to the plurality of vertical nanowires of the second semiconductor channel.

[0006] Another exemplary embodiment includes an integrated circuit logic device having one or more semiconductor structures, at least one of which comprises a first semiconductor channel comprising a plurality of vertical nanowires and a second semiconductor channel comprising a plurality of vertical nanowires, the first semiconductor channel and the second semiconductor channel being configured in a stacked configuration, the plurality of vertical nanowires of the first semiconductor channel being configured to be interleaved with the plurality of vertical nanowires of the second semiconductor channel.

[0007] Another exemplary embodiment includes a method including forming a first semiconductor channel comprising a plurality of vertical nanowires and a second semiconductor channel comprising a plurality of vertical nanowires on a semiconductor substrate, the first semiconductor channel and the second semiconductor channel being configured in a stacked configuration, the plurality of vertical nanowires of the first semiconductor channel being configured to be interleaved with respect to the plurality of vertical nanowires of the second semiconductor channel.

[0008] Another exemplary embodiment includes a method including forming a plurality of layered silicon-insulator-silicon nanowires from a substrate surface. The plurality of nanowires includes a hard mask on a top surface thereof. The method further includes forming a liner on an outer surface of the alternating layered silicon-insulator-silicon nanowires. The liner is formed on a portion of the insulating layer and extends to the hard mask, exposing a lower silicon layer of the layered silicon-insulator-silicon nanowires. The method further includes forming a first oxide layer on an outer surface of the other alternating layered silicon-insulator-silicon nanowires. The first oxide layer is formed on a portion of the insulating layer and extends to a top surface of the substrate, exposing a top silicon layer of the layered silicon-insulator-silicon nanowires. The method further includes thermally oxidizing the exposed lower silicon layer of the layered silicon-insulator-silicon nanowires and the exposed top silicon layer of the layered silicon-insulator-silicon nanowires.

[0009] These and other features, objects and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional side view of a semiconductor structure at a first intermediate stage of manufacture, in accordance with one or more exemplary embodiments. [Diagram 2] 4 is a schematic cross-sectional side view of a semiconductor structure at a second intermediate stage of manufacture in accordance with one or more exemplary embodiments. [Diagram 3] 4 is a schematic cross-sectional side view of a semiconductor structure at a third intermediate stage of manufacture in accordance with one or more exemplary embodiments. [Figure 4] 1 is a schematic cross-sectional side view of a semiconductor structure at a fourth intermediate stage of manufacture in accordance with one or more exemplary embodiments. [Diagram 5] 1 is a schematic cross-sectional side view of a semiconductor structure at a fifth intermediate stage of manufacture in accordance with one or more exemplary embodiments. [Figure 6] 1 is a schematic cross-sectional side view of a semiconductor structure at a sixth intermediate stage of manufacture in accordance with one or more exemplary embodiments. [Figure 7] 1 is a schematic cross-sectional side view of a semiconductor structure at a seventh intermediate stage of manufacturing in accordance with one or more exemplary embodiments. [Figure 8] 1 is a schematic cross-sectional side view of a semiconductor structure at an eighth intermediate stage of manufacturing in accordance with one or more exemplary embodiments. [Figure 9] 1 is a schematic cross-sectional side view of a semiconductor structure at a ninth intermediate stage of manufacture, in accordance with one or more exemplary embodiments. [Figure 10] 1 is a schematic cross-sectional side view of a semiconductor structure at a tenth intermediate stage of manufacturing in accordance with one or more exemplary embodiments. [Figure 11] 1 is a schematic cross-sectional side view of a semiconductor structure at an eleventh intermediate stage of manufacturing, in accordance with one or more exemplary embodiments. [Figure 12] 1 is a schematic cross-sectional side view of a semiconductor structure at a twelfth intermediate stage of manufacture, in accordance with one or more exemplary embodiments; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present disclosure relates generally to semiconductor fabrication techniques, and in particular to structures and methods for fabricating staggered vertical semiconductor channels used to create vertical field effect transistor devices. Vertical stacking of VFETs requires fabricating "L" shaped conductive material, making connection of the source / drain (S / D) contacts of the lower FET difficult. The vertically stacked crystalline semiconductor structure (or vertical fin array) of the exemplary embodiment, with staggered semiconductor fins, ultimately allows for connection of the S / D contacts of the lower FET in an easy and straightforward manner.

[0012] It should be understood that the various layers, structures, and regions shown in the accompanying figures are schematic and not drawn to scale. Additionally, for ease of illustration, one or more layers, structures, and regions of the type commonly used in forming semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from an actual semiconductor structure.

[0013] Furthermore, it should be understood that the embodiments described herein are not limited to the specific materials, features, and process steps shown and described herein. In particular, with respect to semiconductor process steps, it should be emphasized that the description provided herein is not intended to be inclusive of all of the process steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain process steps commonly used to form semiconductor devices, such as, for example, wet cleaning and annealing steps, have not been purposely described herein for purposes of brevity of the specification.

[0014] It should be noted that the same or similar reference numbers are used throughout the drawings to represent the same or similar features, elements, or structures. Therefore, detailed descriptions of the same or similar features, elements, or structures are not repeated in each drawing. As used herein, the term "about" or "substantially" with respect to thickness, width, percentage, range, etc., should be understood to mean to indicate close or approximate, but not exact. For example, as used herein, the term "about" or "substantially" means that there may be a small margin of error, for example, 1% or less of the specified amount.

[0015] Exemplary embodiments for forming a semiconductor structure are described below with reference to Figures 1-12. Referring now to the figures, Figure 1 is a cross-sectional view of a semiconductor structure 100 including a semiconductor substrate 102 and a hard mask layer 104. The semiconductor substrate 102 may include a conventional silicon-on-insulator (SOI) substrate wafer, such as, for example, an extremely thin silicon on insulator (ETSOI) or ultra-thin body and buried oxide (UTBB) silicon on insulator (SOI) substrate wafer known to those skilled in the art. Alternatively, the semiconductor substrate 102 may include a bulk semiconductor substrate wafer. As shown, the substrate 102 may initially include a base layer 102a, e.g., silicon. An insulating layer 102b, e.g., a buried oxide layer, may be formed on the base layer 102a. A silicon layer 102c is subsequently formed over the insulating layer 102b, although the silicon layer 102c may be any other suitable semiconductor layer. In one embodiment, the substrate 102 is a layered silicon-insulator-silicon substrate.

[0016] The top semiconductor layer of semiconductor material of the SOI substrate or bulk substrate may be appropriately doped depending on the integrated circuit application. In an exemplary embodiment of the SOI substrate, the top semiconductor layer may be of fully depleted (FD) configuration. The bulk substrate may include, for example, multiple epitaxially grown semiconductor layers. The process techniques described herein are equally applicable to SOI and bulk substrates, as well as other types of substrates.

[0017] The hard mask layer 104 is deposited on the substrate 102 using any conventional deposition process, such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other similar processes. Suitable materials for the hard mask layer 104 include, for example, TiN, SiO2, TaN, SiN, AlOx, SiC, and the like. The hard mask layer 104 can then be planarized by a planarization process, such as, for example, a chemical mechanical planarization (CMP) process.

[0018] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 2, where the semiconductor structure 100 is patterned to form a series of vertical nanowires 106. The vertical nanowires 106 have substantially vertical sidewalls. Although four vertical nanowires 106 are illustrated in FIG. 2, the number of vertical nanowires 106 should not be considered as limiting. To form the vertical nanowires 106, lithography and etching are performed using any type of patterning technique, such as direct print lithography or sidewall-image-transfer (SIT) process. The direct print lithography process is one of 193i lithography or extreme ultra-violet (EUV) lithography, which are well known to those skilled in the art. The SIT process is sometimes referred to as self-aligned double patterning (SADP) process. In some embodiments, a SIT process may be used to pattern the fine lines in the hard mask 104. For example, lithography may include forming a photoresist (not shown) on the hard mask layer 104, exposing the photoresist to a desired type of radiation, and then developing the exposed photoresist in a resist developer to provide a patterned photoresist on top of the hard mask layer 104.

[0019] Etching is used at least once to transfer the pattern from the patterned photoresist to the hard mask layer 104 and the substrate 102. Etching deeply but not through the substrate 102 forms the vertical nanowires 106. For example, etching through the hard mask layer 104, the silicon layer 102c, the insulating layer 102b, and a portion of the base layer 102a forms the vertical nanowires 106. The etching process may be a dry etch (e.g., reactive ion etching, plasma etching, ion beam etching, or laser ablation). The etching process may be a wet chemical etch (e.g., with potassium hydroxide, or sulfuric acid and hydrogen peroxide). Both dry and wet chemical etching processes may be used. After the pattern is transferred, a resist stripping process, e.g., ashing, is used to remove the patterned photoresist. Ashing is performed with a suitable reactive gas, e.g., O2, N2, H2 / N2, O3, CF4, or any combination thereof.

[0020] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 3. In this figure, a liner 108 is formed on the substrate 102, the hard mask 104, and the vertical nanowires 106. The liner 108 can be any liner material, such as a dielectric material. Suitable dielectric materials include, for example, silicon nitride, silicon oxide, silicon oxynitride, a dielectric metal oxide, a dielectric metal nitride, or a combination thereof. The liner 108 can be formed, for example, by depositing a liner layer using an ALD process. The liner layer 108 can have a thickness in the range of about 1 to about 3 nanometers (nm).

[0021] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in Figure 4, where the etched areas are then filled with oxide 110 on the liner 108 and over the vertical nanowires 106. Suitable oxide materials include, for example, silicon dioxide. In one embodiment, the oxide fill 110 is formed by depositing a blanket layer of oxide over the vertical nanowires 106 and then planarizing the oxide, for example, by a CMP process.

[0022] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 5, in which a portion of the oxide fill 110 is patterned using lithography to expose the tops of the alternating vertical nanowires 106 and the liner 108. In one embodiment, the oxide fill 110 can be selectively removed using an anisotropic etch. For example, in one exemplary embodiment, the anisotropic etch can be performed with hydrofluoric acid, such as a form of gaseous anhydrous HF, along with ammonia. In another exemplary embodiment, the anisotropic etch can be performed with a hydrofluorocarbon plasma etch. For example, the plasma etch can be performed with a hydrofluorocarbon plasma gas in combination with an inert gas. Typically, the inert gas can be at least 90%. In one exemplary embodiment, the hydrofluorocarbon can be C5HF7 and the inert gas can be argon and oxygen, which, when excited in the plasma etch chamber, produces a high density plasma. In an exemplary embodiment, a radio frequency (RF) power source inductively couples power into the chamber while the substrate to be etched is supported on a pedestal. The pedestal is also biased with an RF power source at a power higher than the inductive coupling power. A silicon-containing surface may also be included in the chamber and is held at at least 20° C. to remove fluorine from the plasma. The etch results in high selectivity to the oxide fill 110 (e.g., silicon oxide) compared to the liner 108 (e.g., silicon nitride) and the lithographically patterned photoresist (not shown). Due to the high selectivity of the plasma etch, the liner 108 remains unetched. Thus, the oxide fill 110 is selectively removed during the etch, exposing the tops of the alternating vertical nanowires 106. In one embodiment, the oxide fill 110 is removed down to the top surface of the insulating layer 102b of each of the alternating vertical nanowires 106.

[0023] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 6, where spacers 112 are deposited on the sidewalls of the oxide fill 110 and the liner 108 on the alternating vertical nanowires 106. The spacers 112 can be deposited by any conventional technique, such as ALD and etch-back using an anisotropic dry etch process, such as reactive ion etching (RIE). Suitable materials for the spacers 112 include, for example, amorphous carbon (aC). If necessary, any spacer material on the horizontal portions of the structure 100 can be removed, for example, by RIE. The spacers 112 can have a thickness in the range of about 1 nm to about 3 nm.

[0024] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 7, in which the oxide fill 110 between adjacent spacers 112 is further removed to expose the top surface of the liner 108. In one embodiment, the oxide fill 110 can be selectively removed using an anisotropic etch. In one exemplary embodiment, the anisotropic etch can be performed by a hydrofluorocarbon plasma etch. For example, the plasma etch can be performed using a hydrofluorocarbon plasma gas in combination with an inert gas. In one exemplary embodiment, the inert gas can be at least about 90% of the plasma etch. In one exemplary embodiment, the hydrofluorocarbon can be C5HF7 and the inert gas can be argon and oxygen, which when excited in a plasma etch chamber produces a high density plasma as described above. The etch results in a high selectivity for the oxide fill 110 compared to the liner 108 and the spacers 112. Due to the high selectivity of the plasma etch, the liner 108 and the spacers 112 remain unetched. In another exemplary embodiment, the anisotropic etch can be performed with hydrofluoric acid, such as in the form of gaseous anhydrous HF, along with ammonia.

[0025] Thus, the oxide fill 110 is selectively removed during this etch, exposing the tops of the alternating vertical nanowires 106 and the top surface of the liner 108 between adjacent spacers 112. In addition, the oxide fill 110 remains below the spacers 112. In one embodiment, the oxide fill 110 is removed down to the top surface of the insulating layer 102b of each of the alternating vertical nanowires 106.

[0026] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 8, in which the oxide fill 110 beneath each spacer 112 formed on the sidewall of the liner layer 108 of each of the alternating vertical nanowires 106 is selectively removed by isotropic etching. In one embodiment, the oxide fill 110 can be selectively removed using an isotropic etch. In one exemplary embodiment, the isotropic etch can be performed by a hydrofluorocarbon plasma etch. For example, the plasma etch can be performed using a hydrofluorocarbon plasma gas in combination with an inert gas. Typically, the inert gas can be at least 90%. In one exemplary embodiment, the hydrofluorocarbon can be C5HF7 and the inert gas can be argon and oxygen, which when excited in a plasma etch chamber produces a high density plasma as described above. The etch results in a high selectivity to the oxide fill 110 compared to the liner 108 and the spacers 112. Due to the high selectivity of this plasma etch, the liner 108 and the spacers 112 remain unetched. In another exemplary embodiment, the isotropic etch can be performed with hydrofluoric acid, such as in the form of gaseous anhydrous HF, along with ammonia. As explained above, the isotropic etch selectively removes the oxide fill 110 by flowing a wet etchant between the spacers 112. During this etch, a portion of the oxide fill 110 on the sidewalls of adjacent vertical nanowires 106 can be removed. In addition, a portion of the oxide fill 110 under the spacers 112 of adjacent vertical nanowires 106 can be isotropically recessed.

[0027] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 9, in which the exposed liner 108 over the oxide fill 110 of the alternating vertical nanowires 106 and the exposed liner 108 over the hard mask 104 of each vertical nanowire 106 are selectively removed. In one exemplary embodiment, the exposed liner 108 is selectively removed by isotropic etching. In one exemplary embodiment, the isotropic etch can be performed by a fluorocarbon plasma etch. For example, the plasma etch can be performed using a fluorocarbon plasma gas in combination with an inert gas. Typically, the inert gas can be at least 90%. In one exemplary embodiment, the fluorocarbon can be CF4 and the inert gas can be oxygen and nitrogen, which when excited in a plasma etch chamber produces a high density plasma as described above. In another exemplary embodiment, the fluorocarbon can be CF4 and the inert gas can be argon, which when excited in a plasma etch chamber produces a high density plasma as described above. The etch results in a high selectivity to the exposed liner 108 compared to the oxide filler 110 and the spacers 112 .

[0028] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 10, in which the spacers 112 have been removed. The spacers 112 can be removed by any suitable etching process, including but not limited to a wet etch process or a dry etch. For example, the etching can be performed using an RIE or plasma etch process and N2 / H2 chemistry or N2 / H2 chemistry in an inert gas such as argon.

[0029] The next step in forming the vertically stacked fins of the semiconductor device 100 is illustrated in FIG. 11, where the exposed silicon portions 102a and 102c are subjected to a thermal oxidation process known in the art. A thermal oxidation process is performed to oxidize the exposed portions 102a of the alternating vertical nanowires 106 and the exposed portions 102c of the alternating vertical nanowires 106. This process forms an oxide in the exposed portions 102a of the alternating vertical nanowires 106 and in the exposed portions 102c of the alternating vertical nanowires 106. As illustrated, the formed oxide is the same as the oxide fill 110.

[0030] The next step in forming the vertically stacked fins of the semiconductor structure 100 is illustrated in FIG. 12. In this figure, the exposed portions of the structure 100 are then filled with an oxide material. The oxide material may be the same as or different from the oxide fill 110. In one exemplary embodiment, the oxide fill 110 is the same as the oxide fill 110. In one embodiment, the oxide fill 110 is formed by depositing a blanket layer of oxide over the exposed portions of the structure 100 and the vertical nanowires 106, and then planarizing the oxide, for example, by a CMP process. The resulting structure 100 includes vertical crystalline nanowires 106 that are staggered at the pitch between two layers containing the vertical nanowires 106 in a stacked configuration. The resulting structure 100 has staggered crystalline semiconductor channels 102a and 102c that have the same pitch, but are shifted or translated between the upper and lower levels of the vertical fin array.

[0031] In one embodiment, the fins at the bottom of the stack may form PFET transistors and the fins at the top of the stack may form NFET transistors, however, the invention is not so limited and may include structures where the transistors at the bottom of the stack and the transistors at the top of the stack are PFETs and PFETs, NFETs and NFETs, or NFETs and PFETs, respectively.

[0032] The vertically stacked staggered semiconductor fins disclosed herein may be subjected to one or more additional process steps. For example, the first field effect transistor may further include a source / drain region and a gate structure including a gate dielectric layer and a metal gate layer. The second field effect transistor stacked on the first field effect transistor may further include a source / drain region and a gate structure including a gate dielectric layer and a metal gate layer. In addition, one or more conductive vias may be in communication with either the gate structure of the first FET device or the gate structure of the second FET device.

[0033] The source / drain regions may be formed, for example, by growing epitaxial semiconductor material on the exposed top surface of the nanowire 106 of the first field effect transistor. An epitaxial growth process is performed to deposit a crystalline layer on an underlying crystalline substrate, which acts as a seed crystal. The epitaxial layer may be grown from a gas or liquid precursor. The epitaxial silicon material may be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process. The type of epitaxial material and dopants used to form the source region 112 will vary depending on whether the FET device is P-type or N-type. Examples of semiconductor materials that may be suitable for epitaxial growth of the source / drain regions include, but are not limited to, silicon (single crystal, polysilicon, or amorphous), germanium (single crystal, polycrystalline, or amorphous), or combinations thereof.

[0034] After the semiconductor material is grown, it is doped with dopant atoms, for example, by in-situ doping or ion implantation, or by in-situ doping during epitaxy. In this exemplary embodiment, the semiconductor material is doped with a p-type dopant, such as, for example, boron, aluminum, gallium, indium, or alloys thereof, to form a PFET source region. As described below, in other embodiments, the semiconductor material may be doped with an n-type dopant, such as, for example, phosphorus, antimony, arsenic, or alloys thereof. After the doping process, the semiconductor material is doped with about 1×10 19 atoms / cm 3 ~Approx. 5×10 21 atoms / cm 3 The dopant may have a concentration in the range of 0.1 to 1.0 μm.

[0035] It should be understood that the methods described herein for fabricating semiconductor structures can be incorporated into semiconductor process flows for fabricating other types of semiconductor devices, as well as integrated circuits including various analog and digital or mixed signal circuits. In particular, integrated circuit dies can be fabricated that include various devices such as transistors, diodes, capacitors, inductors, and the like. Integrated circuits according to embodiments can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., mobile phones), solid state media storage devices, functional circuits, and the like. Systems and hardware incorporating such integrated circuits are considered to be part of the embodiments described herein.

[0036] Further, the various layers, regions, and / or structures described above may be implemented into an integrated circuit (chip). The resulting integrated circuit chip may be distributed by a manufacturer in raw wafer form as bare die (i.e., as a single wafer with multiple unpackaged chips) or in packaged form. In the latter case, the chip may be mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other upper level carrier) or in a multi-chip package (such as a ceramic carrier with surface or buried wiring or both). In either case, the chip may be incorporated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing the integrated circuit chip, ranging from toys and other sub-applications to high performance computer products with displays, keyboards or other input devices, and central processing units.

[0037] Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these detailed embodiments, and various other changes and modifications may be made by those skilled in the art without departing from the scope of the invention.

[0038] In a preferred embodiment of the present invention described above, a method is provided that includes: forming a plurality of layered silicon-insulator-silicon vertical nanowires from a substrate surface, the plurality of nanowires having a hard mask on their upper surface; forming liners on outer surfaces of alternating layered silicon-insulator-silicon vertical nanowires, the liners being formed on a portion of the insulating layer and extending to the hard mask, exposing the lower silicon layers of the layered silicon-insulator-silicon vertical nanowires; forming a first oxide layer on outer surfaces of other alternating layered silicon-insulator-silicon vertical nanowires, the first oxide layer being formed on a portion of the insulating layer and extending to the substrate upper surface, exposing the upper silicon layers of the layered silicon-insulator-silicon vertical nanowires; and thermally oxidizing the exposed lower silicon layers of the layered silicon-insulator-silicon nanowires and the exposed upper silicon layers of the layered silicon-insulator-silicon nanowires. Preferably, the method further comprises depositing a second oxide layer over the outer surface of the substrate surface and the first oxide layer and over the liner.

Claims

1. A substrate including a semiconductor material; a first semiconductor channel comprising a plurality of vertical nanowires, each vertical nanowire comprising a first semiconductor layer of the semiconductor material, a first insulating layer on the first semiconductor layer, and a first oxide layer on the first insulating layer; a second semiconductor channel comprising a plurality of vertical nanowires, each vertical nanowire including a second oxide layer on the substrate, a second insulating layer on the second oxide layer, and a second semiconductor layer of the semiconductor material on the second insulating layer; 1. A semiconductor structure comprising: the first semiconductor channel and the second semiconductor channel are configured in a stacked configuration; A semiconductor structure configured such that each of the plurality of vertical nanowires of the first semiconductor channel is interleaved with each of the plurality of vertical nanowires of the second semiconductor channel.

2. 10. The semiconductor structure of claim 1 wherein said substrate is a bulk substrate.

3. 3. The semiconductor structure of claim 2 wherein said bulk substrate comprises silicon.

4. 10. The semiconductor structure of claim 1 wherein said semiconductor material comprises silicon.

5. 10. The semiconductor structure of claim 1 wherein said plurality of vertical nanowires of said first semiconductor channel and said plurality of vertical nanowires of said second semiconductor channel are disposed within a third oxide layer.

6. 10. The semiconductor structure of claim 1 , wherein said first semiconductor channel comprises a first vertical field effect transistor and said second semiconductor channel comprises a second vertical field effect transistor, said second vertical field effect transistor configured to be stacked above said first vertical field effect transistor.

7. 2. The semiconductor structure of claim 1 wherein said first semiconductor channel is n-channel and said second semiconductor channel is p-channel.

8. 2. The semiconductor structure of claim 1 wherein said first semiconductor channel is p-channel and said second semiconductor channel is n-channel.

9. A semiconductor device comprising: a first liner disposed on a portion of the substrate and on a portion of the first semiconductor layer and the first insulating layer of the plurality of vertical nanowires of the first semiconductor channel; a second liner disposed on a portion of the second semiconductor layer and the second insulating layer of the plurality of vertical nanowires of the second semiconductor channel; 10. The semiconductor structure of claim 1 further comprising:

10. A logic device comprising at least one semiconductor structure according to any one of the preceding claims.

11. 11. An integrated circuit comprising the logic device of claim 10.

12. A method of forming a substrate comprising: forming a first semiconductor channel comprising a plurality of vertical nanowires, each vertical nanowire including a first semiconductor layer of the semiconductor material, a first insulating layer on the first semiconductor layer, and a first oxide layer on the first insulating layer; forming a second semiconductor channel comprising a plurality of vertical nanowires, each vertical nanowire including a second oxide layer on the substrate, a second insulating layer on the second oxide layer, and a second semiconductor layer of the semiconductor material on the second insulating layer; A method comprising: the first semiconductor channel and the second semiconductor channel are formed in a stacked configuration; A method, wherein each of the plurality of vertical nanowires of the first semiconductor channel is formed interleaved with each of the plurality of vertical nanowires of the second semiconductor channel.

13. The method of claim 12 , wherein the semiconductor material comprises silicon.

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