Quantum Computing Array

Abstract

The quantum processing system includes a first set of control electronics operating at a first temperature. A second set of control electronics is communicatively coupled to the first set of control electronics and operates at a second control temperature lower than the first temperature. The second set of control electronics includes one or more circuits configured to perform write and read operations on one or more qubits. There is a qubit array including one or more qubits and operating at a third control temperature lower than the second temperature. The qubit array is controlled by the second set of control electronics.

Description

[Technical field]

[0001] The present disclosure relates generally to superconducting devices, and more particularly to scalable qubit architectures. [Background technology]

[0002] Superconducting quantum computing is an implementation of a quantum computer in superconducting electronic circuits. Quantum computing studies the application of quantum phenomena for information processing and communication. Various models of quantum computing exist, the most commonly seen model includes the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states but can be in a quantum superposition of both states. A quantum gate is a generalization of a logic gate. However, a quantum gate describes the transformation that one or more qubits will undergo after a gate is applied to them, given their initial state. Summary of the Invention

[0003] According to various embodiments, methods and systems are provided for controlling qubits in a quantum processing system. There is a first set of control electronics operating at a first temperature. There is a second set of control electronics communicatively coupled to the first set of control electronics and operating at a second control temperature lower than the first temperature. The second set of control electronics includes one or more circuits configured to perform write operations on one or more qubits and one or more circuits configured to perform read operations on the one or more qubits. There is a qubit array including one or more qubits and operating at a third control temperature lower than the second temperature. The qubit array is controlled by the second set of control electronics.

[0004] In one embodiment, the first temperature is at substantially room temperature.

[0005] In one embodiment, there is a first set of interconnects between the first and second sets of control electronics configured to at least one of control, monitor or provide one or more reference signals to the second set of control electronics, including at least one of a voltage reference, a current reference or a clock reference that does not scale with the number of qubits in the qubit array. There may be a second set of interconnects between the second set of control electronics and the qubit array configured to at least one of monitor or provide dynamic signals to one or more qubits of the qubit array, with one interconnect in the second set of interconnects for each of the one or more qubits of the qubit array.

[0006] In one embodiment, the second set of control electronics includes a plurality of write controllers, each write controller including an independently programmable qubit control circuit. There can be a first signal processing element configured to process a common portion of the waveform shape for amplitude and phase, and each write controller includes a second signal processing element configured to process a portion that is qubit specific. Each independently programmable element of the write controller can be configured to process a unique combination of amplitude and phase of the waveform shape for a corresponding qubit in the qubit array.

[0007] In one embodiment, the first signal processing element includes a high resolution digital-to-analog converter and the second signal processing element includes a low resolution digital-to-analog converter having a lower resolution than the first signal processing element.

[0008] In one embodiment, the qubit array includes a plurality of clusters, each cluster arranged to provide maximum separation of the resonant frequencies of its corresponding qubits to minimize cross talk between adjacent clusters of the plurality of clusters.

[0009] In one embodiment, the second set of control electronics is in complementary metal oxide semiconductor (CMOS) technology.

[0010] In one embodiment, the second set of control electronics is further configured to provide power management circuitry for the qubit array.

[0011] In one embodiment, the second control temperature is a cryogenic temperature between 1 and 4 Kelvin.

[0012] In one embodiment, the third control temperature is a cryogenic temperature of approximately 240 mK.

[0013] In one embodiment, the qubit array is divided into groups, with each group containing a diverse set of qubit center frequencies such that cross-talk between adjacent qubits is reduced.

[0014] In one embodiment, at least one of the one or more circuits configured to perform a write operation includes two separate multiplier mixers for separately deriving the upper and lower sidebands.

[0015] According to one embodiment, a method of controlling an array of qubits is provided. A first set of control electronics is operated at a first temperature. A second set of control electronics communicatively coupled to the first set of control electronics is operated at a second control temperature lower than the first temperature. The second set of control electronics includes one or more circuits configured to perform write operations on one or more qubits and one or more circuits configured to perform read operations on the one or more qubits. A qubit array including the one or more qubits is operated at a third control temperature lower than the second temperature. The qubit array is controlled by the second set of control electronics.

[0016] In one embodiment, the first temperature is substantially at room temperature. The second controlled temperature is a cryogenic temperature between 1 and 4 Kelvin. The third controlled temperature is a cryogenic temperature of approximately 240 mK.

[0017] In one embodiment, a first set of interconnects is provided between the first and second sets of control electronics for at least one of controlling, monitoring or providing one or more reference signals to the second set of control electronics, including at least one of a voltage reference, a current reference or a clock reference that does not scale with the number of qubits in the qubit array. A second set of interconnects is provided between the second set of control electronics and the qubit array for at least one of monitoring or providing dynamic signals to the one or more qubits of the qubit array. There is one interconnect in the second set of interconnects for each of the one or more qubits of the qubit array.

[0018] In one embodiment, a common portion of the waveform shape is processed for amplitude and phase using a first signal processing element that is external to the multiple write controllers, and a unique portion of the waveform signal is processed using a second signal processing element that is local to a write controller of the multiple write controllers.

[0019] In one embodiment, the qubit array is divided into groups, with each group containing a diverse set of qubit center frequencies such that cross-talk between adjacent qubits is reduced.

[0020] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0021] The drawings are of exemplary embodiments. They do not show all embodiments. In addition, or instead, other embodiments may be used. Details that may be obvious or unnecessary may be omitted to save space for a more effective illustration. Some embodiments may be practiced with additional components or steps, or without all components or steps shown, or both. When the same reference numeral appears in different drawings, it refers to the same or similar components or steps. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 illustrates an exemplary architecture of a quantum computing system in accordance with an exemplary embodiment. [Diagram 2] FIG. 1 illustrates a qubit system having three main components, according to an exemplary embodiment. [Figure 3A] A diagram showing a conventional qubit architecture. [Figure 3B] FIG. 1 illustrates standard control and readout hardware. [Figure 4] FIG. 1 is a block diagram of a dynamic range and power optimized programmable qubit array for quantum computing in accordance with an illustrative embodiment. [Figure 5A] FIG. 1 shows example waveforms for a conventional approach to communicating with qubits. [Figure 5B] FIG. 1 illustrates a more efficient approach to communicating with qubits, in accordance with an example embodiment. [Figure 6] FIG. 1 is a conceptual block diagram of a dynamic range and power optimized programmable array for quantum computing, in accordance with an illustrative embodiment. [Figure 7] FIG. 2 illustrates a low power single sideband write controller in accordance with an example embodiment. [Figure 8] FIG. 1 illustrates a low power single sideband write controller system in accordance with an exemplary embodiment. [Figure 9] 1 is a block diagram of an example frequency plan for qubits of an array of qubits based on their center frequencies in accordance with an example embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Overview In the following detailed description, numerous specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, or circuitry, or combinations thereof, have been described at a relatively high level, without detail, to avoid unnecessarily obscuring aspects of the present teachings.

[0024] The present disclosure relates generally to superconducting devices and, more particularly, to power-efficient and scalable qubit architectures. Electromagnetic energy associated with a qubit can be stored in so-called Josephson junctions, as well as in the capacitive and inductive elements used to form the qubit. In one example, to read out the state of the qubit, a microwave signal is applied to a microwave readout cavity that couples to the qubit at the cavity frequency. For example, the qubit can be directly excited by an electrical waveform having a predetermined amplitude, phase, and frequency. The frequency of the excitation waveform can be the resonant frequency of the qubit, and the shape of the waveform could be Gaussian, or a set of derivatives thereof. Each qubit can also be excited by another qubit that is weakly coupled to it using a capacitive mechanism.

[0025] The transmitted microwave signal passes through multiple thermal isolation stages and low-noise amplifiers used to block or reduce noise and improve the signal-to-noise ratio. Much of the process is carried out in a cryogenic environment (e.g., in a cryogenic chamber), while the qubit's microwave signal is finally measured at room temperature. The amplitude and / or phase of the returned / output microwave signal conveys information about the state of the qubit, such as whether the qubit has dephasised to a ground or excited state. The microwave signal that conveys quantum information about the qubit state is usually weak (e.g., on the order of a few microwave photons). To measure this weak signal with room-temperature electronics (i.e., outside the cryogenic environment), low-noise quantum-limited amplifiers (QLAs), such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs), can be used as preamplifiers (i.e., first amplification stages) at the output of the quantum system to boost the quantum signal while adding a minimal amount of noise dictated by quantum mechanics to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, certain Josephson microwave components that use Josephson amplifiers or Josephson mixers, such as Josephson circulators, Josephson isolators, and Josephson mixers, can be used in scalable quantum processors.

[0026] The ability to include more qubits is important to making the potential of quantum computers possible. In order for quantum processors to function, a reduction in the temperature of the computing environment to cryogenic temperatures is used. Generally, as the temperature is reduced, performance improves, for example, by reducing the number of qubits remaining in thermally excited states and by reducing the thermal spread of qubit transition frequencies. Thus, the lower the temperature, the better for the performance of the quantum processor.

[0027] Applicants have realized that improvements can be made in two main aspects to increase the computational power and reliability of quantum computers. The first is the number of qubits themselves. The more qubits in a quantum processor, the more states can in principle be manipulated and stored. The second is a lower error rate. This concerns precisely manipulating the states of the qubits and performing sequential operations that provide consistent results, not simply unreliable data. Therefore, to improve the fault tolerance of quantum computers, a large number of physical qubits must be used to store logical qubits. In this way, local information is delocalized, which makes the quantum computer less susceptible to local errors, and as a result, the performance of measurements in the eigenbase of qubits, similar to parity checks in classical computers, improves for more fault-tolerant qubits.

[0028] Exemplary Architecture FIG. 1 illustrates an exemplary architecture 100 of a quantum computing system, according to an exemplary embodiment. Architecture 100 includes a qubit array 112 that includes a plurality of qubits 114. Qubit array 112 is disposed within a refrigeration unit 110, which may be a dilution refrigerator. The refrigeration unit may also house a control circuitry block 113, sometimes referred to herein as a second set of control electronics. For example, control circuitry block 113 may be configured to provide various functions, such as performing write and / or read operations on one or more qubits in qubit array 112. In one embodiment, control circuitry block 113 is also configured to provide power management for the control circuitry and read circuitry of control circuitry block 113, as described in more detail in FIG. 6.

[0029] It should be noted that it is difficult to implement a bandgap reference system in such a zone due to the temperature characteristics at the second controlled temperature. Thus, in one embodiment, the bandgap reference system is implemented at room temperature (T1), while other parts of the power management system (such as voltage-to-current converters, voltage or resistance (V / R) or other custom current generators) are implemented at low T by using a bandgap reference signal implemented at room temperature. Thus, by using such partitioning of the power management system, the architecture described herein can achieve a high precision bandgap reference while providing a low noise power management system by providing a substantial portion of the power management circuitry in the cryogenic environment at the second controlled temperature (T2).

[0030] In one embodiment, refrigeration unit 110 may have multiple chambers or regions, each with a different controlled temperature. For example, control circuit block 113 may be at a controlled temperature that is between 1K and 4K, while qubit array 112 is at a controlled temperature of 240mK or below. Dilution refrigerators are cryogenic devices that provide continuous cooling down to temperatures as low as 2mK. Most of the physical volume of architecture 100 is due to the large size of refrigeration unit 110. The best performance for the qubits can be obtained at the lowest temperature. However, due to thermodynamic efficiency, the lowest temperature cannot be easily achieved in one step from room temperature. In this regard, applicants have determined that it is energy inefficient to operate the auxiliary electronics at 240mK, and therefore they are not placed in the third controlled temperature environment (T3), but are instead placed in the second controlled temperature environment (T2). The coolant / agent used in each of these temperature ranges (e.g., liquid nitrogen at 77K, liquid He for 4K and below) may also be different.

[0031] In one embodiment, the refrigeration unit 110 may use liquid helium as a coolant to reach the near absolute zero temperatures at which the system operates. For example, a "dry" refrigeration unit may operate using two gas-sealed cycles: one with He-4 that brings the refrigerator down to 3K (the "pulse tube" cycle), and the other with a He-3 / He-4 mixture that brings the refrigerator down to 10mK or the lowest temperature (the "dilution" cycle). The only liquid in the system is inside the refrigerator, where the He-3 / He-4 mixture condenses.

[0032] There is a measurement and control unit 130, sometimes referred to herein as the first set of control electronics, that is external to the refrigeration unit 110. For example, the measurement and control unit 130 may operate at room temperature. The measurement and control unit 130 may also communicate with the quantum processor through an opening 116, sometimes referred to as the bulkhead of the dilution refrigerator 110, which also forms an airtight seal that separates the ambient atmospheric pressure from the vacuum pressure of the cryostat during operation. A practical challenge with known refrigeration devices that house qubits 114 is that the number of qubits that can be stored within the refrigeration unit is limited due to the number of wires between the measurement and control unit 130 and the qubits 114 that are measured by it.

[0033] As the number of qubits in qubit array 114 increases, e.g., from 53 qubits to hundreds, thousands, or more, opening 116 may not be large enough to accommodate all of the lines (e.g., electrical wires) 120 supporting qubit array 112 in dilution refrigerator 110. Stated another way, access to the vacuum environment of dilution refrigerator 110 is limited to the number of connectors that can fit through bulkhead opening 116.

[0034] Thus, in one aspect, provided herein is an architecture that significantly reduces the number of wires 120 between measurement and control unit 130 and qubit array 112 housed within a refrigerated environment. In one embodiment, the number of wires 120 is reduced to approximately ten (e.g., power management interface, clock interface, instrumentation interface, digital interface, etc.), regardless of the size of qubit array 112.

[0035] Reference is now made to Figure 2, which illustrates a qubit system 200 having three main components separated into three different temperature zones: (i) a first set of control electronics 202 (representing measurement and control electronics 130 in Figure 1) operated at a first temperature (e.g., room temperature), (ii) a second set of control electronics 204 (representing control unit 113 in Figure 1) operated at a second temperature (e.g., 1K-4K), and (iii) a qubit array 206 (representing qubit array 112 in Figure 1) operated at a third temperature lower than the second temperature (e.g., 240mK). In one embodiment, the second set of control electronics is in complementary metal oxide semiconductor (CMOS) technology.

[0036] There is a first set of interconnects 203 between the first and second sets of control electronics operable to at least one of control, monitor or provide one or more reference signals, including at least one of a voltage reference, a current reference or a clock reference, that do not scale with the number of qubits in qubit array 206. There is a second set of interconnects 205 between the second set of control electronics 204 and qubit array 206 operable to at least one of monitor or provide dynamic signals to one or more qubits of the qubit array, with one interconnect in the second set of interconnects for each of the one or more qubits of the qubit array.

[0037] Such partitioning and interconnection of different circuit components results in advantageous utilization of electronic devices 202 and 204 to maximize the dynamic range per unit power consumption of system 200.

[0038] Referring again to FIG. 1, in one embodiment, the measurement and control electronics 130 includes digital I / O. It may further include a power management unit (PMU) that includes one or more bandgap references and reference currents. The control circuit block 113 may include one or more integrated circuits maintained at cryogenic temperatures that provide high fidelity signals to the qubits 114 in the qubit array 112. Many parts of the control circuit block provide superior performance at cryogenic temperatures, which results in significant power reduction in the control circuit block 113. For example, parts of the control circuit may include an arbitrary waveform generator, clock circuitry, mixers, output drivers, etc. At cryogenic temperatures, the mobility of the transistors is increased, the on-resistance of the transistors is reduced, and thermal noise is reduced. Additionally, the conductivity of the substrate is reduced, which improves the quality factor of the inductors and favors reduced power consumption for the same performance compared to room temperature. Using this multi-temperature zone approach, signal communication between the measurement and control electronics block 130 and the control circuitry block 113 is accomplished using a significantly reduced number of connectors, thereby greatly simplifying aspects of the system design and instrumentation, such as fewer cables and component assembly. Additionally, this multi-temperature zone approach favors scalability of qubits 114 to large qubit array 112 systems. In one aspect, the interface from the measurement and control electronics block 130 to the control circuitry block 113 remains the same even when the number of qubits 114 is increased.

[0039] The first cryogenic temperature control circuit block 113 utilizes several approaches to implement low power and provide high fidelity signal communication to the qubits 114, which are described in more detail below. In one embodiment, the control circuit block includes a digital to analog converter (DAC) pair, a mixer pair, an attenuator, and an impedance matching network, which are described in more detail below.

[0040] Exemplary Block Diagram To understand the features of the present disclosure, it may be helpful to contrast them with known techniques. To that end, FIGS. 3A and 3B show a conventional qubit architecture 300A and standard control and readout hardware 300B, respectively. As shown in FIG. 3A, there are three main operating temperatures, including software and control logic 304 at room temperature, first control layer 306 at 3K, and qubit chip 308 at 10 mK. Architecture 300A consumes a significant amount of power and requires numerous interfaces between control logic 304 and cryogenic environments 306 and 308, thereby hindering scalability. For example, each digital-to-analog converter (DAC) consumes a significant amount of power and is not scalable at room temperature. In this regard, it is noted that power is proportional to the dynamic range, which is related to the signal-to-noise ratio. For the same signal, thermal noise scales proportionally to absolute temperature, thereby improving the signal-to-noise ratio at low temperatures for the same signal amplitude. Thus, achieving a similar signal-to-noise ratio at room temperature would require much higher power consumption.

[0041] In contrast to the known architectures of Figures 3A and 3B, the teachings herein provide, in various embodiments, one or more of: (i) a lower sampling frequency of the DAC resulting in a substantial reduction in power consumption; (ii) an increase in dynamic range per milliwatt of power consumed by using a number of system / circuit / algorithmic approaches described herein (e.g., combining waveform features of the waveforms used to excite each qubit and providing common features using a low-power waveform generator); and (iii) built-in calibration for improved dynamic range by processing the DAC signals in current mode. For example, each block may use built-in self-calibration. Stated another way, each block may include its own independent signal analysis procedure to ensure that it consumes a minimal amount of power.

[0042] Reference is now made to FIG. 4, which is a block diagram of a dynamic range and power optimized programmable qubit array for quantum computing, according to an exemplary embodiment. System 400 includes multiple clusters of qubits 402(A)-402(D). The advantageous clustering is described in more detail below. The system includes a local channel low power phased locked loop (PLL), such as 416, for each write / read channel controller 410. There is a common reference clock for the entire system 400. There are digital control blocks, such as 420, that may be shared between the clusters. Each group of local channel low power PLLs receives a signal from the reference clock via its corresponding buffer.

[0043] As shown in FIG. 4, architecture 400 provides an arrangement for multiple channels of a qubit array. Each write / read controller (e.g., 410) provides band-limited single-sideband pulses for a single qubit. Each WR / RD channel controller interfaces with its corresponding qubit to provide write pulses and read state information of the corresponding cluster. Signal processing is performed using CMOS transistor level circuitry. In contrast to architecture 400, existing approaches utilize direct digitization of signals. For example, a digital-to-analog converter is responsible for providing the frequency shift in addition to the specific waveform used to communicate with each qubit. Traditional approaches result in the generation of a unique waveform used to control each qubit, typically with a center frequency of 4-8 GHz. In traditional approaches, both the waveform and the specific frequency offset are realized using a digital-to-analog converter, which uses higher currents.

[0044] For example, a digital-to-analog converter may provide a 100 MHz signal, placed at a 450 MHz offset relative to its center. The highest bandwidth of the signal is therefore 450+0.5*100=500 MHz. According to the Nyquist sampling theorem, the clock frequency must be at least 1000 MHz (i.e., twice the signal bandwidth). If this offset did not exist, then the bandwidth would only be 100 MHz, and a 200 MHz clock would have been sufficient. Therefore, for the same bandwidth (i.e., the information content of the signal), the frequency offset results in higher power consumption. To provide the desired resolution of the DAC (e.g., 12-14 bits), a higher power DAC and a higher sampling frequency are required. Typically, a higher resolution DAC implies a large number of channels to be communicated between the cryogenic chamber and the control logic outside the cryogenic chamber (e.g., room temperature). Alternatively, there could be one channel with a large fan-out for all qubits. Neither of these is the optimal choice for power, area, and scalability for a quantum system.

[0045] In contrast to known architectures, the teachings herein provide signals that are much smaller bandwidth in baseband and upconvert them using various offset frequencies generated from a local PLL. Using the previous example, a 100MHz bandwidth is provided at an offset of 450MHz, or 100MHz with no offset. In one aspect, the teachings herein prevent wideband digitization using high power and are more suitable for low temperature. In one embodiment, a zero or low frequency offset implementation for the DAC is used, and a mixer is used to move information from one frequency to another. For example, there are two ways to obtain a 100MHz signal around a center frequency of 5.5GHz. In the first approach, the signal is digitized up to 1GHz and upconverted using a mixer with a local oscillator (LO) frequency of 6.5GHz. In the second approach, the signal is digitized up to 200 MHz and either a 5.7 GHz LO (lower sideband, 5.7-0.2=5.5 GHz) or a 5.3 GHz LO (upper sideband, 5.3+0.2=5.5 GHz) is used. The use of mixers therefore reduces the clock frequency used in the digital-to-analog converter, reducing power consumption.

[0046] The room temperature electronics and the cryogenic electronics in the cryogenic chamber interface with very few wires. For example, in one embodiment, the DAC is implemented with low power consumption, so it can be in the cryogenic environment T2, and very few interconnects / cables need to be provided between the first temperature zone T1 and the cryogenic chamber. All components of the WR / RD controller are integrated in the control circuit block 113 in the cryogenic environment 110, thereby eliminating a large number of wires between the cryogenic environment and the first set of control electronics at room temperature.

[0047] Reference is now made to FIG. 5A, which illustrates an exemplary waveform 500A of a conventional approach in communicating with a qubit. Each trapezoid represents a center frequency of a qubit, which may be between 4.5 GHz and 5.5 GHz. Therefore, there is a wide range of resonant frequencies for different qubits. With today's technology, the center frequency Fc of a qubit cannot be known precisely. Qubit technology is still in its infancy, and it is a challenge to develop a qubit with a predetermined frequency with high precision. For example, in some scenarios, consistent fabrication of a qubit to have a center frequency of 5.20 GHz cannot be repeatedly achieved.

[0048] Typically, there is a center frequency, such as 5 GHz, and the frequency offset is achieved in the digital domain. In this case, the center frequency offset (e.g., the difference between the midpoints of the trapezoid) and the information content of the signal (e.g., the width of the trapezoid) are combined (e.g., the two waveforms are multiplied) to provide the required center frequency of each qubit. The high power consumption is caused by the fact that the frequency offset results in higher frequency components to be digitized. In principle, digitization consumes more power than lesser digitization and subsequent mixing, as will be explained below in the context of FIG. 5B.

[0049] In contrast, Figure 5B illustrates a more power-efficient approach to communicating with qubits, in accordance with an exemplary embodiment. Each qubit can be measured to determine what frequency can be used to excite the qubit (e.g., 5.27 GHz). This determination can be used to logically group the qubits, as described herein. In other scenarios, when the center frequencies of the qubits are more easily controlled during fabrication, the qubits can be physically grouped, as described herein.

[0050] Once the center frequency of each qubit in the qubit array is determined, the qubit array is divided into different groups, each group containing the most diverse set of center frequencies of qubits. In this way, signals can be provided to each qubit with better fidelity and less interference. For example, an array of 16 qubits may contain four qubits with a center frequency of 4 GHz, four qubits with a center frequency of 5.5 GHz, four qubits with a center frequency of 6 GHz, and four qubits with a center frequency of 7 GHz. The 16 qubit array may be divided into groups of four, each having a qubit with a center frequency of 4 GHz, 5.5 GHz, 6 GHz, and 7 GHz. In this way, interference between the qubits is significantly reduced. In various embodiments, the groupings described herein can be logical groupings (based on determining the center frequencies of each of the qubits in the array, while the qubits are in different locations on the chip) or physical groupings, where the qubits are specifically configured to have a predetermined center frequency. The latter is becoming increasingly more prominent as qubit fabrication technology improves.

[0051] In the architecture associated with waveform 500B, two mixers 516 and 518 are used. The two mixers 516 and 518 are used to create different combinations of frequencies, including their sums and differences. In this way, power is conserved.

[0052] FIG. 6 is a conceptual block diagram of a dynamic range and power optimized programmable array for quantum computing, according to an exemplary embodiment. System 600 includes components that operate at three different temperatures. In an exemplary embodiment of system 600, a first set of control electronics 630 operates at a first temperature, which may be at room temperature. For example, the first set of control electronics 630 represents the measurement and control electronics 130 of FIG. 1. The remaining components are at different levels of cryogenic temperature. In one embodiment, read controller (RXIQ) 640 is part of the control circuitry block that is operated at a first cryogenic temperature (e.g., 1-4K), sometimes referred to herein as the second control temperature. Block 608 provides clock sources for phase reference frequencies that are in-phase (I) and in quadrature (Q). It includes a phase-locked loop (PLL) coupled to a divider network (e.g., divide by 2). The write and read controllers require quadrature clocks, therefore a divide-by-two circuit is used to provide frequency division and quadrature generation with a 50% duty cycle.

[0053] The second control temperature includes various components shown in block 602, except for qubit array 650, which is operated at a third control temperature (e.g., 240 mK) lower than the second control temperature (e.g., 1 K-4 K). For example, the second control temperature may include a phase-locked loop (PLL) or delay-locked loop (DLL) 606, and a power management unit 604, a write controller 660 for each qubit of qubit array 650. There may be a clock source 610 coupled to PLL / DLL block 606. There may be a single low power and low jitter oscillator 668. There may be a buffer 670 coupled between PLL / DLL block 606 and write controller 660. Additional components may be present as shown in FIG. 6. It will be understood that the components of block 602 are presented by way of example only and not by way of limitation. Alternative and additional components may also be used within the second control temperature.

[0054] Reference is now made to Figures 7 and 8, which show a controller system having a low power single sideband write controller 700 and multiple write controllers 800, in accordance with an exemplary embodiment. Figures 7 and 8 are substantially similar, with the primary difference being that Figure 8 shows multiple write controllers 802(1)-802(N). For brevity, the primary discussion will be with respect to Figure 7, while it will be understood that similar concepts also apply to Figure 8.

[0055] In FIG. 7, the write controller has a programmable output amplitude and provides a low jitter output. In one embodiment, the jitter is less than 100 fsec. The write controller 700 has a quadrature architecture in that it provides an in-phase input channel I and a quadrature input channel Q offset by 90 degrees, each of which is received by a retimer (R) 704. Each channel is provided to a corresponding DAC 706A / B. In one embodiment, each DAC 706A / B is current mode. Each DAC 706A / B provides a "unique" portion of the waveform to a corresponding qubit. With regard to the term "unique," consider, by way of example, that there are five waveforms, X1, X2, X3, X4, and X5, each of which differs in its envelope shape but is otherwise similar. In this case, the unique portion of the waveform is given as the average of these N waveforms. This implies that the unique part is given by Xu=0.2*sum(X1:X5) and the DAC per channel represents the difference in the waveforms, Xdi=Xi-Xu, where i=1:1:5.

[0056] In one embodiment, DACs 706A and 706B are programmable for dynamic range using at least one of parameters related to sampling rate (e.g., speed), resolution (e.g., number of bits), and supply voltage (e.g., affecting the selection of an analog current source implementation).

[0057] Each write controller 802(1)-802(N) in FIG. 8 provides signals to the qubits. To ensure substantially similar arrival times of the signals to the individual qubits, all write controllers 802(1)-802(N) use a single clock from a single PLL. The first block in the write controller includes a digital-to-analog converter (DAC) for each in-phase (I) and quadrature-phase (Q) path (i.e., DACS 706A and 706B), which converts a digital representation of the waveform received at their corresponding input to a representative analog waveform. In addition to providing a baseband analog representation of the signal, each DAC 706A / B can provide an analog signal centered on a low intermediate frequency. For example, DAC 706A can provide a signal with a bandwidth of 100 MHz at a frequency offset of 450 MHz. This suggests that the signal occupies frequency components between 400 and 500 MHz. In this process, there are clock spurious tones that should be filtered out using a baseband filter. Thus, each write controller 802(1)-802(N) includes a first signal processing element (e.g., 706C and 706D) configured to process the common portion of the waveform shape for amplitude and phase, and a second signal processing element (e.g., 706A and 706B) configured to process the portion that is qubit-specific. In the example of FIG. 8, these processing elements are shown as DACs 706A-706D.

[0058] The clean signal after the baseband filter (e.g., 708A / B) is provided to a mixer (e.g., 710A-D), which upconverts it to the desired frequency of the qubits. After upconversion, a programmable gain function (e.g., 712A-D) provides the appropriate amplitude to the qubits. During the process of digital-to-analog conversion, various Nyquist-mapped frequencies are also generated in the system, which should be filtered out using a baseband filter. The bandwidth f BB , and f SFor a signal with a sampling clock frequency of m, the Nyquist map term is m*f S ±n*f BB where m and n are integers such that {m,n}={1,2,...}.

[0059] In the mixing process, both single sideband mixing and double sideband mixing can be obtained. An example of double sideband mixing is given by Equation 1 below: Y=G*A BB *cos(ω BB t)*cos(ω LO t)=G*A BB *{cos(ω LO +ω BB )t+cos(ω LO -ω BB )t}. (Formula 1) where: G is the gain of the mixer, A BB represents the amplitude of the baseband signal at the mixer input.

[0060] Therefore, in double sideband, the frequency components, (ω LO +ω BB ), and (ω LO -ω BB ) are both present. To reduce the bandwidth, a single sideband can be used, using both in-phase and quadrature phase from the baseband and LO, respectively, resulting in the following output given in Equation 2 below: Y LSB =G*A BB [cos(ω BB t)*cos(ω LO t)+sin(ω BB t)*sin(ω LO t)]=G*A BB *cos(ω LO -ω BB )t. (Formula 2)

[0061] Another implementation is given by the relationship in Equation 3 below: Y LSB =G*A BB [-sin(ω BBt)*cos(ω LO t)+cos(ω BB t)*sin(ω LO t)]=G*A BB *sin(ω LO -ω BB )t. (Formula 3)

[0062] The resulting frequency (ω LO -ω BB ) is the LO frequency ω LO Since θ is lower than θ, the relationship in Equation 3 above is the lower sideband. Similarly, by rearranging the phases, the upper sideband can also be implemented as given by Equation 4 below: Y USB =G*A BB [sin(ω BB t)*cos(ω LO t)+cos(ω BB t)*sin(ω LO t)]=G*A BB *sin(ω LO +ω BB )t. (Formula 4)

[0063] Another implementation of the upper sideband is given by Equation 5 below: Y USB =G*A BB [cos(ω BB t)*cos(ω LO t)-cos(ω BB t)*cos(ω LO t)]=G*A BB *cos(ω LO +ω BB )t. (Equation 5)

[0064] Thus, by using both the upper and lower sidebands, twice the frequency range can be achieved compared to simply using one of the sidebands. For example, (ω LO ±ω BB A system that would be able to provide both frequencies (ω LO +ω BB ) (upper sideband) and (ω LO -ω BB) (lower sideband) compared to systems that can only provide 2ω BB over a frequency range of

[0065] In one embodiment, each output of the DACs 706A / B is filtered by an anti-aliasing filter 708A / B, sometimes referred to herein as a programmable integrated filter. Each filter 708A / B is programmable for gain, bandwidth, and supply voltage.

[0066] The output of the filter 708A is mixed (710A) with a corresponding local oscillator signal (e.g., LO2-I and LO2-Q, respectively), which may be summed or subtracted based on the desired center frequency. In one embodiment, each integrated multiplier 710A / B is programmable for single sideband versus double sideband. Between these two modes, the integrated multiplier 710A / B provides signal conditioning and gain steps. In various embodiments, each integrated multiplier 710A / B may be configurable for upper and lower sidebands, or provide either upper and lower sidebands, or both. In one embodiment, two separate multiplier mixers are used to obtain the upper and lower sidebands separately. One of these sidebands is selected for output with low latency.

[0067] The output of the arithmetic operation may be provided to a programmable gain amplifier (PGA) block 714. The programmable gain amplifier 714 is configured to process the unique portion of the waveform shape for amplitude and phase to excite the qubit. For example, instead of arranging the PGAs 714 as in FIG. 7, in one embodiment, one PGA may be coupled to each of the mixers, as shown by PGAs 714A and 714B in FIG. 8, after the full mixing operation is performed. Thus, a vector addition may be performed by each write controller 802(1)-802(N), as given by way of example by Equation 6 below: Y = αXi + βXq (Equation 6) where Xi and Xq are quadrature signals that are 90 degree phase shifted versions of each other.

[0068] There is a linear driver 716 coupled to the output of the PGA 714 that provides additional drive and is operable to digitally enable / disable different stages of the driver 718. In some embodiments, the PGA 714 can be implemented using a single circuit whose output signal is provided to a driver that includes N stages, M of which are biased at different current levels that are selected using digital control, or a switchable array of cells inside the PGA 714 that scales the input signal and is digitally programmed. There is a matching network (MN) 718 to provide maximum power transfer to a load (i.e., a DUT or qubit) coupled to the output of the linear driver 716.

[0069] It is noted that qubits generally use two types of waveforms to be excited: (i) symmetric Gaussian, and (ii) Derivative Removal by Adiabatic Gate (DRAG) framework. DRAG is a multi-transition variant of anti-adiabatic drive, where multiple low-lying gap states in the adiabatic evolution can be avoided simultaneously, greatly reducing computation time compared to the adiabatic limit. A DRAG pulse can be considered as a maximally Gaussian pulse with an additional perturbation. If all qubits in an array of qubits use the same waveform, only one programmable DAC can be used, which can be shared among the N qubits, resulting in reduced power consumption. A common shared DAC (e.g., with reconfigurable resolution (e.g., number of bits) and power consumption) can provide the maximally Gaussian shape. Such a DAC can be current mode. In one embodiment, the DAC includes two parts: (i) an array of current sources, and (ii) a set of digital decoders for activating those current sources, in the context of a current-steering DAC, where the unit element of the signal is a current. Two exemplary implementations of the reconstruction described herein can be implemented. The first approach involves maintaining the same resolution (e.g., number of bits) and the full-scale current of the DAC can be adjusted. This approach results in a change in the total output current, reducing power consumption by reducing the total current through the analog part.

[0070] The second approach involves maintaining the same full-scale current level (i.e. the maximum current the DAC can provide when all current sources are on) at which the number of bits in the DAC can be adjusted. The second approach results in the adjustment of the current consumption of the digital and analog parts.

[0071] In one embodiment, the per-channel DACs 706 can be independently programmed with a common (e.g., shared) DAC. For example, there is a common DAC 706C for the in-phase signal and a common DAC 706D for the quadrature-phase signal. These signals are shared among multiple write controllers 802(1)-802(N). The total baseband current is obtained as the sum of the common shared DAC and the unique, per-channel DAC (e.g., 708A and 708B), and the sum is provided to the mixer for up-conversion.

[0072] In one embodiment, each cluster of integrated circuit processing elements (e.g., in each write controller 802(1)-802(N)) shares the same clocking element (e.g., PLL 724) 724. For each cluster of integrated circuit processing elements 802(1)-802(2), including components 704, 706A / B, 708A / B, 710A-D, 712A-D, 714A / B, 716, 718, and 720, that share multiple clocking elements, multiple clock references are switched into the internal clock receiver and quadrature generator block 722 of a unique signal channel.

[0073] In one embodiment, each integrated circuit signal processing element 802(1)-802(N) includes a programmable digital-to-analog converter (DAC) 706A and 706B for processing an in-phase signal (I) and / or a quadrature-phase signal Q. There is a programmable integration filter 708A coupled to the in-phase DAC 706A, and a programmable integration filter 708B coupled to the quadrature-phase DAC 706B. There is a programmable integration multiplier 710A coupled to the in-phase analog filter 708A. The programmable integration multiplier 710B is coupled to the quadrature-phase analog filter 708B. The programmable integration multiplier 710C is coupled to the quadrature-phase analog filter 708C. The programmable integration multiplier 710D is coupled to the quadrature-phase analog filter 708D. A variable gain attenuator (e.g., 712A-D) is configured to scale the signal output from the corresponding mixer (e.g., 710A-D). There are programmable combiners (e.g., 714A, and 714B) configured to combine signals from each in-phase (I) and quadrature (Q) path and from in-phase and quadrature-phase multipliers 710A and 710B to create single sideband signals for the lower sideband (LO-RF) and upper sideband (LO+RF). A low latency selection element 716 selects between the upper sideband signal and the lower sideband signal and provides it to a final driver 718. The final driver 718 is configured to provide a signal to a matching network element 720. In an alternative embodiment, the matching network 720 is shared between the channels (i.e., write controllers 802(1)-802(N)), thereby saving further area and power.

[0074] In one embodiment, baseband filters 708 in FIG. 7 (and baseband filters 708A / B in FIG. 8) may each be implemented as a low-power baseband filter per channel, while a medium-power baseband filter may be shared among all channels of write controllers 802(1)-802(N) to reduce power consumption.

[0075] A tunable network element, sometimes referred to herein as matching network 720, is configured to provide maximum power transfer between each write controller 802(1)-802(N) and its corresponding qubit, represented by Qx-Qk in FIG. 8.

[0076] In one embodiment, the qubit array includes multiple clusters, each cluster arranged to provide maximum separation of resonant frequencies to minimize cross talk between adjacent clusters. In this regard, reference is made to FIG. 9. FIG. 9 is a block diagram of an example frequency plan of qubits in an array of qubits based on their center frequencies, according to an example embodiment. This equally spaced concentric hexagonal arrangement provides an equal amount of physical separation between each qubit and its neighbors. Each box in the array 900 represents a qubit. Each box pattern represents a unique center frequency for a qubit. A predetermined physical distance is maintained to minimize cross talk between different qubits. The distance between qubits having similar center frequencies is maximized. In this manner, deterministic cross talk between qubits is reduced.

[0077] In an embodiment where the fabrication process is more controlled and the center frequency is configurable, the center frequency may be set by the fabrication process itself. In other scenarios where the fabrication process cannot predetermine the exact center frequency of the qubits, the groupings described herein are logical (i.e., not physical) groupings. For example, the determination of the center frequency is accomplished by providing a waveform of a particular amplitude at a certain frequency and enabling readout circuitry (e.g., 640 in FIG. 6). Mechanisms for adjusting the center frequency of a qubit include flux-coupled arrangements, where an additional magnetic field is superimposed on the qubit under consideration.

[0078] For example, the determined center frequencies of the qubits are used to group the qubits. More specifically, the center frequency of each qubit in the qubit array is determined and the qubit array is logically divided into different groups, each group containing the most diverse set of qubit center frequencies.

[0079] The pattern of each box representing a qubit dictates a different center frequency. In an embodiment where the fabrication process is more controlled and the center frequency can be precisely defined, the qubits can be spatially arranged to provide minimal interference to adjacent and second-neighboring qubits. This improves the fidelity of the computation. In this way, signals can be provided to each qubit with better fidelity and less interference. Thus, the qubit chip implements the qubits in a spatial manner to minimize cross talk between the qubits and provide signal fidelity. The arrangement can follow the uniform spatial arrangement of the qubit resonator. Each qubit is equidistantly separated from its neighbors. For example, if a qubit Qn is surrounded by multiple qubits QA, QB, QC, QD, and QE, the interference terms between each pair of {Qn, Qx}, x=A, B, C, D, E remain the same. Therefore, it is sufficient to transmit only one cancellation term (e.g., a copy of the main signal) when the qubit Qn is in the active state. Thus, if the desired signal is Yqn, then the cancellation term is given as α*Yqn. This term (signal=α*Yqn) is sent to each of Qx and summed with the respective Qx signal to cancel the x-talk effect resulting from spatial interference of Qn.

[0080] Considering the circular arrangement contour for static reciprocal cancellation in Fig. 9, such an arrangement leads to deterministic signal coupling that can be easily cancelled in the current domain since the x-talk is a static component. Another advantage of this arrangement relates to the fact that only one term is sufficient to cancel the cross-talk across the entire array (since the spatial distance between any two frame patterns is constant across the qubit array). Such an arrangement facilitates a cross-talk cancellation term that can be implemented in the current mode to preserve linearity.

[0081] Conclusion The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the above-described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

[0082] While the foregoing has described what is believed to be the best mode and / or other examples, it is understood that various modifications may be made therein, and that the subject matter disclosed herein may be embodied in various forms and examples, and that the present teachings may be applied in numerous applications, only a few of which have been described herein. It is intended by the appended claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0083] The components, steps, features, objects, benefits, and advantages described herein are merely exemplary. Neither them nor any description thereof is intended to limit the scope of protection. Although various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, orders, positions, dimensions, sizes, and other details described herein, including the appended claims, are approximate and not precise. They are intended to have a reasonable range consistent with the function to which they relate and that is common in the art to which they pertain.

[0084] Numerous other embodiments are contemplated, including embodiments having fewer, additional, or different, or combinations of components, steps, features, objects, benefits, and advantages, as well as embodiments in which the components and / or steps are arranged and / or ordered differently.

[0085] The call flows, flowcharts, and block diagrams in the drawings herein illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the drawings. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or acts or executes a combination of dedicated hardware and computer instructions.

[0086] While the foregoing has been described in connection with exemplary embodiments, it is understood that the term "exemplary" is intended merely as an example, not best or optimal. Except as stated immediately above, nothing described or shown is intended to, or should be construed as, providing the public with any component, step, feature, object, benefit, advantage, or equivalent, whether or not they are recited in the claims.

[0087] It will be understood that the terms and expressions used herein have the ordinary meanings given such terms and expressions with respect to their corresponding respective areas of inquiry and study, unless a specific meaning is otherwise stated herein. Relative terms such as first and second and the like may be used merely to distinguish one entity or action from another, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variations thereof are intended to encompass a non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements may include not only those elements, but other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by "a" or "an" does not, without further constraints, preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0088] An Abstract is provided to enable the reader to quickly grasp the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above Detailed Description, various features may be grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the appended claims reflect, inventive subject matter lies in fewer than all features of a single disclosed embodiment. Thus, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. 1. A quantum processing system, comprising: a first set of control electronics operating at a first temperature; a second set of control electronics communicatively coupled to the first set of control electronics and operating at a second control temperature lower than the first temperature, the second set of control electronics comprising: one or more circuits configured to perform a write operation on one or more qubits; and one or more circuits configured to perform a read operation on the one or more qubits; the second set of control electronics including: a qubit array including the one or more qubits and operating at a third control temperature lower than the second temperature, the qubit array being controlled by the second set of control electronics; and A quantum processing system comprising:

2. The quantum processing system of claim 1 , wherein the first temperature is at room temperature.

3. 3. The quantum processing system of claim 1, further comprising a first set of interconnects between the first and second sets of control electronics configured to at least one of control, monitor or provide one or more reference signals to the second set of control electronics, including at least one of a voltage reference, a current reference or a clock reference that does not scale with the number of qubits in the qubit array.

4. 4. The quantum processing system of claim 1, further comprising a second set of interconnects between the second set of control electronics and the qubit array configured to at least one of monitor or provide dynamic signals to the one or more qubits of the qubit array, wherein there is one interconnect in the second set of interconnects for each of the one or more qubits of the qubit array.

5. 5. The system of claim 1, wherein the second set of control electronics comprises a plurality of write controllers, each write controller comprising an independently programmable qubit control circuit.

6. 6. The system of claim 5, further comprising a first signal processing element configured to process a common portion of the waveform shapes for amplitude and phase, and each write controller includes a second signal processing element configured to process a portion that is specific to a qubit.

7. 7. The system of claim 6, wherein each independently programmable element of a write controller is configured to process a unique combination of amplitude and phase of a waveform shape for a corresponding qubit in the qubit array.

8. the first signal processing element includes a high resolution digital-to-analog converter; The system of claim 6 or 7, wherein the second signal processing element includes a low-resolution digital-to-analog converter having a lower resolution than the first signal processing element.

9. 9. The system of claim 1 , wherein the qubit array comprises a plurality of clusters, each cluster arranged to provide maximum separation of resonant frequencies of its corresponding qubits to minimize cross talk between adjacent clusters of the plurality of clusters.

10. 10. A system according to any preceding claim, wherein the second set of control electronics is in complementary metal oxide semiconductor (CMOS) technology.

11. 11. The system of claim 1, wherein the second set of control electronics is further configured to provide power management circuitry for the qubit array.

12. The system of any one of claims 1 to 11, wherein the second control temperature is a cryogenic temperature between 1 and 4 Kelvin.

13. 13. The system of claim 1, wherein the third control temperature is a cryogenic temperature of approximately 240 mK.

14. 14. The quantum processing system of claim 1, wherein the qubit array is divided into groups, each group containing a diverse set of qubit center frequencies such that cross talk between adjacent qubits is reduced.

15. 15. The system of claim 1, wherein at least one of the one or more circuits configured to perform the write operation includes two separate multiplier mixers for separately obtaining upper and lower sidebands.

16. 1. A method of controlling an array of qubits, comprising the steps of: operating a first set of control electronics at a first temperature; operating a second set of control electronics communicatively coupled to the first set of control electronics at a second control temperature lower than the first temperature, the second set of control electronics comprising: one or more circuits configured to perform a write operation on one or more qubits; and one or more circuits configured to perform a read operation on the one or more qubits; said operating comprising: operating a qubit array including the one or more qubits at a third controlled temperature lower than the second temperature, the qubit array being controlled by the second set of control electronics; A method comprising:

17. the first temperature is at room temperature; the second control temperature is a cryogenic temperature between 1 and 4 Kelvin; 17. The method of claim 16, wherein the third controlled temperature is a cryogenic temperature of approximately 240 mK.

18. providing a first set of interconnects between the first and second sets of control electronics for at least one of controlling, monitoring, or providing one or more reference signals to the second set of control electronics, including at least one of a voltage reference, a current reference, or a clock reference that does not scale with the number of qubits in the qubit array; providing a second set of interconnects between the second set of control electronics and the qubit array for at least one of monitoring or providing a dynamic signal to the one or more qubits of the qubit array, where there is one interconnect in the second set of interconnects for each of the one or more qubits of the qubit array; 18. The method of claim 16 or 17, further comprising:

19. processing the common portion of the waveform shapes for amplitude and phase with a first signal processing element external to the plurality of write controllers; processing the distinctive portion of the waveform signal with a second signal processing element local to a write controller of the plurality of write controllers; 19. The method of any one of claims 16 to 18, further comprising:

20. 20. The method of any one of claims 16 to 19, wherein the qubit array is divided into groups, each group containing a diverse set of centre frequencies of qubits such that cross talk between adjacent qubits is reduced.

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