Graded epitaxy buried contact

Abstract

A semiconductor device design is provided having a buried power rail with a graded epitaxy buried contact. In one aspect, the semiconductor FET device includes at least one gate disposed on a substrate, a source and a drain on either side of the at least one gate, where at least one of the source and drain has a graded surface, a buried power rail buried in the substrate, and a buried contact connecting the buried power rail to the graded surface of the at least one source and drain. A sidewall spacer separates the buried power rail from the substrate. The top of the graded surface of the at least one source and drain is above the top surface of the buried contact. A method of forming the semiconductor FET device is also provided.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device design having buried power rails, and more particularly to a semiconductor device design having buried power rails with a sloped epitaxy buried contact architecture for optimal contact resistance and low parasitic capacitance, and techniques for the fabrication thereof. [Background technology]

[0002] The continuous scaling of semiconductor device architectures presents some significant challenges in delivering power to semiconductor devices. Specifically, the size of the interconnect lines that deliver power to semiconductor devices can only be reduced to a degree that does not adversely affect device performance.

[0003] One approach to alleviating congestion in device designs is to embed the power rails that bring power to the semiconductor device within the substrate rather than placing them on top of the semiconductor device. Power rails configured in this manner are also referred to herein as "embedded power rails."

[0004] Although the buried power rail design frees up some overhead space above the device, conventional device designs still require relatively large contact structures to connect the buried power rails to the source and drain. These large contact structures result in large undesirable contact-to-gate parasitic capacitances.

[0005] Therefore, an improved semiconductor device design having buried power rails but with minimal parasitic capacitance would be desirable. Summary of the Invention

[0006] The present invention provides a semiconductor device design having a buried power rail with a graded epitaxy buried contact architecture for optimal contact resistance and low parasitic capacitance, and techniques for its fabrication. In one aspect of the present invention, a semiconductor field effect transistor (FET) device is provided. The semiconductor FET includes at least one gate disposed on a substrate, a source and a drain on either side of the at least one gate, where at least one of the source and drain has a graded surface, a buried power rail buried in the substrate, and a buried contact connecting the buried power rail to the graded surface of the at least one source and drain.

[0007] In another aspect of the invention, another semiconductor FET device is provided that includes at least one gate disposed on a substrate, a source and a drain on either side of the at least one gate, where at least one of the source and drain has an inclined surface, a buried power rail buried in the substrate below the inclined surface, a sidewall spacer separating the buried power rail from the substrate, and a buried contact connecting the buried power rail to the inclined surface of the at least one source and drain, where a top of the inclined surface of the at least one source and drain is above a top surface of the buried contact.

[0008] In yet another aspect of the invention, a method of forming a semiconductor FET device is provided, the method including forming a device structure having at least one gate disposed on a substrate, a source and a drain on either side of the at least one gate, and a buried power rail buried in the substrate, etching at least one of the source and drain to create a sloped surface along a portion of the at least one source and drain, and forming a buried contact connecting the buried power rail to the sloped surface of the at least one source and drain, wherein a top of the sloped surface of the at least one source and drain is above a top surface of the buried contact.

[0009] In yet another aspect of the present invention, another method of forming a semiconductor FET device is provided, the method including forming a device structure having at least one gate disposed on a substrate, a source and a drain on either side of the at least one gate, an interlayer dielectric (ILD) surrounding the at least one gate, and a buried power rail buried in the substrate, patterning a contact trench in the ILD to expose at least one of the source and drain, etching the at least one source and drain to create a sloped surface along a portion of the at least one source and drain exposed in the contact trench, performing epitaxial regrowth to form a surface dopant-semiconductor alloy contact layer on the sloped surface, and forming a buried contact in the contact trench connecting the buried power rail to the sloped surface of the at least one source and drain, wherein a top of the sloped surface of the at least one source and drain is above a top surface of the buried contact.

[0010] A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a top-down view of an overall semiconductor field effect transistor (FET) design presented herein with a device stack and a gate oriented orthogonal to the device stack, in accordance with an embodiment of the present invention. [Diagram 2] FIG. 1 is a cross-sectional view illustrating the formation of device stacks (e.g., a first device stack, a second device stack, etc.) on a substrate using a hard mask, taken through the device stacks between two of the gates in the source and drain regions of the devices, according to an embodiment of the present invention, each of the device stacks including a first sacrificial layer deposited on the substrate and alternating second sacrificial layers and active layers deposited on the first sacrificial layer. [Diagram 3] FIG. 1 is a cross-sectional view through a device stack between two of the gates in the source and drain regions of the device, showing that the substrate is recessed to form a trench in the substrate at the base of the device stack, and the device stack is embedded in a shallow trench isolation (STI) oxide filling the trench, according to an embodiment of the invention. [Figure 4] FIG. 1 is a cross-sectional view through the device stack between two of the gates in the source and drain regions of the device, illustrating a partial recess etch of the STI oxide in a trench between adjacent device stacks according to an embodiment of the invention. [Diagram 5] FIG. 13 is a cross-sectional view through the device stack between two of the gates in the source and drain regions of the device showing sidewall spacers formed along the sidewalls of the trench between adjacent device stacks at the base of the device stack in accordance with an embodiment of the present invention. [Figure 6]FIG. 1 is a cross-sectional view through a device stack between two of the gates in the source and drain regions of the device showing a buried power rail formed in a trench between sidewall spacers in accordance with an embodiment of the present invention. [Figure 7] FIG. 13 is a cross-sectional view through the device stack between two of the gates in the source and drain regions of the device showing an additional dielectric deposited in a trench above the buried power rail and recessed with the STI oxide in accordance with an embodiment of the invention. [Figure 8] FIG. 1 is a cross-sectional view through the center of one of the device stacks perpendicular to the gate showing a sacrificial gate and a sacrificial gate hardmask formed on the device stack, a dielectric spacer formed alongside the sacrificial gate hardmask and the sacrificial gate, and the sacrificial gate and dielectric spacer used as a mask to pattern a trench in the device stack between the sacrificial gates, according to an embodiment of the invention. [Figure 9] FIG. 1 is a cross-sectional view through the center of one of the device stacks perpendicular to the gate showing the first sacrificial layer being selectively removed and replaced with a bottom dielectric insulating layer, inner spacers being formed alongside the sacrificial layer, sources and drains being formed on either side of the active layer, and the sacrificial gate being surrounded by an interlayer dielectric (ILD) in accordance with an embodiment of the invention. [Figure 10] FIG. 1 is a cross-sectional view taken through the center of one of the device stacks perpendicular to the gate, showing a sacrificial gate being selectively removed to form a gate trench in the ILD, the sacrificial layer being selectively removed through the gate trench to form gaps between active layers, and depositing a conformal gate dielectric into each of the gate trenches and gaps to line them, in accordance with an embodiment of the invention. [Figure 11]FIG. 2 is a cross-sectional view taken through the center of one of the device stacks perpendicular to the gate, illustrating at least one work function setting metal deposited in the gate trench and gap on and in contact with the gate dielectric according to an embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view showing source and drain epitaxy on one side of a replacement metal gate in a device stack, and a bottom dielectric insulating layer isolating the source and drain from the substrate, taken through the device stack between two of the gates in the source and drain regions of the device, in accordance with an embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view through a device stack between two of the gates in the source and drain regions of the device, showing a contact trench patterned in the additional dielectric to expose at least a portion of at least one of the source and drain, according to an embodiment of the invention. [Figure 14] FIG. 13 is a cross-sectional view through a device stack between two of the gates in the source and drain regions of the device, illustrating that an etch has been used to create a downwardly sloping surface along the exposed portions of at least one source and drain in accordance with an embodiment of the invention. [Figure 15] FIG. 1 is a cross-sectional view through the device stack between two of the gates in the source and drain regions of the device showing an optional trench epitaxy layer grown on the exposed sloped surface in the contact trench according to an embodiment of the invention. [Figure 16] FIG. 1 is a cross-sectional view through a device stack between two of the gates in the source and drain regions of a device showing epitaxy amorphization implantation and rapid laser annealing along the sloped surface of at least one of the source and drain to lower contact resistance between the sloped surface of at least one of the source and drain and a buried metal contact according to an embodiment of the present invention. [Figure 17]A cross-sectional view through a device stack between two of the gates in the source and drain regions of the device, showing a buried contact formed in a contact trench connecting a buried power rail to an angled surface of at least one of the source and drain, in accordance with an embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view through the device stack between two of the gates in the source and drain regions of the device, illustrating the use of metallization techniques to complete the device structure in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] As mentioned above, the use of buried power rails can eliminate overhead congestion in semiconductor device designs. In a buried power rail design, the interconnects that deliver power to a semiconductor device are buried in the substrate beneath the device. However, traditional buried power rail designs still require relatively large contact structures above the source and drain to provide low contact resistance. As a result, a significant amount of contact-to-gate parasitic capacitance still exists.

[0013] Advantageously, provided herein is a semiconductor device design featuring a buried power rail for scaling benefits and a graded epitaxy buried contact architecture for optimizing contact resistance to the source and drain. Because the graded design minimizes contact resistance, the total footprint of the graded contact design can be desirably minimized to provide reduced contact-to-gate parasitic capacitance.

[0014] An exemplary method for forming a semiconductor field effect transistor (FET) device according to the present technology is described below with reference to FIGS. 1-18. In each of the following figures, a cross-sectional view through a portion of a semiconductor FET device is shown. See, for example, FIG. 1, which shows a top-down view of a general semiconductor FET device design, illustrating the orientation of various cuts through the device that will be depicted in each figure. With reference to FIG. 1, the present semiconductor FET device includes a device stack of sacrificial and active layers, and the gate of the semiconductor FET device is oriented perpendicular to the device stack. A sacrificial gate is shown in FIG. 1. Specifically, as described in more detail below, a replacement metal gate or RMG process is utilized herein, where these sacrificial gates act as placeholders during the formation of the source and drain, and are later replaced with a replacement metal gate. However, the orientation of the gate relative to the device stack is the same for both the sacrificial gate and the replacement metal gate.

[0015] As shown in FIG. 1, cross section X provides a view of a cut through the device stack between two of the gates at the source and drain regions of the device. Cross section Y provides a view of a cut through the center of the device stack perpendicular to the gate. For example, as shown in FIG. 2 (cross section X), the process begins with the formation of at least one device stack 212a, b, etc. on a substrate 202. According to an exemplary embodiment, the substrate 202 is a bulk semiconductor wafer, such as a bulk silicon (Si) wafer, a bulk germanium (Ge) wafer, a bulk silicon germanium (SiGe) wafer, or a bulk III-V semiconductor wafer, or a combination thereof. Alternatively, the substrate 202 can be a semiconductor-on-insulator (SOI) wafer. An SOI wafer includes an SOI layer that is separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide, it is referred to herein as a buried oxide or BOX. The SOI layer may include any suitable semiconductor, such as Si, Ge, SiGe, or III-V semiconductors, or combinations thereof. The substrate 202 may already have pre-built structures (not shown), such as transistors, diodes, capacitors, resistors, interconnects, wiring, etc.

[0016] According to an exemplary embodiment, the formation of the device stacks 212a, b, etc. includes first depositing the sacrificial and active layers on top of each other in a vertical orientation as a stack on the substrate 202, and then patterning the sacrificial / active layers into individual device stacks 212a, b, etc. using standard lithography and etching techniques. By way of example only, in one exemplary embodiment, the sacrificial and active layers are nanosheets formed as a stack on the substrate 202. The term "nanosheet" as used herein generally refers to a sheet or layer having nanoscale dimensions. Additionally, the term "nanosheet" is intended to encompass other nanoscale structures such as nanowires. For example, the term "nanosheet" may refer to a nanowire having a larger width, or the term "nanowire" may refer to a nanosheet having a smaller width, or vice versa.

[0017] In a standard lithography and etching process, a lithography stack (not shown), e.g., photoresist / organic planarization layer (OPL) / anti-reflective coating (ARC), is used to pattern the hard mask 210 with the footprints and locations of each of the device stacks 212a, b, etc. Suitable hard mask materials include, but are not limited to, nitride hard mask materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or oxide hard mask materials such as silicon oxide (SiOx), or both. Alternatively, the hard mask 210 may be formed by other suitable techniques, including, but not limited to, sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and other self-aligned multi-patterning (SAMP). An etch is then used to transfer the pattern from the hard mask 210 to the underlying stack of sacrificial and active layers. For the stack etch, a directional (anisotropic) etching process such as reactive ion etching (RIE) can be used.

[0018] As shown in FIG. 2, the device stack 212a, b, etc. specifically includes (first) sacrificial layers 204a, b, etc. deposited on the substrate 202, and alternating layers of (second) sacrificial layers 206a, b, etc. and active layers 208a, b, etc. deposited on the sacrificial layers 204a, b, etc. The term "sacrificial" as used herein refers to a structure that is removed in whole or in part during the fabrication of a semiconductor FET device. In contrast, the active layers 208a, b, etc. remain in place and act as channels for the semiconductor FET device. It should be noted that the number of sacrificial layers 206a, b, etc. and active layers 208a, b, etc. shown in the figures are provided merely as examples to illustrate the present technology. For example, embodiments are contemplated herein in which there are more or fewer sacrificial layers 206a, b, etc. or more or fewer active layers 208a, b, etc. than those shown, or both.

[0019] According to an exemplary embodiment, each of the sacrificial layers 204a, b, etc. and the sacrificial layers 206a, b, etc. / active layers 208a, b, etc. are deposited / formed on the substrate 202 using an epitaxial growth process. In one exemplary embodiment, the sacrificial layers 204a, b, etc. and the sacrificial layers 206a, b, etc. / active layers 208a, b, etc. each have a thickness of about 10 nanometers (nm) to about 25 nm and ranges therebetween.

[0020] As described above, the sacrificial and active layers are first blanket deposited / formed on the substrate 202 and then patterned into individual device stacks 212a,b, etc. As a result, based on this process, the sacrificial layers 204a,b, etc. will have the same composition and thickness in each of the device stacks 212a,b, etc., as will the sacrificial layers 206a,b, etc. and the active layers 208a,b, etc. The materials employed for the sacrificial layers 206a,b, etc. and the active layers 208a,b, etc. are such that the sacrificial layers 206a,b, etc. can be selectively removed relative to the active layers 208a,b, etc. during fabrication. Furthermore, as described in more detail below, the materials employed for the sacrificial layers 204a,b, etc. should be such that the sacrificial layers 204a,b, etc. can be selectively removed relative to the sacrificial layers 206a,b, etc. during fabrication to form the bottom dielectric insulating layer.

[0021] For example, according to an exemplary embodiment, sacrificial layers 204a, b, etc. and sacrificial layers 206a, b, etc. are each formed from SiGe, while active layers 208a, b, etc. are formed from Si. For etching SiGe versus Si, high temperature liquid phase SC1, gas phase hydrogen chloride (HCl), gas phase chlorine trifluoride (ClF 3 ), and other reactive cleaning processes (RCPs) have selectivity.

[0022] Additionally, an etchant such as dry HCl can be used to selectively remove high germanium (Ge) content SiGe relative to low Ge content SiGe. In this case, according to an exemplary embodiment, the sacrificial layers 204a, b, etc. are formed from SiGe having a high Ge content. For example, in one exemplary embodiment, the high Ge content SiGe is SiGe having about 50% Ge to about 100% Ge (i.e. pure Ge) and ranges therebetween. For example, in one non-limiting example, the sacrificial layers 204a, b, etc. are formed from SiGe60 (SiGe having about 60% Ge content). The use of SiGe with a higher Ge content allows the sacrificial layers 204a, b, etc. to be selectively etched relative to the sacrificial layers 206a, b, etc. when forming the bottom dielectric insulating layer (see below). In that case, the sacrificial layers 206a, b, etc. are preferably formed from low Ge content SiGe. For example, in one exemplary embodiment, low Ge content SiGe is SiGe having about 20% Ge to about 50% Ge and ranges therebetween. For example, in one non-limiting example, sacrificial layers 206a,b, etc. are formed from SiGe30 (which is SiGe with about 30% Ge content).

[0023] Shallow trench isolation (STI) techniques are then utilized to isolate the device stacks 212a,b, etc. STI generally involves patterning a trench in a substrate and then filling the trench with a dielectric such as an oxide (sometimes referred to generally herein as an "STI oxide"). Although not explicitly shown in the figures, a liner (e.g., thermal oxide or silicon nitride (SiN)) may be deposited in the trench prior to the STI oxide.

[0024] To begin the STI process, the substrate 202 is first recessed to form trenches 302a,b,c, etc. in the substrate 202 at the base of the device stacks 212a,b, etc. See FIG. 3 (Cross-Section X). By way of example only, the recessing of the substrate 202 can be performed using a directional (anisotropic) etching process such as RIE. A hard mask 210 protects the device stacks 212a,b, etc. during the recessing etch. The device stacks 212a,b, etc. are then recessed with an STI oxide 304 that fills the trenches 302a,b,c, etc. as shown in FIG. 3. Suitable STI oxides 304 include, but are not limited to, oxide low-k materials such as silicon oxide (SiOx) and / or oxide ultra-low-k interlayer dielectric (ULK-ILD) materials, e.g., having a dielectric constant κ of less than 2.7. By way of comparison, silicon dioxide (SiO2) has a dielectric constant κ value of 3.9. Suitable ultra-low-k dielectric materials include, but are not limited to, porous organosilicate glass (pSiCOH). A process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) can be used to deposit the STI oxide 304. Following deposition, a process such as chemical mechanical polishing (CMP) can be used to planarize the STI oxide 304. As shown in FIG. 3, the top surface of the STI oxide 304 is now flush with the top surface of the hard mask 210.

[0025] In this example, a buried power rail is to be formed between adjacent device stacks 212a, b, etc. To do this, selective recessing of the STI oxide 304 present between adjacent device stacks 212a, b, etc. and in trench 302b is performed. The purpose of the STI oxide 304 is to only partially recess the STI oxide 304 present between adjacent device stacks 212a, b, etc. and in trench 302b. In other words, the STI oxide 304 on the opposite / outside of device stacks 212a, b, etc. and in trenches 302a and 302c should remain unaffected. Therefore, first a patterned block mask 402 is formed on the STI oxide 304 covering / masking the STI oxide 304 outside the device stacks 212a, b, etc. See FIG. 4 (Cross-Section X). Suitable materials for the block mask 402 include, but are not limited to, organic planarization layer (OPL) materials.

[0026] Next, a partial recess etch of the STI oxide 304 between adjacent device stacks 212a,b, etc. and within trench 302b is performed. By way of example only, recessing the STI oxide 304 can be performed using a directional (anisotropic) etching process such as RIE. By "partial" we mean that after recessing, a portion of the STI oxide 304 remains on the substrate 202 at the bottom of trench 302b. See, for example, FIG. 4.

[0027] Sidewall spacers 502 are then formed along the sidewalls of trench 302b at the base of device stacks 212a, b, etc. between adjacent device stacks 212a, b, etc. See FIG. 5 (Cross-Section X). According to an exemplary embodiment, sidewall spacers 502 are formed by first depositing a suitable spacer material on top of device stacks 212a, b, etc., and then patterning the spacer material into individual spacers along the device stack sidewalls using a directional (anisotropic) etching process such as RIE. Suitable spacer materials for sidewall spacers 502 include, but are not limited to, silicon carbide (SiC) and / or silicon oxycarbide (SiOC). In the natural state, spacers can only be formed along the sidewalls of exposed device stacks, specifically the sidewalls between adjacent device stacks 212a, b, etc. over trench 302b. Initially, the maximum length of the sidewall spacers is formed along the exposed sidewalls. However, as shown in FIG. 5, the sidewall spacers 502 are then recessed.

[0028] As will become apparent from the ensuing description, the sidewall spacers 502 act as a protective layer that separates / insulates the buried power rails from the substrate 202. For this reason, the recessed sidewall spacers 502 must still cover the substrate 202 along the sidewalls of the trench 302b. According to an exemplary embodiment, the recessed sidewall spacers 502 cover the substrate 202 along the sidewalls of the trench 302b as well as the sacrificial layers 204a,b, etc. (and optionally a portion of the bottommost sacrificial layer 206a,b, etc.) along the sidewalls of the device stacks 212a,b, etc., as shown in FIG.

[0029] A buried power rail 602 is then formed in the trench 302b between the sidewall spacers 502. See FIG. 6 (Cross-section X). According to an exemplary embodiment, the buried power rail 602 is formed by depositing a metal or combination of metals in the trench 302b and then using an etch to selectively recess the metal below the top surface of the sidewall spacers 502. Suitable metals for the buried power rail 602 include, but are not limited to, copper (Cu), cobalt (Co), ruthenium (Ru), or tungsten (W), or combinations thereof. Processes such as sputtering, evaporation, or electrochemical plating can be used to deposit the metal in the trench 302b. A metal selective etch can be used to recess the buried power rail 602. According to an exemplary embodiment, in the buried power rail 602, the top surface of the recessed buried power rail 602 is below the sacrificial layers 204a,b, etc. of the device stacks 212a,b, etc., as shown in Figure 6. Following formation of the buried power rail 602, any remaining block mask 402 is removed. By way of example only, an ashing process may be used to remove the OPL block mask.

[0030] Following removal of the block mask 402, an additional dielectric 702 is then deposited over the device structure, including in the trench 302b, over the buried power rail 602, followed by CMP. The dielectric 702 and STI oxide 304 are then recessed and the remaining hard mask 210 is removed. See FIG. 7 (cross section X). Suitable materials for the dielectric 702 include, but are not limited to, oxide low-k materials, such as SiOx, or oxide ULK-ILD materials, such as pSiCOH, or both. By way of example only, recessing the dielectric 702 and SDI oxide 304 can be performed using a directional (anisotropic) etching process, such as RIE. Based on this process, the buried power rail 602 is now buried in the substrate 202 at the base of the device stacks 212a, b, etc., for example between the device stacks 212a and 212b. However, the STI oxide 304 and sidewall spacers 502 separate the buried power rail 602 from the substrate 202 .

[0031] 7, the top surface of the dielectric 702 is now below the tops of the sidewall spacers 502, and the top surface of the STI oxide 304, which is substantially coplanar with the top surface of the dielectric 702, is below the top surfaces of the sacrificial layers 204a,b, etc. in each of the device stacks 212a,b, etc. As described in more detail below, exposing the sacrificial layers 204a,b, etc. along the sidewalls of the device stacks 212a,b, etc. allows the sacrificial layers 204a,b, etc. to be replaced with a bottom dielectric insulating layer. The bottom dielectric insulating layer prevents source-drain leakage current through the substrate 202.

[0032] As noted above, a replacement metal gate or RMG process is utilized where a sacrificial gate is placed early in the process to allow for the formation of the source and drain. The sacrificial gate is later removed and replaced with a replacement metal gate. To illustrate the replacement metal gate process and the steps involved, the following will refer to cross section Y of the device structure, which provides a view of a cut through the center of one of the device stacks perpendicular to the gate as highlighted above.

[0033] Specifically, as shown in FIG. 8 (cross section Y), a sacrificial gate 802 is then formed on the device stacks 212a, b, etc., above the channel regions of the semiconductor FETs. See FIG. 8. FIG. 8 provides a view of a cut through the device stack 212a. However, the process flow is the same for the device stack 212b. To form the sacrificial gate 802, a sacrificial gate material is first blanket deposited on the device stacks 212a, b, etc. Suitable sacrificial gate materials include, but are not limited to, polysilicon (poly-Si) and / or amorphous silicon (a-Si). Processes such as CVD, ALD, or PVD can be utilized to deposit the sacrificial gate material on the device stacks 212a, b, etc.

[0034] A sacrificial gate hardmask 801 is then formed on the sacrificial gate material, marking the footprint and location of each of the sacrificial gates 802. Suitable materials for the sacrificial gate hardmask 801 include, but are not limited to, nitride hardmask materials, such as SiN, SiON, or silicon carbonitride (SiCN), or combinations thereof, or oxide hardmask materials, such as SiOx, or both. An etch using the sacrificial gate hardmask 801 is then used to pattern the sacrificial gate material into individual sacrificial gates 802 as shown in FIG. 8. A directional (anisotropic) etching process, such as RIE, can be utilized for the sacrificial gate etch.

[0035] 8, a dielectric spacer 804 is then formed alongside the sacrificial gate hardmask 801 and the sacrificial gate 802. Suitable materials for the dielectric spacer 804 include, but are not limited to, SiOx, SiC, or SiCO, or combinations thereof. Processes such as CVD, ALD, or PVD can be utilized to deposit the dielectric spacer 804 alongside the sacrificial gate hardmask 801 / sacrificial gate 802.

[0036] As highlighted above, the sacrificial gate 802 will act as a placeholder for the final gate of the semiconductor FET device. Specifically, the sacrificial gate 802 will be removed later in the process and replaced with a metal gate stack that will act as the final gate of the semiconductor FET device. In this case, these final gates of the semiconductor FET device are also referred to herein as "replacement metal gates" or simply "RMGs." The use of a replacement metal gate process is advantageous because it prevents the metal gate stack materials from being exposed to conditions that could cause damage during subsequent processing steps. For example, the high-k dielectrics used in the replacement metal gate stack can be damaged by exposure to high temperatures. For this reason, these gate stack materials are only placed near the end of the process.

[0037] The sacrificial gate 802 and dielectric spacers 804 are then used as a mask to pattern a trench 806 in the device stack 212a between the sacrificial gate 802. A directional (anisotropic) etching process, such as RIE, can be utilized to etch the trench 806. As shown in FIG. 8, the trench 806 extends through each of the sacrificial layers 206a and the active layer 208a, terminating on the sacrificial layer 204a. Although not shown in the figure, the same process is utilized to form the sacrificial gate, the dielectric spacers, and the trench in the device stack 212b.

[0038] This etch patterns device stack 212a into a plurality of individual FET stacks 212a', 212a'', and 212a''', as shown in Figure 8. The patterned portions of sacrificial layer 206a and active layer 208a are now designated as 206a', 206a'', and 206a''', and 208a', 208a'', and 208a''', respectively.

[0039] The sacrificial layer 204a is then selectively removed and replaced with a bottom dielectric insulating layer 902. See FIG. 9 (cross-section Y). For example, as discussed above, the sacrificial layer 204a can be formed of high Ge content SiGe (e.g., SiGe with about 50% Ge to about 100% Ge (i.e., pure Ge) and ranges therebetween, such as SiGe60). An etchant such as dry HCl can then be used to remove the sacrificial layer 204a to form a cavity 901 (shown in dotted lines) at the bottom of the device stack 212a. A dielectric material is then deposited in the cavity 901 to form the bottom dielectric insulating layer 902 shown in FIG. 9. Suitable dielectric materials for the bottom dielectric insulating layer 902 include, but are not limited to, SiOx and / or SiN. Processes such as CVD, ALD, or PVD can be utilized to deposit the dielectric material in the cavity 901. As mentioned above, the bottom dielectric insulating layer 902 is used to prevent source-drain leakage current through the substrate 202. Although not shown in the figures, the same process is utilized to remove the sacrificial layer 204a and replace it with the bottom dielectric insulating layer 902.

[0040] Sources and drains are then formed in trenches 806 on either side of sacrificial layers 206a', 206a'', and 206a''' and active layers 208a', 208a'', and 208a'''. But first, inner spacers 904 are formed alongside sacrificial layers 206a', 206a'', and 206a'''. To do this, a selective etch is performed to laterally recess the exposed sacrificial layers 206a', 206a'', and 206a''' along the sidewalls of FET stacks 212a', 212a'', and 212a'''. See FIG. 9. This recessing etch forms pockets along the sidewalls of FET stacks 212a', 212a'', and 212a''', which are filled with spacer material to form inner spacers 904 within the pockets. These inner spacers 904 will offset the replacement metal gates from the sources and drains (see below). As discussed above, according to an exemplary embodiment, the sacrificial layers 206a', 206a'', and 206a''' are formed of SiGe. A SiGe-selective non-directional (isotropic) etching process can then be used for the recessing etch. Suitable spacer materials for the inner spacers 904 include, but are not limited to, silicon nitride (SiN), SiOx, SiC, or SiCO, or combinations thereof. Processes such as CVD, ALD, or PVD can be utilized to deposit the spacer material in the pocket. Excess spacer material is removed from the trench 806 using a directional (anisotropic) etching process such as RIE.

[0041] Sources and drains 906 are then formed in the trenches 806 on either side of the sacrificial layers 206a', 206a'', and 206a''', and the active layers 208a', 208a'', and 208a'''. According to an exemplary embodiment, the sources and drains 906 are formed from epitaxial materials, such as epitaxial Si, epitaxial SiGe, etc., that are in situ doped (i.e., as they are grown) or ex situ doped (e.g., via ion implantation). Suitable n-type dopants include, but are not limited to, phosphorus (P) and / or arsenic (As). Suitable p-type dopants include, but are not limited to, boron (B), aluminum (Al), and / or gallium (Ga). With the inner spacers 904 in place along the sidewalls of the FET stacks 212a', 212a'', and 212a''', epitaxial growth of the source and drain 906 is modeled on the (exposed) ends of the active layers 208a', 208a'', and 208a'''.

[0042] Following formation of the source and drain 906, the sacrificial gate 802 is selectively removed. To do this, the sacrificial gate 802 is first surrounded by an inter-layer dielectric (ILD) 908. Suitable ILD materials include, but are not limited to, oxide low-k materials such as SiOx, or oxide ULK-ILD materials such as pSiCOH, or both. A process such as CVD, ALD, or PVD can be utilized to deposit the ILD 908 around the sacrificial gate 802. Following deposition, a process such as chemical mechanical polishing (CMP) can be used to planarize the ILD 908.

[0043] The sacrificial gate 802 is then selectively removed to form a gate trench 1002 in the ILD 908 over the FET stacks 212a', 212a'', and 212a''', see FIG. 10 (cross section Y). The sacrificial layers 206a', 206a'', and 206a''', which are now accessible through the gate trench 1002, are then selectively removed. The removal of the sacrificial layers 206a', 206a'', and 206a''', frees the active layers 208a', 208a'', and 208a''', from the FET stacks 212a', 212a'', and 212a''', in the channel region of the device. Specifically, the FET stacks 212a', 212a'', and 212a''', now have gaps between the active layers 208a', 208a'', and 208a''', in the channel region of the device. The active layers 208a', 208a'', and 208a''' will be used to form the channel of a FET device. The gate trench 1002 and gaps in the FET stacks 212a', 212a'', and 212a''' allow for the formation of a replacement metal gate, i.e., including a gate dielectric and at least one work function setting metal, that completely surrounds a portion of each of the active layers 208a', 208a'', and 208a''', in a gate-all-around configuration.

[0044] For example, a conformal gate dielectric 1004 is first deposited into each of the gate trenches 1002 and gaps to line them, so that a conformal gate dielectric 1004 is now present over the active layers 208a', 208a'', and 208a''' in the channel region of the FET device. See FIG. 10. According to an exemplary embodiment, the gate dielectric 1004 is a high-k material. The term "high-k" as used herein refers to a material that has a dielectric constant, κ, that is much higher than that of silicon dioxide (e.g., SiO 2 Unlike 4, hafnium oxide (HfO 2 ) has a dielectric constant κ=25). Suitable high-k gate dielectrics include, but are not limited to, HfO 2or lanthanum oxide (La 2 O 3 ), or both. To deposit the gate dielectric 1004, a process such as CVD, ALD, or PVD can be utilized. According to an exemplary embodiment, the gate dielectric 1004 has a thickness ranging from about 1 nanometer (nm) to about 5 nm and therebetween. The deposition of the gate dielectric 1004 can be followed by a reliability anneal. In one exemplary embodiment, the reliability anneal is performed at a temperature ranging from about 500° C. to about 1200° C. and therebetween, for a duration ranging from about 1 nanosecond to about 30 seconds and therebetween. Preferably, the reliability anneal is performed in the presence of an inert gas, such as a nitrogen-containing atmosphere.

[0045] At least one work function setting metal 1102 is then deposited in the gate trench 1002 and gap in contact with the gate dielectric 1004. See FIG. 11 (cross section Y). Suitable n-type work function setting metals include, but are not limited to, titanium nitride (TiN), tantalum nitride (TaN), or aluminum (Al)-containing alloys, such as titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), or tantalum aluminum carbide (TaAlC), or combinations thereof. Suitable p-type work function setting metals include, but are not limited to, TiN, TaN, or tungsten (W), or combinations thereof. TiN and TaN are relatively thick (e.g., greater than about 2 nm) when used as p-type work function setting metals. However, a very thin layer of TiN or TaN (e.g., less than about 2 nm) may be used under the Al-containing alloy resulting in an n-type work function setting stack to improve electrical properties such as gate leakage current. Thus, there is some overlap between the exemplary n-type and p-type work function setting metals shown above. Processes such as CVD, ALD, or PVD can be utilized to deposit the work function setting metal 1102. Following deposition, a process such as CMP can be used to remove the metal overlayer.

[0046] At this point, we have a device structure that includes at least one gate (i.e., replacement metal gate-gate dielectric 1004 and work function setting metal 1102) with a source and drain 906 on either side of the at least one gate. A channel (i.e., active layers 208a', 208a'', and 208a''') interconnects the source and drain 906. A buried power rail 602 is buried in the substrate 202 between the sidewall spacers 502. Referring again to cross section X of the device structure, which provides a view of a cut through the device stack between two of the gates as highlighted above, FIG. 12 depicts a view through the source and drain 906 epitaxy in each of the device stacks 212a and 212b to one side of the replacement metal gate (not visible in this depiction). As shown in FIG. 12, a bottom dielectric insulating layer 902 separates the source and drain 906 from the substrate 202. The bottom dielectric insulating layer 902 prevents source-drain leakage current through the substrate 202 .

[0047] The next task is to form buried contacts to the buried power rail 602 and to the source and drain 906. As mentioned above, the buried contacts will have a graded architecture to optimize the contact resistance to the source and drain 906.

[0048] To form the buried contact, first the contact trench 1304 is patterned in the dielectric 702 and the ILD 908. See FIG. 13 (Cross-Section X). To do this, a patterned block mask 1302 is formed on the ILD 908 to mark the footprint and location of the contact trench 1304. Suitable materials for the block mask 1302 include, but are not limited to, OPL materials. An etch is then performed using the block mask 1302 to form the contact trench 1304 shown in FIG. 13. For the contact trench etch, a directional (anisotropic) etching process such as RIE can be utilized. The etch chemistry used is preferably selective to etching dielectric 702 and ILD 908 over sidewall spacers 502. In that way, the contact trench etch is self-aligned to the sidewall spacers 502, preventing shorting of the buried contact to the substrate 202. By way of example only, as discussed above, the dielectric 702 and ILD 908 can be an oxide low-k material such as SiOx and / or an oxide ULK-ILD material such as SiCOH, while the sidewall spacers 502 can be formed of SiC and / or SiOC. A directional etch process such as an RIE etch can then be utilized to selectively pattern the dielectric 702 and ILD 908 with respect to the sidewall spacers 502. By way of example only, a SF6 / O2 based RIE can provide the necessary etch selectivity. See, for example, Oda et al., "Optimizing the SiC Plasma Etching Process For Manufacturing Power Devices," CS MANTECH Conference, pp. 125-128 (May 2015), the contents of which are incorporated herein by reference as if fully set forth. As shown in FIG. 13, at least a portion of the buried power rail 602 is now exposed at the bottom of the contact trench 1304.

[0049] As shown in FIG. 13, within the contact trench 1304, at least a portion of at least one of the source and drain (hereafter given the reference number 906′) is also exposed. An etch is then utilized to create a downwardly sloping surface 1402 along the exposed portion of the source and drain 906′. See FIG. 14 (Cross-Section X). According to an exemplary embodiment, the surface 1402 is sloping at an angle θ ranging from about 95° to about 150° and any range therebetween. By way of example only, the sloping surface 1402 along the source and drain 906′ is created using a directional etch process that relies on the crystallographic properties of the etch of the source and drain 906′. See, for example, U.S. Pat. No. 9,287,123, entitled “Techniques for Forming Angled Structures for Reduced Defects in Heteroepitaxy of Semiconductor Films,” issued to Srinivasan et al., the contents of which are incorporated herein by reference as if fully set forth. Alternatively, another method for creating the sloped surface 1402 along the source and drain 906' is to pattern the block mask 1302 with tapered sidewalls (not shown) using an etching process such as RIE. These tapered sidewalls will be transferred to the ILD 908 while the ILD 908 is open. An etching process such as RIE can then be used to etch the source and drain 906', which will be sloped based on the tapered sidewalls. As described in more detail below, reshaping the surface of the source and drain 906' in the contact trench 1304 in this manner advantageously enables the use of amorphization implants and epitaxial regrowth induced by low thermal budget annealing, e.g., laser annealing (LA), to provide low contact resistance along the sloped surface 1402 between the semiconductor and the buried contact.

[0050] Etching processes such as RIE can cause damage to the inclined surface 1402 and can leave contaminating residues on the inclined surface 1402. Therefore, according to an exemplary embodiment, a thin trench epitaxy layer 1502 is optionally grown on the exposed inclined surface 1402 in the contact trench 1304. See FIG. 15 (cross section X). Doing so improves the quality of the epitaxial material along the inclined surface 1402 of the source and drain 906', which can also be used to adjust the material composition of the epitaxial material of the source and drain 906' along the inclined surface 1402, if desired. For the source and drain 906 / 906', the layer 1502 can be formed of in-situ or ex-situ doped epitaxial material, such as epitaxial Si, epitaxial SiGe, etc. As mentioned, suitable n-type dopants include, but are not limited to, P and / or As, and suitable p-type dopants include, but are not limited to, B, Al, or Ga, or combinations thereof. The choice of dopant depends on the host semiconductor material, and dopants with high solid solubility are preferably selected. The trench epitaxy layer 1502 may be different for n-channel FET (nFET) and p-channel FET (pFET) devices. If different trench epitaxy layers 1502 are used for different (e.g., nFET and pFET) devices, standard blocking and patterning techniques are used to block a first set of devices and open a second set of devices, selectively grow trench epitaxy layer 1502 on the inclined surfaces 1402 of the second set of devices, and then the sequence is repeated to selectively grow trench epitaxy layer 1502 on the inclined surfaces 1402 of the first set of devices. According to one exemplary embodiment, for an nFET device, the trench epitaxy layer 1502 is 1×10 21 atoms / cm 3The Si is doped with more than 1×10 atomic percent (equivalent to more than 2 at.%) phosphorus (P), and in the case of a pFET device, the trench epitaxy layer 1502 has a higher Ge content than the source and drain 906 / 906′ by more than 60 at.%. 21 atoms / cm 3 % (equivalent to greater than 2 at.%) gallium (Ga) doped SiGe. According to an exemplary embodiment, trench epitaxy layer 1502 has a thickness ranging from about 1 nanometer (nm) to about 7 nm and any range therebetween.

[0051] In either case, whether or not an optional trench epitaxy layer 1502 is utilized, an epitaxial regrowth of the amorphized surface layer is then performed to form a surface dopant-semiconductor alloy layer, i.e., contact layer 1602, having a high concentration of activated dopant. See FIG. 16 (cross section X). The activated dopant provides free electrical carriers (electrons and holes) to reduce the contact resistivity along the inclined surfaces 1402 of the source and drain 906' and the metal material of the buried contact 1702 (see FIG. 17 described below) that will be formed adjacent to the inclined surfaces 1402. In general, an amorphization implant is used to intentionally disrupt the ordered crystalline structure of the material in which the implantation is being performed. An amorphization implant also disrupts the bond structure between the dopants, for example, by breaking the bonds within the dopant clusters and forming a more homogenous mixture of the host semiconductor and the target concentration or ratio of dopant atoms. The amorphization implant may be selected to add dopants to the amorphized contact layer 1602 to a target level of dopant concentration depending on the dopant concentration level in the inclined surface 1402 and / or the (optional) trench epitaxy layer 1502. The amorphization implant may utilize ions of dopants or electrically neutral elements (e.g., ions of constituents of the underlying host semiconductor, such as ions of Si and / or Ge). Because the placement of dopants during the implantation process into the amorphized inclined surface 1402 / (optional) trench epitaxy layer 1502 is random in nature, the resulting doped amorphous material typically has a more homogeneous distribution of dopants than doped materials amorphized by neutral atoms / ions. Laser annealing is then performed to recrystallize the amorphized material.

[0052] In the recrystallization process, the dopants are activated by incorporating the dopant atoms into the growing crystal lattice. The duration of the laser anneal is selected to be short to maintain the activated dopants (see below), but sufficient to allow complete recrystallization of the amorphous material. The short anneal duration allows for a rapid temperature ramp down to confine the dopant atoms in the semiconductor crystal lattice. Furthermore, the anneal temperature and duration, or equivalently, the anneal thermal budget, are selected to be small enough that the gate dielectric 1004 and the work function setting metal 1102 are not affected thereby, e.g., the equivalent electrical thickness (EOT) of the gate dielectric 1004 does not increase by more than 0.25 Angstroms (Å) due to this rapid anneal. A suitable millisecond or nanosecond annealing process can satisfy these thermal budget requirements and allow for a rapid temperature ramp down to confine the semiconductor recrystallization and activated dopants. By way of example only, millisecond annealing can be in the form of flash lamp or laser annealing, and nanosecond annealing can be in the form of laser or electron beam annealing. Characteristic durations of these fast anneals range from about 30 milliseconds to about 10 nanoseconds, and ranges therebetween. In one exemplary embodiment, fast laser annealing (LA), also referred to herein as "fast LA," refers to a wide range of laser anneal durations ranging from about 10 milliseconds to about 10 nanoseconds, and ranges therebetween. The resulting surface semiconductor-dopant alloy, i.e., contact layer 1602, is metastable, with the active dopant concentration being above the maximum thermodynamically tolerable (i.e., thermodynamic limit). The thermodynamic limit of the active dopant is related to the maximum solid solubility of the dopant in the host material. The thermodynamic limit of an active dopant is typically one-quarter its maximum solid solubility. For dopants with high solid solubility, the thermodynamic limit of the active dopant is approximately 2×10 20 cm -3 ~Approx. 4×10 20 cm -3and ranges therebetween. The surface amorphization and rapid recrystallization sequence results in a surface concentration of about 2×10 21 cm -3 Advantageously, forming a contact layer 1602 having a high active dopant content results in a low contact resistivity (ρ c ) will be obtained.

[0053] The amorphization implant is aided by the sloping surfaces 1402 of the source and drain 906'. Specifically, it is difficult to perform an amorphization implant in a vertical surface. Another way of looking at it is that if one were to forgo the reshaping of the source and drain in the contact trench 1304 and instead perform a sequence of surface amorphization and rapid recrystallization on source and drain epitaxy that has both horizontal and vertical surfaces, only the horizontal surfaces would receive the proper treatment, resulting in the contact layer 1602 being formed only on the horizontal surfaces, resulting in a high contact resistance R. c This is likely to result in an increase in

[0054] According to another exemplary embodiment, the composition of the inclined surface 1402 and / or the (optional) trench epitaxy layer 1502 is about 3×10 21 atoms / cm 3 of phosphorus (P) doped silicon, with a Ge content of greater than about 60% for pFET devices. 21 atoms / cm 3The SiGe is doped with boron (B). Aluminum (Al) and gallium (Ga) are suitable dopants with high solid solubility for SiGe with a Ge content greater than about 60%, which in this example is not present in the pFET tilted surface 1402 / (optional) trench epitaxy layer 1502. Ga ions are therefore suitable as amorphization implant ions for the pFET devices. A suitable standard blocking mask is deposited and patterned to block the FET devices and expose the pFET devices, and a Ga ion implant is performed with zero degree tilt into the exposed pFET source / drain tilted surface 1402 / (optional) trench epitaxy layer 1502. In one exemplary embodiment, the Ga implant energy is about 1 kiloelectron volt (keV) to about 8 keV and a range therebetween, e.g., about 4 keV, and the Ga ion implant dose is about 1×10 15 atoms / cm 2 ~Approx. 5×10 15 atoms / cm 2 and ranges therebetween, e.g., about 2.5×10 15 atoms / cm 2 To accelerate the amorphization process, a low temperature amorphization implant can be performed at a temperature below room temperature (e.g., at a wafer temperature of minus 100° C.). The resulting amorphous layer thickness on the pFET source / drain sloped surfaces ranges from about 3 nm to about 12 nm and therebetween, e.g., near optimally about 7 nm. In one exemplary embodiment, the resulting concentration of Ga in the amorphized SiGe layer is about 2×10 21 atoms / cm 3 ~Approx. 5×10 21 atoms / cm 3 , e.g., the near-optimal 3 × 10 21 atoms / cm 3 In this exemplary embodiment, a similar aluminum ion amorphization implant could be used instead.

[0055] The block mask is then stripped off the nFET device without affecting the amorphous surface layer already present on the pFET source / drain. Phosphorus is a dopant with high solid solubility for silicon and is present in sufficient amounts in the nFET tilted surface 1402 / (optional) trench epitaxy layer 1502, therefore Ge ions are selected as the amorphization implant ions for the nFET device. No additional block mask is required since Ge is electrically neutral with respect to Si and SiGe doping, thus reducing costs, and the Ge ion implant is performed with zero degree tilt into the exposed nFET and pFET source / drain tilted surfaces 1402 / trench epitaxy layer 1502. According to an exemplary embodiment, the Ge implant energy is about 1 keV to about 8 keV and a range therebetween, e.g., about 4 keV, and the Ge implant dose is about 1×10 14 atoms / cm 2 ~5×10 14 atoms / cm 2 and ranges therebetween, e.g., about 2×10 14 atoms / cm 2 . A low temperature amorphization implant can be performed at a temperature below room temperature (e.g., at a wafer temperature of minus 100° C.) to accelerate the amorphization process. In one exemplary embodiment, the resulting amorphous layer thickness on the nFET source / drain graded surfaces ranges from about 3 nm to about 12 nm and therebetween, e.g., near optimal, about 7 nm. The amorphous layer thickness present on the pFET source / drain graded surfaces remains near optimal. Due to the low implanted Ge dose, the chemical composition of the graded surfaces 1402 / trench epitaxy layer 1502 of both nFET and pFET does not appreciably change. The resulting concentration of P in the amorphized Si layer is about 1×10 21 atoms / cm 3 After forming a surface amorphous layer along the source / drain graded surfaces 1402 / trench epitaxy layer 1502 of the nFET and pFET, respectively, a rapid LA is performed to recrystallize the material and to create a metastable semiconductor-dopant alloy contact layer 1602 with a high concentration of active dopant.

[0056] According to one exemplary embodiment, solid phase epitaxy (SPE) or solid epitaxial regrowth is induced by fast laser annealing (LA). Such laser annealing process is performed at a temperature ranging from about 800° C. to about 950° C. and therebetween, for a duration ranging from about 50 microseconds to about 3 milliseconds and therebetween. For this purpose, a triangular temperature-time laser spike annealing process can be used. The preferred peak temperature of the laser spike annealing process is in the range of about 800° C. to about 950° C. and therebetween, and the preferred duration at 50 degrees below the peak temperature is in the range of about 50 microseconds to about 250 microseconds and therebetween. This can be done using a millisecond laser annealing apparatus. According to another exemplary embodiment, liquid phase epitaxy (LPE) or liquid epitaxial regrowth is induced by fast laser annealing. Such laser annealing processes are performed at temperatures ranging from about 1200° C. to about 1300° C. and therebetween, for durations ranging from about 10 nanoseconds to about 1000 nanoseconds and therebetween. This is performed using a nanosecond melt laser annealing apparatus. Advantageously, the nanosecond melt laser annealing apparatus may include a combination of millisecond laser annealing and nanosecond laser annealing. By way of example only, LPE-induced laser annealing may be performed with millisecond-scale temperature ramping to intermediate temperatures ranging from about 600° C. to about 750° C. and therebetween, with superposition of nanosecond temperature spikes to above the melting point of the source and drain amorphized material in the inclined surface 1402 / trench epitaxy layer 1502. Both laser-induced SPE and LPE may be performed with durations ranging from about 10 nanoseconds to about 1000 nanoseconds and therebetween. 21 cm -3 16, which results in the formation of a contact layer 1602 having a high active dopant content or greater, which results in a low contact resistivity (ρc ) leading to

[0057] A metal or combination of metals is then deposited on the graded contact layer 1602 in the contact trenches 1304 and then recessed to form buried contacts 1702 connecting the buried power rail 602 to the graded contact layer 1602 of the source and drain 906'. See Figure 17 (Cross Section X).

[0058] The contact resistance between the metal material and the doped semiconductor is a bottleneck in miniaturized semiconductor devices with small contact areas. Therefore, the metal compound directly adjacent to the source / drain is usually selected to form a low contact resistivity to the doped semiconductor material of the source / drain. The contact resistivity of the semiconductor-metal interface is a material property and depends on both the active concentration of dopants in the adjacent semiconductor and the Schottky barrier height between the adjacent metal compound and the semiconductor. A higher concentration of active dopants results in a lower contact resistivity, and a lower Schottky barrier height results in a lower resistivity. Various techniques can be used to reduce the Schottky barrier height, including forming different silicide or germanosilicide interfacial metal compounds for the nFET source / drain and the pFET source / drain. For example, nickel and platinum germanosilicide reduce the Schottky barrier height for pFET devices, while titanium silicide reduces the Schottky barrier height for nFET devices. This technique requires a complex processing scheme to form different metal stacks for the pFET and nFET devices for the buried contact 1702. Prior art contact resistivities between silicide / germanosilicide and doped semiconductors are approximately 2×10 -9 Ωcm 2 The presence of contact layer 1602 with high active dopant content reduces the contact resistivity to most silicides / germanosilicides to approximately 1×10 -9 Ωcm 2Advantageously, this greatly simplifies the buried contact structure and fabrication process, allowing a single metal stack to be used everywhere while enabling ultra-low contact resistivity to be achieved for n-doped and p-doped semiconductors.

[0059] According to one exemplary embodiment, the surface of the contact layer 1602 is cleaned to remove any native oxide immediately prior to depositing metal in the contact trenches 1304, and a thin Ti / TiN stack (not shown) is deposited on the cleaned contact layer 1602 surface without exposing it to an oxidizing environment. Processes such as sputtering, evaporation, chemical vapor deposition, atomic layer deposition, or combinations thereof can be used to deposit the Ti / TiN stack in the contact trenches 1304. The purpose of the Ti is to form an interfacial titanium silicide / germanosilicide 1701, and the purpose of the TiN is to protect the Ti from oxidation and other chemical attack. In one exemplary embodiment, the thickness of the Ti is less than about 5 nm, and the thickness of the TiN is also less than about 5 nm.

[0060] The structure is then subjected to a rapid thermal anneal that maintains the metastable semiconductor-dopant alloy of the contact layer 1602, thereby forming the interfacial titanium silicide and / or germanosilicide 1701. An exemplary silicidation anneal is a millisecond anneal at a temperature of about 800° C. for a duration ranging from about 50 microseconds to about 3 milliseconds and therebetween, similar to the SPE-induced laser anneal described above. The silicidation anneal can be performed immediately after depositing the Ti / TiN stack or later in the process sequence. The remainder of the trench 1304 is then filled with an elemental metal to reduce the series electrical resistance of the metal buried contact 1702. Suitable elemental metals for the buried contact 1702 include, but are not limited to, Cu, Co, Ru, or W, or combinations thereof. Processes such as sputtering, evaporation, electrochemical plating, chemical vapor deposition, atomic layer deposition, or combinations thereof can be used to deposit elemental metal in contact trench 1304, followed by chemical mechanical polishing and a metal-selective recess etch.

[0061] The metal-metal interface is approximately 1×10 -10 Ωcm 2 These resistances are usually negligible compared to the resistance of the semiconductor-metal interface, but the semiconductor-metal resistivity is less than 1×10 -9 Ωcm 2 If the thickness is less than 1×10 for both n-doped and p-doped semiconductors, the presence of up to three metal-metal interfaces (silicide / Ti / TiN / elemental metal) can be problematic. Furthermore, the presence of multiple metal layers increases the series resistance of the buried contact 1702 for narrow trenches 1304. Advantageously, the presence of a graded contact layer 1602 with a high active dopant content allows for an even simpler buried contact structure. -9 Ωcm 2The single elemental metal is selected to form a suitable interfacial silicide / germanosilicide that achieves the following semiconductor contact resistivity as well as to enable low series resistance of the buried contact 1702. In this exemplary embodiment, suitable single elemental metals for the buried contact 1702 include, but are not limited to, Co, Ru, or W, or combinations thereof, which form silicides and germanosilicides of cobalt, ruthenium, or tungsten, respectively. As shown in FIG. 17, the buried contact 1702 directly contacts the buried power rail 602. The buried contact 1702 contacts the layer 1602 through an interfacial silicide or germanosilicide compound 1701 along the sloped surface 1402 of the source and drain 906'. The contact resistivity ρ c When the contact area becomes larger, the contact resistance R between the semiconductor source and drain 906 / 906′ and the buried metal contact 1702 becomes smaller. c is small for both n-doped and p-doped semiconductors, approximately 1×10 -9 Ωcm 2 An ultra-low contact resistivity of R is achieved because the inclined surface of the contact layer 1602 has a larger contact area than a purely horizontal contact surface. c A larger reduction in the

[0062] Sidewall spacers 502 aligned with buried power rail 602 and buried contact 1702 separate buried power rail 602 and buried contact 1702 from substrate 202. As also shown in Figure 17, the tops of angled surfaces 1402 of source and drain 906' are preferably higher (i.e., above) the top surfaces of buried contact 1702. In this manner, the spacing between buried contact 1702 and adjacent source and drain contacts is optimized (see below).

[0063] A middle-of-line (MOL) metallization technique is then utilized to complete the semiconductor FET device structure. For example, as shown in FIG. 18 (cross-section X), a (second) ILD 1801 is deposited on the (first) ILD 908 to fill the contact trench 1304 above the buried contact 1702. As discussed above, suitable ILD materials include, but are not limited to, oxide low-k materials such as SiOx, or oxide ULK-ILD materials such as pSiCOH, or both. Processes such as CVD, ALD, or PVD can be utilized to deposit the ILD 1801. Following deposition, a process such as CMP can be used to planarize the ILD 1801.

[0064] A so-called damascene or dual damascene process is then utilized to form interconnects in ILD908 and / or ILD1801. In a damascene or dual damascene process, features (e.g., vias and / or trenches) are first patterned in the dielectric using lithography and etching techniques, and then the features are filled with contact metal to form the interconnects (e.g., conductive vias and / or metal lines). In a dual damascene process, when the vias are patterned before the trenches, this is also referred to herein as a "via-first process." Conversely, when the trenches are patterned before the vias, this is also referred to herein as a "trench-first process."

[0065] Suitable contact metals include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or platinum (Pt), or combinations thereof. The contact metal may be deposited in the features using a process such as evaporation, sputtering, or electrochemical plating. Following deposition, a surface layer may be removed using a process such as CMP. Prior to depositing the contact metal in the features, a conformal barrier layer (not shown) may be deposited in the features to line them. The use of such a barrier layer helps prevent diffusion of the contact metal into the surrounding dielectric. Suitable barrier layer materials include, but are not limited to, ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN), or combinations thereof. Additionally, prior to depositing the contact metal, a seed layer (not shown) may be deposited in the features to line them. The seed layer facilitates plating of the contact metal into the features.

[0066] As shown in FIG. 18, contact to source and drain 906′ is made through buried contact 1702 and buried power rail 602, and contact to source and drain 906 is made through source and drain contact 1802, source and drain contact 1804, and metal line 1806. In particular, the spacing between buried contact 1702 and source and drain contact 1802 is optimized by recessing the top surface of buried contact 1702 below the top of sloped surface 1402 of source and drain 906′. From another perspective, increasing the height of buried contact 1702 would undesirably reduce the spacing between buried contact 1702 and source and drain contact 1802, i.e., from S1 to S2 (where S2 <S1)になるであろう。

[0067] Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to these precise embodiments, and that those skilled in the art may make various other changes and modifications without departing from the scope of the invention.

Claims

1. A semiconductor field effect transistor (FET) device, comprising: at least one gate disposed on the substrate; a source and a drain on either side of the at least one gate, at least one of the source and drain having an inclined surface; a buried power rail embedded in the substrate; a buried contact connecting said buried power rail to said sloped surface of said at least one source and drain; Equipped with a sidewall spacer aligned with said buried power rail separating said buried power rail from said substrate, said sidewall spacer also separating said buried contact from said substrate. Semiconductor FET device.

2. 10. The semiconductor FET device of claim 1, wherein said sidewall spacers comprise a material selected from the group consisting of silicon carbide (SiC), silicon oxycarbide (SiOC), and combinations thereof.

3. 2. The semiconductor FET device of claim 1, wherein a top of said sloping surface of said at least one source and drain is above a top surface of said buried contact.

4. 2. The semiconductor FET device of claim 1, wherein said buried power rail comprises a metal selected from the group consisting of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and combinations thereof.

5. 2. The semiconductor FET device of claim 1, wherein said sloping surfaces of said at least one source and drain are sloping at an angle θ ranging from 95° to 150° and any range therebetween.

6. 10. The semiconductor FET device of claim 1 further comprising a trench epitaxial layer disposed on said inclined surface.

7. 2. The semiconductor FET device of claim 1, wherein said buried contact comprises a metal selected from the group consisting of Cu, Co, Ru, W, and combinations thereof.

8. 10. The semiconductor FET device of claim 1 further comprising a bottom dielectric layer separating said source and drain from said substrate.

9. 10. The semiconductor FET device of claim 1 further comprising at least one active layer interconnecting said source and drain.

10. 2. The semiconductor FET device of claim 1, wherein said sloped surface further comprises a surface dopant-semiconductor alloy contact layer.

11. 2. The semiconductor FET device of claim 1, further comprising a sidewall spacer separating said buried power rail from said substrate, said buried power rail being embedded in said substrate below said sloped surface, and a top of said sloped surface of said at least one source and drain being above a top surface of said buried contact.

12. 1. A method of forming a semiconductor FET device, the method comprising: forming a device structure comprising at least one gate disposed on a substrate, a source and a drain on either side of the at least one gate, and a buried power rail buried in the substrate; Etching at least one of the source and drain to create a sloped surface along a portion of the at least one source and drain; forming a buried contact connecting said buried power rail to said angled surface of said at least one source and drain; wherein a top of the sloped surface of the at least one source and drain is above a top surface of the buried contact.

13. 13. The method of claim 12, further comprising growing a trench epitaxy layer on the inclined surface of the at least one source and drain.

14. The method of claim 12 further comprising the step of performing epitaxial regrowth to form a surface dopant-semiconductor alloy contact layer on the inclined surface.

15. forming a device structure comprising at least one gate disposed on a substrate, a source and a drain on either side of the at least one gate, an inter-layer dielectric (ILD) surrounding the at least one gate, and a buried power rail buried in the substrate; patterning a contact trench in the ILD to expose at least one of the source and drain; performing epitaxial regrowth to form a surface dopant-semiconductor alloy contact layer on the inclined surface; The method of claim 12 further comprising:

16. 16. The method of claim 15, further comprising growing a trench epitaxy layer on the sloped surface of the at least one source and drain.

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