Method and apparatus for performing memory operations - Patents.com

Abstract

A method and apparatus for performing a memory operation are provided. The method for performing a memory operation includes the steps of: generating an operation command, the operation command including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extended Header Segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS is not zero, and the EHS indicating a storage address corresponding to a plurality of EHS operation commands, respectively; and sending the operation command to a Universal Flash Storage (UFS) device controller. Command interaction can be reduced, overall command overhead can be reduced, and memory operation efficiency can be improved.

Description

[Technical field]

[0001] This application relates to storage technologies, and more particularly to methods and apparatus for performing memory operations. [Background technology]

[0002] In universal flash storage (UFS) technology, data and information transmission is performed between a UFS host controller and a UFS device controller through command interaction. In the current UFS protocol information unit (UPIU), the command has a limited defined length, so the command can only carry a small amount of information. If the functional operation to be completed is complicated, the performance advantages of UFS technology cannot be fully utilized.

[0003] The related technology provides an accelerated read command that can support 4K data. The command can trigger the UFS device controller to perform continuous accelerated read-back of data at one time. However, for a large amount of data storage operation, the technology still requires multiple command interactions. This increases the command interaction overhead. However, the performance advantages of the UFS technology cannot be realized. Summary of the Invention

[0004] This application provides a method and apparatus for performing memory operations to reduce command interactions, reduce overall command overhead, and improve memory operation efficiency.

[0005] According to a first aspect, the application provides a method for performing a memory operation, the method including: a UFS host controller generating an operation command. The operation command includes a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an extended header segment. The length of the UPIU frame header is a first length (32B). The total length of the EHS is N KB-32B. The total length is greater than the difference between 4KB and the first length. The EHS indicates storage addresses respectively corresponding to a plurality of EHS operation commands. The UFS host controller sends the operation command to a UFS device controller. The UFS device controller determines the storage addresses respectively corresponding to the plurality of EHS operation commands based on the operation command, and performs corresponding memory operations at the storage addresses respectively corresponding to the plurality of EHS operation commands. The UFS device controller returns a processing result to the UFS host controller.

[0006] In the related art, the UFS host controller detects a command transmitted between the UFS host controller and the UFS device controller. When the length of the command exceeds a specified length (e.g., 4KB), the UFS host controller executes corresponding logic control to truncate the command, and only 4KB of the command is prepared for transmission to the UFS device controller. The remaining part can be sent in the next command or immediately discarded. The UFS device controller can also generate a 4KB command or data by executing the same method. However, in this application, the specified length is extended so that the UFS host controller and the UFS device controller can support the transmission of NKB of commands or data, where N is greater than 4, and 32B of the NKB can be used for the UPIU frame header, and the remaining length (NKB-32B) can be used for the extend header segment (EHS). The EHS with a length of NKB-32B is not available in the related art. Therefore, the command transmitted between the UFS host controller and the UFS device controller can carry more information. Correspondingly, the UPIU frame header includes an EHS total length field, which indicates that the EHS length is not zero.

[0007] As mentioned above, the operation command in this application includes a UPIU frame header and an EHS, and the total length of the command is N KB (N>4). The length of the UPIU frame header is a first length (32B), and the total length of the EHS is N KB-32B. Thus, compared with the operation command in the current technology, the operation command in this application can carry more information. Based on this, when multiple EHS operation commands need to be executed, the UFS host controller can send multiple EHS operation commands to the UFS device controller through one operation command.

[0008] The UPIU frame header includes an EHS total length field. The EHS total length field indicates that the length of the EHS is not 0, and the EHS indicates storage addresses corresponding to multiple EHS operation commands, respectively. The multiple EHS operation commands can indicate multiple read operations, multiple write operations, or multiple erase operations, i.e., multiple EHS operation commands that are all read operations, all write operations, or all erase operations can be sent to the UFS device controller at one time through one operation command.

[0009] The maximum length of the EHS can be N KB-32B, that is, the total length of the EHS is equal to or less than N KB-32B. The specific value of the total length can be determined based on the length of data actually written to the EHS. A storage address corresponding to any one of a plurality of EHS operation commands can be expressed in the form of a starting address of a certain data length. For example, the memory operation is a read operation, the starting address corresponding to the read operation is the starting address of data to be read in a storage area of ​​the memory, and the data length is the length of the data to be read starting from the starting address.

[0010] The UFS host controller obtains storage addresses corresponding to the plurality of EHS operation commands, respectively. The operation commands sent to the UFS device controller can carry related information to indicate the storage addresses corresponding to the plurality of EHS operation commands, respectively.

[0011] After receiving the operation command, the UFS device controller can extract information from the corresponding bytes based on the format of the operation command, including the number of the multiple EHS operation commands, the total length of the EHS, and the storage address and data length corresponding to each of the multiple EHS operation commands.

[0012] The UFS device controller performs corresponding operations on the multiple storage areas determined in the above steps based on the operation type indicated in the operation command, e.g., a read operation, a write operation, or an erase operation. When the memory operation is a read operation, the UFS device controller retrieves stored data from the multiple indicated storage areas. When the memory operation is a write operation, the UFS device controller writes data sent by the UFS host controller to the multiple indicated storage areas. When the memory operation is an erase operation, the UFS device controller erases data from the multiple indicated storage areas.

[0013] When the memory operation is a read operation, the UFS device controller returns the read data to the UFS host controller. When the memory operation is a write operation, the UFS device controller returns a write success response to the UFS host controller. When the memory operation is an erase operation, the UFS device controller returns an erase success response to the UFS host controller.

[0014] In addition to the above fields, the operation command in this application may also include other fields. For example, the UPIU frame header also includes an operation command index field (xx00 0001b) and a flag field (Flags). These fields may follow the relevant rules in the protocol. This is not particularly limited in this application.

[0015] In this application, based on the expanded operation command, one operation command can carry storage addresses and data lengths corresponding to multiple EHS operation commands, respectively, and only a few command interactions are required to request to execute memory operations for multiple addresses, thereby reducing command interactions. In addition, since the UFS host controller and the UFS device controller can support a larger amount of data to be transmitted, more data can be carried in one command when the UFS device controller receives and returns data again. Therefore, the return command is also reduced, and the overall command overhead is reduced. During the execution of memory operations, each command needs to be scheduled by the block layer (Block) and transmitted by the driver layer (Driver) and physical layer. After the method in this application is used, IO aggregation can be performed for multiple EHS operation commands, and the corresponding processes, such as scheduling and transmission, can be combined, thereby further reducing the processing procedures of memory operations and improving memory operation efficiency.

[0016] In one possible implementation, the UPIU frame header further includes a number of EHS operation commands. The EHS includes a start address and a data length of a logical block address (LBA) corresponding to each of the EHS operation commands. That is, the EHS includes a number of LBAs, and each LBA corresponds to a data length.

[0017] In one possible implementation, the UPIU frame header further includes a first logical block address and a total data length corresponding to a plurality of EHS operation commands. The EHS includes a physical page number (PPN) corresponding to each of the plurality of EHS operation commands.

[0018] According to a second aspect, the application provides a UFS host controller including a processor and an interface circuit. The processor is configured to generate an operation command, the operation command including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extended Header Segment (EHS). The UPIU frame header includes a total length field of the EHS, the total length field of the EHS indicates a length of the EHS is not zero, and the EHS indicates a storage address corresponding to each of the multiple EHS operation commands. The interface circuit is configured to send the operation command to a Universal Flash Storage (UFS) device controller.

[0019] In one possible implementation, the UPIU frame header contains a number of EHS operation commands.

[0020] In one possible implementation, the UPIU frame header includes a starting logical block address and total data length corresponding to multiple EHS operation commands.

[0021] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, multiple write operations, or multiple erase operations. The storage addresses corresponding to the multiple EHS operation commands may be consecutive or non-consecutive.

[0022] In one possible implementation, the EHS includes a starting logical block address and a data length corresponding to each of a number of EHS operation commands.

[0023] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, and the storage addresses corresponding to the multiple EHS operation commands are consecutive.

[0024] In one possible implementation, the EHS includes physical page numbers that correspond to each of a number of EHS operation commands.

[0025] According to a third aspect, the application provides a UFS device including a processor, an interface circuit, and a storage medium. The interface circuit is configured to receive an operation command from a Universal Flash Storage (UFS) host controller, the operation command including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extended Header Segment (EHS). The UPIU frame header includes a total length field of the EHS, the total length field of the EHS indicates a length of the EHS is not zero, and the EHS indicates storage addresses respectively corresponding to the plurality of EHS operation commands. The processor is configured to determine, based on the operation command, storage addresses respectively corresponding to the plurality of EHS operation commands, and perform corresponding memory operations on the storage medium at the storage addresses respectively corresponding to the plurality of EHS operation commands.

[0026] In one possible implementation, the UPIU frame header contains a number of EHS operation commands.

[0027] In one possible implementation, the UPIU frame header includes a starting logical block address and total data length corresponding to multiple EHS operation commands.

[0028] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, multiple write operations, or multiple erase operations. The storage addresses corresponding to the multiple EHS operation commands may be consecutive or non-consecutive.

[0029] In one possible implementation, the EHS includes a starting logical block address and a data length corresponding to each of a number of EHS operation commands.

[0030] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, and the storage addresses corresponding to the multiple EHS operation commands are consecutive.

[0031] In one possible implementation, the EHS includes physical page numbers that correspond to each of a number of EHS operation commands.

[0032] According to a fourth aspect, the present application provides a UFS host control device including a processing module and a transmitting module. The processing module is configured to generate an operation command, and the operation command includes a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extended Header Segment (EHS). The UPIU frame header includes a total length field of the EHS, and the total length field of the EHS indicates that the length of the EHS is not zero, and the EHS indicates a storage address corresponding to each of the multiple EHS operation commands. The transmitting module is configured to transmit the operation command to a Universal Flash Storage (UFS) device controller.

[0033] In one possible implementation, the UPIU frame header contains a number of EHS operation commands.

[0034] In one possible implementation, the UPIU frame header includes a starting logical block address and total data length corresponding to multiple EHS operation commands.

[0035] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, multiple write operations, or multiple erase operations. The storage addresses corresponding to the multiple EHS operation commands may be consecutive or non-consecutive.

[0036] In one possible implementation, the EHS includes a starting logical block address and a data length corresponding to each of a number of EHS operation commands.

[0037] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, and the storage addresses corresponding to the multiple EHS operation commands are consecutive.

[0038] In one possible implementation, the EHS includes physical page numbers that correspond to each of a number of EHS operation commands.

[0039] According to a fifth aspect, the application provides a UFS device including a receiving module and a processing module. The receiving module is configured to receive an operation command from a universal flash storage (UFS) host controller, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS). The UPIU frame header includes a total length field of the EHS, the total length field of the EHS indicates that the length of the EHS is not zero, and the EHS indicates storage addresses respectively corresponding to the multiple EHS operation commands. The processing module is configured to determine, based on the operation command, storage addresses respectively corresponding to the multiple EHS operation commands, and perform corresponding memory operations on a storage medium at the storage addresses respectively corresponding to the multiple EHS operation commands.

[0040] In one possible implementation, the UPIU frame header contains a number of EHS operation commands.

[0041] In one possible implementation, the UPIU frame header includes a starting logical block address and total data length corresponding to multiple EHS operation commands.

[0042] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, multiple write operations, or multiple erase operations. The storage addresses corresponding to the multiple EHS operation commands may be consecutive or non-consecutive.

[0043] In one possible implementation, the EHS includes a starting logical block address and a data length corresponding to each of a number of EHS operation commands.

[0044] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, and the storage addresses corresponding to the multiple EHS operation commands are consecutive.

[0045] In one possible implementation, the EHS includes physical page numbers that correspond to each of a number of EHS operation commands.

[0046] According to a sixth aspect, the application provides a computer-readable storage medium comprising a computer program which, when executed on a computer, enables the computer to carry out a method according to any implementation of the first aspect. [Brief description of the drawings]

[0047] [Figure 1] 1 is a flowchart showing an example of accelerated readout in the related art. [Diagram 2] FIG. 1 is a diagram of an example configuration of a hardware system according to the present application. [Diagram 3] 1 is a flow chart of an example of a method for performing memory operations according to the present application. [Figure 4] FIG. 2 is a diagram of an example structure of an action command according to the present application. [Diagram 5] FIG. 2 is a diagram of an example structure of an action command according to the present application. [Figure 6] 4 is a flow chart of an example of a method for performing a read operation according to the present application. [Figure 7] 1 is a schematic diagram of an example of a UFS host control device according to the present application; [Figure 8] 1 is a schematic diagram of an example of a UFS device control device according to the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] In order to make the purpose, technical solution and advantages of this application clearer, the following will clearly and fully describe the technical solution of this application with reference to the accompanying drawings of this application. It is obvious that the described embodiments are only a part, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative efforts also fall within the protection scope of this application.

[0049] In this specification, embodiments, claims, and accompanying drawings of this application, the terms "first", "second", and the like are merely intended to distinguish and describe, and should not be understood as indicating or implying relative importance or sequence. Also, the terms "comprise", "have", and variations thereof are intended to cover a non-exclusive inclusion, for example, including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to the literally recited steps or units, but may include other steps or units not literally recited, or other steps or units inherent in such a process, method, product, or apparatus.

[0050] It should be understood that in this application, "at least one" means one or more, and "plurality" means two or more. The term "and / or" is used to describe an association relationship between related objects and indicates that three relationships may exist. For example, "A and / or B" may represent three cases: only A is present, only B is present, and both A and B are present, where A and B may be singular or plural. The character " / " generally indicates an "or" relationship between related objects. "At least one of" or similar expressions may indicate any combination of the following, including any combination of one or more of the following. For example, at least one of a, b, or c may indicate a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c may be singular or plural.

[0051] Fig. 1 is a flow chart showing an example of accelerated read in the related art. In step 1 shown in Fig. 1, when the UFS host controller finds that all wide-range IO reads hit the entry, it sends a dedicated write buffer DPIU, prepare for transfer, and data out command sequence, and also sends a read operation command for multiple physical page numbers (PPN). In step 2, the UFS host controller sends an accelerated read command, triggering the UFS device controller to perform continuous accelerated read return of data at once.

[0052] However, the above-mentioned accelerated read operation requires two steps to complete, and a total of at least eight UPIU command interactions are performed. When the functional operations to be completed are relatively complex, the performance advantages of UFS technology cannot be fully utilized. In particular, the command interaction is a simultaneous command interaction of multiple slots, and it is necessary to separately add command ownership marks to the UFS host controller and the UFS device controller in order to avoid the complex processing and the high overhead of the command interaction caused by command failure.

[0053] To solve the above technical problems, this application provides a method for performing a memory operation, which is illustrated by the following embodiments.

[0054] 2 is a diagram of an example of a hardware system according to the present application. As shown in FIG. 2, a UFS host includes an application, a UFS driver, a UFS host controller, and an interface circuit. A UFS device includes a storage medium (user storage), a UFS device controller, and an interface circuit.

[0055] Commands and data between the UFS host and the UFS device are transmitted through the interface circuits of the UFS host and the UFS device. The UFS host controller is responsible for generating operation commands, and the UFS device controller is responsible for analyzing the commands and controlling the execution of the memory operations.

[0056] Based on the above structure, in the related art, the UFS host controller detects a command transmitted between the UFS host controller and the UFS device controller. When the length of the command exceeds a specified length (e.g., 4KB), the UFS host controller executes corresponding logic control to truncate the command, and only 4KB of the command is prepared for transmission to the UFS device controller. The remaining part can be sent in the next command or immediately discarded. The UFS device controller can also generate a 4KB command or data by executing the same method. However, in this application, the above specified length is extended so that the UFS host controller and the UFS device controller can support the transmission of NKB of commands or data, where N is greater than 4, and 32B of the NKB can be used for the UPIU frame header, and the remaining length (NKB-32B) can be used for the extend header segment (EHS). The EHS with a length of NKB-32B is not available in the related art. Therefore, the command transmitted between the UFS host controller and the UFS device controller can carry more information. Correspondingly, the UPIU frame header includes an EHS total length field, which indicates that the EHS length is not zero.

[0057] It should be noted that the UFS host and the UFS device in this application may be integrated into the same electronic device with memory capability to jointly complete memory operations. Alternatively, the UFS host and the UFS device may be separately located on different electronic devices. For example, the UFS host is located on a user device such as a mobile phone or tablet computer, and the UFS device is located on a memory such as a hard disk, a register, or a flash memory.

[0058] 3 is a flow chart of an example of a method for performing a memory operation according to the present application. As shown in FIG. 3, the method in this embodiment can be jointly performed by the above-mentioned UFS host controller and UFS device controller. The method for performing a memory operation can include the following steps:

[0059] Step 301: The UFS host controller generates an operation command.

[0060] As mentioned above, the operation command in this application includes a UPIU frame header and an EHS, and the total length of the command is N KB (N>4). The length of the UPIU frame header is a first length (32B), and the total length of the EHS is N KB-32B. Thus, compared with the operation command in the current technology, the operation command in this application can carry more information. Based on this, when multiple EHS operation commands need to be executed, the UFS host controller can send multiple EHS operation commands to the UFS device controller through one operation command.

[0061] The UPIU frame header includes an EHS total length field. The EHS total length field indicates that the length of the EHS is not 0, and the EHS indicates storage addresses corresponding to multiple EHS operation commands, respectively. The multiple EHS operation commands can indicate multiple read operations, multiple write operations, or multiple erase operations, i.e., multiple EHS operation commands that are all read operations, all write operations, or all erase operations can be sent to the UFS device controller at one time through one operation command.

[0062] The maximum length of the EHS can be N KB-32B, that is, the total length of the EHS is equal to or less than N KB-32B. The specific value of the total length can be determined based on the length of data actually written to the EHS. A storage address corresponding to any one of a plurality of EHS operation commands can be expressed in the form of a starting address of a certain data length. For example, the memory operation is a read operation, the starting address corresponding to the read operation is the starting address of data to be read in a storage area of ​​the memory, and the data length is the length of the data to be read starting from the starting address.

[0063] Step 302: The UFS host controller sends an operation command to the UFS device controller.

[0064] The UFS host controller obtains storage addresses corresponding to the plurality of EHS operation commands, respectively. The operation commands sent to the UFS device controller can carry related information to indicate the storage addresses corresponding to the plurality of EHS operation commands, respectively.

[0065] In one possible implementation, the UPIU frame header further includes a number of EHS operation commands. The EHS includes a start address and a data length of a logical block address (LBA) corresponding to each of the EHS operation commands. That is, the EHS includes a number of LBAs, and each LBA corresponds to a data length.

[0066] In this embodiment, the storage addresses corresponding to the multiple EHS operation commands are contiguous or discontinuous. For example, the multiple EHS operation commands indicate multiple read operations. Take read operation 1, read operation 2, and read operation 3 as an example, read operation 1 corresponds to LBA1 and data length 1, read operation 2 corresponds to LBA2 and data length 2, and read operation 3 corresponds to LBA3 and data length 3. LBA1, LBA2, and LBA3 may be contiguous, that is, the storage areas of data read by read operation 1, read operation 2, and read operation 3 are adjacent in memory. LBA1, LBA2, and LBA3 may be discontinuous, that is, the storage areas of data read by read operation 1, read operation 2, and read operation 3 are not adjacent in memory and are separated from each other. It should be understood that the LBAs corresponding to the multiple EHS operation commands respectively may instead be some LBAs contiguous and other LBAs discontinuous.

[0067] For example, Figure 4 is a diagram of an example structure of an operation command according to this application. As shown in Figure 4, the UPIU frame header in the operation command occupies a total of 32B from Bytes 0 to 31. Byte 8 is filled with an EHS length (Total EHS Length), e.g., 32B, and Byte 9 is filled with the number of EHS operation commands (Total EHS Num), e.g., 4.

[0068] The EHS in the operation command occupies 32 bytes. Bytes 0-3 are filled with LBA0 of the first memory operation, and bytes 4-7 are filled with LEN0 of the first memory operation. Bytes 8-11 are filled with LBA1 of the second memory operation, and bytes 12-15 are filled with LEN1 of the second memory operation. Bytes 16-19 are filled with LBA2 of the third memory operation, and bytes 20-23 are filled with LEN2 of the third memory operation. Bytes 24-27 are filled with LBA3 of the fourth memory operation, and bytes 28-31 are filled with LEN3 of the fourth memory operation. In this embodiment, the row number in the EHS represents the index number of the first byte in a group of four bytes, and the column number represents the offset of the index number of each byte in the group of bytes relative to the index number of the first byte. It is noted that the index numbers of the bytes in the EHS may alternatively be represented in other ways. This is not a particular limitation in this application.

[0069] In one possible implementation, the UPIU frame header further includes a first logical block address and a total data length corresponding to a plurality of EHS operation commands. The EHS includes a physical page number (PPN) corresponding to each of the plurality of EHS operation commands.

[0070] In this embodiment, the storage addresses corresponding to the multiple EHS operation commands are consecutive, and the start address of the PPN corresponding to the multiple EHS operation commands corresponds to the start address of the LBA corresponding to the multiple EHS operation commands. Based on this, only the start address of the LBA corresponding to the multiple EHS operation commands may be embedded in the UPIU frame header. Thus, the LBA having the total data length corresponding to the multiple EHS operation commands can indicate the storage area of ​​all the data processed by the multiple EHS operation commands in the memory. In addition, only when a read operation is performed can the UFS host controller obtain the correspondence between the LBA and the PPN. This is because the data has already been stored in the memory, the storage location of the data is determined, and therefore the correspondence between the LBA and the PPN can be established.

[0071] For example, Figure 5 is a diagram of an example structure of an operation command according to this application. As shown in Figure 5, the UPIU frame header in the operation command occupies Bytes 0 to 31, a total of 32B. Byte 8 is filled with the Total EHS Length, which may be, for example, 32B. Bytes 18 to 21 are filled with the first logical block address (LBA[3]-LBA[0]) corresponding to multiple read operations. Bytes 26 to 29 are filled with the total data length (Length[3]-Length[0]) corresponding to multiple read operations.

[0072] The EHS in the operation command occupies 32 bytes. Bytes 0-3 are filled with PPN0 (PPN0[3]-PPN0[0]) of the first read operation. Bytes 4-7 are filled with PPN1 (PPN1[3]-PPN1[0]) of the second read operation. Bytes 8-11 are filled with PPN2 (PPN2[3]-PPN2[0]) of the third read operation. Bytes 12-15 are filled with PPN3 (PPN3[3]-PPN3[0]) of the fourth read operation.

[0073] FIG. 6 is a flow chart of an example of a method for performing a read operation according to this application. As shown in FIG. 6, the UFS host controller sends a read operation command to the UFS device controller. The read operation command includes a UPIU frame header and an EHS, which includes addresses of data to be read by multiple read operations in the storage area of ​​the memory. After obtaining the stored data from those addresses, the UFS device controller returns the data to the UFS host controller by using a Data In UPIU command, and the whole read operation is completed. It can be seen that, compared with the procedure shown in FIG. 1, in the method in this application, only one operation command is needed to request to read data of multiple addresses, and the command interaction is reduced. In addition, since the UFS host controller and the UFS device controller can support a larger amount of data to be transmitted, when the UFS device controller receives and returns data again, more data can be carried in one command. Therefore, the return command is also reduced, and the overall command overhead is reduced.

[0074] Step 303: The UFS device controller determines storage addresses corresponding to the multiple EHS operation commands respectively based on the operation commands.

[0075] After receiving the operation command, the UFS device controller can extract information from the corresponding bytes based on the format of the operation command, including the number of the multiple EHS operation commands, the total length of the EHS, and the storage address and data length corresponding to each of the multiple EHS operation commands.

[0076] In one possible implementation, according to the structure shown in FIG. 4, the UFS device controller extracts the length of the EHS from byte 8 in the UPIU frame header and the number of EHS operation commands from byte 9. LBA0 of the first memory operation is extracted from bytes 0-3 of the EHS, and LEN0 of the first memory operation is extracted from bytes 4-7. LBA1 of the second memory operation is extracted from bytes 8-11, and LEN1 of the second memory operation is extracted from bytes 12-15. LBA2 of the third memory operation is extracted from bytes 16-19, and LEN2 of the third memory operation is extracted from bytes 20-23. LBA3 of the fourth memory operation is extracted from bytes 24-27, and LEN3 of the fourth memory operation is extracted from bytes 28-31.

[0077] In one possible implementation, according to the structure shown in FIG. 5, the UFS device controller extracts the EHS length from byte 8 in the UPIU frame header, extracts the first LBA (LBA[3]-LBA[0]) corresponding to the multiple read operations from bytes 18-21, and extracts the total data length (Length[3]-Length[0]) corresponding to the multiple read operations from bytes 26-29. The PPN0 (PPN0[3]-PPN0[0]) of the first read operation is extracted from bytes 0-3 in the EHS. The PPN1 (PPN1[3]-PPN1[0]) of the second read operation is extracted from bytes 4-7 in the EHS. The PPN2 (PPN2[3]-PPN2[0]) of the third read operation is extracted from bytes 8-11 in the EHS. The PPN3 of the fourth read operation (PPN3[3]-PPN3[0]) is extracted from bytes 12-15 in the EHS.

[0078] Based on the above information, the UFS device controller can determine the storage area in memory for the data to be processed by each memory operation.

[0079] Step 304: The UFS device controller performs corresponding memory operations at storage addresses respectively corresponding to the multiple EHS operation commands.

[0080] The UFS device controller performs corresponding operations on the multiple storage areas determined in the above steps based on the operation type indicated in the operation command, e.g., a read operation, a write operation, or an erase operation. When the memory operation is a read operation, the UFS device controller retrieves stored data from the multiple indicated storage areas. When the memory operation is a write operation, the UFS device controller writes data sent by the UFS host controller to the multiple indicated storage areas. When the memory operation is an erase operation, the UFS device controller erases data from the multiple indicated storage areas.

[0081] Step 305: The UFS device controller returns the processing result to the UFS host controller.

[0082] When the memory operation is a read operation, the UFS device controller returns the read data to the UFS host controller. When the memory operation is a write operation, the UFS device controller returns a write success response to the UFS host controller. When the memory operation is an erase operation, the UFS device controller returns an erase success response to the UFS host controller.

[0083] In addition to the above fields, the operation command in this application may also include other fields. For example, the UPIU frame header also includes an index field (xx00 0001b) and a flag field (Flag) of the operation command. These fields may follow the relevant rules in the protocol. This is not particularly limited in this application.

[0084] In this application, based on the expanded operation command, one operation command can carry storage addresses and data lengths corresponding to multiple EHS operation commands, respectively, and only a few command interactions are required to request to execute memory operations for multiple addresses, thereby reducing command interactions. In addition, since the UFS host controller and the UFS device controller can support a larger amount of data to be transmitted, more data can be carried in one command when the UFS device controller receives and returns data again. Therefore, the return command is also reduced, and the overall command overhead is reduced. During the execution of memory operations, each command needs to be scheduled by the block layer (Block) and transmitted by the driver layer (Driver) and physical layer. After the method in this application is used, IO aggregation can be performed for multiple EHS operation commands, and the corresponding processes, such as scheduling and transmission, can be combined, thereby further reducing the processing procedures of memory operations and improving memory operation efficiency.

[0085] 7 is a schematic diagram of an example of a configuration of a UFS host control device according to this application. As shown in FIG. 7, the device in this embodiment can be the UFS host controller in the above-mentioned embodiment. The device includes a processing module 701 and a sending module 702.

[0086] The processing module 701 is configured to generate an operation command, where the operation command includes a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS). The UPIU frame header includes a total length field of the EHS, where the total length field of the EHS indicates that the length of the EHS is not zero, and the EHS indicates a storage address corresponding to each of the multiple EHS operation commands. The sending module 702 is configured to send the operation command to a universal flash storage (UFS) device controller.

[0087] In one possible implementation, the UPIU frame header contains a number of EHS operation commands.

[0088] In one possible implementation, the UPIU frame header includes a starting logical block address and total data length corresponding to multiple EHS operation commands.

[0089] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, multiple write operations, or multiple erase operations. The storage addresses corresponding to the multiple EHS operation commands may be consecutive or non-consecutive.

[0090] In one possible implementation, the EHS includes a starting logical block address and a data length corresponding to each of a number of EHS operation commands.

[0091] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, and the storage addresses corresponding to the multiple EHS operation commands are consecutive.

[0092] In one possible implementation, the EHS includes physical page numbers that correspond to each of a number of EHS operation commands.

[0093] The apparatus in this embodiment can be configured to implement the technical solution of the method embodiment shown in FIG. 3, and the implementation principle and technical effect are similar, and the details will not be described again here.

[0094] 8 is a schematic diagram of an example of a configuration of a UFS device control device according to this application. As shown in FIG. 8, the device in this embodiment may be the UFS device controller in the above-mentioned embodiment. The device includes a receiving module 801 and a processing module 802.

[0095] The receiving module 801 is configured to receive an operation command from a universal flash storage (UFS) host controller, where the operation command includes a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS). The UPIU frame header includes a total length field of the EHS, where the total length field of the EHS indicates a length of the EHS is not zero, and the EHS indicates storage addresses respectively corresponding to the multiple EHS operation commands. The processing module 802 is configured to determine, based on the operation command, storage addresses respectively corresponding to the multiple EHS operation commands, and perform corresponding memory operations on a storage medium at the storage addresses respectively corresponding to the multiple EHS operation commands.

[0096] In one possible implementation, the UPIU frame header contains a number of EHS operation commands.

[0097] In one possible implementation, the UPIU frame header includes a starting logical block address and total data length corresponding to multiple EHS operation commands.

[0098] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, multiple write operations, or multiple erase operations. The storage addresses corresponding to the multiple EHS operation commands may be consecutive or non-consecutive.

[0099] In one possible implementation, the EHS includes a starting logical block address and a data length corresponding to each of a number of EHS operation commands.

[0100] In one possible implementation, the multiple EHS operation commands indicate multiple read operations, and the storage addresses corresponding to the multiple EHS operation commands are consecutive.

[0101] In one possible implementation, the EHS includes physical page numbers that correspond to each of a number of EHS operation commands.

[0102] The apparatus in this embodiment can be configured to implement the technical solution of the method embodiment shown in FIG. 3, and the implementation principle and technical effect are similar, and the details will not be described again here.

[0103] In the implementation process, the steps in the above-mentioned method embodiments can be implemented by using hardware integrated logic circuits in a processor or by using instructions in the form of software. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The general-purpose processor can be a microprocessor, or the processor can be any conventional processor or the like. The steps of the method disclosed in the embodiments of this application can be directly presented as being performed and completed by a hardware encoding processor, or can be performed and completed by a combination of hardware and software modules in the encoding processor. The software modules can be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is placed in the memory, and the processor reads the information in the memory and completes the steps in the above-mentioned method in combination with the processor's hardware.

[0104] The memory in the above-described embodiments may be volatile or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM) used as an external cache. By way of example and not limitation, numerous forms of RAM may be used, such as, for example, static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchlink dynamic random access memory (synchlink DRAM, SLDRAM), and direct rambus dynamic random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein includes, but is not limited to, these and any other suitable types of memory.

[0105] Those skilled in the art can recognize that, in combination with the examples described in the embodiments disclosed in this application, the units and algorithm steps can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed by hardware or computer software depends on the specific applications and design constraints of these technical solutions. Those skilled in the art can implement the described functions using different methods for each specific application, but these implementations should not be considered as going beyond the scope of this application.

[0106] It can be clearly understood by those skilled in the art that, for the sake of simple and concise description, the detailed operation processes of the above-mentioned systems, devices, and units are referred to the corresponding processes in the foregoing method embodiments, and the details will not be described again here.

[0107] In some embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiment described is merely an example. For example, the division into units is merely a logical functional division, and may be a different division in actual implementation. For example, multiple units or components may be combined or integrated into other systems, or some features may be ignored or not implemented. In addition, the illustrated or described mutual couplings, direct couplings, or communication connections may be implemented by using some interfaces. Indirect couplings or communication connections between devices or units may be implemented in electrical, mechanical, or other forms.

[0108] The units described as separate parts may or may not be physically separated, and the parts illustrated as units may or may not be physical units, located in one location or distributed over multiple network units. Some or all of the units may be selected based on the actual requirements to achieve the objectives of the solution of the embodiment.

[0109] In addition, multiple functional units in the embodiments of this application may be integrated into a single processing unit, each of which may exist physically independently, or two or more units may be integrated into a single unit.

[0110] When functions are implemented in the form of a software functional unit and sold or used as an independent product, those functions may be stored in a computer-readable storage medium. Based on such understanding, the technical solution in this application may be essentially implemented in the form of a software product, or a part of the technical solution may be implemented in the form of a software product. The computer software product is stored in a storage medium and includes some instructions for instructing a computer device (personal computer, server, network device, or the like) to execute all or part of the steps in the method in the embodiment of this application. The aforementioned storage medium includes any medium that can store program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or a compact disk.

[0111] The above description is merely a specific implementation of this application, and is not intended to limit the scope of protection of this application. Any modifications or replacements that a person skilled in the art can easily think of within the technical scope disclosed in this application shall fall within the scope of protection of this application. Therefore, the scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. A method for performing a memory operation, comprising: generating an operation command, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; sending the operational command to a Universal Flash Storage (UFS) device controller; having the UPIU frame header includes a number of the EHS operation commands; method.

2. A method for performing a memory operation, comprising: generating an operation command, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; sending the operational command to a Universal Flash Storage (UFS) device controller; having The UPIU frame header includes a first logical block address and a total data length corresponding to the plurality of EHS operation commands. method.

3. A method for performing a memory operation, comprising: generating an operation command, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; sending the operational command to a Universal Flash Storage (UFS) device controller; having the plurality of EHS operation commands indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations, and the storage addresses corresponding to the plurality of EHS operation commands are consecutive or non-consecutive; The EHS includes a first logical block address and a data length corresponding to each of the plurality of EHS operation commands. method.

4. A method for performing a memory operation, comprising: generating an operation command, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; sending the operational command to a Universal Flash Storage (UFS) device controller; having the plurality of EHS operation commands indicate a plurality of read operations, and the storage addresses corresponding to the plurality of EHS operation commands are consecutive; the EHS includes physical page numbers corresponding to the plurality of EHS operation commands, method.

5. A method for performing a memory operation, comprising: receiving an operation command from a Universal Flash Storage (UFS) host controller, the operation command including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extended Header Segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; determining the storage addresses corresponding to the plurality of EHS operation commands, respectively, based on the operation commands; performing corresponding memory operations at the storage addresses corresponding to each of the plurality of EHS operation commands; having the UPIU frame header includes a number of the EHS operation commands; method.

6. A method for performing a memory operation, comprising: receiving an operation command from a Universal Flash Storage (UFS) host controller, the operation command including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extended Header Segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; determining the storage addresses corresponding to the plurality of EHS operation commands, respectively, based on the operation commands; performing corresponding memory operations at the storage addresses corresponding to each of the plurality of EHS operation commands; having The UPIU frame header includes a first logical block address and a total data length corresponding to the plurality of EHS operation commands. method.

7. A method for performing a memory operation, comprising: receiving an operation command from a Universal Flash Storage (UFS) host controller, the operation command including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extended Header Segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; determining the storage addresses corresponding to the plurality of EHS operation commands, respectively, based on the operation commands; performing corresponding memory operations at the storage addresses corresponding to each of the plurality of EHS operation commands; having the plurality of EHS operation commands indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations, and the storage addresses corresponding to the plurality of EHS operation commands are consecutive or non-consecutive; The EHS includes a first logical block address and a data length corresponding to each of the plurality of EHS operation commands. method.

8. A method for performing a memory operation, comprising: receiving an operation command from a Universal Flash Storage (UFS) host controller, the operation command including a Universal Flash Storage Protocol Information Unit (UPIU) frame header and an Extended Header Segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; determining the storage addresses corresponding to the plurality of EHS operation commands, respectively, based on the operation commands; performing corresponding memory operations at the storage addresses corresponding to each of the plurality of EHS operation commands; having the plurality of EHS operation commands indicate a plurality of read operations, and the storage addresses corresponding to the plurality of EHS operation commands are consecutive; the EHS includes physical page numbers corresponding to the plurality of EHS operation commands, method.

9. A universal flash storage (UFS) host controller having a processor and an interface circuit, comprising: The processor is configured to generate an operation command, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; the interface circuitry is configured to send the operational command to a Universal Flash Storage (UFS) device controller; the UPIU frame header includes a number of the EHS operation commands; controller.

10. A universal flash storage (UFS) host controller having a processor and an interface circuit, comprising: The processor is configured to generate an operation command, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; the interface circuitry is configured to send the operational command to a Universal Flash Storage (UFS) device controller; The UPIU frame header includes a first logical block address and a total data length corresponding to the plurality of EHS operation commands. controller.

11. A universal flash storage (UFS) host controller having a processor and an interface circuit, comprising: The processor is configured to generate an operation command, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; the interface circuitry is configured to send the operational command to a Universal Flash Storage (UFS) device controller; the plurality of EHS operation commands indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations, and the storage addresses corresponding to the plurality of EHS operation commands are consecutive or non-consecutive; The EHS includes a first logical block address and a data length corresponding to each of the plurality of EHS operation commands. controller.

12. A universal flash storage (UFS) host controller having a processor and an interface circuit, comprising: The processor is configured to generate an operation command, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; the interface circuitry is configured to send the operational command to a Universal Flash Storage (UFS) device controller; the plurality of EHS operation commands indicate a plurality of read operations, and the storage addresses corresponding to the plurality of EHS operation commands are consecutive; the EHS includes physical page numbers corresponding to the plurality of EHS operation commands, controller.

13. A universal flash storage (UFS) device having a processor, an interface circuit, and a storage medium, comprising: the interface circuit is configured to receive an operation command from a universal flash storage (UFS) host controller, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; the processor is configured to determine, based on the operation commands, the storage addresses corresponding to each of the plurality of EHS operation commands; and to perform corresponding memory operations on the storage medium at the storage addresses corresponding to each of the plurality of EHS operation commands; the UPIU frame header includes a number of the EHS operation commands; device.

14. A universal flash storage (UFS) device having a processor, an interface circuit, and a storage medium, comprising: the interface circuit is configured to receive an operation command from a universal flash storage (UFS) host controller, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; the processor is configured to determine, based on the operation commands, the storage addresses corresponding to each of the plurality of EHS operation commands; and to perform corresponding memory operations on the storage medium at the storage addresses corresponding to each of the plurality of EHS operation commands; The UPIU frame header includes a first logical block address and a total data length corresponding to the plurality of EHS operation commands. device.

15. A universal flash storage (UFS) device having a processor, an interface circuit, and a storage medium, comprising: the interface circuit is configured to receive an operation command from a universal flash storage (UFS) host controller, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; the processor is configured to determine, based on the operation commands, the storage addresses corresponding to each of the plurality of EHS operation commands; and to perform corresponding memory operations on the storage medium at the storage addresses corresponding to each of the plurality of EHS operation commands; the plurality of EHS operation commands indicate a plurality of read operations, a plurality of write operations, or a plurality of erase operations, and the storage addresses corresponding to the plurality of EHS operation commands are consecutive or non-consecutive; The EHS includes a first logical block address and a data length corresponding to each of the plurality of EHS operation commands. device.

16. A universal flash storage (UFS) device having a processor, an interface circuit, and a storage medium, comprising: the interface circuit is configured to receive an operation command from a universal flash storage (UFS) host controller, the operation command including a universal flash storage protocol information unit (UPIU) frame header and an extended header segment (EHS), the UPIU frame header including a total length field of the EHS, the total length field of the EHS indicating a length of the EHS that is not zero, the EHS indicating storage addresses respectively corresponding to a plurality of EHS operation commands; the processor is configured to determine, based on the operation commands, the storage addresses corresponding to each of the plurality of EHS operation commands; and to perform corresponding memory operations on the storage medium at the storage addresses corresponding to each of the plurality of EHS operation commands; the plurality of EHS operation commands indicate a plurality of read operations, and the storage addresses corresponding to the plurality of EHS operation commands are consecutive; the EHS includes physical page numbers corresponding to the plurality of EHS operation commands, device.

17. A computer readable storage medium comprising a computer program, which when executed on a computer enables the computer to carry out the method according to any one of claims 1 to 8.

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