Stabilized power supply circuit

Abstract

To make it possible to improve phase compensation characteristics including a light load period with less output current.SOLUTION: A stabilized power supply circuit outputs an output voltage that is stabilized so that the difference between a reference voltage and a voltage obtained by dividing the output voltage becomes zero, and comprises: a PMOS-type transistor MP1 that has a source connected with a first power supply terminal 1 and obtains the output voltage from a drain; a PMOS-type transistor MP2 in which the transistor MP1 and a source are connected with each other; a resistance R3 for phase compensation that is provided between a drain of the transistor MP2 and the ground; a capacitor C1 for phase compensation that is connected with the transistor MP2 side of the resistance R3; and a bias circuit 9 that supplies a bias voltage to a gate of the transistor MP2. A voltage of the resistance R3 is superimposed on the voltage obtained by dividing the output voltage through the capacitor C1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a stabilized power supply circuit capable of supplying a stabilized output voltage. [Background technology]

[0002] As a conventional example of a stabilized power supply circuit composed of a regulator circuit etc., for example, Patent Document 1 discloses a stabilized power supply circuit in which a phase compensation resistor is provided between the output terminal of an output transistor and the output terminal of the stabilized power supply circuit. In this stabilized power supply circuit, a phase compensation signal generated by the phase compensation resistor is fed back to a comparison amplifier means, so that a low ESR capacitor can be used as the output stabilizing capacitor without inserting a resistor equivalent to the ESR. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-032133 A Summary of the Invention [Problem to be solved by the invention]

[0004] A stabilized power supply circuit has a phase compensation circuit to stabilize the output, but obtaining a stable output voltage even in the region where the output current is small is a particular challenge. Recently, the current consumption of stabilized power supply circuits has been reduced year by year in order to extend the operating time of battery-powered devices and other equipment equipped with stabilized power supply circuits. Under these circumstances, there is a demand for improved phase compensation characteristics, especially during light loads when the output current is small.

[0005] An object of the present invention is to provide a stabilized power supply circuit capable of improving phase compensation characteristics, including during light load periods when the output current is small. [Means for solving the problem]

[0006] The present invention is a stabilized power supply circuit that outputs an output voltage stabilized such that the difference between a reference voltage and a voltage obtained by dividing an output voltage becomes zero, the stabilized output voltage being outputted by a first transistor of a first conductivity type having a source connected to a first power supply and obtaining the output voltage from a drain thereof, a second transistor of the first conductivity type having a source connected to the first transistor, a phase compensation resistor element provided between the drain of the second transistor and a ground or a second power supply, a phase compensation capacitor connected to the second transistor side of the phase compensation resistor element, and a phase compensation capacitor connected to the gate of the second transistor. , which is a voltage offset with respect to the gate voltage of the first transistor a bias circuit for supplying a bias voltage, and a voltage of the phase compensation resistor element is superimposed on a voltage obtained by dividing the output voltage via the phase compensation capacitor. the bias circuit includes a third transistor of a second conductivity type and a constant current source, the third transistor having a gate connected to the gate of the first transistor, a drain connected to the source of the first transistor, and a source connected to the gate of the second transistor and the constant current source; Provide a stabilized power supply circuit.

[0007] The present invention also provides the above-mentioned stabilized power supply circuit, comprising: a voltage divider circuit having one end connected to the drain of the first transistor and dividing the output voltage; and an error amplifier supplying a voltage proportional to a difference between the divided voltage of the output voltage and the reference voltage to a gate of the first transistor, wherein the phase compensation capacitor has one end connected to the drain of the second transistor and the phase compensation resistive element, and the other end connected to a common connection point of the voltage divider circuit.

[0009] The present invention also provides a method for producing a semiconductor device comprising the steps of: a first transistor of a first conductivity type having a source connected to a first power supply and a drain from which the output voltage is obtained; a second transistor of a first conductivity type having a source connected to the first transistor; a phase compensation resistor element provided between the drain of the second transistor and ground or a second power supply; a phase compensation capacitor connected to the second transistor side of the phase compensation resistor element; and a bias circuit that supplies a bias voltage to the gate of the second transistor, the bias voltage being a voltage offset with respect to the gate voltage of the first transistor, wherein the voltage of the phase compensation resistor element is superimposed on a voltage obtained by dividing the output voltage via the phase compensation capacitor; The bias voltage supplied by the bias circuit is Out The present invention provides a stabilized power supply circuit that increases in response to an increase in output current.

[0010] The present invention also provides the above-mentioned stabilized power supply circuit, wherein the bias circuit includes a third transistor of a second conductivity type, a constant current source, and a current source connected in parallel to the constant current source and supplying a current proportional to the output current, and the third transistor has a gate connected to the gate of the first transistor, a drain connected to the source of the first transistor, and a source connected to the gate of the second transistor, the constant current source, and the current source. Effect of the Invention

[0011] According to the present invention, it is possible to provide a stabilized power supply circuit capable of improving phase compensation characteristics, including during light load periods when the output current is small. [Brief description of the drawings]

[0012] [Figure 1] 1 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a first embodiment. [Diagram 2] 11 is a characteristic diagram showing an example of a change in drain current characteristic in a transistor MP2 depending on the presence or absence of a bias voltage. FIG. [Diagram 3] 1 is a circuit diagram showing a specific configuration example of a stabilized power supply circuit according to a first embodiment. [Figure 4] 3 is a characteristic diagram illustrating an example of gain and phase characteristics in the stabilized power supply circuit of the first embodiment. FIG. [Diagram 5] 4 is a characteristic diagram showing an example of a phase margin characteristic with respect to an output current in the stabilized power supply circuit of the first embodiment. FIG. [Figure 6] FIG. 4 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a second embodiment. [Figure 7] 10 is a characteristic diagram showing an example of a change in drain current characteristic due to the presence or absence of a bias voltage in a transistor MP2 and due to an increase in the bias voltage. [Figure 8] FIG. 11 is a circuit diagram showing a specific configuration example of a stabilized power supply circuit according to the second embodiment. [Figure 9] 10 is a characteristic diagram showing an example of a phase margin characteristic with respect to an output current in the stabilized power supply circuit according to the second embodiment. FIG. [Figure 10] FIG. 1 is a circuit diagram showing a configuration of a stabilized power supply circuit of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a specifically disclosed embodiment of a stabilized power supply circuit according to the present invention (hereinafter, referred to as the present embodiment) will be described in detail with reference to the drawings.

[0014] (Background to the present embodiment) First, an example of a conventional stabilized power supply circuit will be described as a comparative example.

[0015] Fig. 10 is a circuit diagram showing the configuration of a stabilized power supply circuit of a comparative example. Fig. 6 shows a configuration example of a power supply circuit (hereinafter referred to as an "LDO regulator circuit") that is capable of low saturation operation (LDO (Low Drop-Out)) and is configured to output a stabilized voltage.

[0016] The stabilized power supply circuit 50 has a power supply terminal 51, an output terminal 53, a reference voltage source 55, and an error amplifier 56. A power supply voltage VDD is applied to the power supply terminal 51, and an output voltage VOUT is output from the output terminal 53 as the output of the power supply circuit. The error amplifier 56 has a reference voltage source 55 that supplies a reference voltage VREF connected to its inverting input terminal, and a gate of a PMOS type transistor Tr1 for output connected to its output terminal. The transistor Tr1 has a source connected to the power supply terminal 51, and a drain connected to the output terminal 53 and a voltage dividing circuit 57. The voltage dividing circuit 57 is composed of voltage dividing resistors R1 and R2 connected in series between the output terminal 53 and ground, and a common connection point of the voltage dividing resistors R1 and R2 is connected to the non-inverting input terminal of the error amplifier 56.

[0017] The stabilized power supply circuit 50 is configured such that the difference between the reference voltage VREF of the reference voltage source 55 and the feedback signal voltage obtained by resistively dividing the output voltage VOUT using voltage-dividing resistors R1 and R2 is amplified by an error amplifier 56 and applied to an output transistor Tr1, thereby making the output voltage VOUT a predetermined value.

[0018] The output terminal of the error amplifier 56 is connected to the gates of the output transistor Tr1 and the phase compensation transistor Tr2. The drain of the transistor Tr2 is connected to ground via a phase compensation resistor R3. The phase compensation transistor Tr2 mirrors the drain current of the output transistor Tr1. A phase compensation capacitor C1 is connected between the connection point between the drain of the transistor Tr2 and the resistor R3 and the connection point between the voltage dividing resistors R1 and R2. The connection point between the voltage dividing resistors R1 and R2 and the capacitor C1 is connected to the non-inverting input terminal of the error amplifier 56. A stabilization capacitor CL having an equivalent series resistance ESR is connected between the output terminal 53 and ground. In addition, a load resistor RL as a circuit load of the stabilized power supply circuit 50 is connected to the output terminal 53.

[0019] In the stabilized power supply circuit 50, the capacitance of the phase compensation capacitor C1 is set to a value sufficiently smaller than that of the stabilizing capacitor CL, thereby preventing the occurrence of a phase lag up to high frequencies. In addition, a phase compensation signal generated by the phase compensation resistor R3 is applied to the non-inverting input terminal of the error amplifier 56 via the capacitor C1, together with a feedback signal voltage obtained by dividing the output voltage VOUT. This cancels out the phase lag due to the frequency characteristics at the non-inverting input terminal of the error amplifier 56, and acts to cancel out the pole generated by the stabilizing capacitor CL connected to the output terminal 53. Therefore, even if the equivalent series resistance ESR of the stabilizing capacitor CL is small and the zero point frequency determined by the capacitance value of the stabilizing capacitor CL and the resistance value of the equivalent series resistance ESR becomes a high frequency, the output voltage VOUT of the stabilized power supply circuit is prevented from becoming unstable.

[0020] In the configuration of the comparative example described above, a ceramic capacitor with a low equivalent series resistance ESR can be used as the output voltage stabilization capacitor CL under normal load conditions. However, under light load conditions with a small output current, the drain current of the output transistor Tr1 decreases, and the phase compensation transistor Tr2 has a smaller aspect ratio than the transistor Tr1, so that the transistor Tr2 operates in the subthreshold region. During subthreshold operation, the phase compensation transistor Tr2 cannot supply current to the phase compensation resistor R3, and therefore cannot apply a sufficient phase compensation signal, resulting in an insufficient phase compensation effect and possible oscillation.

[0021] In view of the above circumstances, this embodiment shows an example of the configuration of a stabilized power supply circuit that is capable of performing sufficient phase compensation even under a light load condition where the output current is small.

[0022] (First embodiment) 1 is a circuit diagram showing the configuration of a stabilized power supply circuit according to a first embodiment. In this embodiment, a power supply circuit configured to output a stabilized voltage is shown having a configuration that enables the use of a capacitor with a low equivalent series resistance as a capacitor for stabilizing the output voltage.

[0023] The stabilized power supply circuit 10 has a first power supply terminal (VDD) 1, an output terminal (VOUT) 3, a reference voltage source (VREF) 5, and an error amplifier (OP) 6. A power supply voltage VDD is applied to the first power supply terminal 1 as a high potential power supply, which is a first power supply. The output terminal 3 outputs an output voltage VOUT as an output of the power supply circuit. The error amplifier 6 has a reference voltage source 5 that supplies a reference voltage VREF connected to its inverting input terminal, and has a gate of a PMOS type transistor MP1, which is an output transistor, connected to its output terminal. The transistor MP1 corresponds to a first transistor of a first conductivity type, has a source connected to the first power supply terminal 1, and a drain connected to the output terminal 3 and a voltage dividing circuit 7, and obtains a predetermined output voltage from the drain. The voltage dividing circuit 7 is composed of voltage dividing resistors R1 and R2 connected in series between the output terminal 3 and ground, and a common connection point of the voltage dividing resistors R1 and R2 is connected to the non-inverting input terminal of the error amplifier 6, and divides the output voltage VOUT.

[0024] In the stabilized power supply circuit 10, the output voltage VOUT is resistively divided by voltage dividing resistors R1 and R2 and applied as a feedback signal voltage to the non-inverting input terminal of the error amplifier 6. The difference between the reference voltage VREF at the inverting input terminal and the feedback signal voltage is then amplified and output by the error amplifier 6, and applied to the gate of the output transistor MP1. As a result, the difference between the reference voltage and the feedback signal voltage is controlled to be zero, and the output voltage VOUT is configured to be stabilized to a predetermined value.

[0025] The stabilized power supply circuit 10 is provided with a PMOS-type transistor MP2 for phase compensation, the source of which is connected to that of the transistor MP1 for output, and is configured so that the transistor MP2 mirrors the drain current of the transistor MP1. The transistor MP2 corresponds to a second transistor of a first conductivity type. The output terminal of the error amplifier 6 is connected to the gate of the transistor MP1 for output and to the gate of the transistor MP2 for phase compensation via a bias circuit 9, which will be described later. The transistor MP2 for phase compensation has an aspect ratio smaller than that of the transistor MP1 for output. For example, the gate lengths of the transistors MP1 and MP2 are equal, and the ratio of the gate widths is set to MP1:MP2=n:1 (n>1). When no bias voltage is applied to the transistor MP2, the gate-source voltages of the transistors MP1 and MP2 are common, so that the drain current of the transistor MP2 is 1 / n of the drain current of the transistor MP1.

[0026] The drain of the transistor MP2 is connected to ground via a resistor R3 serving as a phase compensation resistor element. A capacitor C1 serving as a phase compensation capacitor is connected between the connection point between the drain of the transistor MP2 and the resistor R3 and the connection point between the voltage dividing resistors R1 and R2. The connection point between the voltage dividing resistors R1 and R2 and the capacitor C1 is connected to the non-inverting input terminal of the error amplifier 6. A stabilization capacitor CL having an equivalent series resistance ESR is connected between the output terminal 3 and ground. A load resistor RL serving as a circuit load of the stabilizing power supply circuit 10 is also connected to the output terminal 3.

[0027] In the stabilized power supply circuit 10 constituting an LDO regulator circuit, the pole frequency fp1 and the zero frequency fz1 generated at the output terminal are expressed by the following equations. fp1=1 / (2π×CL×RL) …(1) fz1=1 / (2π×CL×ESR) …(2)

[0028] In the above formula, CL is the capacitance value of the stabilization capacitor CL, RL is the resistance value of the load resistor RL, and ESR is the equivalent series resistance value of the stabilization capacitor CL.

[0029] As shown in formula (1), the frequency fp1 of the pole generated at the output terminal changes depending on the value of the load resistor RL, and moves to a lower frequency when the resistance value of the load resistor RL is large. On the other hand, since there is a pole generated in the error amplifier 6 and the output transistor MP1, if these two poles become close to each other, the feedback voltage may oscillate with a phase delay of 180 degrees. This phenomenon tends to occur when the two poles are in a low frequency band and a ceramic capacitor with a small equivalent series resistance ESR is used as the stabilization capacitor CL, as the zero point frequency fz1 becomes a high frequency band.

[0030] In the stabilized power supply circuit 10 of the first embodiment, the voltage generated across resistor R3 in accordance with the drain current of the phase compensation transistor MP2 acts as a phase compensation signal to perform phase compensation. The phase compensation signal from resistor R3 for phase compensation is superimposed on a feedback signal voltage obtained by dividing the output voltage VOUT by voltage dividing resistors R1 and R2 via capacitor C1, and is applied to the non-inverting input terminal of error amplifier 6.

[0031] The stabilized power supply circuit 10 of the first embodiment has a bias circuit 9 that applies a bias voltage VB between the gate of the phase compensation transistor MP2 and the output terminal of the error amplifier 6. The bias circuit 9 functions as a constant voltage source, and by applying the bias voltage VB to the gate of the phase compensation transistor MP2 from the bias circuit 9 to bias it in the forward direction, it becomes possible to cause a drain current of a predetermined amount or more to flow through the transistor MP2.

[0032] Fig. 2 is a characteristic diagram showing an example of the change in drain current characteristic of transistor MP2 depending on whether or not a bias voltage is applied. Fig. 2 shows the change in the drain current of transistor MP2 relative to the output current of the stabilized power supply circuit 10. When no bias voltage is applied, transistor MP2 has a drain current proportional to the output current, as shown by the characteristic indicated by the dashed line. When a bias voltage is applied, transistor MP2 has a large drain current in a region where the output current is small, as shown by the characteristic indicated by the solid line.

[0033] In the configuration of FIG. 1, the gate-source voltage of transistor MP1 is Vgs1, and the gate-source voltage of transistor MP2 is Vgs2. By providing a bias circuit 9 and applying a bias voltage VB, the voltage of the gate of the phase compensation transistor MP2 becomes lower than the voltage at the output terminal of the error amplifier 6. Specifically, the gate-source voltage Vgs2 of transistor MP2 becomes larger by the bias voltage VB, Vgs2=Vgs1+VB, and Vgs2>Vgs1, so that the gate voltage of transistor MP2 is lower than the gate voltage of transistor MP1. As a result, the drain current of the phase compensation transistor MP2 increases compared to when no bias voltage is applied.

[0034] The voltage at resistor R3 for phase compensation is set by the drain current of transistor MP2 for phase compensation and the resistance value of resistor R3. By applying bias voltage VB so that gate-source voltage Vgs2 of transistor MP2 is larger than gate-source voltage Vgs1 of transistor MP1, transistor MP2 is ensured to have a sufficient gate-source voltage even in a region where the drain current of transistor MP1 is small, and does not enter subthreshold operation.

[0035] In this embodiment, compared with the case where no bias voltage is applied, the voltage across the resistance R3 for phase compensation increases, and it acts to cancel out the pole (the above formula (1)) generated at the output terminal. At this time, even in a region where the output current is small, it becomes possible to generate a zero point by the capacitor C1 for phase compensation, and the phase delay can be canceled out. As a result, even when the load is light and the drain current of the output transistor MP1 is small, the frequency characteristics in the loop of non-inverting input terminal of error amplifier 6 → output terminal of error amplifier 6 → output transistor MP1 → output terminal 3 → resistance R1 → non-inverting input terminal of error amplifier 6 are improved. In this case, different from the case where no bias voltage is applied, the phase delay by 180° at a low frequency is suppressed, and even if the equivalent series resistance ESR of the stabilization capacitor CL is small, the output voltage VOUT is stably output.

[0036] Note that the values of the capacitor C1 for phase compensation, the resistance R3, and the voltage dividing resistors R1 and R2 of the voltage dividing circuit 7 are set to appropriate values so as to obtain a stable output voltage.

[0037] FIG. 3 is a circuit diagram showing a specific configuration example of the stabilization power supply circuit of the first embodiment. The stabilization power supply circuit 10A in FIG. 3 shows a specific circuit configuration example of the stabilization power supply circuit 10 and the bias circuit 9. Here, the description will be centered on the parts different from the configuration of the stabilization power supply circuit 10 shown in FIG. 1, and the same components will be denoted by the same reference numerals and the description thereof will be omitted.

[0038] The stabilization power supply circuit 10A includes a first power supply terminal (VDD) 1, a second power supply terminal (VSS) 2, an output terminal (VOUT) 3, a current source (IS) 4, a reference voltage source (VREF) 5, and an error amplifier (OP) 6. The first power supply terminal 1 is applied with a first power supply voltage VDD as a high-potential power supply which is the first power supply. The second power supply terminal 2 is applied with a second power supply voltage VSS (VSS < VDD) as a low-potential power supply which is the second power supply. The current source 4 is a current source connected to the first power supply terminal 1 and supplying a current IS.

[0039] The stabilized power supply circuit 10A has an error amplifier 6 including NMOS transistors (NMOS transistors) MN2, MN3, and MN5, and PMOS transistors (PMOS transistors) MP3 and MP4. The transistors MN2, MN3, and MN5 form a differential circuit. The transistors MP3 and MP4 are current-mirror connected, and form an active load of the differential circuit formed by the transistors MN2, MN3, and MN5. The stabilized power supply circuit 10A also has an NMOS transistor MN4 that is current-mirror connected to the transistor MN5. The gate and drain of the transistor MN4 are connected to a current source 4, and the transistor MN4 supplies a current IS of the current source 4 to the transistor MN5 as a bias current.

[0040] The error amplifier 6 has an inverting input terminal 61 (gate of transistor MN2) connected to the reference voltage source 5, and a non-inverting input terminal 62 (gate of transistor MN3) connected to a common connection point of voltage-dividing resistors R1 and R2 of a voltage-dividing circuit 7. The output terminal 63 (common connection point of the drains of transistor MN2 and transistor MP3) of the error amplifier 6 is connected to the gate of an output PMOS transistor MP1. The transistor MP1 has a source connected to the first power supply terminal 1, and a drain connected to the output terminal 3 and the voltage-dividing circuit 7. The voltage-dividing circuit 7 is connected between the output terminal 3 and the second power supply terminal 2.

[0041] The stabilized power supply circuit 10A includes an output transistor MP1 and a PMOS transistor MP2 for phase compensation, the sources of which are connected to each other. The source of the transistor MP2 is connected to the first power supply terminal 1, and the gate is connected to the output terminal 63 of the error amplifier 6 via a bias circuit 9. The drain of the transistor MP2 is connected to the second power supply terminal 2 via a phase compensation resistor R3, and is also connected to one end of a phase compensation capacitor C1. The other end of the capacitor C1 is connected to the non-inverting input terminal 62 of the error amplifier 6.

[0042] The bias circuit 9 is configured with NMOS type transistors MN1 and MN6. The transistor MN6 functions as a constant current source, is connected to the transistors MN4 and MN5 in a current mirror configuration, and supplies the current IS of the current source 4 to the transistor MN1. The transistor MN1 corresponds to a third transistor of a second conductivity type, and is provided between the gate of the transistor MP2 and the output terminal 63 of the error amplifier 6. Specifically, the gate of the transistor MN1 is connected to the output terminal 63 of the error amplifier 6, the drain is connected to the first power supply terminal 1, and the source of the transistor MN1 and the drain of the transistor MN6 are connected to each other. The gate of the transistor MP2 for phase compensation is connected to the connection point between the source of the transistor MN1 and the drain of the transistor MN6.

[0043] In the configuration of FIG. 3, the gate-source voltage of the transistor MN1 of the bias circuit 9 corresponds to the bias voltage VB of FIG. 1. As described above, the gate-source voltage Vgs2 of the transistor MP2 for phase compensation is greater than the gate-source voltage Vgs1 of the transistor MP1 for output by the gate-source voltage VB of the transistor MN1. At this time, the drain current of the transistor MP2 is 1 / n+α of the drain current of the transistor MP1. Therefore, even during a light load in which the drain current of the transistor MP1 for output is small, the drain current of the transistor MP2 for phase compensation is ensured to be equal to or greater than a predetermined amount, and the voltage generated in the resistor R3 for phase compensation cancels out the pole generated at the output terminal 3, and the output voltage VOUT is output stably.

[0044] Fig. 4 is a characteristic diagram showing an example of gain and phase characteristics in the stabilized power supply circuit of the first embodiment. In Fig. 4, the phase characteristics in the configuration of the first embodiment shown in Fig. 1 and Fig. 3 are shown by a solid line, the gain characteristics are shown by a dashed line, and the phase characteristics in the configuration of the comparative example shown in Fig. 10 are shown by a dashed line, and the gain characteristics are shown by a two-dot chain line.

[0045] In the illustrated example, in the configuration of the embodiment, the phase margin at a gain of 0 dB is 96 deg, which is a significant improvement over the phase margin of 3.6 deg in the comparative example. By applying a bias voltage to the gate of the phase compensation transistor MP2, even in an area where the output current is small, the phase delay can be cancelled out by the zero point generated by the phase compensation capacitor C1, and the phase margin can be secured.

[0046] 5 is a characteristic diagram showing an example of the phase margin characteristic with respect to the output current in the stabilized power supply circuit of the first embodiment. In the configuration of the embodiment, a large phase margin can be secured in a region where the drain current of the output transistor MP1 is small. In this embodiment, even in a region where the output current is small, a sufficient current is passed through the phase compensation resistor to cancel the phase delay and obtain the effect of phase compensation. Therefore, even under light load, the phase margin can be secured and the phase compensation effect can be enhanced, thereby improving the stability of the power supply circuit.

[0047] Second embodiment 6 is a circuit diagram showing the configuration of a stabilized power supply circuit of the second embodiment. A stabilized power supply circuit 10B of the second embodiment is provided with a bias circuit 9B instead of the bias circuit 9 constituting the stabilized power supply circuit 10 of the first embodiment. The bias circuit 9B of the second embodiment is configured so that the bias voltage VB increases as the output current increases. Specifically, a transistor MP5 is provided, the source and gate of which are mutually connected to those of the transistor MP1, and the drain of which is connected to the current mirror circuit 11. A drain current proportional to the output current flowing through the drain of the transistor MP1 flows through the transistor MP5. The bias voltage VB increases as the drain current of the transistor MP5 increases.

[0048] In the stabilized power supply circuit 10 of the first embodiment described above, the phase lag increases as the output current increases, which makes the output voltage VOUT unstable. According to the second embodiment, the phase compensation signal can be increased more than in the first embodiment as the output current increases, so that the output current VOUT can be further stabilized.

[0049] FIG. 7 is a characteristic diagram showing an example of the change in drain current characteristic due to the presence or absence and increase of bias voltage in the transistor MP2. As shown in the figure, when no bias voltage is applied, the transistor MP2 has a drain current proportional to the output current as shown by the dashed line. When a constant bias voltage is applied, the transistor MP2 has a large drain current in the region where the output current is small as shown by the dashed line, but in the region where the output current is large, the increase in the drain current with respect to the increase in the output current is smaller than when no bias is applied. When the bias voltage is increased according to the increase in the output current, the transistor MP2 has a large drain current in the region where the output current is small, as in the case where a constant bias voltage is applied, as shown by the solid line. Furthermore, in the region where the output current is large, the drain current flows in proportion to the output current almost the same as when no bias is applied.

[0050] Fig. 8 is a circuit diagram showing a specific example of the configuration of the stabilized power supply circuit of the second embodiment. The stabilized power supply circuit 10C of Fig. 8 shows a specific example of the circuit of the bias circuit 9B. Here, the following description will focus on the parts that differ from the stabilized power supply circuit 10B shown in Fig. 6, and the same components are denoted by the same reference numerals and will not be described.

[0051] The bias circuit 9B includes NMOS transistors MN1 and MN6, a PMOS transistor MP5, and a current mirror circuit 11. The connections of the transistors MN1 and MN6 are similar to those in the embodiment shown in FIG. 3 described above, and therefore will not be described in detail here.

[0052] The transistor MP5 and the current mirror circuit 11 function as a current source that supplies a current proportional to the output current to the drain of the transistor MN1. The source and gate of the transistor MP5 are mutually connected to those of the transistor MP1, and a drain current proportional to the output current flowing to the drain of the transistor MP1 flows through the transistor MP5. The current mirror circuit 11 includes NMOS transistors MN7 and MN8. The gate and drain of the transistor MN7 are connected to the drain of the transistor MP5, and the source is connected to the second power supply voltage VSS. The gate of the transistor MN8 is mutually connected to that of the transistor MN7, the source is connected to the second power supply voltage VSS, and the drain is connected to the source of the transistor MN1 and the drain of the transistor MN6. Thus, in the bias circuit 9B of FIG. 9, the current mirror circuit 11 is connected in parallel to the transistor MN6, which is a constant current source.

[0053] With the above configuration, the drain current proportional to the output current of transistor MP5 is mirrored to the drain of transistor MN8. The drain current of transistor MN1 is the sum of the current IS mirrored to transistor MN6 and the current proportional to the output current mirrored to transistor MN8. As a result, the gate-source voltage of transistor MN1, which is the bias voltage VB, is proportional to both the current IS and the output current, and the bias voltage VB can also be increased in accordance with an increase in the output current.

[0054] 9 is a characteristic diagram showing an example of the phase margin characteristic with respect to the output current in the stabilized power supply circuit of the second embodiment. In the configurations of the first and second embodiments, a large phase margin can be ensured in a region where the drain current of the output transistor MP1 is small. In addition, in the configuration of the second embodiment, a larger phase margin can be ensured than in the first embodiment in a region where the drain current of the output transistor MP1 is large.

[0055] As described above, according to this embodiment, by applying a bias voltage to the gate of the phase compensation transistor, sufficient phase compensation is possible even when the drain current of the output transistor is low and the load is light. That is, even in the region where the output current of the stabilized power supply circuit is small, a sufficient phase compensation effect can be obtained by securing a phase margin, and the phase compensation characteristic can be improved in the entire region of the output current. Therefore, a stable output voltage can be obtained in the entire current region. Therefore, it is possible to use a ceramic capacitor with a low equivalent series resistance ESR as the output voltage stabilization capacitor CL while improving stability in the entire current region. This embodiment is useful for a low-voltage output LDO regulator circuit, a voltage tracker, etc., in which it is difficult to generate a zero point at a low frequency.

[0056] In the stabilized power supply circuit of this embodiment, one of the PMOS transistor and the NMOS transistor is also referred to as a transistor of a first conductivity type, and the other, which has the opposite polarity, is also referred to as a transistor of a second conductivity type. In the configuration example of the above-mentioned embodiment, the PMOS transistor is the first conductivity type, and the NMOS transistor is the second conductivity type.

[0057] In the above embodiment, the power supply voltage is VDD>VSS, but if the power supply voltage is reversed, the PMOS transistors can be replaced with NMOS transistors and the NMOS transistors can be replaced with PMOS transistors. In this case, the NMOS transistors are the first conductivity type and the PMOS transistors are the second conductivity type.

[0058] Although various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It is clear that a person skilled in the art can come up with various modified or amended examples within the scope of the claims, and it is understood that these also naturally belong to the technical scope of the present invention. In addition, the components in the above-mentioned embodiments may be arbitrarily combined within the scope of the present invention. [Industrial Applicability]

[0059] INDUSTRIAL APPLICABILITY The present invention has an effect of improving phase compensation characteristics, including during light load periods with small output currents, and is useful for stabilized power supply circuits such as LDO regulator circuits. [Explanation of symbols]

[0060] 10,10A~10C: Stabilized power supply circuit 1: First power supply terminal (VDD) 2: 2nd power supply terminal (VSS) 3: Output terminal (VOUT) 4: Current source (IS) 5: Reference voltage source (VREF) 6: Error amplifier 61: inverting input terminal, 62: non-inverting input terminal, 63: output terminal 7: Voltage divider circuit 9, 9B: Bias circuit Tr1, MP1: Output transistors (PMOS transistors) Tr2, MP2: Phase compensation transistors (PMOS transistors) MP3, MP4, MP5: Transistor (PMOS transistor)

[0061] MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8: Transistors (NMOS transistors) R3: Resistor for phase compensation C1: Capacitor for phase compensation CL: Stabilizing capacitor ESR: Equivalent series resistance of stabilizing capacitor CL RL: Load resistance

Claims

1. A stabilized power supply circuit that outputs a stabilized output voltage so that the difference between a reference voltage and a voltage obtained by dividing an output voltage becomes zero, a first transistor of a first conductivity type having a source connected to a first power supply and having a drain from which the output voltage is obtained; a second transistor of a first conductivity type having a source connected to that of the first transistor; a phase compensation resistor element provided between the drain of the second transistor and a ground or a second power supply; a phase compensation capacitor connected to the second transistor side of the phase compensation resistor; a bias circuit that supplies a bias voltage to a gate of the second transistor, the bias voltage being a voltage offset with respect to a gate voltage of the first transistor; a voltage of the phase compensation resistor is superimposed on a voltage obtained by dividing the output voltage via the phase compensation capacitor; the bias circuit includes a third transistor of a second conductivity type and a constant current source; the third transistor has a gate connected to the gate of the first transistor, a drain connected to the source of the first transistor, and a source connected to the gate of the second transistor and the constant current source; Stabilized power supply circuit.

2. 2. The stabilized power supply circuit according to claim 1, a voltage divider circuit having one end connected to the drain of the first transistor and dividing the output voltage; an error amplifier that supplies a voltage proportional to a difference between a voltage obtained by dividing the output voltage and the reference voltage to a gate of the first transistor; one end of the phase compensation capacitor is connected to the drain of the second transistor and the phase compensation resistor element, and the other end is connected to a common connection point of the voltage divider circuit; Stabilized power supply circuit.

3. A stabilized power supply circuit that outputs an output voltage stabilized so that the difference between a reference voltage and a voltage obtained by dividing an output voltage is zero, comprising: a first transistor of a first conductivity type having a source connected to a first power supply and having a drain from which the output voltage is obtained; a second transistor of a first conductivity type having a source connected to that of the first transistor; a phase compensation resistor element provided between the drain of the second transistor and a ground or a second power supply; a phase compensation capacitor connected to the second transistor side of the phase compensation resistor; a bias circuit that supplies a bias voltage to a gate of the second transistor, the bias voltage being a voltage offset with respect to a gate voltage of the first transistor; a voltage of the phase compensation resistor is superimposed on a voltage obtained by dividing the output voltage via the phase compensation capacitor; the bias voltage supplied by the bias circuit increases in accordance with an increase in the output current of the first transistor; Stabilized power supply circuit.

4. 4. The stabilized power supply circuit according to claim 3, The bias circuit includes: a third transistor of a second conductivity type; a constant current source; and a current source connected in parallel to the constant current source and supplying a current proportional to the output current; the third transistor has a gate connected to the gate of the first transistor, a drain connected to the source of the first transistor, and a source connected to the gate of the second transistor, the constant current source, and the current source; Stabilized power supply circuit.

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