Nitride semiconductor light emitting device

Abstract

A nitride semiconductor light emitting device capable of improving light output is provided. [Solution] The nitride semiconductor light emitting device includes a substrate 2 whose growth surface 21 is a c-plane having an off-angle θ, an AlN buffer layer 3 made of AlN formed on the growth surface 21, an n-type semiconductor layer 4 formed on the AlN buffer layer 3, an active layer emitting ultraviolet light formed on the n-type semiconductor layer 4, and a p-type semiconductor layer formed on the active layer. An upper surface 31 of the AlN buffer layer 3 has a step-terrace structure having a plurality of terraces T2 and a plurality of steps S2 connecting the terraces T2. The average value of height H of the plurality of steps S2 is 7.1 nm or less. The average value of width W of the plurality of terraces T2 is 350 nm or less.

Description

[Technical Field]

[0001] The present invention relates to a nitride semiconductor light emitting device. [Background technology]

[0002] Patent Document 1 discloses an ultraviolet light emitting device including a substrate, an underlayer formed on the substrate, a first clad layer formed on the underlayer, an ultraviolet light emitting layer formed on the first clad layer, and a second clad layer formed on the light emitting layer. In the ultraviolet light emitting device described in Patent Document 1, the step height of the interface between the underlayer and the first clad layer is set to 10 nm or more and 60 nm or less. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-29607 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the ultraviolet light emitting device described in Patent Document 1, the light output in an example where the step height is relatively small has not been considered.

[0005] The present invention has been made in view of the above circumstances, and has an object to provide a nitride semiconductor light-emitting device that can improve light output. [Means for solving the problem]

[0006] In order to achieve the above object, the present invention provides a substrate comprising a c-plane growth surface having an off-angle, an AlN buffer layer made of AlN formed on the growth surface, an n-type semiconductor layer formed on the AlN buffer layer, an active layer that emits ultraviolet light formed on the n-type semiconductor layer, and a p-type semiconductor layer formed on the active layer, wherein the top surface of the AlN buffer layer has a step-terrace structure having a plurality of terraces and a plurality of steps connecting the terraces, and the average height of the plurality of steps is 5.0nm or more 7.1 nm or less, and the average width of the plurality of terraces is 250nm or more A nitride semiconductor light-emitting device having an emission wavelength of 350 nm or less is provided. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a nitride semiconductor light emitting device that can improve light output. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram illustrating a configuration of a nitride semiconductor light emitting device according to an embodiment. [Figure 2] 1 is a schematic cross-sectional view showing an enlarged portion of a nitride semiconductor light-emitting device according to an embodiment. [Figure 3A] 1 is an AFM image of the top surface of an AlN buffer layer of a wafer grown under the same manufacturing conditions as in Example 1. [Figure 3B] 3B is a cross-sectional profile of the dashed line in FIG. 3A. [Figure 4A] 1 is an AFM image of the top surface of an AlN buffer layer of a wafer grown under the same manufacturing conditions as in Comparative Example 1. [Figure 4B] 4B is a cross-sectional profile of the dashed line in FIG. 4A. [Figure 5] 10 is a graph showing the relationship between average step height and light output in an experimental example. [Figure 6] 10 is a graph showing the relationship between the average terrace width and the optical output in an experimental example. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Embodiment Mode] An embodiment of the present invention will be described with reference to Figures 1 and 2. The embodiment described below is shown as a preferred specific example for carrying out the present invention, and although various technically preferable technical matters are specifically exemplified, the technical scope of the present invention is not limited to this specific embodiment.

[0010] (Nitride semiconductor light emitting device 1) FIG. 1 is a schematic diagram illustrating the configuration of a nitride semiconductor light-emitting element 1. Note that in FIG. 1, the dimensional ratios in the stacking direction of each semiconductor layer of the nitride semiconductor light-emitting element 1 (hereinafter also simply referred to as "light-emitting element 1") do not necessarily match the actual ones. Hereinafter, the stacking direction of each semiconductor layer of the light-emitting element 1 (i.e., the direction perpendicular to the bottom surface of the substrate 2) will be referred to as the up-down direction. Also, one side in the up-down direction, on which each semiconductor layer of the substrate 2 is grown (e.g., the upper side in FIG. 1), will be referred to as the upper side, and the opposite side (e.g., the lower side in FIG. 1) will be referred to as the lower side. Note that the expressions up-down are for convenience and do not limit the orientation of the light-emitting element 1 relative to the vertical direction, for example, when the light-emitting element 1 is in use.

[0011] The light-emitting element 1 is, for example, a light-emitting diode (LED) or a semiconductor laser (LD: Laser Diode). In this embodiment, the light-emitting element 1 is a light-emitting diode that emits light with a wavelength in the ultraviolet region. In particular, the light-emitting element 1 in this embodiment emits ultraviolet light with a central wavelength of 240 nm or more and 365 nm or less. The light-emitting element 1 can be used in fields such as sterilization (e.g., air purification, water purification, etc.), medical care (e.g., phototherapy, measurement and analysis, etc.), UV curing, etc.

[0012] The light-emitting element 1 includes an AlN buffer layer 3, an n-type semiconductor layer 4, a compositionally graded layer 5, an active layer 6, an electron blocking layer 7, and a p-type semiconductor layer 8, which are arranged in this order on a substrate 2. The light-emitting element 1 also includes an n-side electrode 11 provided on the n-type semiconductor layer 4, and a p-side electrode 12 provided on the p-type semiconductor layer 8.

[0013] The semiconductor constituting the light emitting element 1 is, for example, Al a Ga b In 1-a-b In this embodiment, a group III nitride semiconductor having two to four elements represented by the formula N (0≦a≦1, 0≦b≦1, 0≦a+b≦1) can be used. c Ga 1-c The semiconductor material uses a binary or ternary group III nitride semiconductor represented by N (0≦c≦1). Some of these group III elements may be replaced with boron (B), thallium (Tl), etc. Also, some of the nitrogen may be replaced with phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc.

[0014] The substrate 2 is made of a material that transmits the light emitted by the active layer 6. The substrate 2 is a sapphire (Al2O3) substrate. FIG. 2 is a schematic cross-sectional view parallel to the vertical direction of the light-emitting device 1, showing an enlarged view of the periphery of the AlN buffer layer 3. The growth plane 21 formed on the upper surface of the substrate 2 is a c-plane having an off-angle θ. The off-angle θ is, for example, 0.2° to 1.5°, more preferably 1.0°±0.3° (i.e., 0.7° to 1.3°). Note that FIG. 2 is merely a schematic view, and the shapes of the growth plane 21 of the substrate 2 and the upper surface 31 of the AlN buffer layer 3 may differ from the actual shapes.

[0015] The growth surface 21 of the substrate 2 has a step-terrace structure with multiple terraces T1 formed of a c-plane with an off-angle θ and multiple steps S1 connecting the terraces T1. The step-terrace structure is formed by alternating terraces T1 and steps S1 in multiple steps. The substrate 2 is not particularly limited, but may have, for example, an off-angle θ of 0.2° and an average terrace width of 60.2 nm, an off-angle θ of 0.6° and an average terrace width of 20.1 nm, an off-angle θ of 1.0° and an average terrace width of 12.0 nm, or an off-angle θ of 1.5° and an average terrace width of 8.0 nm. Alternatively, the substrate 2 may be, for example, an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate.

[0016] The AlN buffer layer 3 is formed on the substrate 2. The AlN buffer layer 3 is made of undoped aluminum nitride. An undoped semiconductor layer refers to a semiconductor layer to which no impurities have been intentionally added during the formation of the semiconductor layer, and includes semiconductor layers that unavoidably contain trace amounts of impurities.

[0017] The AlN buffer layer 3 is formed by step flow growth, and the upper surface 31 of the AlN buffer layer 3 has a step-terrace structure having a plurality of terraces T2 inclined with respect to an imaginary plane perpendicular to the vertical direction, and a plurality of steps S2 connecting the terraces T2.

[0018] On the upper surface 31 of the AlN buffer layer 3, the average height H of the steps S2 is 7.1 nm or less, and the average width W of the terraces T2 is 350 nm or less. This presumably results in an appropriate planarization of the active layer 6, which is formed using the AlN buffer layer 3 as a base layer, improving the monochromaticity of the light emitted from the active layer 6, thereby improving the optical output of the light-emitting device 1 in a desired wavelength band. The height H of the steps S2 is the length of the steps S2 in the vertical direction. The width of the terraces T2 is the length of the terraces T2 in a direction perpendicular to the vertical direction, in which the terraces T2 and the steps S2 are continuous (e.g., the horizontal direction in FIG. 2 ). Hereinafter, the average height H of the steps S2 on the upper surface 31 of the AlN buffer layer 3 will be referred to as the "average step height," and the average width W of the terraces T2 on the upper surface 31 of the AlN buffer layer 3 will be referred to as the "average terrace width."

[0019] The average step height is preferably less than 7.0 nm, and the average terrace width is more preferably 325 nm or less. From the viewpoint of inducing step flow growth in the AlN buffer layer 3, the average step height is preferably 5.0 nm or more, and the average terrace width is preferably 250 nm or more.

[0020] The average step height can be calculated, for example, as follows: First, the surface shape of the AlN buffer layer 3 is measured using an atomic force microscope (AFM). Then, at least one cross-sectional profile is extracted from the measured AFM image along both the direction in which the terraces T2 and steps S2 continue and the vertical direction. Then, the average value of the heights H of the steps S2 is obtained by dividing the sum of the heights H of the multiple steps S2 appearing in the extracted at least one cross-sectional profile by the number of steps S2.

[0021] The average terrace width can be obtained, for example, by dividing the sum of the widths of the terraces T2 appearing in at least one cross-sectional profile extracted as described above by the number of terraces T2.

[0022] On the AlN buffer layer 3, undoped Al p Ga1-p It may also include a buffer layer made of N (0≦p≦1).

[0023] The n-type semiconductor layer 4 is formed on the AlN buffer layer 3. The n-type semiconductor layer 4 is, for example, AlN doped with n-type impurities. q Ga 1-q The n-type cladding layer is formed of Al (0≦q≦1). In this embodiment, silicon (Si) is used as the n-type impurity. The same applies to semiconductor layers containing n-type impurities other than the n-type semiconductor layer 4. Note that germanium (Ge), selenium (Se), tellurium (Te), or the like may also be used as the n-type impurity. The Al composition ratio q of the n-type semiconductor layer 4 is, for example, 45% or more and 65% or less.

[0024] The shape of the upper surface of the n-type semiconductor layer 4 is inherited from the shape of the upper surface 31 of the AlN buffer layer 3. In this case, the shape of the upper surface of the n-type semiconductor layer 4 becomes flatter as the thickness of the n-type semiconductor layer 4 increases up to a certain thickness. However, once the thickness of the n-type semiconductor layer 4 exceeds the certain thickness, it is considered that the change in the shape of the upper surface of the n-type semiconductor layer 4 due to the increase in thickness will substantially disappear. Because the n-type semiconductor layer 4 is a semiconductor layer that generates current, it is formed to a relatively large thickness (e.g., 1 μm or more) to enable current to flow. However, the thickness of the n-type semiconductor layer 4 is usually larger than the certain thickness. In this embodiment, the thickness of the n-type semiconductor layer 4 is, for example, 1600 nm or more and 3600 nm or less. The n-type semiconductor layer 4 may have a single-layer structure or a multi-layer structure.

[0025] The compositionally graded layer 5 is formed on the n-type semiconductor layer 4. The compositionally graded layer 5 is made of Al r Ga 1-r N (0≦r≦1). The Al composition ratio at each position in the vertical direction of the composition gradient layer 5 increases toward the upper side. Note that the composition gradient layer 5 may include a region in which the Al composition ratio does not increase toward the upper side, for example, in a very small region in the vertical direction (for example, a region of 5% or less of the entire vertical direction of the composition gradient layer 5).

[0026] The compositionally graded layer 5 preferably has an Al composition ratio at its lower end that is substantially the same as (for example, within 5% difference) the Al composition ratio at the upper end of the n-type semiconductor layer 4 adjacent to the lower side of the compositionally graded layer 5. Also, the compositionally graded layer 5 preferably has an Al composition ratio at its upper end that is substantially the same as (for example, within 5% difference) the Al composition ratio at the lower end of the barrier layer 61 adjacent to the upper side of the compositionally graded layer 5. Silicon is doped in the compositionally graded layer 5. The silicon concentration in the compositionally graded layer 5 is, for example, 5.0×10 18 atoms / cm 3 or more and 5.0×10 19 atoms / cm 3 or less.

[0027] The active layer 6 is formed on the compositionally graded layer 5. The active layer 6 in this embodiment has a multiple quantum well structure having a plurality of well layers 621, 622. The bandgap of the active layer 6 is adjusted so that it can emit ultraviolet light with a central wavelength of 240 nm or more and 365 nm or less. When the active layer 6 has a multiple quantum well structure as in this embodiment, from the viewpoint of improving the light output, the central wavelength of the ultraviolet light emitted by the active layer 6 is preferably 250 nm or more and 300 nm or less, and more preferably 260 nm or more and 290 nm or less. In this embodiment, the active layer 6 has three barrier layers 61 and three well layers 621, 622 each, and the barrier layers 61 and the well layers 621, 622 are alternately stacked. In the active layer 6, a barrier layer 61 is located at the lower end, and a well layer 622 is located at the upper end.

[0028] Each barrier layer 61 is formed of Al s Ga 1-s N (0 < s ≤ 1). The Al composition ratio s of each barrier layer 61 is, for example, 75% or more and 95% or less. Also, the film thickness of each barrier layer 61 is, for example, 2 nm or more and 50 nm or less.

[0029] The well layers 621, 622 are formed of Al t Ga 1-t N (0 < t < 1). The Al composition ratio t of each well layer 621, 622 is smaller than the Al composition ratio s of the barrier layer 61 (that is, t < s).

[0030] The three well layers 621, 622 have different configurations: the bottom well layer 621, which is the well layer disposed at the bottom, and the upper well layers 622, which are the two well layers other than the bottom well layer 621. For example, the thickness of the bottom well layer 621 is 1 nm or more larger than the thickness of each of the two upper well layers 622, and the Al composition ratio of the bottom well layer 621 is 2% or more larger than the Al composition ratio of each of the two upper well layers 622. In this embodiment, the upper well layer 622 has a thickness of 2 nm to 4 nm and an Al composition ratio of 25% to 45%, and the bottom well layer 621 has a thickness of 4 nm to 6 nm and an Al composition ratio of 35% to 55%. The difference in thickness between the bottom well layer 621 and each of the upper well layers 622 can be 2 nm to 4 nm.

[0031] By making the Al composition ratio of the bottom well layer 621 larger than that of the upper well layer 622, the crystallinity of the bottom well layer 621 is improved. This is because the difference in Al composition ratio between the bottom well layer 621 and the n-type semiconductor layer 4 is reduced. Improving the crystallinity of the bottom well layer 621 also improves the crystallinity of each semiconductor layer of the active layer 6 formed above the bottom well layer 621. This improves the carrier mobility in the active layer 6 and improves the light output. This effect becomes more pronounced as the thickness of the bottom well layer 621 increases; however, in order to prevent an increase in the electrical resistance of the entire light-emitting device 1, the thickness of the bottom well layer 621 is designed to be equal to or less than a predetermined value.

[0032] In this embodiment, the active layer 6 has a multi-quantum well structure with three well layers 621, 622, but is not limited to this and may have a multi-quantum well structure with two or four or more well layers. Also, the active layer 6 may have a single quantum well structure with only one well layer.

[0033] The electron blocking layer 7 is formed on the active layer 6. The electron blocking layer 7 has a role of improving the electron injection efficiency into the active layer 6 by suppressing the occurrence of an overflow phenomenon in which electrons leak from the active layer 6 to the p-type semiconductor layer 8 side (hereinafter also referred to as the electron blocking effect). The electron blocking layer 7 has a stacked structure in which a first layer 71 and a second layer 72 are stacked in order from the bottom side.

[0034] The first layer 71 is provided on the active layer 6. The first layer 71 is composed of, for example, Al u Ga 1-u N (0 ≤ u ≤ 1). The Al composition ratio u of the first layer 71 is, for example, 90% or more, and in this embodiment, it is composed of aluminum nitride. The film thickness of the first layer 71 is, for example, 0.5 nm or more and 5.0 nm or less.

[0035] The second layer 72 is composed of, for example, Al v Ga 1-v N (0 < v < 1). The Al composition ratio v of the second layer 72 is smaller than the Al composition ratio t of the first layer 71 (that is, v < t), and is, for example, 70% or more and 90% or less. The film thickness of the second layer 72 is larger than the film thickness of the first layer 71, and is, for example, 15 nm or more and 100 nm or less.

[0036] Since a semiconductor layer with a larger Al composition ratio has a larger electrical resistance value, if the film thickness of the first layer 71 with a relatively high Al composition ratio is made too large, it will cause an excessive increase in the overall electrical resistance value of the light-emitting device 1. Therefore, it is preferable to make the film thickness of the first layer 71 relatively small. On the other hand, if the film thickness of the first layer 71 is made small, the probability that electrons tunnel through the first layer 71 from the bottom side to the top side may increase. Therefore, in the light-emitting device 1 of this embodiment, by forming the second layer 72 on the first layer 71, the electrons are suppressed from tunneling through the entire electron blocking layer 7.

[0037] Each of the first layer 71 and the second layer 72 can be an undoped layer, a layer containing n-type impurities, a layer containing p-type impurities, or a layer containing both n-type and p-type impurities. Magnesium (Mg) can be used as the p-type impurity, but other elements such as zinc (Zn), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba), and carbon (C) can also be used. The same applies to other semiconductor layers containing p-type impurities. When each electron blocking layer 7 contains an impurity, the impurity may be contained in the entire electron blocking layer 7 or in part of the electron blocking layer 7. In this embodiment, the entire electron blocking layer 7 is an undoped layer.

[0038] The p-type semiconductor layer 8 is formed on the electron blocking layer 7. The p-type semiconductor layer 8 has a smaller Al composition ratio than the electron blocking layer 7, and is made of Al doped with p-type impurities. w Ga 1-w N (0≦w≦1). In this embodiment, the p-type semiconductor layer 8 has a p-type cladding layer 81 and a p-type contact layer 82 in this order from the bottom.

[0039] The p-type cladding layer 81 is provided so as to contact the upper surface of the electron blocking layer 7. The Al composition ratio of the p-type cladding layer 81 can be smaller than the Al composition ratio of the semiconductor layer (i.e., the second layer 72) adjacent to the p-type cladding layer 81 in the electron blocking layer 7, and can be larger than the Al composition ratio of the p-type contact layer 82. The thickness of the p-type cladding layer 81 is, for example, not less than 9 nm and not more than 105 nm.

[0040] The p-type contact layer 82 is a layer to which the p-side electrode 12 (described later) is connected, and is doped with a high concentration of p-type impurities. The p-type contact layer 82 is configured to have a low Al composition ratio (for example, 10% or less) to achieve ohmic contact with the p-side electrode 12, and from this perspective, it is preferably formed of p-type gallium nitride (GaN). Because the p-type contact layer 82 with a low Al composition ratio can absorb ultraviolet light emitted from the active layer 6, the thickness of the p-type contact layer 82 is preferably 50 nm or less, and more preferably 25 nm or less. Furthermore, from the perspective of suppressing the occurrence of short circuits, the thickness of the p-type contact layer 82 is preferably 5 nm or more.

[0041] The n-side electrode 11 is formed on an exposed surface 41 of the n-type semiconductor layer 4 that is exposed above the active layer 6. The n-side electrode 11 may be, for example, a multilayer film in which titanium (Ti), aluminum, titanium, and titanium nitride (TiN) are laminated in this order on the n-type semiconductor layer 4. Furthermore, when the light-emitting element 1 is flip-chip mounted as described below, the n-side electrode 11 may be made of a material that can reflect ultraviolet light emitted from the active layer 6.

[0042] The p-side electrode 12 is formed on the upper surface of the p-type semiconductor layer 8. The p-side electrode 12 can be made of, for example, rhodium (Rh). In this embodiment, the p-side electrode 12 is a reflective electrode having a reflectance of 50% or more, preferably 60% or more, at the center wavelength of light emitted from the active layer 6, but is not limited to this.

[0043] The light-emitting element 1 can be used by being flip-chip mounted on a package substrate (not shown). That is, the side of the light-emitting element 1 on which the n-side electrode 11 and the p-side electrode 12 are provided in the vertical direction faces the package substrate, and each of the n-side electrode 11 and the p-side electrode 12 is mounted on the package substrate via gold bumps or the like. In the flip-chip mounted light-emitting element 1, light is extracted from the substrate 2 side (i.e., the lower side). However, this is not a limitation, and the light-emitting element 1 may also be mounted on the package substrate by wire bonding or the like. In addition, in this embodiment, the light-emitting element 1 is a so-called horizontal light-emitting element in which both the n-side electrode 11 and the p-side electrode 12 are provided on the upper side of the light-emitting element 1, but this is not a limitation, and the light-emitting element may also be a vertical light-emitting element. A vertical light-emitting element is a light-emitting element in which an active layer is sandwiched between an n-side electrode and a p-side electrode.

[0044] (Method of manufacturing the light-emitting element 1) Next, an example of a method for manufacturing the light emitting device 1 of this embodiment will be described. In this embodiment, an AlN buffer layer 3, an n-type semiconductor layer 4, a compositionally graded layer 5, an active layer 6, an electron blocking layer 7, and a p-type semiconductor layer 8 are epitaxially grown in this order on a disk-shaped substrate 2 by metal organic chemical vapor deposition (MOCVD). That is, in this embodiment, the disk-shaped substrate 2 is placed in a chamber, and source gases for each semiconductor layer to be formed on the substrate 2 are introduced into the chamber, thereby forming each semiconductor layer on the substrate 2. As source gases for epitaxially growing each semiconductor layer, trimethylaluminum (TMA) as an aluminum source, trimethylgallium (TMG) as a gallium source, ammonia (NH) as a nitrogen source, tetramethylsilane (TMSi) as a silicon source, and biscyclopentadienylmagnesium (CpMg) as a magnesium source can be used.

[0045] The MOCVD method is also called metal organic vapor phase epitaxy (MOVPE). When epitaxially growing each semiconductor layer on the substrate 2, other epitaxial growth methods such as molecular beam epitaxy (MBE) and hydride vapor phase epitaxy (HVPE) can also be used.

[0046] In the manufacturing method of the light-emitting element 1 of this embodiment, manufacturing conditions are designed so that the average step height on the upper surface 31 of the AlN buffer layer 3 is 7.1 nm or less and the average terrace width is 350 nm or less. For example, increasing the growth rate of the AlN buffer layer 3 tends to decrease the average step height. The growth rate of the AlN buffer layer 3 can be adjusted by, for example, adjusting the growth temperature of the AlN buffer layer 3, the supply amount of the source gas, etc. The appropriate values ​​for each manufacturing condition may vary depending on other manufacturing conditions and the manufacturing equipment used. Furthermore, the shape of the upper surface 31 of the AlN buffer layer 3 is affected not only by the growth rate but also by the shape of the growth surface 21 of the substrate 2. As described above, by appropriately adjusting the factors affecting the upper surface 31 of the AlN buffer layer 3, the AlN buffer layer 3 is grown by step flow growth, and its upper surface 31 is formed into the shape described above.

[0047] After each semiconductor layer is formed on the disk-shaped substrate 2, a mask is formed on a portion of the p-type semiconductor layer 8, i.e., on a portion other than the portion that will become the exposed surface 41 of the n-type semiconductor layer 4. Then, the region where the mask is not formed is removed by etching from the top surface of the p-type semiconductor layer 8 to partway up and down the n-type semiconductor layer 4. As a result, an exposed surface 41 that is exposed upward is formed on the n-type semiconductor layer 4. After the exposed surface 41 is formed, the mask is removed.

[0048] Next, an n-side electrode 11 is formed on the exposed surface 41 of the n-type semiconductor layer 4, and a p-side electrode 12 is formed on the p-type semiconductor layer 8. The n-side electrode 11 and the p-side electrode 12 may be formed by a well-known method such as an electron beam evaporation method or a sputtering method. The completed product is cut into pieces of desired dimensions, and a plurality of light-emitting elements 1 as shown in FIG. 1 are manufactured from one wafer.

[0049] (Actions and Effects of the Embodiments) In the light-emitting device 1 of this embodiment, the upper surface 31 of the AlN buffer layer 3 has a step-terrace structure including a plurality of terraces T2 and a plurality of steps S2 connecting the terraces T2. The upper surface 31 of the AlN buffer layer 3 has an average step height of 7.1 nm or less and an average terrace width of 350 nm or less. This improves the light output of the light-emitting device 1. This is presumably because the active layer 6 formed using the AlN buffer layer 3 as an underlying layer is appropriately planarized, improving the monochromaticity of the light emitted from the active layer 6 and thereby improving the light output of the light-emitting device 1 in the desired wavelength band. These numerical values ​​are supported by experimental examples described below.

[0050] Furthermore, the average step height is less than 7.0 nm, which makes it possible to further improve the light output of the light-emitting element 1. This value is supported by experimental examples that will be described later.

[0051] Furthermore, the average terrace width is 325 nm or less, which makes it possible to further improve the light output of the light-emitting element 1. This value is supported by experimental examples that will be described later.

[0052] The light-emitting device 1 further includes a compositionally graded layer 5 between the n-type semiconductor layer 4 and the active layer 6, in which the Al composition ratio increases toward the active layer 6. This improves the crystallinity of the active layer 6, and, combined with the planarization of the active layer 6 by setting the average step height to 7.1 nm or less and the average terrace width to 350 nm or less as described above, further improves the light output.

[0053] Furthermore, in the light-emitting element 1, the p-side electrode 12 is a reflective electrode, and the thickness of the p-type contact layer 82 is 50 nm or less. That is, the light-emitting element 1 of this embodiment has a configuration in which ultraviolet light emitted from the active layer 6 toward the p-side electrode 12 is reflected by the p-side electrode 12 and extracted from the substrate 2. With such a configuration, the phase difference between the direct output light and the reflected output light is designed so that the direct output light, which is emitted directly from the active layer 6 toward the substrate 2, and the reflected output light, which is reflected from the active layer 6 by the p-side electrode 12 and extracted from the substrate 2, constructively interfere with each other. However, if the interfaces of the semiconductor layers are not flat, light scattering is likely to occur at the interfaces of the semiconductor layers, making it difficult to align the phases of the direct output light and the reflected output light, which may impair the improvement of the light output. On the other hand, as described above, the light-emitting device 1 of this embodiment has an average step height of 7.1 nm or less and an average terrace width of 350 nm or less on the upper surface 31 of the AlN buffer layer 3, and therefore it is considered that the step height and terrace width of each semiconductor layer formed on the AlN buffer layer 3 will also be small (i.e., flatness will be improved). Therefore, in the light-emitting device 1 of this embodiment, light scattering at the interface of each semiconductor layer is suppressed, and the phases of the directly emitted light and the reflected emitted light are more likely to be aligned, which makes it easier to improve the light output.

[0054] As described above, according to this embodiment, it is possible to provide a nitride semiconductor light emitting device that can improve the light output.

[0055] [Experimental Example] This experimental example is an example of evaluating the optical output of a wafer when the average step height and average terrace width on the upper surface of the AlN buffer layer are variously changed. Note that, among the names of components used in this experimental example, those that are the same as those used in the previous embodiments represent the same components as those in the previous embodiments unless otherwise specified.

[0056] In this experimental example, wafers according to Examples 1 to 5 and Comparative Examples 1 to 3 were prepared. As shown in Table 1 below, the wafers according to Examples 1 to 5 and Comparative Examples 1 to 3 have the same basic structure as the light-emitting device in the embodiment. The differences between Examples 1 to 5 and Comparative Examples 1 to 3, which will be described in detail later, are the average step height and average terrace width. The basic structure common to the wafers according to Examples 1 to 5 and Comparative Examples 1 to 3 is shown in Table 1.

[0057] [Table 1]

[0058] The Al composition ratio of each layer listed in Table 1 is a value estimated from the Al secondary ion intensity measured by secondary ion mass spectrometry (SIMS). The column for the Al composition ratio of the compositionally graded layer in Table 1 indicates that the Al composition ratio at each position in the vertical direction of the compositionally graded layer gradually increases from 55% to 85% from the bottom to the top of the compositionally graded layer. For the wafers in Examples 1 to 5 and Comparative Examples 1 to 3, the substrates used had a c-plane growth surface with an off-angle of 1.0°±0.3°.

[0059] Furthermore, the average step height and average terrace width were calculated for the wafers according to Examples 1 to 5 and Comparative Examples 1 to 3. The calculation methods will be explained below.

[0060] The average step height was calculated as follows. First, wafers were prepared on which an AlN buffer layer had been grown under manufacturing conditions equivalent to those of Examples 1 to 5 and Comparative Examples 1 to 3. Next, the shape of the top surface of the AlN buffer layer of each wafer was measured using an AFM. FIG. 3A shows an AFM image of the top surface of the AlN buffer layer of a wafer grown under the same manufacturing conditions as Example 1, and FIG. 4A shows an AFM image of the top surface of the AlN buffer layer of a wafer grown under the same manufacturing conditions as Comparative Example 1. In this example, a 5 μm square area was measured at the center of the top surface of each wafer.

[0061] Next, cross-sectional profiles were obtained at five random locations in each AFM image, both vertically and in the direction of the succession of terraces and steps. The cross-sectional profiles at the dashed-dotted lines in Figure 3A are shown in Figure 3B, and the cross-sectional profiles at the dashed-dotted lines in Figure 4A are shown in Figure 4B.

[0062] The average step height was calculated by measuring the height H of all steps S2 that appeared in the five cross-sectional profiles obtained from each AFM image and averaging these values. Note that although extremely small steps appear in Figure 3B, these extremely small steps are also counted as one step.

[0063] The average terrace width was calculated by measuring the width W of all terraces T2 that appeared in the five cross-sectional profiles obtained from each AFM image and averaging them. In this experimental example, the length in the left-right direction between the vertices of the upper convex portions located on both sides of terrace T2 in the cross-sectional profiles shown in Figures 3B and 4B (i.e., the direction perpendicular to the up-down direction, in which the terraces and steps are continuous) was considered to be the width W of terrace T2. Although very small terraces appear in Figure 3B, these very small terraces were also counted as one terrace.

[0064] In Figures 3B and 4B, the terraces on both sides are cut off midway, making it impossible to accurately measure the width of the entire terrace. Terraces that appear only partially were ignored when calculating the average terrace width. The same applies when steps appear on both sides and are cut off midway.

[0065] The average step heights and average terrace widths calculated as described above for Examples 1 to 5 and Comparative Examples 1 to 3 are shown in Table 2. Table 2 also lists the optical outputs of the wafers for Examples 1 to 5 and Comparative Examples 1 to 3, which will be described later.

[0066] [Table 2]

[0067] As shown in Table 2, Examples 1 to 5 satisfy the requirements of an average step height of 7.1 nm or less and an average terrace width of 350 nm or less, while Comparative Examples 1 to 3 have an average step height exceeding 7.1 nm and an average terrace width exceeding 350 nm.

[0068] Then, in each of Examples 1 to 5 and Comparative Examples 1 to 3, a current of 20 mA was applied while the wafer was on, and the optical output was measured. The optical output of each of Examples 1 to 5 and Comparative Examples 1 to 3 was measured using a photodetector installed below (i.e., on the substrate side of) each of Examples 1 to 5 and Comparative Examples 1 to 3. The relationship between the average step height and the optical output is shown in FIG. 5, and the relationship between the average terrace width and the optical output is shown in FIG. 6. The emission wavelength of each of Examples 1 to 5 and Comparative Examples 1 to 3 was 260 nm or more and 290 nm or less.

[0069] As can be seen from Table 2, Figures 5 and 6, Examples 1 to 5, which have an average step height of 7.1 nm or less and an average terrace width of 350 nm or less, can obtain higher light output than Comparative Examples 1 to 3, which have an average step height of more than 7.1 nm and an average terrace width of more than 350 nm.

[0070] Furthermore, the optical output can be further increased by setting the average step height to less than 7.0 nm as in Examples 1 to 4. Furthermore, the higher the average step height, the larger the average terrace width tends to be, and from the viewpoint of setting the average step height to less than 7.0 nm, the average terrace width is preferably 325 nm or less.

[0071] (Summary of the embodiment) Next, the technical ideas grasped from the above-described embodiments will be described by using the reference numerals and the like in the embodiments. However, the reference numerals and the like in the following description do not limit the components in the claims to the members and the like specifically shown in the embodiments.

[0072] [1] A first embodiment of the present invention is a nitride semiconductor light-emitting device 1 comprising: a substrate 2 having a growth surface 21 made of a c-plane with an off-angle θ; an AlN buffer layer 3 made of AlN formed on the growth surface 21; an n-type semiconductor layer 4 formed on the AlN buffer layer 3; an active layer 6 that emits ultraviolet light formed on the n-type semiconductor layer 4; and a p-type semiconductor layer 8 formed on the active layer 6; wherein an upper surface 31 of the AlN buffer layer 3 has a step-terrace structure having a plurality of terraces T2 and a plurality of steps S2 connecting the terraces T2, an average height H of the plurality of steps S2 is 7.1 nm or less, and an average width W of the plurality of terraces T2 is 350 nm or less. This makes it possible to improve the optical output of the nitride semiconductor light emitting element 1.

[0073] [2] A second embodiment of the present invention is the first embodiment, wherein the average value of the height H of the plurality of steps S2 is less than 7.0 nm. This makes it possible to further improve the optical output of the nitride semiconductor light emitting element 1.

[0074] [3] A third embodiment of the present invention is the first or second embodiment, wherein an average value of widths W of the plurality of terraces T2 is 325 nm or less. This makes it possible to further improve the optical output of the nitride semiconductor light emitting element 1.

[0075] [4] A fourth embodiment of the present invention is any one of the first to third embodiments, further comprising a composition gradient layer 5 between the n-type semiconductor layer 4 and the active layer 6, the Al composition ratio of which increases toward the active layer 6. This makes it possible to further improve the optical output of the nitride semiconductor light emitting element 1.

[0076] [5] A fifth embodiment of the present invention is any one of the first to fourth embodiments, further comprising a reflective electrode 12 formed on the p-type semiconductor layer 8 to reflect light emitted from the active layer 6, the p-type semiconductor layer 8 having a p-type contact layer 82 made of p-type GaN, and a film thickness of the p-type contact layer 82 being 50 nm or less. This makes it possible to further improve the optical output of the nitride semiconductor light emitting element 1.

[0077] (Addendum) Although the embodiments of the present invention have been described above, the invention according to the claims is not limited to the above-described embodiments. It should be noted that not all of the combinations of features described in the embodiments are necessarily essential to the means for solving the problems of the invention. Furthermore, the present invention can be implemented by appropriately modifying it within the scope of its spirit. For example, a configuration in which the configurations of the above-described embodiments are appropriately combined may be adopted. [Explanation of symbols]

[0078] 1...Nitride semiconductor light emitting device 12...p side electrode (reflecting electrode) 2...Substrate 21…Growth aspect 3...AlN buffer layer 31…Top surface 4...n-type semiconductor layer 5…composition gradient layer 6…Active layer 8...p-type semiconductor layer 82...p-type contact layer H: Step height S2...Step T2…Terrace θ: Off-angle of the substrate

Claims

1. a substrate having a c-plane growth surface with an off-axis angle; an AlN buffer layer made of AlN formed on the growth surface; an n-type semiconductor layer formed on the AlN buffer layer; an active layer that emits ultraviolet light and is formed on the n-type semiconductor layer; a p-type semiconductor layer formed on the active layer, an upper surface of the AlN buffer layer has a step-terrace structure including a plurality of terraces and a plurality of steps connecting the terraces; the average height of the steps is 5.0 nm or more and 7.1 nm or less; an average width of the plurality of terraces is 250 nm or more and 350 nm or less; Nitride semiconductor light emitting element.

2. The average height of the steps is less than 7.0 nm. The nitride semiconductor light emitting device according to claim 1 .

3. The average width of the plurality of terraces is 325 nm or less. The nitride semiconductor light emitting device according to claim 2 .

4. a composition gradient layer between the n-type semiconductor layer and the active layer, the composition gradient layer having an Al composition ratio that increases toward the active layer; The nitride semiconductor light emitting device according to claim 1 .

5. a reflective electrode formed on the p-type semiconductor layer and configured to reflect light emitted from the active layer; the p-type semiconductor layer has a p-type contact layer made of p-type GaN, The thickness of the p-type contact layer is 50 nm or less. The nitride semiconductor light emitting device according to claim 1 .

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