Combined programmable gain amplifier and comparator for low power and low area readout in image sensors

Abstract

To provide a combined programmable gain amplifier and comparator for low power and low area readout in an image sensor.SOLUTION: A switchable amplifier and comparator 90 includes an operational amplifier having an inverting input 32, a non-inverting input 38, a first differential output 48 and a second differential output 50, the first differential output being switchably coupled to the inverting input and the second differential output being switchably coupled to the non-inverting input. A first feedback capacitor 68 is coupled to the inverting input and switchably coupled to the first differential output, and a second feedback capacitor 72 is coupled to the non-inverting input and switchably coupled to the second differential output. Each of a capacitive load Cload including capacitors 102a and 102b, a diode clamp circuit including diodes 106a and 106b, and a resistive load including resistors 110a and 110b is switchably coupled between the first differential output and the second differential output.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to image sensing arrays, and more particularly to a composite programmable gain amplifier and comparator for low power and small area readout in image sensors. [Background technology]

[0002] 1, a schematic diagram shows a prior art programmable gain amplifier (PGA) with correlated double sampling and a subsequent comparator for readout of pixel sensors in an image sensing array. The input signal for the prior art programmable gain amplifier with correlated double sampling and the comparator is a voltage source V pix 1. The output of a typical pixel sensor is shown at the source of a source follower transistor 12 which has its drain connected to a source line 18. The source of source follower transistor 12 drives a current indicated by reference numeral 16 onto a column line 18.

[0003] In the prior art, the output voltage on column line 18 is amplified by a programmable gain amplifier (PGA) 20, which provides a correlated double sampling function. The output of PGA 20 is an analog signal. Comparator 22 compares the analog output of PGA 20 to a ramp signal on line 24, as is well known in the art.

[0004] Comparator 22 is typically a preamplifier followed by a latch. The preamplifier reduces the kickback effect from the latch and also amplifies the differential signal at its input. The latch converts the preamplifier output to rail-to-rail levels for digital processing.

[0005] 2, a schematic diagram shows in more detail a prior art programmable gain amplifier 10 including an amplifier 30 and a comparator 22 with correlated double sampling such as that depicted in FIG. columnis the capacitance of the sampling capacitor C during the ss phase when the switch 36 is closed. s 34 to the inverting input 32 of the operational amplifier 30, and during the sr phase when switch 42 is closed, sampling capacitor C s The signal is sampled from column 18 through 40 to the non-inverting input 38 of op amp 30 .

[0006] During these two sampling phases ss and sr, switches 44 and 46 controlled by the Clamp_1 signal are closed, shorting output node 48 to the inverting input 32 of amplifier 30 and output node 50 to the non-inverting input 38 of amplifier 30.

[0007] After the Clamp_1 signal is deasserted, the Clamp_2 signal is asserted, followed by the crowbar (CB) signal, which closes switch 52, shorting output node Out_P 54 of comparator 22 to inverting input 56 of comparator 22, and closes switch 58, shorting output node Out_N 60 of comparator 22 to non-inverting input 62 of comparator 22.

[0008] The crowbar signal cb closes switch 64, shorting together the input plates of capacitors 34 and 40. The crowbar signal cb also closes switch 66, connecting feedback capacitor Cf 68 between output node 48 of amplifier 30 and its inverting input 32, and closes switch 70, connecting feedback capacitor Cf 72 between output node 50 of amplifier 30 and its non-inverting input 38.

[0009] The crowbar signal cb also closes switches 74 and 76, connecting output nodes 48 and 50 of amplifier 30 to input nodes 56 and 62, respectively, of comparator 22 through capacitors Cc 78 and 80, respectively.

[0010] At the end of the crowbar (cb) phase, the difference between the voltages at nodes 48 and 50 is (Vss-Vsr). * Cs / Cf. Vss is the V during the ss phase. columnVsr is the V in the sr phase. column This voltage is sampled on the Cc capacitors 78 and 80 during the cb phase.

[0011] When the Ramp_en signal is asserted, switches 82 and 84 are closed, and the difference between the voltages at the Out_P and Out_N nodes 54 and 60 = Out_P - Out_N = (Vsr - Vss) * Cs / Cf-(Ramp_P-Ramp_N). This voltage is converted to rail-to-rail by the subsequent latch.

[0012] Referring now to FIG. 3, a timing diagram shows the relative timing of the ss, sr, cb, Clamp_1, Clamp_2, and Ramp_en control signals applied to operate the prior art programmable gain amplifier and comparator with correlated double sampling of FIG.

[0013] An area, power, and noise tradeoff must be made in the open circuit design of Figure 2. The feedback capacitor is initialized to the minimum differential ramp voltage instead of 0V. The output of the prior art circuit of Figure 2 is:

[0014] Out_P-Out_N=(Vsr-Vss) * Cs / Cf-(Ramp_P-Ramp_N) Summary of the Invention [Means for solving the problem]

[0015] In accordance with an aspect of the invention, a switchable amplifier and comparator circuit includes an operational amplifier having an inverting input, a non-inverting input, a first differential output, and a second differential output, the first differential output being switchably coupled to the inverting input and the second differential output being switchably coupled to the non-inverting input; a first feedback capacitor having a first plate coupled to the inverting input and a second plate switchably coupled to the first differential output; a second feedback capacitor having a first plate coupled to the non-inverting input and a second plate switchably coupled to the second differential output; a capacitive load switchably coupled between the first differential output and the second differential output; a diode clamp circuit switchably coupled between the first differential output and the second differential output; and a resistive load switchably coupled between the first differential output and the second differential output.

[0016] In accordance with an aspect of the invention, the switchable amplifier and comparator circuit further includes a first sampling capacitor coupled between the inverting input and a first switch input node, the first switch input node being switchably coupled to the signal input node, and a second sampling capacitor coupled between the non-inverting input and a second switch input node, the second switch input node being switchably coupled to the signal input node and the first switch input node.

[0017] According to an aspect of the invention, a second plate of the first feedback capacitor is switchably coupled to a positive ramp signal and a second plate of the second feedback capacitor is switchably coupled to a negative ramp signal.

[0018] According to an aspect of the invention, the first feedback capacitor includes a plurality of individual first feedback capacitors programmably connected in parallel with each other, and the second feedback capacitor includes a plurality of individual second feedback capacitors programmably connected in parallel with each other.

[0019] According to an aspect of the invention, a plurality of discrete first feedback capacitors are programmably connected in parallel to one another through pass gates, and a plurality of discrete second feedback capacitors are programmably connected in parallel to one another through pass gates.

[0020] According to an aspect of the invention, a plurality of individual first feedback capacitors have equal capacitances, and a plurality of individual second feedback capacitors programmably connected in parallel with one another have capacitance values ​​that are weighted with respect to one another.

[0021] According to an aspect of the invention, a method for downloading data from an imaging array to a single output circuit includes configuring the output circuit to sample pixel sensor outputs from a column of the array, configuring the output circuit to sample reset state outputs from the column of the array, configuring the output circuit to generate a programmable gain correlated dual signal sampled signal from the sampled pixel sensor outputs and the sampled reset state output, and configuring the output circuit as a comparator that compares the programmable gain correlated dual signal sampled signal to a ramp signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The invention is explained in more detail below with reference to embodiments and drawings. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic diagram illustrating a prior art programmable gain amplifier and comparator with correlated double sampling for readout of pixel sensors in an image sensing array. [Diagram 2] FIG. 2 is a schematic diagram showing in more detail a prior art programmable gain amplifier and comparator with correlated double sampling as depicted in FIG. 1; [Diagram 3]3 is a timing diagram illustrating control signals applied to operate the prior art programmable gain amplifier and comparator with correlated double sampling of FIG. 2. [Figure 4] 2 is a schematic diagram illustrating a composite amplifier and comparator including a programmable gain amplifier and comparator with correlated double sampling for readout of pixel sensors in an image sensing array in accordance with an embodiment of the present invention. [Diagram 5] FIG. 5 is a schematic diagram illustrating in greater detail a composite amplifier and comparator including a programmable gain amplifier and comparator with correlated double sampling as depicted in FIG. 4 in accordance with an embodiment of the present invention. [Figure 6] 6 is a timing diagram illustrating control signals applied to control the switches that make up the composite amplifier and comparator of FIG. 5. [Figure 7] 6 is a schematic diagram of the circuit of FIG. 5 showing an equivalent circuit resulting from the states of the switches in the circuit of FIG. 5 when the circuit is in the sample "ss" phase of operation. [Figure 8] The timing diagram of FIG. 6 includes brackets indicating the control signals applied to the switches to configure the circuit during a sample "ss" phase of the circuit's operation. [Figure 9] FIG. 6 is a schematic diagram of the circuit of FIG. 5 showing the equivalent circuit resulting from the states of the switches in the circuit of the diagram of FIG. 5 when the circuit is in the sample "sr" phase of operation. [Figure 10] The timing diagram of FIG. 6 includes brackets indicating the control signals applied to the switches to configure the circuit during a sample "sr" phase of the circuit's operation. [Figure 11] 6 is a schematic diagram of the circuit of FIG. 5 showing an equivalent circuit resulting from the states of the switches in the circuit of the diagram of FIG. 5 when the circuit is in a programmable gain amplifier phase of operation. [Figure 12] 7 is the timing diagram of FIG. 6 including brackets indicating the control signals applied to the switches to configure the circuit during the programmable gain amplifier phase of the circuit's operation. [Figure 13]FIG. 6 is a schematic diagram of the circuit of FIG. 5 showing the equivalent circuit resulting from the states of the switches in the circuit of the diagram of FIG. 5 when the circuit is in the comparator phase of operation. [Figure 14] 7 is the timing diagram of FIG. 6 including brackets indicating the control signals applied during the comparator phase of the circuit's operation. [Figure 15A] FIG. 2 is a schematic diagram of a passgate configured as a normally closed switch. [Figure 15B] FIG. 1 is a schematic diagram of a passgate configured as a normally open switch. [Figure 16] FIG. 12 is a schematic diagram showing an example circuit for implementing programmable gain in the amplifier circuit shown in FIG. 11. [Figure 17] 1 is a block diagram illustrating a controller coupled to an imaging array and to a composite amplifier and comparator including a programmable gain amplifier and comparator with correlated double sampling in accordance with an embodiment of the present invention.

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[0040] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Those skilled in the art will appreciate that the following description is illustrative only and in no way limiting, and other embodiments will readily suggest themselves to such skilled artisans.

[0042] 4, a schematic diagram illustrates a composite amplifier and comparator 90 including an amplifier 26 and a comparator with correlated double sampling for readout of pixel sensors in an image sensing array in accordance with an embodiment of the present invention. The architecture of the present invention combines the PGA 20 and comparator preamplifier 22 of the prior art arrangement of FIG. 1 into a single block 26 that reduces area and power consumption.

[0043] The composite amplifier and comparator 90 of Figure 4 shares several elements in common with the prior art circuit depicted in Figure 1. Those common elements are designated with the same reference numerals used to identify them in Figure 1.

[0044] As with the prior art arrangement, the input signal for the summing amplifier and comparator 90 is a voltage source V pix 1. The output of a typical pixel sensor is at the source of a source follower transistor 12 which has its drain connected to the input of the pixel line 12. The source of the source follower transistor 12 drives a current, represented by reference numeral 16, onto a column line 18.

[0045] The composite amplifier and comparator 90 uses a single amplifier 26 that acts as both a PGA with correlated double sampling and a comparator. A latch 28 captures the output of the comparator.

[0046] Referring now to Figure 5, a schematic diagram illustrates in greater detail a composite amplifier and comparator 90, such as that depicted in Figure 4, in accordance with an embodiment of the present invention. The circuit of Figure 5 shares several elements in common with the prior art circuit depicted in Figure 2. Those common elements are designated using the same reference numerals used to identify the common elements in Figure 2.

[0047] A differential op-amp 92 couples its inverting input 32 to the column line 18 through a sampling capacitor Cs 34 and a switch 36. The switch 36 is controlled by a sample reset (sr) signal. A non-inverting input 38 of the differential op-amp 92 is coupled to the column line 18 through a sampling capacitor Cs 40 and a switch 42. The switch 42 is controlled by a sample signal (ss).

[0048] The positive output 48 of the differential op-amp 92 is coupled to the inverting input 32 of the differential op-amp 92 through a clamp switch 44. The negative output 50 of the differential op-amp 92 is coupled to the non-inverting input 38 of the differential op-amp 92 through a clamp switch 46.

[0049] The positive output 48 of the differential op amp 92 is also coupled to the inverting input 32 of the differential op amp 92 through a switch 66 in series with a feedback capacitor Cf 68. The negative output 50 of the differential op amp 92 is also coupled to the non-inverting input 38 of the differential op amp 92 through a switch 70 in series with a feedback capacitor Cf 72. Switches 66 and 70 are controlled by a crowbar (cb) signal.

[0050] The common connection of switch 66 and feedback capacitor Cf 68 is coupled through a switch 94 to the Ramp_P signal at 96. The common connection of switch 70 and feedback capacitor Cf 72 is coupled through a switch 98 to the Ramp_N signal at 100.

[0051] A capacitive load including capacitors 102a and 102b is selectively connected across output nodes 54 and 60 of composite amplifier and comparator 90 (which are the same as output nodes 48 and 50 of differential op-amp 92) through switches 104a and 104b. A diode clamp circuit including diodes 106a and 106b is selectively connected across output nodes 54 and 60, respectively, of composite amplifier and comparator 90 through switches 108a and 108b. A resistive load including resistors 110a and 110b is selectively connected across output nodes 54 and 60, respectively, of composite amplifier and comparator 90 through switches 112a and 112b.

[0052] Switches 104a, 104b, 108a, 108b, 112a, and 112b are all controlled by signal RampConn2. Switches 104a and 104b are normally closed when signal RampConn2 is deasserted and open when signal RampConn2 is asserted. Switches 64, 108a, 108b, 112a, and 112b are all normally open when signal RampConn2 is deasserted and closed when signal RampConn2 is asserted.

[0053] Referring now to Figure 6, a timing diagram illustrates control signals applied to control the programmable gain amplifier with correlated double sampling and comparator of Figure 5 during all phases of its operation in accordance with an embodiment of the present invention. The control signals ss, sr, cb, Clamp, RampConn, and RampConn2 are shown and their effects on the circuit of Figure 5 during various phases of its operation are illustrated in Figures 7, 9, 11, and 13.

[0054] Referring now to Figure 7, a schematic diagram depicts the configuration of the circuit of Figure 5 when the circuit is in the sample phase of operation, and shows the equivalent circuit resulting from the state of the switches of the circuit of Figure 5 when the circuit is in the sample phase of operation. During the sample phase of operation, the signals on the column lines are sampled. Switches 42, 44, 46, 94, 98, 104a, and 104b of Figure 5 are closed and shown as wires. Switches 36, 66, 70, 108a, 108b, 112a, and 112b of Figure 5 are open and therefore not shown in Figure 7.

[0055] As can be seen in Figure 7, the voltage V column is the sampling capacitor C during the ss phase when switch 42 is closed. s 5. Signals are sampled from columns 18 through 40 to the non-inverting input 38 of an op-amp 92. As disclosed herein, op-amp 92 acts as both the PGA and the comparator in the circuit of FIG.

[0056] Referring now to FIG. 8, a timing diagram shows the control signals applied to the switches during the sample ss phase of operation of the circuit to control the state of the switches.

[0057] Referring now to Figure 9, a schematic diagram depicts the configuration of the circuit of Figure 5 when the circuit is in the sample sr phase of operation, and shows the equivalent circuit resulting from the state of the switches of the circuit of Figure 5 when the circuit is in the sample sr phase of operation. During this phase of operation, the voltages on the columns in their reset states are sampled. Switches 36, 44, 46, 94, 98, 104a, and 104b are closed. Switches 42, 66, 70, 108a, 108b, 112a, and 112b are open.

[0058] As can be seen in Figure 9, during the sample sr phase of operation, V column The voltage at 18 is sampled onto Cs 34. This sampled voltage is the signal voltage (Vss). Amplifier 92 is reset during this phase.

[0059] Feedback capacitors Cf 68 and 72 are also reset during this phase by sampling Ramp_P 96 and Ramp_N 100 onto feedback capacitors Cf 68 and 72 through switches 94 and 98 controlled by the RampConn signal.

[0060] Voltage V column is the capacitance of the sampling capacitor C during the sr phase when the switch 36 is closed. s 34 from column 18 to the inverting input 32 of op amp 92, and when switch 42 is closed, sampling capacitor C s 5. The input signal is sampled from column 18 through 40 to the non-inverting input 38 of an op-amp 92. As disclosed herein, op-amp 92 acts as both the PGA and the comparator in the circuit of FIG.

[0061] FIG. 10 is a timing diagram showing the control signals applied to the switches during the sample sr phase of operation of the circuit depicted in FIG.

[0062] During these two sampling phases sr and ss shown in Figures 7 and 9, switches 44 and 46 controlled by the Clamp signal are closed, shorting the output node 48 of amplifier 92 to the inverting input 32 of amplifier 92 and shorting the output node 50 of amplifier 92 to the non-inverting input 38 of amplifier 92. The RampConn2 signal is deasserted during these two sampling phases sr and ss. Switches 104a and 104b, which are normally closed, are deasserted to make amplifier 92 more stable. load Capacitors 102a and 102b are connected, which can vary based on the amplifier architecture used. Switches 108a, 108b, 112a, and 112b are open, disconnecting clamping diodes 106a and 106b and resistive loads 110a and 110b from the circuit.

[0063] 11, a schematic diagram depicts the configuration of the circuit of FIG. 5 when the circuit is in the programmable gain amplifier phase of operation. During this phase of operation, switches 64, 66, 70, 104a, and 104b are closed. Switches 36, 42, 44, 46, 94, 98, 108a, 108b, 112a, and 112b are open.

[0064] During this phase of circuit operation, which is the PGA mode of op-amp 92, the cb signal is asserted after the Clamp signal is deasserted. The crowbar signal cb closes switch 64, shorting together the input plates of Cs capacitors 34 and 40. The crowbar signal cb also closes switch 66, connecting feedback capacitor Cf 68 between output node 48 of amplifier 92 and its inverting input 32, and closes switch 70, connecting feedback capacitor Cf 72 between output node 50 of amplifier 30 and its non-inverting input 38.

[0065] The feedback capacitors Cf 68 and 72 and the sampling capacitors Cs 34 and 40 are connected such that at the end of the crowbar cb phase of circuit operation, the output of amplifier 92 (the voltage difference at output nodes 54 and 60) is:

[0066] (Out_P)-(Out_N)=(Vsr-Vss) * Cs / Cf+(Ramp_P_i-Ramp_N_i), where Ramp_P_i and Ramp_N_i are the initial ramp voltages. This calculation takes into account the offset. By ignoring this offset (i.e. (Ramp_P_i-Ramp_N_i)=0), the equation becomes (Out_P)-(Out_N)=(Vsr-Vss) * This is simplified to Cs / Cf.

[0067] Vss is the V during the ss phase in Figure 7. column Vsr is the V in the sr phase in FIG. column It is.

[0068] Referring now to FIG. 12, a timing diagram shows the control signals applied to the switches to configure the circuit during the programmable gain amplifier phase of operation of the circuit of FIG.

[0069] Figure 13 is a schematic diagram of the circuit of Figure 5 and shows an equivalent circuit resulting from the state of the switches of the circuit in Figure 5 when the circuit is in the comparator phase of operation. During this phase of operation, switches 94, 98, 108a, 108b, 112a, and 112b are closed. Switches 36, 42, 44, 46, 64, 66, 70, 104a, and 104b are open.

[0070] Switches 108a and 108b connect clamping diodes 108a and 108b across the circuit's output nodes 54 and 60 to reduce the voltage swing in comparator mode so that the comparator can switch faster. Switches 112a and 112b connect load resistors 112a and 112b across the circuit's output nodes 54 and 60 to increase the bandwidth of the comparator.

[0071] Difference between the voltages at the Out_P and Out_N nodes 54 and 60 = Out_P - Out_N = (Vss - vsr) * Cs / Cf-(Ramp_P-Ramp_N). This voltage is converted to rail-to-rail by the subsequent latch.

[0072] FIG. 14 is a timing diagram illustrating the control signals applied during the comparator phase of operation of the circuit.

[0073] The differential voltage output at nodes 84 and 86 is now:

[0074] (Out_P)-(Out_N)=(Vsr-Vss) * Cs / Cf)-(Ramp_P-Ramp_N)

[0075] The circuit operation, which is described in relation to Figures 5-14, is the same as in the prior art, but achieves that same operation by combining an amplifier and a comparator preamplifier.

[0076] As in the prior art amplifier and comparator depicted in Figure 1, in the composite amplifier and comparator 90 disclosed herein and depicted in Figure 5, the various switches used in the circuits may include CMOS pass gates. A pass gate configured as a normally open switch is identified by reference numeral 120 and depicted in Figure 15A. A pass gate configured as a normally closed switch is identified by reference numeral 122 and depicted in Figure 15B. Both pass gates 120 and 122 have a main terminal 124 and a control terminal 126, and are formed from a p-channel transistor 128 connected in parallel with an n-channel transistor 130.

[0077] Pass gate 120 has an inverter 132 connected between the control input 126 and the gate of a p-channel transistor 128. The gate of n-channel transistor 130 is connected directly to the control input 126. A low signal on the control terminal 126 turns pass gate 120 off, isolating the main terminals 124 from each other, and a high signal on the control input 126 turns pass gate 120 on, connecting the main terminals 124 together.

[0078] Pass gate 122 has an inverter 134 connected between the control input 126 and the gate of n-channel transistor 130. The gate of p-channel transistor 128 is connected directly to the control input 126. A low level signal on the control terminal 126 turns on the pass gate 122 connecting the main terminals 124 together and a high level signal on the control input 126 turns off the pass gate 122 isolating the main terminals 124 from each other. Those skilled in the art will recognize that all of the switches can be configured as shown in FIG. 15A if an additional inverter is connected between the RampConn2 signal and the input 126 of any of the switches shown in FIG. 15A that are configured as normally closed.

[0079] 16, a schematic diagram shows an illustrative circuit 140 for achieving programmable gain in the amplifier circuit shown in FIG. 11 by providing a programmable value for capacitor Cf (reference numerals 68 and 72 in FIGS. 7, 9, and 11). The total capacitance of Cf between nodes 142 and 144 can be changed between values ​​of capacitors Cf1 (146-1), Cf1+Cf2 (146-1+146-2), Cf1+Cf2+Cf3 (146-1+146-2+146-3), and Cf1+Cf2+Cf3+Cf4 (146-1+146-2+146-3+146-4) by selectively closing one or more of switches 148-1, 148-2, 148-3, and 148-4. Switches 148-1, 148-2, 148-3, and 148-4 may be pass gates as shown in Figures 15A and 15B.

[0080] If all of the capacitors have the same value (0.25Cf), the gain can be selectable between 1, 1.33, 2, and 4 by closing one, two, three, or all four of switches 148-1, 148-2, 148-3, and 148-4. Those skilled in the art will recognize that the values ​​of capacitors 146-1, 146-2, 146-3, and 146-4 need not be equal and can be weighted (e.g., 1-2-4-8) to provide other selectable capacitance values.

[0081] 17, a block diagram illustrates a controller 150 coupling control lines 152 to an imaging array 154 and the programmable gain amplifiers with correlated double sampling 26 (one per column) and comparators in accordance with an embodiment of the present invention. The controller 150 is configured to control the operation of the imaging array 154 through the control lines 152 in a manner well known in the art to capture an image. The controller 150 is also configured to provide control signals that control the switches that make up the programmable gain amplifiers with correlated double sampling and comparators 26, and to provide other control signals that direct the operation of the programmable gain amplifiers and comparators 26 in various modes as described herein.

[0082] By synthesizing a programmable gain amplifier and a comparator, a low power and low area readout circuit design in an image sensor is provided. The present invention provides a one-stage implementation of correlated double sampling, offset generation, and comparison with a ramp voltage. The amplifier is reconfigured as a comparator preamplifier during the ramp phase. Compared to separate programmable gain amplifier and comparator stages, this architecture provides low noise because the programmable gain amplifier is not operable during comparator mode, resulting in noise from only one amplifier during both phases. This architecture also meets the same noise specifications as the prior art amplifiers using lower power. This architecture also consumes less area on the integrated circuit die.

[0083] The prior art architecture requires two additional sampling capacitors 78 and 80 to sample against the comparator inputs. Considering just the sampling noise. To have the same sampling noise performance as the present invention, the prior art architecture requires a sampling capacitor with twice the capacitance of the sampling capacitor required by the present invention. This requires a sampling capacitor area for the prior art architecture that is six times the area of ​​the sampling capacitor area required by the present invention. In addition, since the sampling capacitance is doubled, Cf also needs to be doubled for unity gain. Thus, this architecture achieves lower noise performance in a smaller area.

[0084] With twice the number of sampling capacitors at the comparator input for the conventional architecture, the load increase seen by the programmable gain amplifier compared to the architecture of the present invention is four times for small signal settling. For the same settling performance and assuming a single amplifier stage, the current in the amplifier needs to increase by four times for the same unity gain frequency. This results in a further increase in amplifier area and second order effects due to parasitic poles. Thus, this architecture achieves lower power and lower noise performance in a smaller area.

[0085] While embodiments and applications of this invention have been shown and described, it will be apparent to those skilled in the art that many more modifications than those mentioned above are possible without departing from the inventive concepts herein. Accordingly, the invention should not be restricted except in the spirit of the appended claims.

Claims

1. A switchable amplifier and comparator circuit in an integrated circuit for imaging, comprising:

1. An imaging array having a plurality of output column lines, each of the column lines comprising: an operational amplifier having an inverting input, a non-inverting input, a first differential output, and a second differential output, the first differential output being switchably coupled to the inverting input via a switch and the second differential output being switchably coupled to the non-inverting input via a switch; a first feedback capacitor having a first plate coupled to the inverting input and a second plate switchably coupled to the first differential output via a switch; a second feedback capacitor having a first plate coupled to the non-inverting input and a second plate switchably coupled to the second differential output via a switch; a capacitive load switchably coupled between the first differential output and the second differential output via a switch; a diode clamp circuit switchably coupled between the first differential output and the second differential output via a switch; a resistive load switchably coupled between the first differential output and the second differential output via a switch; a switchable amplifier and comparator circuit including an imaging array coupled to the

2. a first sampling capacitor coupled between the inverting input and a first switch input node, the first switch input node being switchably coupled to a signal input node via a switch; a second sampling capacitor coupled between the non-inverting input and a second switch input node, the second switch input node switchably coupled to the signal input node via a switch and switchably coupled to the first switch input node via a switch; 2. The switchable amplifier and comparator circuit of claim 1 further comprising:

3. the second plate of the first feedback capacitor is switchably coupled to a positive ramp signal via a switch; 3. The switchable amplifier and comparator circuit of claim 2, wherein the second plate of the second feedback capacitor is switchably coupled to a negative ramp signal via a switch.

4. the first feedback capacitor comprises a plurality of individual first feedback capacitors programmably connected in parallel with each other; 4. The switchable amplifier and comparator circuit of claim 3, wherein the second feedback capacitor comprises a plurality of separate second feedback capacitors programmably connected in parallel with each other.

5. 4. The switchable amplifier and comparator circuit of claim 3, wherein the plurality of discrete first feedback capacitors are programmably connected in parallel to one another through pass gates, and the plurality of discrete second feedback capacitors are programmably connected in parallel to one another through pass gates.

6. the plurality of individual first feedback capacitors having equal capacitance; 5. The switchable amplifier and comparator circuit of claim 4, wherein the plurality of discrete second feedback capacitors programmably connected in parallel with one another have capacitance values ​​that are weighted with respect to one another.

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