Substrate with built-in electronic components and its manufacturing method

Abstract

To enhance a design freedom of a conductor layer on the outermost layer in an electronic component built-in substrate.SOLUTION: An electronic component built-in substrate 1 includes conductor layers L1 to L6, insulating layers 11 to 15 positioned among the conductor layers L1 to L6, and an electronic component 40 built in the insulating layer 13. The conductor layer L1 is positioned on the uppermost layer, and includes a plurality of terminal electrodes E1 exposed to one surface 1a side. The insulating layers 12, 14 and 15 are formed of a core material obtained by impregnating a core material with a resin material, and the insulating layers 11 and 13 are formed of a resin material containing no core material. Thus, the insulating layer 11 is formed of a resin material containing no core material, which can reduce a diameter of a via conductor 31 formed in the insulating layer 11. Thereby, even when a plurality of terminal electrodes E1 having narrow pitches are formed in the conductor layer L1, routing of wiring can be suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a substrate with built-in electronic components and a manufacturing method thereof, and more particularly to a substrate with built-in electronic components having a multi-layer wiring structure and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a substrate with built-in electronic components having a multi-layer wiring structure. The substrate with built-in electronic components disclosed in Patent Document 1 has an insulating layer in which electronic components are embedded, two wiring layers provided on one surface side of the insulating layer in which the electronic components are embedded, and two wiring layers provided on the other surface side of the insulating layer in which the electronic components are embedded. The insulating layer located between the two wiring layers uses a core material such as glass cloth impregnated with a resin material, thereby ensuring the mechanical strength of the entire substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-339421 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, since it is difficult to form fine via holes in a core material in which a resin material is impregnated into a core material, there is little design freedom in terms of layout for the wiring layer formed on the surface of the core material. In particular, there is a problem in that wiring is required to be routed in order to form multiple terminal electrodes with a narrow pitch, resulting in long wiring distances.

[0005] SUMMARY OF THE PRESENT DISCLOSURE An object of the present invention is to provide a substrate with built-in electronic components that allows greater freedom in designing the outermost conductor layer including the terminal electrodes, and a method for manufacturing the same. [Means for solving the problem]

[0006] The electronic component-embedded substrate according to the present invention comprises a plurality of conductor layers and a plurality of insulating layers each located between two of the plurality of conductor layers adjacent in a stacking direction, the plurality of insulating layers including a first insulating layer in which an electronic component is embedded, the plurality of conductor layers including first, second and third conductor layers stacked on one surface side of the first insulating layer, and fourth, fifth and sixth conductor layers stacked on the other surface side of the first insulating layer, the plurality of insulating layers including a second insulating layer located between the first conductor layer and the second conductor layer, and the third conductor layer, a fourth insulating layer located between the fourth conductor layer and the fifth conductor layer, and a fifth insulating layer located between the fifth conductor layer and the sixth conductor layer, wherein the first conductor layer includes a plurality of terminal electrodes exposed on one surface side, and the sixth conductor layer includes a plurality of terminal electrodes exposed on the other surface side, the third and fourth insulating layers are made of a core material in which a core material is impregnated with a resin material, and at least one of the second and fifth insulating layers is made of a resin material that does not include a core material.

[0007] According to the present invention, since at least one of the second and fifth insulating layers is made of a resin material that does not contain a core material, the diameter of the via conductor formed in at least one of the second and fifth insulating layers can be reduced. This makes it possible to reduce the wiring layout even when multiple terminal electrodes with a narrow pitch are formed in the first or sixth conductor layer.

[0008] In the present invention, both the second and fifth insulating layers may be made of a resin material that does not contain a core material, which allows the diameter of the via conductors formed in the second and fifth insulating layers to be reduced, making it possible to reduce wiring even when multiple terminal electrodes with a narrow pitch are formed in the first and sixth conductor layers.

[0009] In the present invention, the second and third conductor layers may include a plurality of signal wiring patterns connected to electronic components, the third insulating layer may include a coreless region that does not include a core material locally, the coreless region overlaps with the electronic components in a plan view, and the signal wiring patterns included in the second conductor layer and the signal wiring patterns included in the third conductor layer may be connected to each other through a plurality of via conductors that penetrate the coreless region. This makes it possible to reduce the diameter of the via conductors that penetrate the coreless region.

[0010] In the present invention, the first and third conductor layers may include a plurality of signal wiring patterns connected to an electronic component, the third insulating layer may have an opening that overlaps with the electronic component in a plan view, and the plurality of signal wiring patterns included in the first conductor layer and the plurality of signal wiring patterns included in the third conductor layer may be connected to each other through a plurality of via conductors that pass through the openings. This makes it possible to reduce the diameter of the plurality of via conductors that pass through the openings.

[0011] The manufacturing method of a substrate with built-in electronic components according to the present invention includes the steps of: preparing a precursor including a first insulating layer in which electronic components are embedded, first and second conductor layers laminated on one surface side of the first insulating layer, third and fourth conductor layers laminated on the other surface side of the first insulating layer, a second insulating layer located between the first conductor layer and the second conductor layer and made of a core material having a core material impregnated with a resin material, and a third insulating layer located between the third conductor layer and the fourth conductor layer and made of a core material having a core material impregnated with a resin material; and forming fifth and sixth conductor layers on the surfaces of the first and fourth conductor layers via fourth and fifth insulating layers, respectively, wherein at least one of the fourth and fifth insulating layers is made of a resin material that does not contain a core material.

[0012] According to the present invention, since at least one of the fourth and fifth insulating layers is made of a resin material that does not contain a core material, the diameter of the via conductor formed in at least one of the fourth and fifth insulating layers can be reduced, which makes it possible to reduce the wiring layout even when multiple terminal electrodes with a narrow pitch are formed in the fifth or sixth conductor layer.

[0013] In the present invention, both the fourth and fifth insulating layers may be made of a resin material that does not contain a core material, which allows the diameter of the via conductors formed in the fourth and fifth insulating layers to be reduced, making it possible to reduce wiring even when multiple terminal electrodes with a narrow pitch are formed in the fifth and sixth conductor layers.

[0014] The method for manufacturing an electronic component-embedded substrate according to the present invention may further include a step of connecting the signal wiring patterns included in the first conductor layer and the signal wiring patterns included in the second conductor layer to each other through a plurality of via conductors that penetrate a coreless region that does not include a core material locally in the second insulating layer, thereby making it possible to reduce the diameter of the plurality of via conductors that penetrate the coreless region.

[0015] The method for manufacturing a substrate with built-in electronic components according to the present invention may further include a step of connecting the signal wiring patterns included in the fifth conductor layer and the signal wiring patterns included in the second conductor layer through a plurality of via conductors that pass through openings provided in the second insulating layer, thereby making it possible to reduce the diameter of the via conductors that pass through the openings. Effect of the Invention

[0016] As described above, according to the present invention, it is possible to provide a substrate with built-in electronic components, which allows greater freedom in designing the outermost conductor layer including the terminal electrodes, and a method for manufacturing the same. [Brief description of the drawings]

[0017] [Figure 1]FIG. 1 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 1 according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Diagram 3] FIG. 3 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. [Figure 4] FIG. 4 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. [Diagram 5] FIG. 5 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. [Figure 6] FIG. 6 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Figure 7] FIG. 7 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Figure 8] FIG. 8 is a process diagram for explaining a method for manufacturing the electronic component built-in substrate 1. [Figure 9] FIG. 9 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Figure 10] FIG. 10 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 1. As shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 2 according to the second embodiment of the present invention. [Figure 12] FIG. 12 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 3 according to the third embodiment of the present invention. [Figure 13] FIG. 13 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 3. As shown in FIG. [Figure 14] FIG. 14 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 3. As shown in FIG. [Figure 15] FIG. 15 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 3. As shown in FIG. [Figure 16] FIG. 16 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 3. As shown in FIG. [Figure 17]FIG. 17 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 4 according to the fourth embodiment of the present invention. [Figure 18] FIG. 18 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 4. As shown in FIG. [Figure 19] FIG. 19 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 4. As shown in FIG. [Figure 20] FIG. 20 is a process chart for explaining a method for manufacturing the electronic component built-in substrate 4. As shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0019] <First embodiment> FIG. 1 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 1 according to a first embodiment of the present invention.

[0020] 1, the electronic component built-in substrate 1 according to the first embodiment includes six conductor layers L1 to L6, and insulating layers 11 to 15 located between two conductor layers adjacent to each other in the stacking direction. Here, insulating layer 11 is located between conductor layers L1 and L2, insulating layer 12 is located between conductor layers L2 and L3, insulating layer 13 is located between conductor layers L3 and L4, insulating layer 14 is located between conductor layers L4 and L5, and insulating layer 15 is located between conductor layers L5 and L6. Each of insulating layers 11 to 15 is an interlayer film having conductor layers on both sides, and in this sense, solder resists 21 and 22 do not correspond to insulating layers.

[0021] The conductor layer L1 is located at the top layer, and a part of it is covered with a solder resist 21. The exposed part of the conductor layer L1 that is not covered with the solder resist 21 constitutes a terminal electrode E1 that is located on one surface 1a of the electronic component built-in substrate 1. The conductor layer L6 is located at the bottom layer, and a part of it is covered with a solder resist 22. The exposed part of the conductor layer L6 that is not covered with the solder resist 22 constitutes a terminal electrode E2 that is located on the other surface 1b of the electronic component built-in substrate 1. Electronic components such as semiconductor ICs and passive components (not shown) are mounted on the surface 1a of the electronic component built-in substrate 1. The surface 1b of the electronic component built-in substrate 1 is used as a mounting surface for another circuit board (not shown), or electronic components such as semiconductor ICs and passive components (not shown) are mounted on the surface 1a.

[0022] Of the insulating layers 11 to 15, the insulating layers 12, 14, and 15 are made of a core material in which a core material such as glass fiber is impregnated with a resin material such as epoxy. Since the core material has high strength, the mechanical strength of the electronic component built-in substrate 1 is mainly ensured by the insulating layers 12, 14, and 15. In contrast, the insulating layers 11 and 13 are made of a resin material that does not contain a core material such as glass cloth. A resin material that does not contain a core material such as glass cloth is easier to process than a core material, and it is possible to form small-diameter via holes at a narrow pitch.

[0023] The insulating layer 13 is composed of two insulating layers 13a and 13b, and an electronic component 40 such as a semiconductor IC is embedded in the interface between the two. The electronic component 40 is mounted on the surface of the insulating layer 13a in a face-up manner so that a main surface 41 on which electrode pads are provided faces the front surface 1a. When the electronic component 40 is a semiconductor IC, the chip thickness may be reduced to 200 μm or less, for example, about 50 to 100 μm.

[0024] As shown in Fig. 1, two conductor layers adjacent in the stacking direction are connected to each other by a via conductor. For example, the conductor layers L1 and L2 are connected to each other through a via conductor 31 provided to penetrate the insulating layer 11, the conductor layers L2 and L3 are connected to each other through a via conductor 32 provided to penetrate the insulating layer 12, the conductor layers L3 and L4 are connected to each other through a via conductor 33 provided to penetrate the insulating layer 13, the conductor layers L4 and L5 are connected to each other through a via conductor 34 provided to penetrate the insulating layer 14, and the conductor layers L5 and L6 are connected to each other through a via conductor 35 provided to penetrate the insulating layer 15. Furthermore, the conductor layer L3 and the electronic component 40 are connected to each other through a via conductor 36 provided to penetrate the insulating layer 13b.

[0025] Here, the insulating layers 12, 14, 15 made of a core material and the insulating layers 11, 13 made of a resin material that does not contain a core material such as glass cloth have significantly different processability. That is, the insulating layers 11, 13 made of a resin material have excellent processability, so that small-diameter via holes can be easily formed, whereas the insulating layers 12, 14, 15 made of a core material have difficulty in forming small-diameter via holes due to the presence of a core material such as glass cloth. Therefore, the via conductors 32, 34, 35 that penetrate the insulating layers 12, 14, 15 are inevitably larger in diameter than the via conductors 31, 33 that penetrate the insulating layers 11, 13. Thus, it is difficult to form the via conductors 32, 34, 35 at a narrow pitch compared to the via conductors 31, 33.

[0026] In this embodiment, the uppermost conductor layer L1 is formed on the surface of the insulating layer 11 made of a resin material that does not contain a core material such as glass cloth, so that a large number of small-diameter via conductors 31 can be formed at a narrow pitch. Therefore, even if the electrode pitch of the electronic component mounted on one surface 1a side is narrow, the wiring formed on the conductor layer L1 can be shortened, making the layout design easier.

[0027] In this way, since the electronic component built-in substrate 1 according to this embodiment has six conductor layers L1 to L6, more complicated wiring can be formed. Moreover, since the outermost insulating layer 11 located on one surface 1a side is made of a resin material that does not contain a core material such as glass cloth, even when an electronic component with a narrow terminal pitch is mounted on one surface 1a side, the layout design is easy. This effect is remarkable when an electronic component with wire bonding pads requiring many terminals is mounted on the surface layer located on the circuit surface side of the built-in electronic component 40, that is, on the surface 1a side if the built-in electronic component 40 is a face-up type. In this case, many wirings are required to connect the electronic components to each other, but according to this embodiment, these wirings can be laid out at a high density, which greatly contributes to miniaturization. Moreover, since the insulating layers 12, 14, and 15 are made of a core material in which a core material is impregnated with a resin material, the mechanical strength of the electronic component built-in substrate 1 can be sufficiently ensured.

[0028] In this embodiment, since the insulating layers 11 and 15 are made of different materials, there is no symmetry in the stacking direction, and as a result, there is a risk of warping in the electronic component built-in substrate 1. This is because the insulating layer 11 does not contain a core material and therefore has a larger thermal expansion coefficient than the insulating layer 15, which does contain a core material. In order to suppress such warping, a resin material may be selected so that the thermal expansion coefficient of the insulating layer 12 is smaller than the thermal expansion coefficients of the insulating layers 14 and 15. Alternatively or in addition to this, the thickness of the insulating layer 12 may be made thinner than the insulating layers 14 and 15. This increases the symmetry of the thermal expansion coefficient in the stacking direction, making it less likely that the electronic component built-in substrate 1 will warp.

[0029] Next, a method for manufacturing the electronic component built-in substrate 1 according to this embodiment will be described.

[0030] 2 to 10 are process diagrams illustrating a method for manufacturing the electronic component built-in substrate 1 according to this embodiment.

[0031] First, as shown in FIG. 2, a base material is prepared in which conductor layers L4, L5 made of Cu foil or the like are formed on both sides of an insulating layer 14 made of a core material, and this is fixed to a support 50. Next, as shown in FIG. 3, the conductor layer L4 is patterned using a known method such as photolithography to complete the conductor layer L4 having a desired pattern shape. Next, as shown in FIG. 4, an insulating layer 13a is formed by laminating, for example, an uncured (B-stage state) resin sheet or the like on the surface of the insulating layer 14 by vacuum pressure bonding or the like so as to embed the patterned conductor layer L4. Next, an electronic component 40 is placed on the surface of the insulating layer 13a. The electronic component 40 is mounted in a face-up manner so that a main surface 41 on which the electrode pads are exposed faces upward.

[0032] Next, as shown in FIG. 5, the insulating layer 13b and the conductor layer L3 are formed so as to cover the electronic component 40. The insulating layer 13b is preferably formed, for example, by applying an uncured or semi-cured thermosetting resin, heating it to semi-cure it in the case of the uncured resin, and then curing and molding it together with the conductor layer L3 using a press means. The material used for the insulating layer 13b may be the same as that for the insulating layer 13a. In general, the pad size of the built-in electronic component 40 is smaller than that of the terminal electrodes E1 and E2, and a narrow pad pitch is required. Therefore, it is necessary to form a small diameter via in the insulating layer formed on the built-in electronic component 40. Considering this point, it is preferable to use a resin material that does not contain a core material such as glass cloth as the insulating layer 13b.

[0033] 6, via holes are formed in the insulating layer 13, and then via conductors 33 and 36 are formed to fill the via holes. The conductor layer L3 is then patterned using a known method such as photolithography to complete the conductor layer L3 having a desired pattern shape. As a result, a part of the conductor layer L3 is connected to the conductor layer L4 through the via conductor 33, and another part of the conductor layer L3 is connected to the electronic component 40 through the via conductor 36.

[0034] Next, as shown in Fig. 7, the sheet in which the insulating layer 12 and the conductor layer L2 are laminated is vacuum hot pressed so as to embed the conductor layer L3. The material and thickness used for the insulating layer 12 may be the same as those of the insulating layer 14. Thereafter, the support 50 is peeled off as shown in Fig. 8.

[0035] Next, as shown in FIG. 9, via holes are formed in the insulating layers 12 and 14, and then via conductors 32 and 34 are formed to fill the via holes. Furthermore, the conductor layers L2 and L5 are patterned using a known method such as photolithography to complete the conductor layers L2 and L5 having a desired pattern shape. As a result, a part of the conductor layer L2 is connected to the conductor layer L3 through the via conductor 32, and a part of the conductor layer L5 is connected to the conductor layer L4 through the via conductor 34. When forming the via holes in the insulating layers 12 and 14, it is necessary to remove the core material present at the relevant position, so the diameter of the via hole is inevitably large. Accordingly, the diameters of the via conductors 32 and 34 are also large. As a result, a precursor of an electronic component-embedded substrate having four conductor layers L2 to L5 is completed.

[0036] Next, as shown in Fig. 10, a sheet having insulating layer 11 and conductor layer L1 laminated thereon and a sheet having insulating layer 15 and conductor layer L6 laminated thereon are prepared, and the precursor having conductor layers L2 to L5 is sandwiched between these sheets and vacuum hot pressed. Then, via holes are formed in insulating layers 11 and 15, and via conductors 31 and 35 are formed to fill the via holes. Furthermore, the conductor layers L1 and L6 are patterned using a known method such as photolithography, and solder resists 21 and 22 are formed, completing the electronic component-embedded substrate 1 shown in Fig. 1.

[0037] Here, since the insulating layer 11 does not contain a core material such as glass cloth, small diameter via holes can be formed at a narrow pitch by laser processing or blasting in the process of forming via holes in the insulating layer 11. This improves the design freedom of the layout of the conductor layer L1 compared to the case where a core material is used as the material for the insulating layer 11.

[0038] <Second embodiment> FIG. 11 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 2 according to the second embodiment of the present invention.

[0039] 11, the electronic component built-in substrate 2 according to the second embodiment differs from the electronic component built-in substrate 1 according to the first embodiment in that the insulating layer 15 located on the bottom layer side is made of a resin material that does not contain a core material such as glass cloth. Since the other basic configuration is the same as that of the electronic component built-in substrate 1 according to the first embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0040] In this embodiment, the conductor layer L6 located at the bottom layer is formed on the surface of the insulating layer 15 made of a resin material that does not contain a core material such as glass cloth, so that a large number of small-diameter via conductors 35 can be formed at narrow pitches. This makes it easy to design the layout of the conductor layer L6 even when the electrode pitch of electronic components mounted on not only one surface 1a but also the other surface 1b is narrow.

[0041] <Third embodiment> FIG. 12 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 3 according to the third embodiment of the present invention.

[0042] 12, the electronic component built-in substrate 3 according to the third embodiment differs from the electronic component built-in substrate 2 according to the second embodiment in that a core-free region 12A that does not contain a core material is locally provided in the insulating layer 12. Since the other basic configuration is the same as that of the electronic component built-in substrate 2 according to the second embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0043] 12, a coreless region 12A is provided at a position overlapping with an electronic component 40 in a plan view, and a signal terminal of the electronic component 40 is connected to a plurality of signal wiring patterns S3 included in the conductor layer L3 through a via conductor 36, and the signal wiring pattern S3 of the conductor layer L3 is connected to a plurality of signal wiring patterns S2 included in the conductor layer L2 through a via conductor 32S. The signal wiring patterns S2 and S3 are connected to each other through a plurality of via conductors 32S penetrating the coreless region 12A. As described above, since the coreless region 12A does not include a core material, the diameter and pitch of the via conductors 32S formed in the coreless region 12A can be made smaller than the diameter and pitch of the via conductors 32 formed in other regions of the insulating layer 12.

[0044] As a result, even if the electronic component 40 has a large number of signal terminals, the signal wiring patterns S2, S3 can be connected to the conductor layer L1 over the shortest distance without making a detour.

[0045] Next, a method for manufacturing the electronic component built-in substrate 3 according to this embodiment will be described.

[0046] 13 to 16 are process diagrams illustrating a method for manufacturing the electronic component built-in substrate 3 according to this embodiment.

[0047] First, after the steps described with reference to Fig. 2 to Fig. 6, a sheet in which an insulating layer 12 having a coreless region 12A and a conductor layer L2 are laminated is vacuum hot pressed as shown in Fig. 13. The coreless region 12A is positioned so as to overlap with a signal wiring pattern S3 included in the conductor layer L3. Then, the support 50 is peeled off as shown in Fig. 14. The coreless region 12A of the insulating layer 12 may be formed by punching with a die press or processing with a drill or laser while the insulating layer 12 is in an uncured state before vacuum hot pressing.

[0048] 15, via holes are formed in the insulating layers 12 and 14, and then via conductors 32 and 34 are formed to fill the via holes, and the conductor layers L2 and L5 are patterned using a known method such as photolithography to complete the conductor layers L2 and L5 having a desired pattern shape. As a result, the signal wiring pattern S3 included in the conductor layer L2 is connected to the signal wiring pattern S3 of the conductor layer L3 through the via conductor 32S.

[0049] Next, as shown in Fig. 16, the precursor is sandwiched between a sheet in which insulating layer 11 and conductor layer L1 are laminated and a sheet in which insulating layer 15 and conductor layer L6 are laminated, and vacuum hot press is performed. Then, via holes are formed in insulating layers 11 and 15, and via conductors 31 and 35 are formed to fill the via holes. Furthermore, conductor layers L1 and L6 are patterned using a known method such as photolithography, and solder resists 21 and 22 are formed, completing electronic component-embedded substrate 3 shown in Fig. 12.

[0050] In this manner, in the present embodiment, since the insulating layer 12 has a core-free region 12A that does not contain a core material such as glass cloth, it is possible to reduce the diameter and pitch of the via conductors 32S while maintaining the mechanical strength of the insulating layer 12.

[0051] <Fourth embodiment> FIG. 17 is a schematic cross-sectional view for illustrating the structure of an electronic component built-in substrate 4 according to the fourth embodiment of the present invention.

[0052] 17, the electronic component built-in substrate 4 according to the fourth embodiment differs from the electronic component built-in substrate 2 according to the second embodiment in that an opening 12B is provided in the insulating layer 12. Since the other basic configurations are the same as those of the electronic component built-in substrate 2 according to the second embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0053] In the example shown in FIG. 17, an opening 12B is provided at a position overlapping with an electronic component 40 in a plan view. The opening 12B is an area where the insulating layer 12 does not exist (is removed), and the inside of the opening 12B is filled with an insulating layer 11. In this embodiment, a signal terminal of the electronic component 40 is connected to a plurality of signal wiring patterns S3 included in the conductor layer L3 through a via conductor 36, and the signal wiring pattern S3 of the conductor layer L3 is connected to a plurality of signal wiring patterns S1 included in the conductor layer L1 through a via conductor 31S. The signal wiring patterns S1 and S3 are connected to each other through a plurality of via conductors 31S that penetrate the opening 12B. As described above, since the insulating layer 12 does not exist in the opening 12B and is filled with the insulating layer 11, the diameter and pitch of the via conductor 31S formed in the opening 12B can be reduced compared to the diameter and pitch of the via conductor 32 formed in the insulating layer 12.

[0054] As a result, even if the electronic component 40 has many signal terminals, the signal wiring patterns S2 and S3 can be connected to the conductor layer L1 over the shortest distance without making a detour, as in the third embodiment. Moreover, the via conductor 31S directly connects the signal wiring patterns S1 and S3, further shortening the wiring distance between the electronic component 40 and the terminal electrode E1.

[0055] Next, a method for manufacturing the electronic component built-in substrate 4 according to this embodiment will be described.

[0056] 18 to 20 are process diagrams illustrating a method for manufacturing an electronic component built-in substrate 4 according to this embodiment.

[0057] First, after the steps described with reference to Figures 2 to 8, the conductor layers L2 and L5 are patterned to complete the conductor layers L2 and L5 having a desired pattern shape, as shown in Figure 18. At this time, the conductor layer L2 on the insulating layer 12 is entirely removed in the region where the opening 12B is to be formed. Next, as shown in Figure 19, the insulating layer 12 is partially removed by a well-known technique such as drilling or laser processing to form the opening 12B.

[0058] Next, as shown in Fig. 20, the precursor is sandwiched between a sheet in which insulating layer 11 and conductor layer L1 are laminated and a sheet in which insulating layer 15 and conductor layer L6 are laminated, and vacuum hot press is performed. Then, via holes are formed in insulating layers 11 and 15, and via conductors 31 and 35 are formed to fill the via holes. Furthermore, conductor layers L1 and L6 are patterned using a known method such as photolithography, and solder resists 21 and 22 are formed, completing electronic component-embedded substrate 4 shown in Fig. 17.

[0059] In this manner, in the present embodiment, since the openings 12B are provided in the insulating layer 12, it is possible to reduce the diameter and pitch of the via conductors 31S while ensuring the mechanical strength of the insulating layer 12.

[0060] Although a preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention, and it goes without saying that these modifications are also included within the scope of the present invention. [Explanation of symbols]

[0061] 1~4 Electronic component embedded board 1a One surface of a substrate with built-in electronic components 1b The other surface of the electronic component embedded substrate 11~15, 13a, 13b Insulating layer 12A Coreless area 12B opening 21,22 Solder resist 31~36,31S,32S Via conductor 40 Electronic Components 41 Main surface of electronic components 50 Support E1,E2 terminal electrode L1~L6 conductor layer S1~S3 signal wiring pattern

Claims

1. A plurality of conductor layers; a plurality of insulating layers each positioned between two adjacent conductor layers in a stacking direction among the plurality of conductor layers; the plurality of insulating layers includes a first insulating layer having an electronic component embedded therein; the plurality of conductor layers include first, second and third conductor layers stacked on one surface side of the first insulating layer, and fourth, fifth and sixth conductor layers stacked on the other surface side of the first insulating layer; the plurality of insulating layers further include a second insulating layer located between the first conductor layer and the second conductor layer, a third insulating layer located between the second conductor layer and the third conductor layer, a fourth insulating layer located between the fourth conductor layer and the fifth conductor layer, and a fifth insulating layer located between the fifth conductor layer and the sixth conductor layer; the first conductor layer includes a plurality of terminal electrodes exposed on one surface side, the sixth conductor layer includes a plurality of terminal electrodes exposed on the other surface side, The third and fourth insulating layers are made of a core material impregnated with a resin material, At least one of the second and fifth insulating layers is made of a resin material that does not contain a core material, the second and third conductor layers each include a plurality of signal wiring patterns connected to the electronic components; the third insulating layer locally includes a core-free region that does not include the core material, the coreless region overlaps with the electronic component in a plan view, An electronic component-embedded substrate, characterized in that the multiple signal wiring patterns included in the second conductor layer and the multiple signal wiring patterns included in the third conductor layer are connected to each other through multiple via conductors that penetrate the coreless material region.

2. 2. The electronic component built-in substrate according to claim 1, wherein both the second and fifth insulating layers are made of a resin material that does not contain a core material.

3. a step of preparing a precursor including a first insulating layer having an electronic component embedded therein, first and second conductor layers laminated on one surface side of the first insulating layer, third and fourth conductor layers laminated on the other surface side of the first insulating layer, a second insulating layer located between the first conductor layer and the second conductor layer and made of a core material obtained by impregnating a core material with a resin material, and a third insulating layer located between the third conductor layer and the fourth conductor layer and made of a core material obtained by impregnating a core material with a resin material; a step of connecting a plurality of signal wiring patterns included in the first conductor layer and a plurality of signal wiring patterns included in the second conductor layer to each other through a plurality of via conductors that penetrate a core-free region of the second insulating layer that does not locally include the core material; forming fifth and sixth conductor layers on the surfaces of the first and fourth conductor layers via fourth and fifth insulating layers, respectively; 2. A method for manufacturing a substrate with built-in electronic components, wherein at least one of the fourth and fifth insulating layers is made of a resin material that does not contain a core material.

4. 4. The method for manufacturing a substrate with built-in electronic components according to claim 3, wherein both the fourth and fifth insulating layers are made of a resin material that does not contain a core material.

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