Display device

Abstract

To provide a shift resistor that has reduced noise in an output signal and can prevent a deterioration in the characteristics of a transistor.SOLUTION: A display is provided with a first transistor, a second transistor, a third transistor, and a fourth transistor. In the first transistor, a first terminal is connected with first wiring, a second terminal is connected with a gate terminal of the second transistor, and the gate terminal is connected with fifth wiring. In the second transistor, a first terminal is connected with third wiring, and a second terminal is connected with sixth wiring. In the third transistor, a first terminal is connected with second wiring, a second terminal is connected with the gate terminal of the second transistor, and the gate terminal is connected with fourth wiring. In the fourth transistor, a first terminal is connected with the second wiring, a second terminal is connected with the sixth wiring, and the gate terminal is connected with the fourth wiring.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a liquid crystal display device, and more particularly to a shift register configured using transistors. The present invention also relates to a liquid crystal display device having a pixel, a driving method for the liquid crystal display device, and a method for driving the liquid crystal display device. The present invention relates to electronic equipment that has the liquid crystal display device as a display unit. [Background technology]

[0002] In recent years, the development of LCD devices has been actively promoted due to the increase in large display devices such as LCD TVs. In particular, non-crystalline semiconductor (hereinafter referred to as amorphous silicon) is used on an insulating substrate. A pixel circuit and a driving circuit including a shift register and the like are formed using a transistor configured by the above. The technology of forming an integrated circuit (hereinafter referred to as internal circuit) has contributed greatly to reducing power consumption and costs. The internal circuit formed on the insulating substrate is It is connected to a controller IC (hereinafter referred to as an external circuit) via a PC, etc., and its operation is To be controlled.

[0003] Among the internal circuits shown above, the circuit using transistors made of amorphous semiconductors A shift register shown in Patent Document 1 has been devised (for example, Patent Document 1). The output terminal of the shift register is floating for a long period of time, so noise is transmitted to the shift register. This problem of the shift register in Patent Document 1 was solved by To solve this problem, a shift register configuration was devised that does not leave the output terminal floating. (For example, Non-Patent Document 1) [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special table 10-500243 [Non-patent literature]

[0005] [Non-Patent Document 1] 2.0inch a-Si:H TFT-LCD with Low Noise Integrated Gate Driver SID'05 Digest P942-945 Summary of the Invention [Problem to be solved by the invention]

[0006] In the above-mentioned Non-Patent Document 1, during the non-selection period, a transistor connected between the output terminal and the negative power supply Therefore, the output terminal of the shift register shown in Non-Patent Document 1 is not floating, and the shift register shown in Non-Patent Document 1 reduces noise in the output signal. It can be made smaller.

[0007] However, a transistor made of an amorphous semiconductor has a time when it is turned on, and an applied It is known that the characteristics deteriorate depending on the voltage, etc. The threshold voltage shift, which is a shift (rise) of the Therefore, in the shift register shown in Non-Patent Document 1, The transistor connected between the output terminal and the negative power supply is turned on, so this transistor The characteristics of the device deteriorate, resulting in malfunction.

[0008] In view of such a problem, it is desirable to reduce noise in the output signal and Liquid crystal display device having a shift register capable of suppressing deterioration of characteristics of the shift register, and Another object of the present invention is to provide an electronic device equipped with the liquid crystal display device. [Means for solving the problem]

[0009] The liquid crystal display device according to the present invention comprises a pixel section and a shift register formed integrally with the pixel section on an insulating substrate. The shift register has a plurality of flip-flops. Each of the multiple flip-flops turns on at regular intervals during the non-selection period, and the output terminal (scan line) has a transistor that outputs a power supply potential. By turning on the power supply voltage to the scanning line every time the power supply voltage is supplied, multiple flip-flops and Each of these suppresses fluctuations in the potential of the scanning line and suppresses deterioration of the characteristics of the transistor.

[0010] The liquid crystal display device of the present invention includes a first pixel and a second pixel each having a liquid crystal element, a driver circuit, The first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring and the first pixel is electrically connected to the driving circuit via the fifth wiring. The second pixel is electrically connected to the driving circuit via the sixth wiring. The circuit includes a shift register, the shift register includes a plurality of flip-flops, and At least one of the flip-flops includes a first transistor, a second transistor, and a a first terminal of the first transistor, a third transistor, and a fourth transistor; is electrically connected to the first wiring, and the second terminal of the first transistor is electrically connected to the second transistor the gate terminal of the first transistor is electrically connected to the fifth wiring. a first terminal of the second transistor electrically connected to the third wiring, and a second terminal of the second transistor electrically connected to the third wiring; The first terminal of the third transistor is electrically connected to the sixth wiring, and the first terminal of the third transistor is electrically connected to the second wiring. the second terminal is electrically connected to the gate terminal of the second transistor, and the gate The terminal is electrically connected to the fourth wiring, and the first terminal of the fourth transistor is electrically connected to the second wiring. the second terminal of the fourth transistor is electrically connected to the sixth wiring, and the fourth a gate terminal of the transistor is electrically connected to a fourth wiring. do.

[0011] The liquid crystal display device of the present invention includes a first pixel and a second pixel each having a liquid crystal element, and a drive circuit. a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring; The first pixel is electrically connected to the driving circuit via the fifth wiring, and The second pixel is electrically connected to the driving circuit via the first wiring, and the driving circuit A shift register is provided, and the shift register has a plurality of flip-flops. At least one of the flip-flops includes a first transistor, a second transistor, a third transistor, and a a first terminal of the first transistor and a fourth transistor; and a second terminal electrically connected to the gate terminal of the second transistor. The second transistor has a gate terminal electrically connected to a fifth wiring, and a first terminal The third terminal is electrically connected to the third wiring, the second terminal is electrically connected to the first wiring, and the third transistor The first terminal of the transistor is electrically connected to the gate terminal of the second transistor, and the second terminal of the transistor is electrically connected to the gate terminal of the second transistor. is electrically connected to the second wiring, the gate terminal is electrically connected to the fourth wiring, and the fourth The transistor has a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring. the gate terminal is electrically connected to the fourth wiring. do.

[0012] In the present invention, the first transistor, the second transistor, and the third transistor The first and fourth transistors may be N-channel transistors.

[0013] In the present invention, the first transistor, the second transistor, and the third transistor The first transistor and the fourth transistor have a semiconductor layer, and the semiconductor layer is made of amorphous silicon. It's okay to have it.

[0014] In the present invention, a capacitance element is provided between the second terminal and the gate terminal of the first transistor. may be arranged.

[0015] The liquid crystal display device of the present invention includes a first pixel and a second pixel each having a liquid crystal element, and a drive circuit. a path, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring; and a seventh wiring, and the first pixel is connected to the driving The second pixel is electrically connected to the driving circuit via the sixth wiring. The driving circuit has a shift register, and the shift register has a plurality of flip-flops. At least one of the plurality of flip-flops includes a first transistor. a second transistor, a third transistor, a fourth transistor and a fifth transistor The first transistor has a first terminal electrically connected to the first wiring and a second terminal The second transistor is electrically connected to a gate terminal of the second transistor, and the gate terminal is electrically connected to a fifth wiring. the first terminal of the second transistor is electrically connected to the third wiring, and the second transistor is electrically connected to the third wiring. The third transistor has a second terminal electrically connected to the sixth wiring, and a first terminal electrically connected to the second transistor. a first terminal electrically connected to the gate terminal of the transistor, and a second terminal electrically connected to the second wiring; The gate terminal of the fourth transistor is electrically connected to the fourth wiring, and the first terminal of the fourth transistor is electrically connected to the sixth wiring. the gate terminal is electrically connected to the fourth wiring, the second terminal is electrically connected to the second wiring, and the gate terminal is The fifth transistor has a first terminal electrically connected to the sixth wiring. The second terminal is electrically connected to the second wiring, and the gate terminal is electrically connected to the seventh wiring. It is characterized by being connected.

[0016] The liquid crystal display device of the present invention includes a first pixel and a second pixel each having a liquid crystal element, and a drive circuit. a path, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a sixth wiring; and a wiring of the first pixel, the first pixel being electrically connected to the driving circuit via the fifth wiring. the second pixel is electrically connected to the driving circuit via the first wiring. The driving circuit has a shift register, and the shift register has a plurality of flip-flops. At least one of the plurality of flip-flops includes a first transistor, a second transistor, and a a third transistor, a fourth transistor and a fifth transistor, The first transistor has a first terminal electrically connected to the fifth wiring and a second terminal electrically connected to the second transistor. The gate terminal is electrically connected to the fifth wiring. The second transistor has a first terminal electrically connected to the third wiring and a second terminal electrically connected to the sixth wiring. a third transistor having a first terminal electrically connected to the second wiring; the second terminal is electrically connected to a gate terminal of the second transistor, and the gate terminal is connected to the first The fourth transistor is electrically connected to the first wiring, and the first terminal of the fourth transistor is electrically connected to the first wiring. the second terminal is electrically connected to the second wiring, and the gate terminal is electrically connected to the fourth wiring. and the fifth transistor has a first terminal electrically connected to the sixth wiring and a second terminal The gate terminal is electrically connected to the second wiring, and the gate terminal is electrically connected to the first wiring. It is characterized by the following.

[0017] In the present invention, the first transistor, the second transistor, and the third transistor The first transistor, the fourth transistor, and the fifth transistor are N-channel transistors. Good too.

[0018] In the present invention, the first transistor, the second transistor, and the third transistor The first transistor, the fourth transistor, and the fifth transistor each have a semiconductor layer, and the semiconductor layer is an amorphous silicon layer. It may also be rufus silicon.

[0019] In the present invention, the second terminal of the first transistor and the gate of the first transistor A capacitive element may be disposed between the terminals.

[0020] The liquid crystal display device of the present invention includes first to fourth pixels each having a liquid crystal element, and a first A drive circuit, a second drive circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring. line, the fifth wire, the sixth wire, the seventh wire, the eighth wire, the ninth wire, and the first The first pixel has the fifth wiring, the eleventh wiring, and the twelfth wiring. The second pixel is electrically connected to the first driving circuit through a wiring, and the sixth pixel is electrically connected to the sixth driving circuit through a wiring. the third pixel is electrically connected to the first driving circuit via the eleventh line, the fourth pixel is electrically connected to the second driving circuit via a line, and the fourth pixel is electrically connected to the twelfth line. The first driver circuit is electrically connected to the second driver circuit via a line, and the first driver circuit is the second driver circuit has a second shift register, and the first shift register has a plurality of flip-flops, at least one of the plurality of flip-flops a first transistor, a second transistor, a third transistor, and a fourth transistor The first transistor has a first terminal electrically connected to the first wiring and a second terminal The second transistor is electrically connected to a gate terminal thereof, and the gate terminal is electrically connected to a fifth wiring. and the second transistor has a first terminal electrically connected to the third wiring and a second terminal The third transistor has a first terminal electrically connected to the sixth wiring, and a second terminal electrically connected to the second wiring. the second terminal is electrically connected to the gate terminal of the second transistor, and the gate The fourth transistor has a first terminal electrically connected to the second wiring, and a second terminal electrically connected to the third wiring. the second terminal is electrically connected to the sixth wiring, and the gate terminal is electrically connected to the fourth wiring. a second shift register electrically connected to the line, the second shift register having a plurality of flip-flops, At least one of the flip-flops includes a fifth transistor, a sixth transistor, , a seventh transistor, and an eighth transistor; and the fifth transistor is connected to the first terminal is electrically connected to the seventh wiring, and the second terminal is electrically connected to the gate terminal of the sixth transistor. The sixth transistor is electrically connected to the eleventh wiring, and the gate terminal is electrically connected to the eleventh wiring. The first terminal is electrically connected to the ninth wiring, and the second terminal is electrically connected to the twelfth wiring; The seventh transistor has a first terminal electrically connected to the eighth wiring and a second terminal electrically connected to the sixth wiring. The gate terminal is electrically connected to the gate terminal of the transistor, and the gate terminal is electrically connected to the tenth wiring. The eighth transistor has a first terminal electrically connected to the eighth wiring and a second terminal electrically connected to the eighth wiring. The gate terminal is electrically connected to the 12th wiring and the gate terminal is electrically connected to the 10th wiring. It is characterized by the following.

[0021] In the present invention, the fifth wiring and the eleventh wiring are electrically connected, and the sixth wiring and the twelfth wiring may be electrically connected.

[0022] In the present invention, the fifth wiring and the eleventh wiring are the same wiring, and the sixth wiring The first and second wirings may be the same wiring.

[0023] In the present invention, the first wiring and the seventh wiring are electrically connected, and the second wiring and The third and eighth wirings are electrically connected, the third and ninth wirings are electrically connected, and the fourth wiring is electrically connected. The first wiring and the tenth wiring may be electrically connected.

[0024] In the present invention, the first wiring and the seventh wiring are the same wiring, and the second wiring and The third and eighth wirings are the same wiring, the third and ninth wirings are the same wiring, and the fourth wiring The first wiring and the tenth wiring may be the same wiring.

[0025] In the present invention, the first wiring and the seventh wiring are electrically connected, and the second wiring and The third and eighth wirings are electrically connected, the third and ninth wirings are electrically connected, and the fourth wiring is electrically connected. The first wiring and the tenth wiring are electrically connected, and the fifth wiring and the eleventh wiring are electrically connected. The sixth wiring and the twelfth wiring may be electrically connected to each other.

[0026] In the present invention, the first wiring and the seventh wiring are the same wiring, and the second wiring and The third and eighth wirings are the same wiring, the third and ninth wirings are the same wiring, and the fourth wiring The wiring 10 and the wiring 11 are the same wiring, and the wiring 5 and the wiring 12 are the same wiring. The sixth wiring and the twelfth wiring may be the same wiring.

[0027] The liquid crystal display device of the present invention includes first to fourth pixels each having a liquid crystal element, and a first A drive circuit, a second drive circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring. line, the fifth wire, the sixth wire, the seventh wire, the eighth wire, the ninth wire, and the first 0 wiring, and the first pixel is connected to the first driving circuit via the fifth wiring. The second pixel is electrically connected to the first driving circuit through the first wiring. The third pixel is electrically connected to the second driving circuit through the tenth wiring. the fourth pixel is electrically connected to the second driving circuit via the sixth wiring; The first driver circuit has a first shift register, and the second driver circuit has a second shift register. two shift registers, the first of which has a plurality of flip-flops; At least one of the plurality of flip-flops includes a first transistor, a second transistor, a first transistor, a third transistor, and a fourth transistor, The terminal is electrically connected to the fifth wiring, and the second terminal is electrically connected to the gate terminal of the second transistor. The second transistor is electrically connected to the first wiring, and the gate terminal is electrically connected to the fifth wiring. the first terminal is electrically connected to the third wiring, the second terminal is electrically connected to the first wiring, The third transistor has a first terminal electrically connected to the gate terminal of the second transistor. The second terminal is electrically connected to the second wiring, and the gate terminal is electrically connected to the fourth wiring. The fourth transistor has a first terminal electrically connected to the first wiring and a second terminal electrically connected to the second wiring. the gate terminal is electrically connected to the fourth wiring, and the second shift The register has a plurality of flip-flops, and at least one of the plurality of flip-flops One is the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor. a fifth transistor, a first terminal of which is electrically connected to a tenth wiring; The second terminal is electrically connected to the gate terminal of the sixth transistor, and the gate terminal is electrically connected to the tenth transistor. The sixth transistor has a first terminal electrically connected to the eighth wiring. The seventh transistor has a first terminal electrically connected to the sixth wiring, and a second terminal electrically connected to the sixth wiring. The second terminal is electrically connected to the gate terminal of the sixth transistor, and the third terminal is electrically connected to the seventh wiring. The eighth transistor is electrically connected to the first terminal, and the gate terminal is electrically connected to the ninth wiring. is electrically connected to the sixth wiring, the second terminal is electrically connected to the seventh wiring, and the gate terminal The terminal is electrically connected to the ninth wiring.

[0028] In the present invention, the first wiring and the sixth wiring are electrically connected, and the fifth wiring and The first and tenth wirings may be electrically connected to each other.

[0029] In the present invention, the first wiring and the sixth wiring are the same wiring, and the fifth wiring and The first and tenth wirings may be the same wiring.

[0030] In the present invention, the second wiring and the seventh wiring are electrically connected, and the third wiring and The fourth wiring and the ninth wiring are electrically connected to each other. Good too.

[0031] In the present invention, the second wiring and the seventh wiring are the same wiring, and the third wiring and The fourth wiring and the ninth wiring may be the same wiring. stomach.

[0032] In the present invention, the first wiring and the sixth wiring are electrically connected, and the second wiring and The seventh wiring is electrically connected, the third wiring is electrically connected, and the eighth wiring is electrically connected. The first wiring and the ninth wiring are electrically connected, and the fifth wiring and the tenth wiring are electrically connected. It may be done.

[0033] In the present invention, the first wiring and the sixth wiring are the same wiring, and the second wiring and The seventh wiring is the same wiring, the third wiring is the same wiring, and the eighth wiring is the same wiring. The first wiring and the ninth wiring are the same wiring, and the fifth wiring and the tenth wiring are the same wiring. It's okay to have it.

[0034] In the present invention, the first transistor, the second transistor, and the third transistor the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor The first and eighth transistors may be N-channel transistors.

[0035] In the present invention, the first transistor, the second transistor, and the third transistor the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor The eighth transistor and the eighth transistor have a semiconductor layer, and the semiconductor layer is made of amorphous silicon. It's okay to have it.

[0036] In the present invention, the second terminal of the first transistor and the gate of the first transistor a first capacitance element is disposed between the second terminal of the fifth transistor and the A second capacitive element may be disposed between the gate terminal of the transistor.

[0037] The liquid crystal display device of the present invention includes first to fourth pixels each having a liquid crystal element, and a first A drive circuit, a second drive circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring. line, the fifth wire, the sixth wire, the seventh wire, the eighth wire, the ninth wire, and the first 0 wiring, 11th wiring, 12th wiring, 13th wiring, and 14th wiring. The first pixel is electrically connected to the first driving circuit via the fifth wiring. the second pixel is electrically connected to the first driving circuit via the sixth wiring; the third pixel is electrically connected to the second driving circuit via the twelfth wiring, the fourth pixel is electrically connected to the second driving circuit via the thirteenth wiring; The first driving circuit has a first shift register, and the second driving circuit has a second shift register. the first shift register has a plurality of flip-flops, At least one of the flops includes a first transistor, a second transistor, a third transistor, and a a first transistor, a fourth transistor, and a fifth transistor, The first terminal is electrically connected to the first wiring, and the second terminal is connected to the gate terminal of the second transistor. the gate terminal is electrically connected to the fifth wiring, and the second transistor The first terminal of the capacitor is electrically connected to the third wiring, and the second terminal is electrically connected to the sixth wiring. The third transistor has a first terminal electrically connected to the second wiring and a second terminal electrically connected to the first wiring. The gate terminal of the second transistor is electrically connected to the fourth wiring. the fourth transistor has a first terminal electrically connected to the second wiring and a second terminal is electrically connected to the sixth wiring, the gate terminal is electrically connected to the fourth wiring, and the fifth The transistor has a first terminal electrically connected to the second wiring and a second terminal electrically connected to the sixth wiring. The gate terminal is electrically connected to the seventh wiring, and the second shift register has a plurality of flip-flops, at least one of the plurality of flip-flops The sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and and a tenth transistor, and the sixth transistor has a first terminal electrically connected to the eighth wiring. the second terminal is electrically connected to the gate terminal of the seventh transistor, and the gate terminal The seventh transistor has a first terminal electrically connected to the twelfth wiring, and the seventh transistor has a first terminal electrically connected to the tenth wiring. the second terminal is electrically connected to the thirteenth wiring, and the eighth transistor has a first terminal electrically connected to the ninth wiring and a second terminal electrically connected to the gate of the seventh transistor. the gate terminal is electrically connected to the eleventh wiring, and the ninth transistor The resistor has a first terminal electrically connected to the thirteenth wire and a second terminal electrically connected to the ninth wire. and the gate terminal is electrically connected to an eleventh wiring. The first terminal is electrically connected to the thirteenth wiring, and the second terminal is electrically connected to the ninth wiring. The gate terminal is electrically connected to the fourteenth wiring.

[0038] In the present invention, the fifth wiring and the twelfth wiring are electrically connected, and the sixth wiring and the thirteenth wiring may be electrically connected.

[0039] In the present invention, the fifth wiring and the twelfth wiring are the same wiring, and the sixth wiring The 13th and 14th wires may be the same wire.

[0040] In the present invention, the first wiring and the eighth wiring are electrically connected, and the second wiring and The ninth wiring and the ninth wiring are electrically connected, the third wiring and the tenth wiring are electrically connected, and the third wiring and the tenth wiring are electrically connected. The fourth wire and the eleventh wire are electrically connected, and the seventh wire and the fourteenth wire are electrically They may be connected.

[0041] In the present invention, the first wiring and the eighth wiring are the same wiring, and the second wiring and The ninth wiring and the ninth wiring are the same wiring, the third wiring and the tenth wiring are the same wiring, and the third wiring and the tenth wiring are the same wiring. The fourth wiring and the eleventh wiring are the same wiring, and the seventh wiring and the fourteenth wiring are the same wiring. It may also be a line.

[0042] In the present invention, the first wiring and the eighth wiring are electrically connected, and the second wiring and The ninth wiring and the ninth wiring are electrically connected, the third wiring and the tenth wiring are electrically connected, and the third wiring and the tenth wiring are electrically connected. The fourth wire and the eleventh wire are electrically connected, and the fifth wire and the twelfth wire are electrically The sixth wiring and the thirteenth wiring are electrically connected, and the seventh wiring and the fourteenth wiring are electrically connected. The lines may be electrically connected.

[0043] In the present invention, the first wiring and the eighth wiring are the same wiring, and the second wiring and The ninth wiring and the ninth wiring are the same wiring, the third wiring and the tenth wiring are the same wiring, and the third wiring and the tenth wiring are the same wiring. The fourth wiring and the eleventh wiring are the same wiring, and the fifth wiring and the twelfth wiring are the same wiring. The sixth wiring and the thirteenth wiring are the same wiring, and the seventh wiring and the fourteenth wiring are the same wiring. The lines may be the same wiring.

[0044] The liquid crystal display device of the present invention includes first to fourth pixels each having a liquid crystal element, and a first A drive circuit, a second drive circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring. line, the fifth wire, the sixth wire, the seventh wire, the eighth wire, the ninth wire, and the first The first pixel has the fifth wiring, the eleventh wiring, and the twelfth wiring. The second pixel is electrically connected to the first driving circuit through a wiring, and the sixth pixel is electrically connected to the sixth driving circuit through a wiring. the third pixel is electrically connected to the first driving circuit via the eleventh line, the fourth pixel is electrically connected to the second driving circuit via a line, and the fourth pixel is electrically connected to the twelfth line. The first driver circuit is electrically connected to the second driver circuit via a line, and the first driver circuit is the second driver circuit has a second shift register, and the first shift register has a plurality of flip-flops, at least one of the plurality of flip-flops The first transistor, the second transistor, the third transistor, the fourth transistor, and and a fifth transistor, the first transistor having a first terminal electrically connected to the fifth wiring. the second terminal is electrically connected to the gate terminal of the second transistor, and the gate terminal is electrically connected to the fifth wiring, and the second transistor has a first terminal electrically connected to the third wiring. the second terminal is electrically connected to the sixth wiring, and the third transistor is The terminal is electrically connected to the gate terminal of the second transistor, and the second terminal is electrically connected to the second wiring. The fourth transistor is electrically connected to the first wiring, and the gate terminal is electrically connected to the fourth wiring. the first terminal is electrically connected to the sixth wiring, the second terminal is electrically connected to the second wiring, The gate terminal of the fifth transistor is electrically connected to the fourth wiring, and the first terminal of the fifth transistor is electrically connected to the sixth wiring. the first terminal is electrically connected to the second wiring, and the gate terminal is electrically connected to the first wiring. the second shift register is electrically connected to the wiring of the first shift register, and the second shift register has a plurality of flip-flops; At least one of the plurality of flip-flops includes a sixth transistor, a seventh transistor, a sixth transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The first terminal of the transistor is electrically connected to the eleventh wiring, and the second terminal of the transistor is electrically connected to the seventh wiring. The gate terminal is electrically connected to the eleventh wiring. The seventh transistor has a first terminal electrically connected to the ninth wiring and a second terminal electrically connected to the first wiring. The eighth transistor has a first terminal electrically connected to the eighth wiring. the second terminal is electrically connected to the gate terminal of the seventh transistor, and the gate terminal The first terminal of the ninth transistor is electrically connected to the eighth wiring. the second terminal is electrically connected to the twelfth wiring, and the gate terminal is electrically connected to the tenth wiring. a first terminal of a tenth transistor electrically connected to the eighth wiring; The second terminal is electrically connected to the twelfth wiring, and the gate terminal is electrically connected to the seventh wiring. It is characterized by being connected.

[0045] In the present invention, the fifth wiring and the eleventh wiring are electrically connected, and the sixth wiring and the twelfth wiring may be electrically connected.

[0046] In the present invention, the fifth wiring and the eleventh wiring are the same wiring, and the sixth wiring The first and second wirings may be the same wiring.

[0047] In the present invention, the first wiring and the seventh wiring are electrically connected, and the second wiring and The third and eighth wirings are electrically connected, the third and ninth wirings are electrically connected, and the fourth wiring is electrically connected. The first wiring and the tenth wiring may be electrically connected.

[0048] In the present invention, the first wiring and the seventh wiring are the same wiring, and the second wiring and The third and eighth wirings are the same wiring, the third and ninth wirings are the same wiring, and the fourth wiring The first wiring and the tenth wiring may be the same wiring.

[0049] In the present invention, the first wiring and the seventh wiring are electrically connected, and the second wiring and The third and eighth wirings are electrically connected, the third and ninth wirings are electrically connected, and the fourth wiring is electrically connected. The first wiring and the tenth wiring are electrically connected, and the fifth wiring and the eleventh wiring are electrically connected. The sixth wiring and the twelfth wiring may be electrically connected to each other.

[0050] In the present invention, the first wiring and the seventh wiring are the same wiring, and the second wiring and The third and eighth wirings are the same wiring, the third and ninth wirings are the same wiring, and the fourth wiring The wiring 10 and the wiring 11 are the same wiring, and the wiring 5 and the wiring 12 are the same wiring. The sixth wiring and the twelfth wiring may be the same wiring.

[0051] In the present invention, the first transistor, the second transistor, and the third transistor the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor The eighth transistor, the ninth transistor, and the tenth transistor are N-channel It may be a type transistor.

[0052] In the present invention, the first transistor, the second transistor, and the third transistor the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor The eighth transistor, the ninth transistor, and the tenth transistor are semiconductor layers and the semiconductor layer may be amorphous silicon.

[0053] In the present invention, the second terminal of the first transistor and the gate of the first transistor a first capacitance element is disposed between the second terminal of the sixth transistor and the first A second capacitive element may be disposed between the gate terminal of the transistor.

[0054] The present invention is an electronic device equipped with the liquid crystal display device described above.

[0055] The switches shown in this specification can be of various types. For example, There are electrical switches and mechanical switches, that is, switches that can control the flow of current. It is not limited to a specific one, and various types can be used. For example, It may be a transistor or a diode (e.g., PN diode, PIN diode, It can be a thyristor, a diode connected to a diode, or a transistor connected to a diode. Alternatively, a logic circuit that combines these elements may be used. When using a transistor, the transistor acts as a simple switch, The polarity (conductivity type) is not particularly limited. However, if a small off-state current is desired, It is desirable to use a transistor with a polarity that has a smaller current. There are various types of transistors, including those with an LDD region and those with a multi-gate structure. In addition, the potential of the source terminal of the transistor that operates as a switch is If the transistors operate in a state close to the reference voltage (Vss, GND, 0V, etc.), then the N-channel transistors should be used. When the source terminal voltage is close to the high-potential power supply (such as Vdd), the P-channel It is desirable to use the type because the absolute value of the voltage between the gate and source can be increased. Therefore, the switch can be operated more accurately.

[0056] It is also possible to use both N-channel and P-channel types to form a CMOS switch. When a CMOS switch is used, the P-channel or N-channel switch conducts. Since a current can flow through the resistor, the switch can operate more accurately. For example, whether the voltage of the input signal to the switch is high or low, the appropriate voltage is output. Also, the voltage amplitude value of the signal for turning the switch on or off can be set as It can be made smaller, so power consumption can also be reduced. When using a transistor, the input terminal (either the source terminal or the drain terminal) and The output terminal (the other of the source terminal and drain terminal) and the terminal that controls conduction (the gate terminal On the other hand, when a diode is used as a switch, the terminal that controls the conduction Therefore, it is possible to reduce the wiring required to control the terminals. Yes, it is possible.

[0057] In this specification, being connected means being electrically connected as well as being functionally connected. This includes both directly connected and connected. The structure disclosed in the document also includes connections other than the specified ones. An element (e.g., a switch or transistor) that allows electrical connection between two parts. Even if one or more elements (such as resistors, capacitance elements, inductors, resistance elements, and diodes) are placed Also, circuits that enable functional connections (for example, logic circuits (inverters and NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.) and potential level conversion circuits (power supply circuits such as voltage step-up circuits and voltage step-down circuits, and voltage level shifter circuits, etc.), voltage sources, current sources, switching circuits, and amplifier circuits ( Signal amplitude and current amount, such as operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits There are one or more circuits between them (such as circuits that can increase the Alternatively, they may be directly connected without any other elements or circuits in between. The wiring may be arranged in a manner similar to that described above.

[0058] In addition, if it includes only cases where the device is connected without any intervening elements or circuits, it is considered to be directly connected. Furthermore, when describing something as being electrically connected, it should be written as "electrically connected." There are two types of connections: those that are electrically connected (i.e., those that are connected via another element) and those that are functionally connected. (i.e., when connected via another circuit) and when connected directly (i.e., when connected without any other elements or circuits in between) This includes:

[0059] Note that the display element, the display device, the light-emitting element, and the light-emitting device can take various forms. In addition, it can have various elements. For example, it can be a display element, a display device, a light emitting element, or a light emitting device. The device is an EL element (organic EL element, inorganic EL element, or EL element containing organic and inorganic materials). electron-emitting devices, liquid crystal devices, electronic ink, grating light valves (GLV), Plasma displays (PDP), digital micromirror devices (DMD), piezoelectric sensors displays, or carbon nanotubes, etc., which are controlled by electromagnetic interactions. A display medium in which the trust changes can be applied. EL displays are used as display devices, and field emitters are used as display devices using electron-emitting elements. Flat panel displays (FED) and SED (Surface -conduction Electron-emitter Display) and other liquid Display devices using liquid crystal elements include liquid crystal displays, transmissive liquid crystal displays, and semi-transmissive LCDs, reflective LCDs, and electronic ink displays are used in electronic devices. There is paper.

[0060] Note that in this specification, various types of transistors may be used. Therefore, there is no limitation on the type of transistor that can be applied. Thin-film transistors with non-single-crystal semiconductor films, such as amorphous silicon and polycrystalline silicon Therefore, when a single crystal semiconductor film is used, It can be manufactured at lower manufacturing temperatures, at lower cost, on large substrates, and is transparent. It is possible to manufacture a transistor on a transparent substrate, which can transmit light, and The light transmission through the display element can be controlled by using a resistor. It can be formed using an I substrate, etc. Also, MOS type transistors, junction type transistors, etc. This allows for the application of resistors, bipolar transistors, etc. It is possible to manufacture transistors with low current consumption and transistors with high current supply capacity. It is possible to manufacture small-sized transistors and to configure circuits with low power consumption. In addition, compound semiconductors such as ZnO, a-InGaZnO, SiGe, and GaAs can be used. and thin-film transistors, which are made by thinning them, are applied. These features allow for production at low temperatures or at room temperature, and the use of low heat resistance Transistors can be formed directly on a substrate, such as a plastic substrate or a film substrate. In addition, transistors formed by inkjet or printing methods can be used. These features allow for manufacturing at room temperature, in a low vacuum, and on large substrates. It is also possible to manufacture it without using a mask (reticle). Therefore, the layout of the transistor can be easily changed. and other transistors. This makes it possible to form a bendable transistor. The non-single-crystal semiconductor film may contain hydrogen or halogen. The type of substrate on which the ion beam is formed can be various and is not limited to a specific one. Therefore, for example, the substrate may be a single crystal substrate, an SOI substrate, a glass substrate, or a quartz substrate. Substrate, plastic substrate, paper substrate, cellophane substrate, stone substrate, stainless steel substrate A substrate having a stainless steel foil can also be used. The transistor is then transferred to another substrate and arranged on the other substrate. The other substrate may be a single crystal substrate, an SOI substrate, a glass substrate, or the like. substrate, quartz substrate, plastic substrate, paper substrate, cellophane substrate, stone substrate, stainless steel A substrate made of stainless steel or a substrate made of stainless steel foil can be used. By using these substrates, it is possible to form transistors with good characteristics and also to reduce power consumption. It is possible to form transistors with low power consumption and to make devices that are not easily damaged. It can also be made heat resistant.

[0061] The structure of the transistor can take various forms. For example, a multi-gate structure having two or more gate electrodes may be used. When the gate structure is used, the channel regions are connected in series, so multiple The transistors are connected in series. The off-state current can be reduced, and the withstand voltage of the transistor can be improved, thereby improving reliability. Also, when operating in the saturation region, even if the voltage between the drain and source changes, the drain and The current between the source and the capacitor does not change much, making it possible to achieve a flat characteristic. The structure may be such that gate electrodes are arranged above and below the channel. By using a structure in which the channels are arranged, the channel area increases, thereby increasing the current value. This also makes it easier for a depletion layer to form, reducing the S value. When gate electrodes are placed above and below the This becomes:

[0062] In addition, there are structures in which the gate electrode is placed above the channel, and structures in which the gate electrode is placed below the channel. a structure in which the channel region is divided into multiple regions, a positive staggered structure, a reverse staggered structure, The gate electrodes are connected in parallel or in series. In addition, the source electrode and drain electrode overlap the channel (or a part of it). The source electrode and the drain electrode may overlap the channel (or a part of it). However, by using a structure in which charges are accumulated in part of the channel, the operation becomes unstable. It is also possible to provide an LDD region. By providing the D region, the off-current is reduced and the breakdown voltage of the transistor is improved, resulting in a high signal quality. This improves reliability and reduces the drain-source voltage when operating in the saturation region. Even if the temperature changes, the current between the drain and source does not change much, and the characteristics are flat. can be done.

[0063] It should be noted that various types of transistors can be used in this specification, and various substrates can be used. Therefore, all of the circuits are formed on the glass substrate. It may be formed on a plastic substrate or on a single crystal substrate. It may be formed on a silicon-on-insulator (SOI) substrate, or on any other substrate. All circuits are formed on the same substrate, reducing the number of components and costs. It is possible to reduce the number of connections to the circuit components, improving reliability. Alternatively, a part of the circuit may be formed on a substrate, and another part of the circuit may be formed on the substrate. The circuitry may be formed on a separate substrate. In other words, all of the circuits may be formed on the same substrate. For example, a part of the circuit may be formed using transistors on a glass substrate, and the circuit Another part is formed on a single crystal substrate, and the IC chip is mounted on a COG (Chip On Glass) Alternatively, the IC chip may be connected to a glass substrate by TAB (T It is bonded to the glass substrate using a PC board or automated bonding. In this way, by forming part of the circuit on the same board, This reduces the number of connections to the circuit components, which reduces costs and improves reliability. In addition, it is possible to improve the performance of the device in areas where the driving voltage or driving frequency is high. Since the power consumption increases, it is recommended not to form such parts on the same board. This can prevent an increase in power consumption.

[0064] In this specification, one pixel refers to one element whose brightness can be controlled. Therefore, as an example, one pixel refers to one color element, and one color element Therefore, the brightness is expressed as R (red), G (green), and B (blue). In the case of a color display device, the smallest unit of an image is a triplet of R, G, and B pixels. The color elements are not limited to three colors, and more than three colors can be used. You can also add colors other than RGB. For example, you can add white to create RGBW (W is White) can also be used. For example, yellow, cyan, magenta, emerald, etc. can be used in RGB. It is also possible to add one or more colors such as green or vermilion. For each color, you can add similar colors. For example, R, G, B1, B2 B1 and B2 are both blue, but they have slightly different frequencies. By using color elements, it is possible to display more realistic images and reduce power consumption. As another example, it is possible to use multiple regions to create a single color element. When controlling the pixel density, one pixel corresponds to one area. When performing this, there are multiple areas for controlling brightness for each color element, and the gradation is controlled across all of them. The area for controlling brightness is expressed as one pixel. In this case, one color element is made up of multiple pixels. The size of the area that contributes to the display may differ depending on the color. In the brightness control area, which has multiple pixels that make up one color element, In this element, the signals supplied to each are slightly different to widen the viewing angle. When describing one pixel (three colors), it means that one pixel is composed of three pixels of R, G, and B. When describing one pixel (one color), for one color element, When there are a plurality of pixels, they are considered as one pixel.

[0065] In this specification, pixels include those arranged (arranged) in a matrix. Here, the pixels being arranged (arranged) in a matrix means that they are arranged vertically or horizontally. In this case, the number of pixels may be increased or decreased, including those arranged in a straight line and those arranged in a jagged line. Therefore, for example, when displaying full color using three color elements (e.g., RGB), , stripe arrangement, or the dots of the three color elements are so-called delta arrangement This also includes the case where the image is arranged in a Bayer pattern. The color elements are not limited to three colors, and may be more than three. For example, RGBW (W is white) or RG B plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area for each pixel may be different. This reduces power consumption. Furthermore, the life of the display element can be extended.

[0066] The transistors are at least a gate, a drain, and a source. It is a device with three terminals, and has a channel region between the drain region and the source region. A current can flow through the drain region, the channel region, and the source region. The source and drain are different depending on the structure and operating conditions of the transistor. It is difficult to determine whether the deviation is the source or the drain. In this case, the regions that function as source and drain are called source and drain. In that case, for example, they may be written as the first terminal and the second terminal. A transistor has at least three regions including a base, an emitter, and a collector. In this case, the emitter and the collector may be connected to the first terminal. It may be written as terminal or second terminal.

[0067] The gate is a gate electrode and a gate wiring (also called a gate line or a gate signal line). The gate electrode is the entire structure including the channel region, or a part of it. a semiconductor film forming an LDD (Lightly Doped Drain) region, etc.; This refers to the conductive film that overlaps with the gate insulating film. is a wiring for connecting the gate electrodes of each pixel or for connecting the gate electrodes to other wiring. I'm talking about lines.

[0068] However, there are also parts that function as gate electrodes and gate wiring. Such a region may be called a gate electrode or a gate wiring. However, there are also regions where the gate electrode and the gate wiring cannot be clearly distinguished. If there is a channel region overlapping with the gate wiring that is arranged in a stretched manner, The region functions as a gate wiring, but also as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring.

[0069] In addition, the region formed of the same material as the gate electrode and connected to the gate electrode is also Similarly, it is made of the same material as the gate wiring and is connected to the gate wiring. The area where the gate is located may also be called the gate wiring. It does not overlap with the region or has the function of connecting with another gate electrode. However, in order to provide a margin during manufacturing, It is made of the same material as the wiring and has a region that is connected to the gate electrode and gate wiring. Therefore, such a region may also be called a gate electrode or a gate wiring.

[0070] Also, for example, in a multi-gate transistor, the gate electrode of one transistor The gate electrode of another transistor is connected to the gate electrode of the other transistor by a conductive film made of the same material as the gate electrode. Such a region is often used for connecting gate electrodes. Since it is a region, it can be called gate wiring, but multi-gate transistors can be called one transistor. It can also be considered as a transistor, so it can be called a gate electrode. Those formed of the same material as the gate electrode and gate wiring and connected to them are They may also be called gate electrodes or gate wiring. The conductive film of the connected portion may also be called a gate electrode or a gate wiring. .

[0071] The gate terminal is a gate region, a part of the gate electrode, or a gate electrode and a It refers to all or part of an area that is electrically connected.

[0072] The source includes a source region, a source electrode, and a source wiring (a source line or a source signal line). The source region refers to the whole or part of the source region. Semiconductors that contain a large amount of P-type impurities (such as boron and gallium) or N-type impurities (such as phosphorus and arsenic) Therefore, it refers to a region that contains a small amount of P-type or N-type impurities. The LDD (Lightly Doped Drain) region is not included in the source region. The source electrode is made of a material different from that of the source region and is electrically connected to the source region. However, the source electrode refers to the conductive layer in the source region. The source line is the line that connects the source electrodes of each pixel. Alternatively, it refers to a wiring for connecting a source electrode to another wiring.

[0073] However, there are also parts that function as both source electrodes and source wiring. Such a region may be called a source electrode or a source wiring. In other words, there are regions where the source electrode and the source wiring cannot be clearly distinguished. For example, if there is a source region overlapping with the extended source wiring, This region functions as a source wiring, but also as a source electrode. Therefore, such a region may be called a source electrode or a source wiring. .

[0074] In addition, the region formed of the same material as the source electrode and connected to the source electrode and the region formed of the source electrode The part connecting the source electrode and the source region may also be called the source electrode. The overlapping portion can also be called the source electrode. The region formed of the material and connected to the source wiring may also be called the source wiring. Such a region may not have the function of connecting to another source electrode in the strict sense. However, in order to provide a margin during manufacturing, the source electrode and source wiring are made of the same material. There are regions that are connected to the source electrode and source wiring. It may also be called a source electrode or a source wiring.

[0075] In addition, for example, the conductive film in the portion connecting the source electrode and the source wiring is also You can call it that, or you can call it source wiring.

[0076] The source terminal is a part of the source region or the source electrode, or a part electrically connected to the source electrode. Refers to part or all of the connected area.

[0077] The drain is the same as the source.

[0078] In this specification, a semiconductor device refers to a semiconductor element (such as a transistor or a diode). Also, any device that can function by utilizing the characteristics of semiconductors. The display device may be a device having a display element (such as a liquid crystal element or a light emitting element). It should be noted that a plurality of pixels including display elements such as liquid crystal elements and EL elements, and the pixels It may also refer to a display panel body on which peripheral driving circuits are formed on the same substrate. , peripheral driving circuits arranged on the substrate by wire bonding or bumps, so-called It may also include an IC chip connected by chip-on-glass (COG). A flexible board with ICs, resistors, capacitors, inductors, transistors, etc. It may also include a flexible printed circuit (FPC) or a printed wiring board (PWB). The backlight unit may include optical sheets such as a polarizing plate and a retardation plate. (light guide plate, prism sheet, diffusion sheet, reflective sheet, light source (LED, cold cathode tube, etc.) The light-emitting device may include, in particular, an EL element or an FE element. This refers to a display device that has a self-luminous display element such as the element used in D. refers to a display device having a liquid crystal element.

[0079] In this specification, the term "formed on something" refers to a material that is formed on something. When we say "on top of" or "on top of," it means "on top of something." It is not limited to direct contact. If there is no direct contact, that is, if there is another object between them, This also includes cases where the layer is sandwiched between layers. For example, on top of layer A (or on top of layer A), When we say that layer B is formed, it means that layer B is formed directly on top of layer A. And another layer (such as layer C or layer D) is formed directly on top of layer A, and on top of that This also includes the case where layer B is formed in direct contact with the surface of the substrate. The same applies to mounting, which is not limited to being directly on top of an object, but may have another object in between. Therefore, for example, if layer B is formed above layer A, When we say "layer B" here, it means that layer B is formed directly on layer A, and layer B is formed directly on layer A. Another layer (such as layer C or layer D) is formed adjacent to it, and layer B is formed directly on top of it. This also includes cases where the object is formed under or below something. The same applies to cases where there is direct contact and cases where there is no direct contact. do. [Effects of the Invention]

[0080] According to the present invention, it is possible to suppress the deterioration of the characteristics of the transistor. This can prevent malfunction of the shift register caused by deterioration of the characteristics of the shift register. This makes it possible to suppress display defects in the liquid crystal display device caused by malfunction of the resistor. [Brief explanation of the drawings]

[0081] [Figure 1] FIG. 1 is a diagram illustrating embodiment 1. [Figure 2] FIG. 1 is a diagram illustrating embodiment 1. [Figure 3] FIG. 1 is a diagram illustrating embodiment 1. [Figure 4] FIG. 1 is a diagram illustrating embodiment 1. [Figure 5] FIG. 1 is a diagram illustrating embodiment 1. [Figure 6] FIG. 1 is a diagram illustrating embodiment 1. [Figure 7] FIG. 1 is a diagram illustrating embodiment 1. [Figure 8] FIG. 1 is a diagram illustrating embodiment 1. [Figure 9] FIG. 1 is a diagram illustrating embodiment 1. [Figure 10] FIG. 1 is a diagram illustrating embodiment 1. [Figure 11] FIG. 1 is a diagram illustrating embodiment 1. [Figure 12] FIG. 1 is a diagram illustrating embodiment 1. [Figure 13] FIG. 10 is a diagram illustrating a second embodiment. [Figure 14] FIG. 10 is a diagram illustrating a second embodiment. [Figure 15] FIG. 10 is a diagram illustrating a second embodiment. [Figure 16] FIG. 10 is a diagram illustrating a second embodiment. [Figure 17] FIG. 10 is a diagram illustrating a second embodiment. [Figure 18] FIG. 10 is a diagram illustrating a second embodiment. [Figure 19] FIG. 10 is a diagram illustrating embodiment 3. [Figure 20] FIG. 10 is a diagram illustrating embodiment 3. [Figure 21] FIG. 10 is a diagram illustrating embodiment 3. [Figure 22] FIG. 10 is a diagram illustrating embodiment 3. [Figure 23] FIG. 10 is a diagram illustrating embodiment 4. [Figure 24] FIG. 10 is a diagram illustrating embodiment 4. [Figure 25] FIG. 10 is a diagram illustrating embodiment 4. [Figure 26] FIG. 10 is a diagram illustrating embodiment 4. [Figure 27] FIG. 10 is a diagram illustrating embodiment 5. [Figure 28] FIG. 10 is a diagram illustrating embodiment 5. [Figure 29] FIG. 10 is a diagram illustrating embodiment 5. [Figure 30] FIG. 10 is a diagram illustrating embodiment 5. [Figure 31] FIG. 10 is a diagram illustrating embodiment 5. [Figure 32] FIG. 13 is a diagram illustrating embodiment 6. [Figure 33] FIG. 13 is a diagram illustrating embodiment 6. [Figure 34] FIG. 13 is a diagram illustrating embodiment 6. [Figure 35] FIG. 13 is a diagram illustrating embodiment 6. [Figure 36] FIG. 13 is a diagram illustrating embodiment 7. [Figure 37] FIG. 13 is a diagram illustrating embodiment 7. [Figure 38] FIG. 13 is a diagram illustrating embodiment 7. [Figure 39] FIG. 13 is a diagram illustrating embodiment 7. [Figure 40] FIG. 13 is a diagram illustrating embodiment 8. [Figure 41] FIG. 13 is a diagram illustrating embodiment 8. [Figure 42] FIG. 13 is a diagram illustrating embodiment 8. [Figure 43] FIG. 13 is a diagram illustrating embodiment 8. [Figure 44] FIG. 1 is a diagram illustrating embodiment 1. [Figure 45] FIG. 1 is a diagram illustrating embodiment 1. [Figure 46] FIG. 13 is a diagram illustrating embodiment 9. [Figure 47] FIG. 13 is a diagram illustrating embodiment 9. [Figure 48] FIG. 13 is a diagram illustrating embodiment 9. [Figure 49]FIG. 13 is a diagram illustrating embodiment 9. [Figure 50] FIG. 13 is a diagram illustrating embodiment 9. [Figure 51] FIG. 13 is a diagram illustrating embodiment 9. [Figure 52] FIG. 13 is a diagram illustrating embodiment 9. [Figure 53] FIG. 13 is a diagram illustrating embodiment 9. [Figure 54] FIG. 13 is a diagram illustrating embodiment 9. [Figure 55] FIG. 13 is a diagram illustrating embodiment 9. [Figure 56] FIG. 19 is a diagram illustrating embodiment 11. [Figure 57] FIG. 19 is a diagram illustrating embodiment 11. [Figure 58] FIG. 19 is a diagram illustrating embodiment 11. [Figure 59] FIG. 19 is a diagram illustrating embodiment 11. [Figure 60] FIG. 19 is a diagram illustrating embodiment 11. [Figure 61] FIG. 12 is a diagram illustrating embodiment 12. [Figure 62] FIG. 12 is a diagram illustrating embodiment 12. [Figure 63] FIG. 13 is a diagram illustrating embodiment 13. [Figure 64] FIG. 12 is a diagram illustrating embodiment 12. [Figure 65] FIG. 20 is a diagram illustrating embodiment 10. [Figure 66] FIG. 20 is a diagram illustrating embodiment 10. [Figure 67] FIG. 20 is a diagram illustrating embodiment 10. [Figure 68] FIG. 20 is a diagram illustrating embodiment 10. [Figure 69] FIG. 20 is a diagram illustrating embodiment 10. [Figure 70] FIG. 20 is a diagram illustrating embodiment 10. [Figure 71] FIG. 20 is a diagram illustrating embodiment 10. [Figure 72] FIG. 20 is a diagram illustrating embodiment 10. [Figure 73] FIG. 20 is a diagram illustrating embodiment 10. [Figure 74]FIG. 20 is a diagram illustrating embodiment 10. [Figure 75] FIG. 19 illustrates embodiment 14. [Figure 76] FIG. 19 illustrates embodiment 14. [Figure 77] FIG. 19 illustrates embodiment 14. [Figure 78] FIG. 19 illustrates embodiment 14. [Figure 79] FIG. 19 illustrates embodiment 14. [Figure 80] FIG. 19 illustrates embodiment 14. [Figure 81] FIG. 19 illustrates embodiment 14. [Figure 82] FIG. 19 illustrates embodiment 14. [Figure 83] FIG. 19 illustrates embodiment 14. [Figure 84] FIG. 19 illustrates embodiment 14. [Figure 85] FIG. 15 is a diagram illustrating embodiment 15. [Figure 86] FIG. 20 is a diagram illustrating embodiment 17. [Figure 87] FIG. 20 is a diagram illustrating embodiment 18. [Figure 88] FIG. 20 is a diagram illustrating embodiment 18. [Figure 89] FIG. 20 is a diagram illustrating embodiment 18. [Figure 90] FIG. 20 is a diagram illustrating embodiment 19. [Figure 91] FIG. 29 is a diagram illustrating embodiment 20. [Figure 92] FIG. 1 is a diagram illustrating embodiment 1. [Figure 93] FIG. 22 is a diagram illustrating embodiment 22. [Figure 94] FIG. 23 is a diagram illustrating embodiment 23. [Figure 95] FIG. 23 is a diagram illustrating embodiment 23. [Figure 96] FIG. 23 is a diagram illustrating embodiment 23. [Figure 97] FIG. 23 is a diagram illustrating embodiment 23. [Figure 98] FIG. 23 is a diagram illustrating embodiment 23. [Figure 99]FIG. 23 is a diagram illustrating embodiment 23. [Figure 100] FIG. 19 illustrates embodiment 14. [Figure 101] FIG. 19 illustrates embodiment 14. [Figure 102] FIG. 20 is a diagram illustrating embodiment 17. [Figure 103] FIG. 23 is a diagram illustrating embodiment 21. [Figure 104] FIG. 20 is a diagram illustrating embodiment 16. [Figure 105] FIG. 20 is a diagram illustrating embodiment 16. DETAILED DESCRIPTION OF THE INVENTION

[0082] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. It is to be understood that the invention may be practiced in various different ways without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes can be made in form and detail. It should not be construed as being limited to the description of this embodiment mode.

[0083] (Embodiment 1) In this embodiment, the basic configuration of a shift register of a display device of the present invention will be described with reference to the drawings. FIG. 1 shows a single stage of flip-flops in a shift register. The flip-flop shown in Figure 1 is the first stage. A first transistor 101, a second transistor 102, a third transistor 103, and The flip-flop has a first wiring 111, a second wiring 112, a third wiring 113, a fourth transistor 104, and a fourth transistor 104. The first wiring 112, the third wiring 113, the fourth wiring 114, the fifth wiring 115 and the sixth wiring In this embodiment, the first transistor 101 and the second transistor The transistor 102, the third transistor 103 and the fourth transistor 104 are N-channel transistors. The voltage between the gate and source (Vgs) is the threshold voltage (Vth ) is exceeded, the first wiring 111 and the second wiring The third wiring 11 and the second wiring 11 may be called the first power supply line and the second power supply line, respectively. The third and fourth wirings 114 may be referred to as a first signal line and a second signal line, respectively.

[0084] The first terminal (one of the source terminal and the drain terminal) of the first transistor 101 is connected to the first The second terminal (the other of the source terminal and the drain terminal) is connected to the line 111. The gate terminal is connected to the fifth wiring 115. A first terminal of the third transistor 103 is connected to the second wiring 112, and a second terminal of the third transistor 103 is connected to the second wiring 112. The gate terminal of the transistor 102 is connected to the fourth wiring 114. The first terminal of the second transistor 102 is connected to the sixth wiring 116, and the second terminal The first terminal of the fourth transistor 104 is connected to the third wiring 113. The first terminal is connected to the second wiring 112, and the gate terminal is connected to the fourth wiring 116. 114. The second terminal of the first transistor 101 and the second terminal of the second transistor The connection point between the gate terminal of the third transistor 102 and the first terminal of the third transistor 103 is connected to a node. The number is 121.

[0085] The second terminal of the third transistor 103 and the second terminal of the fourth transistor 104 are , are not limited to being connected to the second wiring 112, and may be connected to separate wirings. In addition, the gate terminal of the third transistor 103 and the gate terminal of the fourth transistor 104 The port terminal is not limited to being connected to the fourth wiring 114, but may be connected to a separate wiring. It's fine.

[0086] Next, the operation of the flip-flop shown in FIG. 1 will be explained with reference to the timing chart in FIG. 3. In FIG. 2, the set period, the selection period, and the non-selection period are The non-selection period is divided into a first non-selection period, a second non-selection period, and a third non-selection period. The first non-selection period, the second non-selection period, and the third non-selection period are repeated in sequence. It's repeating.

[0087] Note that a potential of V1 is supplied to the first wiring 111, and a potential of V2 is supplied to the second wiring 112. However, V1>V2.

[0088] However, it is not limited to the first wiring 111 being supplied with the potential of V1. Alternatively, a digital signal or an analog signal may be input. The second wiring 112 is not necessarily supplied with the potential of V2, but may be supplied with another potential. A digital signal or an analog signal may be input.

[0089] Signals are input to the third wiring 113, the fourth wiring 114, and the fifth wiring 115. The signal input to the third wiring 113 is the first clock signal, and the signal input to the fourth wiring 11 The signal input to the fourth wiring is the second clock signal, and the signal input to the fifth wiring 115 is The third wiring 113, the fourth wiring 114, and the fifth wiring 115 are connected to the start signal. The signal input to the GND terminal has an H signal potential of V1 (hereinafter also referred to as the H level) and an L signal potential of V2 (hereinafter also referred to as the H level). This is a digital signal of V2 (hereinafter also referred to as L level).

[0090] However, it is not limited to the first clock signal being input to the third wiring 113, and other Alternatively, a constant potential or current may be input. The wiring 114 is not limited to the second clock signal being input, and other signals may be input. Alternatively, a constant potential or current may be input to the fifth wiring 115. It is not limited to the start signal being input to the input terminal, and other signals may be input. A constant potential or current may be input.

[0091] Moreover, the H level of the signal input to the third wiring 113, the fourth wiring 114, and the fifth wiring 115 The potential of the H signal is not limited to V1 and the potential of the L signal is not limited to V2. There are no particular limitations on the potentials of these electrodes as long as they are higher than the potentials of the electrodes.

[0092] A signal is output from the sixth wiring 116. is the output signal of the flip-flop and is also the start signal of the next flip-flop. The signal output from the sixth wiring 116 is fed to the fifth flip-flop of the next stage. The signal output from the sixth wiring 116 is the voltage of the H signal. The potential of the L signal is V2 (hereinafter also referred to as the L level). It is a digital signal.

[0093] In FIG. 2, a signal 213 is a signal input to the third wiring 113, and a signal 214 is a signal input to the third wiring 114. The signal 215 is a signal input to the fourth wiring 114, and the signal 216 is a signal input to the fifth wiring 115. The signal 216 is a signal output from the sixth wiring 116. is the potential at node 121 in FIG.

[0094] First, during the period A shown in FIG. 2 and the set period shown in FIG. 3(A), the signal 213 is at the L level. Therefore, the signal 214 becomes L level and the signal 215 becomes H level. The first transistor 101 and the fourth transistor 104 are turned off. At this time, the second terminal of the first transistor 101 becomes the source terminal, and the The potential of the node 121 (potential 221) is changed from the potential of the fifth wiring 115 to the potential of the first transistor 10. Since the value is obtained by subtracting the threshold voltage of 1 (Vth101), it becomes V1-Vth101. Therefore, the second transistor 102 is turned on, and the potential of the sixth wiring 116 is Since the potential of 113 is equal to that of V2, the flip-flop The flip-flop outputs an L level signal from the sixth wiring 116 while keeping the second transistor 102 on. do.

[0095] During the period B shown in FIG. 2 and the selection period shown in FIG. 3(B), the signal 213 is at the H level, and the signal 2 14 remains at L level, and signal 215 goes to L level. The first transistor 103 and the fourth transistor 104 remain off, and the first transistor 1 At this time, the second terminal of the second transistor 102 becomes the source terminal. The potential of the node 121 (potential 221) starts to increase. Since the lead 121 is in a floating state (hereinafter also referred to as a floating state), the second lead The sixth wiring is formed by the capacitive coupling of the parasitic capacitance between the gate terminal and the second terminal of the transistor 102. The potential of the second transistor 116 rises at the same time (also called bootstrap operation). The voltage Vgs between the gate and source of the transistor 102 is Vth102+α (Vth102: The threshold voltage of the second transistor 102, α, is an arbitrary positive number, and the sixth wiring 116 The potential of the flip-flop is at the H level (V1). By setting the potential of the sixth wiring 121 to V1+Vth102+α, the H level is It can output from 16.

[0096] During the period C in FIG. 2 and the first non-selection period shown in FIG. 3(C), the signal 213 is at the L level. , the signal 214 becomes H level and the signal 215 remains L level. The first transistor 103 and the fourth transistor 104 are turned on, and the first transistor The node 121 and the sixth wire 116 are connected to the third transistor 101 and the sixth wire 116, respectively. The potential of the second wiring 112 is supplied via the fourth transistor 103 and the fourth transistor 104. Therefore, it becomes L level.

[0097] During the period D in FIG. 2 and the second non-selection period shown in FIG. 3(D), the signal 213 remains at the L level. , the signal 214 becomes L level, and the signal 215 remains L level. Then, the third transistor 103 and the fourth transistor 104 are turned off, and the first transistor The resistor 101 remains off. Therefore, the node 121 and the sixth wire 116 are connected to the L Maintain the level.

[0098] During the period E in FIG. 2 and the third non-selection period shown in FIG. 3(E), the signal 213 is at H level. , signal 214 remains at L level, and signal 215 remains at L level. , the first transistor 101, the third transistor 103, and the fourth transistor 104 Therefore, the node 121 and the sixth wiring 116 remain at the L level. do.

[0099] From the above, the flip-flop of FIG. 1 has the third transistor 103 and the fourth transistor The third transistor 103 and the second transistor 104 are turned on only during the first non-selection period. and the fourth transistor 104 can be prevented from deteriorating in characteristics (shift in threshold voltage). The flip-flop of FIG. The first one is turned on only during the set period, and the second one is turned on only during the set period and the selection period. The deterioration of the characteristics of the first transistor 101 and the second transistor 102 can also be suppressed. do.

[0100] Furthermore, the flip-flop of FIG. 1 operates in the first non-selection period. Since V2 is supplied to the gate 121 and the sixth wiring 116, malfunction of the flip-flop is suppressed. This is because, during the non-selection period, V2 is supplied to the node 121 and the sixth wiring 116. This is because the potential of the line 116 can be stably maintained at V2.

[0101] The flip-flop shown in FIG. 1 includes a first transistor 101 and a second transistor 10 2. The third transistor 103 and the fourth transistor 104 are all N-channel transistors. Therefore, the flip-flop in Figure 1 is Since amorphous silicon can be used as the semiconductor layer of the transistor, the manufacturing process is simple. This simplifies the manufacturing process, reduces manufacturing costs, and improves yields. Furthermore, it is possible to manufacture semiconductor devices such as large display panels. The manufacturing process can be simplified even if polysilicon or single crystal silicon is used as the semiconductor layer of the transistor. This can be achieved.

[0102] In addition, the flip-flop in Figure 1 has a semiconductor layer that is prone to characteristic degradation (threshold voltage Even when amorphous silicon is used, where the voltage shift is clearly visible, the transistor characteristics are not deteriorated. Since the amount of heat generated can be suppressed, a semiconductor device such as a display panel having a long life can be manufactured. Cut.

[0103] Here, the first transistor 101, the second transistor 102, and the third transistor 1 The functions of the first transistor 101 and the fourth transistor 104 will be described. The input transistor has a function of selecting the timing at which the potential of the first wiring 111 is supplied. The second transistor 102 functions as a sixth transistor. The timing of supplying the voltage to the wiring 116 is selected, and the potential of the node 121 is set to a value corresponding to the bootstrap operation. It functions as a bootstrap transistor. The transistor 103 supplies the potential of the second wiring 112 to the node 121. The fourth transistor has a function of selecting the The switch 104 has a function of supplying the potential of the second wiring 112 to the sixth wiring 116. It functions as a switching transistor.

[0104] Note that, as long as the operation is the same as that shown in FIG. 1, the arrangement and number of transistors may be changed. As can be seen from FIG. 3, which explains the operation of the flip-flop of FIG. 1, In this embodiment, the set period, the selection period, the first non-selection period, the second non-selection period, and the third non-selection period are included. During the selection period, it is sufficient that conduction is maintained as shown by the solid lines in FIGS. Therefore, if the transistors and other components are arranged and operated in a way that satisfies this requirement, Transistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches, various logic elements It is also possible to newly place logic circuits, etc.

[0105] For example, as shown in FIG. 4, the gate terminal of the second transistor 102 shown in FIG. A capacitance element 401 may be disposed between the terminals. This allows the bootstrap operation during the selection period to be performed more stably. Since the parasitic capacitance between the gate terminal and the second terminal of the transistor 102 can be reduced, The capacitor 401 can be switched on and off at high speed. Alternatively, a gate insulating film may be used as a conductive layer, and a gate electrode layer and a wiring layer may be used as an insulating layer. A gate insulating film is used as a layer, and a gate electrode layer and an impurity-doped semiconductor are used as a conductive layer. Alternatively, an interlayer film (insulating film) may be used as the insulating layer, and a wiring layer and a transparent conductive layer may be used as the conductive layer. A light electrode layer may also be used. Note that the same reference numerals are used to designate the same components as in FIG. The explanation will be omitted.

[0106] The flip-flop shown in FIG. 5 can also perform the same operation as that shown in FIG. As such, the first transistor 101 shown in FIG. 1 may be diode-connected. The first transistor 101 is diode-connected, and the first wiring 111 is insufficient. This reduces the number of wirings and power supplies (V1) by one. Common reference numerals are used for common parts and their explanations are omitted.

[0107] Next, the shift register having the flip-flop of the present embodiment will be described with reference to FIG. This will be explained with reference to the following.

[0108] The shift register is made up of a first wiring 611, a second wiring 612, a third wiring 613, a fourth wiring 614, and a A line 614, a fifth wiring 615, a sixth wiring 616, wirings 622_1 to 622_n, and n wirings The flip-flops 601_1 to 601_n (n stages) are provided. N: 0 or a positive integer) flip-flop 601 is connected to a first wiring 611 and a second wiring 6 12, the third wiring 613 and the fourth wiring 614. The flip-flop 601 has a first wiring 611, a second wiring 612, a fourth wiring 614 and a fifth wiring 615. The flip-flop 601 in the 3+3Nth stage is connected to the first wiring 61 1, the second wiring 612, the fifth wiring 615 and the third wiring 613. For example, the flip-flop 601_i (flip-flops 601_1 to 601_i) in the i-th stage Among the flip-flops 601_2 to 601_n, n-1 is the flip-flop 601_i-1 in the (i-1)th stage and the flip-flop 601_i+1 in the (i+1)th stage. The flip-flop 601_i is connected to the flip-flop 601_i+1 in the i-th stage and the flip-flop 601_i in the i+1-th stage. The connection point with the flip-flop 601_i+1 is the wiring 622_i (wiring 622_1 to 622 _n). The first stage flip-flop 601_1 is connected to the sixth wiring 616 and the second-stage flip-flop 601_2, and the first-stage flip-flop The connection between the flip-flop 601_1 and the second stage flip-flop 601_2 is made by a wiring 622. The n-th flip-flop 601_n is connected to the n-1th flip-flop. The flip-flop 601_n-1 is connected to the wiring 622_n.

[0109] In the flip-flop 601 at the 1+3Nth stage, the first wiring 611 and the second wiring 61 The second, third wiring 613, and fourth wiring 614 correspond to the first wiring 111 and the second wiring 112 in FIG. It is connected to the wiring 112, the third wiring 113, and the fourth wiring 114. In the flip-flop 601, the first wiring 611, the second wiring 612, the fourth wiring 114, The fifth wiring 615 corresponds to the first wiring 111, the second wiring 112, and the third wiring 113 shown in FIG. 113, and the fourth wiring 114. In the 3+3Nth stage flip-flop 601, The first wiring 611, the second wiring 612, the fifth wiring 615, and the third wiring 613 are These correspond to the first wiring 111, the second wiring 112, the third wiring 113, and the fourth wiring 61 in FIG. 4. For example, among the flip-flops 601_i in the i-th stage, The fifth wiring 115 shown in FIG. 1 of the flip-flops 601_2 to 601_n-1 and the sixth wiring 116 are connected to the flip-flop 601_i-1 in the (i-1)th stage in FIG. 1 of the flip-flop 601_i+1 in the (i+1)th stage. 5 is connected to the wiring 115 of the first stage flip-flop 601_1 in FIG. The fifth wiring 115 and the sixth wiring 116 shown in FIG. 6 are the sixth wiring 616 and the second wiring 116 shown in FIG. The second flip-flop 601_2 is connected to the fifth wiring 115 shown in FIG. , the fifth wiring 115 and the sixth wiring 116 shown in FIG. 1 of the n-th stage flip-flop 601_n. 16 is the sixth wiring shown in FIG. 1 of the n-1th stage flip-flop 601_n-1. 116, which is connected to the wiring 622_n in FIG.

[0110] Next, one form of a top view of the shift register shown in FIG. 6 is shown in FIG. The shift register shown in Figure 1 is a shift register using flip-flops, and n The flip-flop 601_n in the nth stage and the flip-flop 601_n+1 in the n+1th stage are The flip-flop included in the shift register of FIG. 1, the second transistor 102, the third transistor 103 and the fourth transistor 10 4 is arranged. And each flip-flop that the shift register of FIG. These are a first wiring 611, a second wiring 612, a third wiring 613, a fourth wiring 614, and The first transistor 101 and the second transistor 102 are connected to a fifth wiring 615. The first transistor 102, the third transistor 103, and the fourth transistor 104 are inverted staggered. The transistor structure is a channel etch type. A first transistor 101, a second transistor 102, a third transistor 103 and a fourth transistor The transistor 104 may be a channel protection type. The first transistor 102, the third transistor 103, and the fourth transistor 104 are transistors A top gate type transistor may also be used.

[0111] In addition, the layout diagram of the shift register shown in FIG. 92 is a diagram showing a first conductive film 9201, a semiconductor layer 9202, a contact 9203, and a second conductive film 9204. The first conductive film 9201 functions as a gate electrode. The semiconductor layer 9202 does not contain impurities. The contact 9203 is an intrinsic amorphous semiconductor film that is not a conductive film. The conductive film 9204 functions to electrically connect the conductive film 9204 to the conductive film 9206 .

[0112] In the shift register of FIG. 92, the wiring width of the first wiring 611 is set to the wiring width of the third wiring 613, The width of the fourth wiring 614 and the width of the fifth wiring 615 can be made smaller. This is because the current flowing through the first wiring 611 is also transmitted through the third wiring 613, the fourth wiring 614, and Since the width of the first wiring 611 is smaller than that of the fifth wiring 615, the shift level can be reduced even if the width of the first wiring 611 is reduced. Similarly, the shift register of FIG. 92 has a second The width of the wiring 612 is set to the width of the third wiring 613, the width of the fourth wiring 614, and the width of the fifth wiring 615. The width of the second wiring 612 can be made smaller than that of the wiring 615. Since the current flowing through the second wiring 612 is larger than the current flowing through the first wiring 611, the wiring width of the second wiring 612 is It is desirable that the width of the wiring 611 in FIG. The shift register in Figure 92 can reduce the pitch of one flip-flop. The shift register in Figure 92 allows each transistor to be arranged efficiently. The channel width of the transistor can be increased.

[0113] Also, the shift register of FIG. 92 has a larger channel width of the second transistor 102. This makes the bootstrap operation easier because the second transistor Since the channel width of the second transistor 102 is large, the gate terminal of the second transistor 102 and the This is because the parasitic capacitance between the two terminals becomes large. By increasing the channel width of the second transistor 102, a high driving capability can be obtained. This is because the channel width of the second transistor 102 is large. This is because the current supply capacity of the stator 102 increases. In this shift register, the wiring width of the first wiring 611 and the second wiring 612 is reduced, and In this case, the area in which the transistors can be arranged can be increased. By preferentially increasing the channel width of the transistor 102, a higher driving capability can be obtained. Therefore, the channel width of the second transistor can be set to be equal to or smaller than that of the first transistor. 01, the channel width of the third transistor 103, the channel width of the fourth transistor 104 It is desirable to make it larger than the channel width of the

[0114] In addition, the shift register of FIG. 92 has a U-shaped channel of the second transistor 102. This allows the channel width of the second transistor 102 to be increased.

[0115] The layout diagram shown in FIG. 92 can also be applied to other shift registers. Cut.

[0116] Next, the operation of the shift register shown in Figure 6 will be explained with reference to the timing chart in Figure 7. I will explain.

[0117] Note that a potential of V1 is supplied to the first wiring 611, and a potential of V2 is supplied to the second wiring 612. However, V1>V2.

[0118] However, it is not limited to the first wiring 611 being supplied with the potential of V1, and other potentials may be applied. Alternatively, a digital signal or an analog signal may be input. The second wiring 612 is not necessarily supplied with the potential V2, but may be supplied with another potential. A digital signal or an analog signal may be input.

[0119] The third wiring 613, the fourth wiring 614, the fifth wiring 615, and the sixth wiring 616 are A signal is input to the third wiring 613, the fourth wiring 614, and the fifth wiring 615. The signals transmitted are three-phase clock signals with a phase difference of 120 degrees. The input signal is a start signal. The signals input to the fifth wiring 615 and the sixth wiring 616 have a potential of V1 for the H signal and V2 for the L signal. It is a digital signal with a potential of V2.

[0120] However, the third wiring 613, the fourth wiring 614, and the fifth wiring 615 each have a phase. It is not limited to the input of three-phase clock signals that are shifted by 120 degrees, and other signals may be input. Alternatively, a constant potential or current may be input to the sixth wiring 61. 6 is not limited to being input with a start signal, and other signals may be input. A constant potential or current may be input.

[0121] In addition, the third wiring 613, the fourth wiring 614, the fifth wiring 615 and the sixth wiring 616 The potential of the H signal of the input signal is not limited to V1 and the potential of the L signal is not limited to V2. As long as the potential is higher than the potential of the L signal, the potential is not particularly limited.

[0122] A signal is output from the wiring 622. For example, a signal is output from the wiring 622_i (i is an arbitrary positive number) ) is the output signal of the flip-flop 601_i in the i-th stage, and i+ It is also the input signal to the first stage flip-flop 601_i+1.

[0123] In FIG. 7, a signal 716 indicates a signal input to the sixth wiring 616. Signal 722_1, signal 722_i, signal 722_i+1, and signal 722_n are each one stage. Signals output from the wiring 622 in the th, i-th, (i+1)-th, and n-th stages (potentials of the wiring 622) This shows:

[0124] As shown in FIG. 7, for example, when the flip-flop 601_i in the i-th stage is in the selection period, An H signal (722_i) is output to the line 622_i. At this time, the (i+1)th flip-flop The step 601_i+1 enters the set period and outputs an L signal to the wiring 622_i+1. The flip-flop 601_i in the i-th stage is in the first non-selection period, and the L signal is output to the wiring 622_i. At this time, the flip-flop 601_i+1 in the (i+1)th stage is in the selection period. Then, the flip-flop 601_i+1 in the i-th stage outputs an H signal to the wiring 622_i+1. i is a second non-selection period, and the wiring 622_i is in a floating state while maintaining the L level. At this time, the flip-flop 601_i+1 in the (i+1)th stage is in the first non-selection period. After that, the flip-flop 601_i in the i-th stage outputs an L signal to the flip-flop 601_i+1. The non-selection period 3 begins, and the wiring 622_i remains at the L level and in a floating state. At this time, the flip-flop 601_i+1 in the (i+1)th stage is in the second non-selection period. 622_i+1 remains at the L level and becomes floating. After that, the flip of the i-th stage The flop 601_i has a first non-selection period, a second non-selection period, a third non-selection period, and a fourth non-selection period until the next set period. Similarly, the flip-flop 601_i+1 in the (i+1)th stage is The third non-selected flip-flop 601_i remains in the selected state until the next set period (the selection period of the flip-flop 601_i in the i-th stage). The first selection period, the first non-selection period, and the second non-selection period are repeated in this order.

[0125] From the above, the shift register in FIG. 6 can use a three-phase clock signal. This reduces the number of times the clock rises or falls, thereby saving power. In addition, in the shift register of this embodiment, each clock signal line (third wiring 613, fourth wiring The number of stages of the flip-flop 601 connected to the fifth wiring 614 and the fifth wiring 615 is single-phase. This reduces the load on each clock signal line by 2 / 3 when using a clock signal. This can be done.

[0126] The shift register in FIG. 6 uses a buffer to transfer the output signal of the flip-flop 601 at each stage. The signals may be output to the wiring 622 of each stage via a plurality of wirings, as shown in FIG. The 8 shift register has flip-flops 601 at each stage connected to the buffer 801. Since the wiring 622 is connected to each stage, a wide margin can be obtained during operation. This is because a large load is connected to the wiring 622, and the signal on the wiring 622 may have delays or waveform distortions. Even if a rounding occurs, it does not affect the operation of the shift register. 1 is an inverter, a logic circuit such as NAND or NOR, an operational amplifier, or a combination of these. A combined circuit can be used.

[0127] Next, a display device having the shift register of the present embodiment will be described with reference to FIG. I will explain.

[0128] The display device includes a signal line driver circuit 901, a scanning line driver circuit 902, and a pixel portion 903. The element section 903 includes a plurality of signal lines S1 extending from the signal line driving circuit 901 in the column direction. 1 to Sm, and a plurality of scanning lines G1 to Gn extending from the scanning line driving circuit 902 in the row direction. and a plurality of electrodes arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. Each pixel 904 is connected to a signal line Sj (one of the signal lines S1 to Sm). The scanning line Gi (any one of the scanning lines G1 to Gn) is connected to the scanning line Gi.

[0129] The scanning lines G1 to Gn correspond to the wirings 622_1 to 622_n in FIGS.

[0130] The wiring and electrodes are made of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), and Butan (Mo), Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg) , Scandium (Sc), Cobalt (Co), Zinc (Zn), Niobium (Nb), Silicon Silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), and oxygen (O), or one or more elements selected from the group Compounds and alloy materials (e.g., indium tin) containing one or more elements selected from the above Oxide (ITO), Indium Zinc Oxide (IZO), Indium Tin Oxide Doped with Silicon Oxide Oxide (ITSO), zinc oxide (ZnO), aluminum neodymium (Al-Nd), magnesium Mg-Ag, or a combination of these compounds. Or, compounds of these with silicon (silicides) (e.g., aluminium silicides) silicon, molybdenum silicon, nickel silicide, etc.) and their compounds with nitrogen (e.g. For example, titanium nitride, tantalum nitride, molybdenum nitride, etc. Silicon (Si) contains a large amount of n-type impurities (such as phosphorus) and p-type impurities (such as boron). The inclusion of these impurities improves the electrical conductivity and Silicon behaves like a metal, making it easier to use as wiring or electrodes. It may be polycrystalline (polysilicon), or amorphous (amorphous silicon). By using single crystal silicon or polycrystalline silicon, the resistance can be reduced. In addition, by using amorphous silicon, it can be produced through a simple manufacturing process. Aluminum and silver have high conductivity, which can reduce signal delay and It is easy to etch, so it is easy to pattern and can be subjected to fine processing. Since molybdenum has high conductivity, it can reduce signal delay. Even when it comes into contact with oxide semiconductors such as IZO or silicon, problems such as material defects can occur. It can be manufactured without any trouble, is easy to pattern and etch, and has high heat resistance. Titanium is preferably used in contact with oxide semiconductors such as ITO and IZO, and silicon. However, it is desirable because it can be manufactured without problems such as material defects and has high heat resistance. Tungsten is desirable because it has high heat resistance. Neodymium is also desirable because it has high heat resistance. In particular, alloying neodymium with aluminum improves heat resistance. Aluminum is preferable because it is less likely to cause hillocks. This is desirable because it can be formed simultaneously with the semiconductor layer of the transistor and has high heat resistance. Addition of indium tin oxide (ITO), indium zinc oxide (IZO), and silicon oxide Indium tin oxide (ITSO), zinc oxide (ZnO), and silicon (Si) are transparent. Since it has the property of transmitting light, it can be used in a portion that transmits light, which is desirable. For example, it can be used as a pixel electrode or a common electrode.

[0131] The wiring and electrodes may be formed in a single layer, or may have a multi-layer structure. By forming it in a single layer structure, the manufacturing process can be simplified and the process time can be reduced. In addition, by using a multi-layer structure, each material can be By utilizing the advantages of each material, the disadvantages of one material can be reduced by using another material. For example, it is possible to form high-performance wiring and electrodes using low-resistance materials (aluminum, By incorporating a material such as silicon into the multilayer structure, it is possible to reduce the resistance of the wiring. In addition, if a material with high heat resistance is included, it is possible to use a material with low heat resistance but with another material. By creating a laminated structure in which a material with a high level of heat resistance is sandwiched between materials with high heat resistance, The heat resistance of the electrode as a whole can be increased. For example, It is desirable to have a laminated structure in which the material is sandwiched between layers containing ribide or titanium. If there are parts that come into direct contact with wiring or electrodes made of other materials, they may have adverse effects on each other. For example, one material may penetrate into another material, changing its properties. It may no longer be able to fulfill its intended purpose, or problems may arise during production, making it impossible to produce properly. In such cases, it is recommended to sandwich or cover one layer with another. For example, indium tin oxide (ITO) and aluminum If you want to make contact with aluminum, it is advisable to place titanium or molybdenum between them. If you want to bring silicon and aluminum into contact, you can insert titanium or molybdenum between them. It is desirable that:

[0132] The wiring and electrodes described above can also be applied to other display devices and shift registers. can be done.

[0133] The signal line driver circuit 901 applies a potential or voltage corresponding to a video signal to the signal lines S1 to Sm. The signal line driver circuit 901 is formed on the same substrate as the pixel portion 903. It is not necessary to form the pixel portion 903 on a single crystal substrate such as an IC. The remaining portion may be formed on a single crystal substrate such as an IC.

[0134] The scanning line driving circuit 902 inputs signals to the scanning lines G1 to Gn. Select (hereinafter referred to as scanning) the first row in order. Then, connect the selected scanning line The pixels 904 corresponding to one scanning line are also selected at the same time. The period during which one scanning line is not selected is called a non-selection period. The scanning line driver circuit 902 may be configured to use the shift register shown in FIG. 6 or FIG. In addition, the scanning line driver circuit 902 is formed on the same substrate as the pixel portion 903. It is characterized by:

[0135] When the pixel 904 is selected, the pixel 904 receives a signal from the signal line driver circuit 901 via a signal line. A potential or current corresponding to the video signal is input. However, if it is not selected, No potential or current corresponding to the video signal is input.

[0136] Next, the operation of the display device shown in FIG. 9 will be explained with reference to the timing chart of FIG. In FIG. 10, one frame period corresponds to the period for displaying one screenful of image. The length of one frame period is not particularly limited, but it is important to consider the length of time it takes for the viewer to notice flickering. It is preferable to set the shutter speed to 1 / 60 seconds or less so that the shutter speed is not noticeable.

[0137] In the timing chart of FIG. 10, the first scanning line G1, the i-th scanning line Gi, The timings at which the +1st row scanning line Gi+1 and the nth row scanning line Gn are selected are shown. is doing.

[0138] In FIG. 10, for example, the i-th row of the scanning line Gi is selected, and the plurality of lines connected to the scanning line Gi are Then, a number of pixels 904 connected to the scanning line Gi are selected. The video signals are written into the display elements, and the brightness or transmittance of each display element is determined by the video signal. After that, when the i-th scanning line Gi is deselected, the i+1-th scanning line The scan line Gi+1 is selected, and a plurality of pixels 904 connected to the scan line Gi+1 are selected. Then, a video signal is supplied to each of the pixels 904 connected to the scanning line Gi+1. is written, and the brightness or transmittance of each display element becomes a value according to the video signal. In addition, since each pixel 904 holds the video signal written therein even when it is in a non-selected state, Each display element maintains a brightness or transmittance according to a video signal.

[0139] From the above, each of the scanning lines G1 to Gn has one gate selection period in one frame period. It is selected during the 1 gate selection period, and is not selected during the non-selection period. The length of the interval is roughly equal to the length of one frame period divided by n, so In other words, the scanning line driver circuit 902 is in a non-selection period. When the shift register shown in FIG. 8 is applied, the flip-flop shown in FIG. 6 or FIG. Each of 601_1 to 601_i is the first non-selection signal for most of one frame period. The scanning period, the second non-selection period, and the third non-selection period are repeated in sequence. The line driving circuit 902 includes the flip-flops 601_1 to 601_i shown in FIGS. Since it is possible to suppress the deterioration of the transistors that each device has, it is possible to extend their lifespan. Furthermore, the display shown in FIG. 9 in which the long-life scanning line driving circuit 902 is integrally formed with the pixel section 903 can be used. The device can also have a longer lifespan.

[0140] As shown in Figure 9, if a pixel can be selected and a video signal can be written to the pixel, the driving The number and arrangement of circuits are not limited to those shown in FIG.

[0141] For example, as shown in FIG. 11, the scanning lines G1 to Gn are connected to a first scanning line driving circuit 1101. The first scanning line driver circuit 1102 may be used for scanning. The first scanning line driver circuit 1101 and the second scanning line driver circuit 1102 are the same as the scanning line driver circuit 902 shown in FIG. The scanning lines G1 to Gn are scanned at the same timing. The scanning line Gn is driven by a first scanning line driving circuit 1101 and a second scanning line driving circuit 1102. By scanning, delays and distortions of the signals output to each of the scanning lines G1 to Gn occur. Therefore, the scanning lines G1 to Gn are scanned at high speed. As the panel size increases, the wiring resistance and parasitic capacitance of the scanning lines G1 to Gn increase. However, the delay and distortion of the signals output to the scanning lines G1 to Gn are reduced. Furthermore, the display device of FIG. 11 has a large panel size. As the number of pixels increases or the resolution of the panel increases, the scanning lines G1 to G2 Even if it is necessary to scan the scanning line Gn at high speed, it is possible to scan the scanning lines G1 to Gn at high speed. This allows for larger screens and higher resolution. 11 indicates that one of the first scanning line driver circuit 1101 and the second scanning line driver circuit 1102 is defective. Even if a problem occurs, the other scanning lines G1 to Gn can be scanned, providing redundancy. Note that the same reference numerals are used for the components common to those in FIG. 9, and the description thereof will be omitted. The timing chart of FIG. 10 can be used for the display device of FIG. 11 in the same way as in FIG. can.

[0142] In the display device shown in FIG. 12, pixels are selected as in FIG. 9, and video signals are written to the pixels. As shown in FIG. 12, a first scanning line driving circuit 1201 and a second scanning line driving circuit The scanning lines G1 to Gn may be scanned row by row by the scanning line driving circuit 1202. The first scanning line driver circuit 1201 and the second scanning line driver circuit 1202 are the same as those shown in FIG. It has the same configuration as the scanning line driving circuit 902, but the driving timing is different. The first scanning line driver circuit 1201 scans the odd-numbered scanning lines, and the second scanning line driver circuit 1202 scans the even-numbered scanning lines. By scanning the scanning lines, the first scanning line driving circuit 1201 and the second scanning line driving circuit The driving frequency of the first scanning line driving circuit 1201 and the second scanning line driving circuit 1202 can be reduced. The pitch of the flip-flops in the driver circuit 1202 is increased by one stage. The display device is driven by a first scanning line driver circuit 1201 and a second scanning line driver circuit 1202. Since the frequency can be reduced, power saving can be achieved. The flip-flops included in the first scanning line driver circuit 1201 and the second scanning line driver circuit 1202 The pitch of one stage is increased, allowing for efficient layout and a smaller frame. Furthermore, the display device of FIG. 12 includes a first scanning line driving circuit 1201 and a second scanning line driving circuit 1202. Since the circuit 1202 is arranged on the left and right, the frame can be made uniform on both sides. The same components as those in the display device of FIG. 9, the timing chart of FIG. 10 can be used.

[0143] Also in the display device shown in FIG. 44, pixels are selected as shown in FIG. 9, and video signals are input to the pixels. As shown in FIG. 44, the first scan line driver circuit 4402 and The scanning lines G1 to Gn may be scanned line by line by the second scanning line driving circuit 4403. In addition, the pixels 904 are connected to left and right signal lines for each row. The number of pixels 904 in the i-th row is connected to the signal line Sj (one of the signal lines S1 to Sm+1). In the i+1th row, it is connected to signal line Sj+1, and in the i-1th row, it is connected to signal line Sj Connected to +1.

[0144] The operation of the display device shown in FIG. 44 will be described with reference to the timing chart of FIG. In FIG. 45, one frame period, which corresponds to the period for displaying one screenful of image, is The length of one frame period is not particularly limited, but if the person viewing the image notices flickering, It is preferable to set the shutter speed to 1 / 60 seconds or less so that the shutter speed is not noticeable.

[0145] In the timing chart of FIG. 45, the first scanning line G1 and the (i-1)th scanning line Gi -1, the i-th scanning line Gi, the i+1-th scanning line Gi+1, and the n-th scanning line Gn. The timing chart in Figure 45 shows the timing at which each selection is made. The period is divided into a selection period Ta and a selection period Tb.

[0146] In the display device of FIG. 44, a positive video signal is sent to each signal line for each column during one frame period. By simply inputting a negative polarity video signal and a negative polarity video signal, dot inversion driving can be performed. The display device of FIG. 44 inverts the polarity of the video signal input to each signal line every frame period. In addition, in the timing chart of Figure 45, The case where the display device performs dot inversion driving and frame inversion driving will be described below.

[0147] In FIG. 45, for example, the selection period Ta of the i-th row scanning line Gi is The selection period Tb of the scanning line Gi of the i-th row overlaps with the selection period Tb of the scanning line Gi of the i+1-th row. The selection period of the scan line Gi+1 overlaps with that of the scan line Gi+1. Therefore, in the selection period Ta, the scan line i-1 The same video signal as that input to pixel 904 in the j+1th column is input to pixel 905 in the i-th row and j-th column. 04. Also, during the selection period Tb, the signal is input to the pixel 904 in the i-th row and j-th column. The same signal as the video signal is input to the pixel 904 in the (i+1)th row and the (j-1)th column. During the selection period Tb, the video signal input to the pixel 904 is the original video signal. During the period Ta, the video signal input to the pixel 904 is a video signal for precharging the pixel 904. Therefore, each pixel 904 receives an input signal during the selection period Ta. It is precharged by a video signal and holds the video signal input during the selection period Tb. Hold.

[0148] From the above, the display device of FIG. 44 can write video signals to the pixels 904 at high speed. Therefore, it is easy to realize a larger size and higher resolution. In this device, video signals of the same polarity are input to each signal line during one frame period. The charge and discharge of the signal lines is small, and low power consumption can be achieved. The load on the IC for supplying the audio signal is significantly reduced, resulting in reduced heat generation and power consumption of the IC. Furthermore, the display device of FIG. 44 includes a first scanning line driver circuit 4402 In addition, the driving frequency of the second scanning line driving circuit 4403 can be reduced to about half.

[0149] 9, 11, 12, and 44 may be different depending on the configuration of the pixel 904. For example, a power supply line maintained at a constant potential, a new scanning line, and In addition, when adding a new scanning line, the same steps as those shown in FIGS. 6 and 8 may be performed. 10. A scanning line driver circuit using the shift register shown in FIG.

[0150] Note that the shift registers and flip-flops shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be freely combined with the configuration of the display device shown in the embodiment. The shift register and flip-flop configurations shown in the embodiment can be freely combined and implemented. It is possible.

[0151] (Embodiment 2) In this embodiment mode, a flip-flop having a different structure from that in Embodiment Mode 1 is shown in FIG. In addition, the same parts as those in the first embodiment are designated by the same reference numerals, and the same or similar parts are designated by the same reference numerals. A detailed description of the functional parts will be omitted.

[0152] The flip-flop shown in FIG. 13 includes a first transistor 101, a second transistor 10 2, the third transistor 103, the fourth transistor 104 and the fifth transistor 13 05. Note that the flip-flop has a first wiring 111, a second wiring 112, a third wiring 113, and a The first wiring 113, the fourth wiring 114, the fifth wiring 115, the sixth wiring 116 and the seventh wiring In this embodiment, the fifth transistor 1305 is an N-channel transistor. The voltage between the gate and source (Vgs) is the threshold voltage (V th), the seventh wiring 1317 is in a conductive state. These may also be called signal lines.

[0153] The first terminal (one of the source terminal and the drain terminal) of the first transistor 101 is connected to the first The second terminal (the other of the source terminal and the drain terminal) is connected to the line 111. The gate terminal is connected to the fifth wiring 115. The first terminal of the third transistor 103 is connected to the gate terminal of the second transistor 102. The second terminal is connected to the second wiring 112, and the gate terminal is connected to the fourth wiring 114. The first terminal of the second transistor 102 is connected to the third wiring 113, and the second terminal The first terminal of the fourth transistor 104 is connected to the sixth wiring 116. The first terminal is connected to the second wiring 112, and the gate terminal is connected to the wiring 114. The first terminal of the fifth transistor 1305 is connected to the sixth wiring 116. The second terminal is connected to the second wiring 112, and the gate terminal is connected to the seventh wiring 1317. It is being done.

[0154] The second terminal of the third transistor 103, the second terminal of the fourth transistor 104, and The second terminal of the fifth transistor 1305 is not necessarily connected to the second wiring 112. The gate of the third transistor 103 may be connected to a separate wiring. The terminal and the gate terminal of the fourth transistor 104 are connected to a fourth wiring 114. are not limited to these and may be connected to separate wirings.

[0155] Next, regarding the operation of the flip-flop shown in Figure 13, the timing chart of Figure 14 is 14 is a diagram showing a configuration of the flip-flop shown in FIG. This is a timing chart for when it operates in the same way as a flop. The same parts as those in the chart are designated by the same reference numerals and will not be described further.

[0156] A signal is input to the seventh wiring 1317. The signal input to the seventh wiring 1317 is the third clock signal. The potential of the signal is V1 (hereinafter referred to as the H level), and the potential of the L signal is V2 (hereinafter referred to as the L level). It is a digital signal.

[0157] However, it is not limited to the seventh wiring 1317 being input with the third clock signal. Other signals may be input, or a constant potential or current may be input.

[0158] In FIG. 14, a signal 1417 is input to the seventh wiring 1317 .

[0159] In the flip-flop of FIG. 13, the fifth transistor is turned on during the set period and the second non-selection period. The sixth wiring 116 is connected to the fifth transistor 1305. Since the potential of the second wiring 112 is supplied via O5, the L level is maintained.

[0160] From the above, the flip-flop of FIG. 13 has a first non-selection period, a second non-selection period, During the first and second non-selection periods of the third non-selection period, the sixth wiring Since V2 is supplied to 116, malfunction of the flip-flop can be further suppressed. This is because, during the non-selection period, the first non-selection period and the second non-selection period are ) V2 is supplied to the sixth wiring 116, and the potential of the sixth wiring 116 is stabilized to V2 This is because it can be maintained at a constant level.

[0161] Furthermore, the fifth transistor 1305 of the flip-flop of FIG. Since the fifth transistor 1305 is turned on only during the non-selection period of the second transistor, the deterioration of the characteristics of the fifth transistor 1305 is suppressed. It is possible.

[0162] The flip-flop of FIG. 13 includes a first transistor 101 and a second transistor 1 02, the third transistor 103, the fourth transistor 104 and the fifth transistor 1 305 are all made up of N-channel transistors. The flip-flop in Figure 13 uses amorphous silicon as the semiconductor layer of the transistor. Since it is possible to use the same, the manufacturing process can be simplified, reducing manufacturing costs and steps. Furthermore, it is possible to improve the yield of semiconductor devices such as large display panels. It is also possible to use polysilicon or single crystal silicon as the semiconductor layer of the transistor. Even if a condensate is used, the manufacturing process can be simplified.

[0163] In addition, the flip-flop in Figure 13 has a semiconductor layer of a transistor that is prone to characteristic degradation (threshold voltage). Even when amorphous silicon is used, where the voltage shift is clearly visible, the transistor characteristics do not deteriorate. Since the degradation can be suppressed, it is possible to manufacture a semiconductor device such as a display panel having a long life. can.

[0164] Here, the function of the fifth transistor 1305 will be described. 05 is a function for selecting the timing for supplying the potential of the second wiring 112 to the sixth wiring 116. It has the function of functioning as a switching transistor.

[0165] If the operation is the same as that shown in FIG. 13, the arrangement and number of transistors may be the same as that shown in FIG. Therefore, it is not limited to transistors, other elements (resistive elements, capacitive elements, etc.), diodes, Diodes, switches, various logic circuits, etc. may be newly placed.

[0166] For example, as shown in FIG. 15, the gate terminal of the second transistor 102 shown in FIG. A capacitor 1501 may be disposed between the first terminal and the second terminal. This allows the bootstrap operation during the selection period to be performed more stably. This allows the parasitic capacitance between the gate terminal and the second terminal of the second transistor 102 to be reduced. The capacitor element 1501 can be switched on and off at high speed. A gate insulating film may be used as the insulating layer, and a gate electrode layer and a wiring layer may be used as the conductive layer. Alternatively, a gate insulating film is used as an insulating layer, and a gate electrode layer and a gate electrode layer doped with impurities are used as a conductive layer. Alternatively, an interlayer film (insulating film) may be used as an insulating layer and an electrically conductive layer may be used. A line layer and a transparent electrode layer may be used. Note that the same reference numerals are used to designate the same components as those in the configuration of FIG. will be used to omit the explanation.

[0167] The flip-flop in FIG. 16 can perform the same operation as that in FIG. 13. As shown in FIG. 13, the first transistor 101 may be diode-connected. The first transistor 101 is diode-connected, and the first wiring 111 is insufficient. This reduces the number of wires and power supplies (V1) by one. Common reference numerals are used for parts that are common to the above, and the explanation thereof will be omitted.

[0168] Next, the shift register having the flip-flop of the present embodiment will be described with reference to FIG. 7. The shift register having the flip-flop shown in FIG. The same parts as those in FIG. 6 are designated by the same reference numerals and will not be described again.

[0169] The shift register is made up of a first wiring 611, a second wiring 612, a third wiring 613, a fourth wiring 614, and a A line 614, a fifth wiring 615, a sixth wiring 616, wirings 622_1 to 622_n, and n wirings The n-stage flip-flops 1701_1 to 1701_n are provided. ) flip-flops 1701_1 to 1701_n are connected to the first wiring 611, the second wiring 612, The first wiring 612, the third wiring 613, the fourth wiring 614, and the fifth wiring 615 are connected to the For example, the flip-flop 1701_i (flip-flop 1701_ Flip Flip 1701_2~Flip (any one of 1701_1~1701_n) Flop_n-1 is the flip-flop 1701_i-1 in the i-1th stage and the flip-flop 1701_i+1 in the i+1th stage. It is connected to the flip-flop 1701_i+1 and is the flip-flop 1701_i in the i-th stage. The connection point between the flip-flop 1701_i+1 in the (i+1)th stage and the flip-flop 1701_i+1 is the wiring 622_i (wiring 622_1 to 622_n). The flip-flop 1701_1 is connected to the sixth wiring 616 and the second-stage flip-flop 1701_2. The first stage flip-flop 1701_1 and the second stage flip-flop 1701_ The connection point with the n-th flip-flop 1 is connected to the wiring 622_1. 701_n is connected to the (n-1)th flip-flop 1701_n-1 and the wiring 622_n. It is being done.

[0170] In the flip-flop 1701 at the 1+3Nth stage, the first wiring 611 and the second wiring 6 12, the third wiring 613, the fourth wiring 614, and the fifth wiring 615 are respectively The first wiring 111, the second wiring 112, the third wiring 113, the fourth wiring 114, and the seventh wiring 1317. In the flip-flop 1701 of the 2+3Nth stage, the first wiring 611, the second wiring 612, the fourth wiring 614, the fifth wiring 615, and the third wiring 613 are , the first wiring 111, the second wiring 112, the third wiring 113, and the fourth wiring 114 in FIG. 13, respectively. The line 114 is connected to the seventh wiring 1317. The flip-flop 60 in the 3+3Nth stage 1, a first wiring 611, a second wiring 612, a fifth wiring 615, a third wiring 613, The fourth wiring 614 corresponds to the first wiring 111, the second wiring 112, and the third wiring 113 shown in FIG. The wire 113 is connected to the fourth wiring 614 and the seventh wiring 1317. Of the first flip-flop 1701_i, flip-flop 1701_2~flip-flop The fifth wiring 115 and the sixth wiring 116 shown in FIG. 13 of the drop 1701_n-1 are The sixth wiring 116 shown in FIG. 13 of the flip-flop 1701_i-1 in the (i-1)th stage, The flip-flop 1701_i+1 in the (i+1)th stage is connected to the fifth wiring 115 shown in FIG. The fifth wiring 1 shown in FIG. 13 of the first stage flip-flop 1701_1 is 15 and the sixth wiring 116 correspond to the sixth wiring 616 and the second-stage flip-flop in FIG. 17, respectively. 13 of the n-th stage. The fifth wiring 115 and the sixth wiring 116 shown in FIG. 13 of the flip-flop 1701_n are , and the sixth wiring 1701_n-1 of the n-1th stage shown in FIG. 16, and is connected to the wiring 622_n in FIG.

[0171] The shift register shown in FIG. 17 operates in the same manner as the shift register shown in FIG. Therefore, the shift register shown in FIG. 17 can be implemented with the timing circuit shown in FIG. A chart can be used.

[0172] Therefore, the shift register of FIG. 17 uses a three-phase clock signal, similar to the first embodiment. Furthermore, the shift register of this embodiment can reduce power consumption by The third wiring 613, the fourth wiring 614, and the fifth wiring 615 are connected to the lock signal lines. The number of flip-flops 1701 used is 2 / 3 of that when a single-phase clock signal is used. Therefore, the load on each clock signal line can be reduced.

[0173] The shift register in FIG. 17 buffers the output signal of the flip-flop 1701 in each stage. The signals may be output to the wiring 622 of each stage via a power amplifier. Such a configuration is shown in FIG. The shift register in Figure 18 has a flip-flop 1701 at each stage connected to a buffer 1801. Since the wiring 622 of each stage is connected via the This is because a large load is connected to the wire 622, and the signal on the wire 622 is delayed. This is because even if a delay or distortion of the waveform occurs, it does not affect the operation of the shift register. The 1801 buffer contains inverters, logic circuits such as NAND and NOR, operational amplifiers, etc. , and a circuit combining these can be used.

[0174] The shift register shown in this embodiment may be used in conjunction with the display devices shown in FIGS. As in the first embodiment, the scanning line driver circuit formed integrally with the pixel section can be applied to the device. By applying this embodiment to the above, the life of the display device can be extended.

[0175] Note that the shift registers and flip-flops shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be freely combined with the configuration of the display device shown in the embodiment. The shift register and flip-flop configurations shown in the embodiment can be freely combined and implemented. It is possible.

[0176] (Embodiment 3) In this embodiment mode, a flip-flop having a different configuration from those in Embodiment Mode 1 and Embodiment Mode 2 is used. 19. Note that the same components as those in the first and second embodiments are designated by the same reference numerals. and detailed description of the same parts or parts having similar functions will be omitted.

[0177] The flip-flop shown in FIG. 19 includes a first transistor 101, a second transistor 10 2, the third transistor 103, the fourth transistor 104, and the fifth transistor 130 5, the sixth transistor 1906, the seventh transistor 1907, and the eighth transistor 1 The flip-flop has a first transistor 908 and a ninth transistor 1909. The first wiring 111, the second wiring 112, the third wiring 113, the fourth wiring 114, the fifth wiring 1 15, the sixth wiring 116 and the seventh wiring 1317. The sixth transistor 1906, the seventh transistor 1907, and the eighth transistor 1908 are connected to the first transistor 1909. The 908 and 9th transistors 1909 are N-channel transistors, and their gates and When the voltage between the sources (Vgs) exceeds the threshold voltage (Vth), the transistor becomes conductive. Let's say.

[0178] The first terminal (one of the source terminal and the drain terminal) of the first transistor 101 is connected to the first The second terminal (the other of the source terminal and the drain terminal) is connected to the line 111. The gate terminal is connected to the fifth wiring 115. The first terminal of the third transistor 103 is connected to the gate terminal of the second transistor 102. The second terminal is connected to the second wiring 112, and the gate terminal is connected to the fourth wiring 114. The first terminal of the second transistor 102 is connected to the third wiring 113, and the second terminal The first terminal of the fourth transistor 104 is connected to the sixth wiring 116. The first terminal is connected to the second wiring 112, and the gate terminal is connected to the wiring 114. The first terminal of the fifth transistor 1305 is connected to the sixth wiring 116. The second terminal is connected to the second wiring 112, and the gate terminal is connected to the seventh wiring 1317. The first terminal of the sixth transistor 1906 is connected to the gate of the eighth transistor 1908. The first terminal is connected to the second wiring 112, and the gate terminal is connected to the second transistor. The first terminal of the seventh transistor 1907 is connected to the gate terminal of the seventh transistor 1902. The first terminal is connected to the first wiring 111, and the second terminal is connected to the gate terminal of the eighth transistor 1908. The eighth transistor 1908 has a gate terminal connected to the first wiring 111. The first terminal of the ninth transistor 1909 is connected to the third wiring 113, and the second terminal of the ninth transistor 1909 is connected to the gate of the ninth transistor 1909. The first terminal of the ninth transistor 1909 is connected to the sixth wiring 116. The second terminal is connected to the second wiring 112. a first terminal of the seventh transistor 1906, a second terminal of the seventh transistor 1907, and a third terminal of the eighth transistor 1908; The connection point of the gate terminal of the eighth transistor 1908 is a node 1922. The connection point between the second terminal of the transistor 1908 and the gate terminal of the ninth transistor 1909 is a node 192 Let's say it's 3.

[0179] The second terminal of the third transistor 103, the second terminal of the fourth transistor 104, the second terminal of the fifth transistor 1305, the second terminal of the sixth transistor 1906, and the ninth The second terminal of the transistor 1909 is not necessarily connected to the second wiring 112. The gate terminal of the third transistor 103 and the The gate terminal of the fourth transistor 104 is not necessarily connected to the fourth wiring. The first terminal of the first transistor 101 and the second terminal of the second transistor 102 may be connected to different wirings. The first terminal of the seventh transistor 1907 and the gate terminal of the seventh transistor 1907 are connected to the first They are not limited to being connected to one wiring 111, but may be connected to separate wirings. In addition, the first terminal of the second transistor 102 and the first terminal of the eighth transistor 1908 is not limited to being connected to the third wiring 113, and may be connected to separate wirings. stomach.

[0180] Next, regarding the operation of the flip-flop shown in Figure 19, the timing chart of Figure 20 is 20 is a circuit diagram of the flip-flop shown in FIG. 19, which is similar to that shown in FIG. 1 and FIG. 13. 2 and 3. This is a timing chart for when the flip-flop operates in the same manner as the flip-flop shown in FIG. 14 are designated by the same reference numerals and will not be described again.

[0181] In FIG. 20, potential 2022 is the potential of node 1922 in FIG. 19, and potential 2023 is This is the potential of node 1923 in FIG.

[0182] In the flip-flop of FIG. 19, during the third non-selection period, the ninth transistor 190 Then, the sixth wiring 116 is connected to the third transistor 1909 via the ninth transistor 1909. Since the potential of the wiring 112 of No. 2 is supplied, the L level is maintained.

[0183] The on / off control of the ninth transistor 1909 will be specifically described. The sixth transistor 1906 and the seventh transistor 1907 constitute an inverter. When a high level is input to the gate terminal of the transistor 1906, the potential of the node 1922 (potential 2022) is approximately V2. However, the potential 2022 at this time is The resistance ratio of the sixth transistor 1906 to the seventh transistor 1907 is determined by the resistance ratio of the sixth transistor 1906 to the seventh transistor 1907. Therefore, the value is slightly higher than V2. When an L level is input to the node 1922, the potential of the node 1922 changes from the potential of the first wiring 111 to the potential of the seventh wiring 112. Since it is the value obtained by subtracting the threshold voltage (Vth1907) of transistor 1907, V1-V Therefore, the first non-selection period, the second non-selection period, and the third non-selection period are During the selection period, the node 121 is at the L level and the node 1922 is at the H level. Therefore, the ninth transistor 1909 is turned on. Since it is controlled by a signal input to the wiring 113, it is turned on in the third non-selection period. The first non-selection period and the second non-selection period are turned off. During the selection period, the node 121 is at the H level and the node 1922 is at the L level. Therefore, the eighth transistor 1908 is turned off. The potential of the gate terminal is the potential of the first non-selection period, which is the period before the set period, that is, the L level. To maintain the voltage, the ninth transistor 1909 is turned off.

[0184] From the above, the flip-flop of FIG. 19 has a first non-selection period, a second non-selection period, and In the third and fourth non-selection periods, V2 is supplied to the wiring 116, and thus the flip-flop This can further suppress malfunctions. This is because, during the non-selection period, 19. The flip-flop in FIG. 19 is a non-selected flip-flop. During the selection period, V2 is supplied to the sixth wiring 116, and therefore, noise on the sixth wiring 116 is suppressed. It can be reduced.

[0185] Furthermore, the flip-flop of FIG. 19 includes a sixth transistor 1906, a seventh transistor The deterioration of the characteristics of the eighth transistor 1907, the eighth transistor 1908 and the ninth transistor 1909 is The sixth transistor 1906 can be suppressed because it is The seventh transistor 1907 is turned on only during the selection period. During the non-selection period of 1, the potential of the node 1922 rises to V1-Vth1907. The eighth transistor 1908 is turned on only during the first non-selection period. During the second non-selection period and the third non-selection period, the potential of the node 1923 is V1-β (β: Vt This is because the transistor is turned on only during the period when the voltage rises to (Vth1907 + Vth1908). This is because the transistor 1909 of No. 9 is turned on only during the third non-selection period.

[0186] The flip-flop of FIG. 19 includes a first transistor 101 and a second transistor 1 02, the third transistor 103, the fourth transistor 104, and the fifth transistor 13 05, the sixth transistor 1906, the seventh transistor 1907, and the eighth transistor The 1908 and 9th transistors 1909 are all N-channel transistors. Therefore, the flip-flop of FIG. Amorphous silicon can be used as the body layer, simplifying the manufacturing process. This allows for a reduction in manufacturing costs and an improvement in yield. It is also possible to manufacture semiconductor devices such as display panels. Even if polysilicon or single crystal silicon is used, the manufacturing process can be simplified. .

[0187] In addition, the flip-flop in Figure 19 has a semiconductor layer of a transistor that is prone to characteristic degradation (threshold voltage). Even when amorphous silicon is used, where the voltage shift is clearly visible, the transistor characteristics do not deteriorate. Since the degradation can be suppressed, it is possible to manufacture a semiconductor device such as a display panel having a long life. can.

[0188] Here, the sixth transistor 1906, the seventh transistor 1907, the eighth transistor The functions of the sixth transistor 1908 and the ninth transistor 1909 will be explained. The potential of the second wiring 112 is supplied to the node 1922 by the timer 1906. The seventh transistor 1907 has a function of switching the transistor. The potential of the first wiring 111 is supplied to the node 1922. The eighth transistor 1908 functions as a diode. The switching transistor has a function of selecting the timing at which the voltage is supplied to the node 1923. The ninth transistor 1909 functions as a transistor that supplies the potential of the second wiring 112 to the sixth The wiring 116 has a function of selecting the timing of supplying the signal. It works like this.

[0189] If the same operation as in FIG. 19 is performed, the arrangement and number of transistors may be the same as in FIG. Therefore, it is not limited to transistors, other elements (resistive elements, capacitive elements, etc.), diodes, Diodes, switches, various logic circuits, etc. may be newly placed.

[0190] For example, as shown in FIG. 21, the gate terminal of the second transistor 102 shown in FIG. A capacitive element 2101 may be disposed between the first terminal and the second terminal. This allows the bootstrap operation during the selection period to be performed more stably. This allows the parasitic capacitance between the gate terminal and the second terminal of the second transistor 102 to be reduced. The capacitor element 2101 can be switched on and off at high speed. A gate insulating film may be used as the insulating layer, and a gate electrode layer and a wiring layer may be used as the conductive layer. Alternatively, a gate insulating film is used as an insulating layer, and a gate electrode layer and a gate electrode layer doped with impurities are used as a conductive layer. Alternatively, an interlayer film (insulating film) may be used as an insulating layer and an electrically conductive layer may be used. A line layer and a transparent electrode layer may be used. The same reference numerals are used to designate the same components as those in the configuration of FIG. will be used to omit the explanation.

[0191] The flip-flop in FIG. 22 can perform the same operation as that in FIG. 19. As shown in FIG. 19, the first transistor 101 may be diode-connected. When the first transistor 101 is diode-connected, a current flows through the first wiring 111. Since the current flowing through the first wiring 111 is reduced, the width of the first wiring 111 can be reduced. 19 are designated by the same reference numerals and will not be described further.

[0192] The flip-flop shown in this embodiment may be applied to the shift registers shown in FIGS. As in the first and second embodiments, a three-phase clock signal can be used. Furthermore, the shift register of this embodiment can realize power saving. The clock signal lines (third wiring 613, fourth wiring 614, fifth wiring 615) are connected to the The number of stages of flip-flops 1701 used is 2 / 3 of that when a single-phase clock signal is used. Therefore, the load on each clock signal line can be reduced.

[0193] The shift register shown in this embodiment may be used in conjunction with the display devices shown in FIGS. As in the first and second embodiments, the present invention can be applied to a device that is formed integrally with a pixel section. By applying this embodiment to the scanning line driving circuit, the life of the display device can be extended. This can be done.

[0194] Note that the shift registers and flip-flops shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be freely combined with the configuration of the display device shown in the embodiment. The shift register and flip-flop configurations shown in the embodiment can be freely combined and implemented. It is possible.

[0195] (Fourth embodiment) In this embodiment, a function block having a configuration different from that of Embodiments 1, 2, and 3 is used. The flip-flop is shown in FIG. 23. Note that, as in the first, second and third embodiments, The same parts or parts with similar functions are shown using the same symbols. A detailed explanation will be omitted.

[0196] The flip-flop shown in FIG. 23 includes a first transistor 101, a second transistor 10 2, the third transistor 103, the fourth transistor 104, and the fifth transistor 130 5, the sixth transistor 1906, the seventh transistor 1907, and the eighth transistor 1 908, the ninth transistor 1909, the tenth transistor 2310, the eleventh transistor The flip-flop has a 12th transistor 2311 and a 13th transistor 2312. The group includes a first wiring 111, a second wiring 112, a third wiring 113, a fourth wiring 114, and a third wiring 115. The fifth wiring 115, the sixth wiring 116 and the seventh wiring 1317 are connected to the fifth wiring 115, the sixth wiring 116 and the seventh wiring 1317. In the embodiment, the tenth transistor 2310, the eleventh transistor 2311, and the first The second transistor 2312 is an N-channel transistor, and the When the voltage (Vgs) exceeds the threshold voltage (Vth), the transistor is in a conductive state.

[0197] The first terminal (one of the source terminal and the drain terminal) of the first transistor 101 is connected to the first The second terminal (the other of the source terminal and the drain terminal) is connected to the line 111. The gate terminal is connected to the fifth wiring 115. A first terminal of the third transistor 103 is connected to the second wiring 112, and a second terminal of the third transistor 103 is connected to the second wiring 112. The gate terminal of the transistor 102 is connected to the fourth wiring 114. The first terminal of the second transistor 102 is connected to the third wiring 113, and the second terminal The first terminal of the fourth transistor 104 is connected to the sixth wiring 116. The first terminal is connected to the sixth wiring 116, and the gate terminal is connected to the fourth wiring 117. The first terminal of the fifth transistor 1305 is connected to the second wiring 112. The first terminal is connected to the sixth wiring 116, and the gate terminal is connected to the seventh wiring 1317. The first terminal of the sixth transistor 1906 is connected to the second wiring 112. The second terminal is connected to the gate terminal of the eighth transistor 1908 and the gate terminal of the eleventh transistor 231. 1, and the gate terminal is connected to the gate terminal of the second transistor 102. A first terminal of the seventh transistor 1907 is connected to the first wiring 111, and a The second terminal is the gate terminal of the eighth transistor 1908 and the second terminal is the gate terminal of the eleventh transistor 2311. The eighth transistor is connected to the gate terminal, and the gate terminal is connected to the first wiring 111. The first terminal of the transistor 1908 is connected to the third wiring 113, and the second terminal is connected to the ninth transistor 1908. The gate terminal of the tenth transistor 2310 is connected to the gate terminal of the tenth transistor 2311. A first terminal of the ninth transistor 1909 is connected to the second wiring 112, and a second terminal of the ninth transistor 1909 is connected to the second wiring 112. The first terminal of the tenth transistor 2310 is connected to the sixth wiring 116. The first terminal is connected to the wiring 112, and the second terminal is connected to the gate terminal of the second transistor 102. A first terminal of the eleventh transistor 2311 is connected to a seventh wiring 1317, and a second terminal of the eleventh transistor 2311 is connected to a seventh wiring 1317. The terminal is connected to the gate terminal of the twelfth transistor 2312. The first terminal of the transistor 2312 is connected to the second wiring 112, and the second terminal of the transistor 2312 is connected to the second wiring 112. The second terminal of the eleventh transistor 2311 is connected to the gate terminal of the eleventh transistor 2312. The connection point of the gate terminal of the twelfth transistor 2312 and the gate terminal of the twelfth transistor 2313 is a node 2324 .

[0198] The first terminal of the third transistor 103, the first terminal of the fourth transistor 104, the first terminal of the fifth transistor 1305, the first terminal of the sixth transistor 1906, the first terminal of the transistor 1909, the first terminal of the tenth transistor 2310, and the The first terminal of the transistor 2312 is not necessarily connected to the second wiring 112. The gate terminal of the third transistor 103 and the The gate terminal of the fourth transistor 104 is not necessarily connected to the fourth wiring 114. The first terminal of the first transistor 101 may be connected to a separate wiring. the first terminal of the seventh transistor 1907 and the gate terminal of the seventh transistor 1907 The terminals are not limited to being connected to the first wiring 111, and may be connected to separate wirings. In addition, the first terminal of the second transistor 102 and the second terminal of the eighth transistor 1908 The first terminal is not limited to being connected to the third wiring 113, but may be connected to a separate wiring. In addition, the gate terminal of the fifth transistor 1305 and the gate terminal of the eleventh transistor 2 The first terminal of 311 is not limited to being connected to the seventh wiring 1317, but may be connected to a separate wiring. They may be connected.

[0199] Next, regarding the operation of the flip-flop shown in Figure 23, the timing chart of Figure 24 is 24 shows the flip-flop of FIG. 23 shown in FIGS. 1, 13 and 19. This is a timing chart for when the flip-flop operates in the same way as the flip-flop shown in Figure 2. 14 and 20, the same reference numerals are used for the same parts. Omitted.

[0200] In FIG. 24, potential 2424 is the potential at node 2324 in FIG.

[0201] In the flip-flop of FIG. 23, the tenth transistor 231 0 is turned on. Then, the node 121 is connected to the second Since the potential of the wiring 112 is supplied, the L level can be maintained more stably. In the third flip-flop, the twelfth transistor 2312 is Then, the node 121 is connected to the second transistor 2312 via the twelfth transistor 2312. Since the potential of the line 112 is supplied, the L level can be maintained more stably.

[0202] The on / off control of the twelfth transistor 2312 will be specifically described. The on / off control of the transistor 2310 is the same as that of the ninth transistor described in Embodiment 3. 19. First, the flip-flop shown in FIG. Similarly, the sixth transistor 1906 and the seventh transistor 1907 constitute an inverter. Therefore, in the first non-selection period, the second non-selection period, and the third non-selection period, Since the node 121 is at L level and the node 1922 is at H level, the 11th transistor Therefore, the twelfth transistor 2312 is connected to the seventh wiring 131. 7, it is turned on during the second non-selection period, and On the other hand, the first non-selection period and the third non-selection period are turned off. During this period, node 121 is at H level and node 1922 is at L level, so The transistor 2311 is turned off. The potential of the element is maintained at the potential of the first non-selection period, which is the period before the set period, that is, the L level. Therefore, the twelfth transistor 2312 is turned off.

[0203] From the above, the flip-flop of FIG. 23 has a first non-selection period, a second non-selection period, and In the third non-selection period, V2 is supplied to the sixth wiring 116 and the node 121. Therefore, malfunction of the flip-flop can be further suppressed. This is because V2 can be supplied to the sixth wiring 116 and the node 121 in this case. 23, the sixth wiring 116 and the node 1 21, V2 is supplied to the sixth wiring 116 and the node 121, thereby reducing noise. It is possible.

[0204] Furthermore, the flip-flop of FIG. 23 includes a tenth transistor 2310, an eleventh transistor Therefore, deterioration of the characteristics of the twelfth transistor 2311 and the twelfth transistor 2312 can be suppressed. This is because the tenth transistor 2310 is turned on only during the third non-selection period. The eleventh transistor 2311 is turned on during the first non-selection period, the second non-selection period, and the During the non-selection period of 3, the potential of the node 2324 is V1-γ (γ: Vth1907+Vth2 311), the 12th transistor 2 This is because 312 is turned on only during the second non-selection period.

[0205] The flip-flop of FIG. 23 includes a first transistor 101 and a second transistor 1 02, the third transistor 103, the fourth transistor 104, and the fifth transistor 13 05, the sixth transistor 1906, the seventh transistor 1907, and the eighth transistor 1908, the ninth transistor 1909, the tenth transistor 2310, the eleventh transistor The first transistor 2311 and the second transistor 2312 are all N-channel transistors. Therefore, the flip-flop of FIG. The semiconductor layer of the photodiode can be made of amorphous silicon, which simplifies the manufacturing process. This allows for simplification, which in turn reduces manufacturing costs and improves yield. This also makes it possible to manufacture semiconductor devices such as large-sized display panels. Even if polysilicon or single crystal silicon is used as the semiconductor layer, the manufacturing process can be simplified. This can be done.

[0206] In addition, the flip-flop in FIG. 23 has a characteristic degradation (threshold voltage) in the semiconductor layer of the transistor. Even when amorphous silicon is used, where the voltage shift is clearly visible, the transistor characteristics do not deteriorate. Since the degradation can be suppressed, it is possible to manufacture a semiconductor device such as a display panel having a long life. can.

[0207] Here, the tenth transistor 2310, the eleventh transistor 2311, and the twelfth transistor The function of the tenth transistor 2310 will be described. The switch 112 has a function of selecting the timing at which the potential of the wiring 112 is supplied to the node 121. The eleventh transistor 2311 functions as a switching transistor. 7 to the node 2324, and The twelfth transistor 2312 functions as a transistor. The switching transistor has a function of selecting the timing of supplying the voltage to the node 121. It functions as such.

[0208] If the operation is the same as that shown in FIG. 23, the arrangement and number of transistors may be the same as that shown in FIG. Therefore, it is not limited to transistors, other elements (resistive elements, capacitive elements, etc.), diodes, Diodes, switches, various logic circuits, etc. may be newly placed.

[0209] For example, as shown in FIG. 25, the gate terminal of the second transistor 102 shown in FIG. A capacitor 2501 may be disposed between the first terminal and the second terminal. This allows the bootstrap operation during the selection period to be performed more stably. This allows the parasitic capacitance between the gate terminal and the second terminal of the second transistor 102 to be reduced. The capacitor element 2501 can be switched on and off at high speed. A gate insulating film may be used as the insulating layer, and a gate electrode layer and a wiring layer may be used as the conductive layer. Alternatively, a gate insulating film is used as an insulating layer, and a gate electrode layer and a gate electrode layer doped with impurities are used as a conductive layer. Alternatively, an interlayer film (insulating film) may be used as an insulating layer and an electrically conductive layer may be used. A line layer and a transparent electrode layer may be used. The same reference numerals are used to designate the same components as those in FIG. 23. will be used to omit the explanation.

[0210] The flip-flop in FIG. 26 can also perform the same operation as in FIG. 23. As shown in FIG. 23, the first transistor 101 may be diode-connected. When the first transistor 101 is diode-connected, a current flows through the first wiring 111. Since the current flowing through the first wiring 111 is reduced, the wiring width of the first wiring 111 can be reduced.

[0211] The flip-flop shown in this embodiment may be applied to the shift registers shown in FIGS. As in the first, second and third embodiments, a three-phase cross-section can be used. Since the shift register signal can be used, power saving can be realized. The register is connected to each clock signal line (third wiring 613, fourth wiring 614, fifth wiring 61 5) When the number of stages of the flip-flop 1701 connected to the This reduces the load on each clock signal line to two-thirds of the load in the previous case.

[0212] The shift register shown in this embodiment may be used in conjunction with the display devices shown in FIGS. As in the first, second and third embodiments, the present invention can be applied to pixel devices. By applying this embodiment to a scanning line driving circuit formed integrally with a display unit, the life of the display device can be improved. It can prolong life.

[0213] Note that the shift registers and flip-flops shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be freely combined with the configuration of the display device shown in the embodiment. The shift register and flip-flop configurations shown in the embodiment can be freely combined and implemented. It is possible.

[0214] (Embodiment 5) In this embodiment, the flip-flop has a P-channel transistor. The case where this is applied will be described with reference to FIG. 27. The flip-flop is composed of N-channel transistors. However, the power supply potential and the H and L levels of the signal are inverted. are.

[0215] FIG. 27 shows a shift register including a plurality of flip-flops, one of which is a stage (for example, a stage 1). The flip-flop shown in FIG. 27 is the first transistor. a first transistor 2701, a second transistor 2702, a third transistor 2703, and a fourth transistor 2704 The flip-flop has a first wiring 2711, a second wiring 2712, a third wiring 2713, a fourth wiring 2714, a fourth wiring 2715, a fifth wiring 2716, a sixth wiring 2717, a sixth wiring 2718, a sixth wiring 2719, a sixth wiring 2720, a sixth wiring 2721, a sixth wiring 2722, a sixth wiring 2723, a sixth wiring 2 The second wiring 2712, the third wiring 2713, the fourth wiring 2714, the fifth wiring 2715, and The first transistor 27 is connected to the sixth wiring 2716. 01, a second transistor 2702, a third transistor 2703 and a fourth transistor The transistor 2704 is a P-channel transistor, and the absolute value of the voltage between its gate and source (| When Vgs|) exceeds the threshold voltage (|Vth|) (when Vgs falls below Vth In addition, the first wiring 2711 and the second wiring 2712 are , may be called the first power supply line and the second power supply line, respectively. The fourth wiring 2714 may be referred to as a first signal line and a second signal line.

[0216] Note that the first transistor 2701, the second transistor 2702, and the third transistor 2703 and the fourth transistor 2704 are the same as the first transistor 101 in FIG. , the second transistor 102, the third transistor 103, and the fourth transistor 104 In addition, the first wiring 2711, the second wiring 2712, the third wiring 2713, and the The fourth wiring 2714, the fifth wiring 2715, and the sixth wiring 2716 are respectively the first wiring 2714, the fifth wiring 2715, and the sixth wiring 2716 shown in FIG. The first wiring 111, the second wiring 112, the third wiring 113, the fourth wiring 114, the fifth wiring 1 15 and the sixth wiring 116.

[0217] The first terminal (one of the source terminal and the drain terminal) of the first transistor 2701 is The second terminal (the other of the source terminal and the drain terminal) is connected to the wiring 2711. The gate terminal is connected to the fifth wiring 2715. A first terminal of the third transistor 2703 is connected to a second wiring 2712. The terminal is connected to the gate terminal of the second transistor 2702, and the gate terminal is connected to the fourth wiring 2 The first terminal of the second transistor 2702 is connected to the third wiring 2713. The second terminal of the fourth transistor 27 is connected to the sixth wiring 2716. The first terminal of 04 is connected to the second wiring 2712, and the second terminal is connected to the sixth wiring 2716. The gate terminal of the first transistor 2 is connected to the fourth wiring 2714. 701, the second terminal of the second transistor 2702, and the gate terminal of the third transistor The connection point with the second terminal of 2703 is set as node 2721 .

[0218] The second terminal of the third transistor 2703 and the second terminal of the fourth transistor 2704 The terminals are not limited to being connected to the second wiring 2712, but may be connected to separate wirings. In addition, the gate terminal of the third transistor 2703 and the gate terminal of the fourth transistor 27 The gate terminal of 04 is not limited to being connected to the fourth wiring 2714, but may be connected to a separate wiring. They may be connected.

[0219] Next, the operation of the flip-flop shown in FIG. 27 will be explained with reference to the timing chart and 28 and 29. In FIG. 28, there are set periods, selected periods, and non-selected periods. The non-selection period is divided into a first non-selection period, a second non-selection period, and a The non-selection period is divided into three non-selection periods: a first non-selection period, a second non-selection period, and a third non-selection period. is repeated in order.

[0220] Note that a potential of V2 is supplied to the first wiring 2711, and a potential of V1 is supplied to the second wiring 2712. However, V1>V2.

[0221] However, it is not limited to supplying the potential of V2 to the first wiring 2711. Alternatively, a digital signal or an analog signal may be input. In addition, the second wiring 2712 is not necessarily supplied with the potential of V1, and may be supplied with another potential. A digital signal or an analog signal may be input.

[0222] Signals are input to the third wiring 2713, the fourth wiring 2714, and the fifth wiring 2715. The signal input to the third wiring 2713 is the first clock signal, and the fourth The signal input to the wiring 2714 is the second clock signal, and the signal input to the fifth wiring 2715 is the The signal sent is a start signal. The potential of the signal input to the fifth wiring 2715 is V1 (hereinafter also referred to as H level). ), and the potential of the L signal is V2 (hereinafter also referred to as the L level).

[0223] However, it is not limited to the first clock signal being input to the third wiring 2713. Other signals may be input, or a constant potential or current may be input. The fourth wiring 2714 is not limited to being input with the second clock signal, and other signals may be input. Alternatively, a constant potential or current may be input to the fifth wiring 2. The start signal is not necessarily input to 715, and other signals may be input. Alternatively, a constant potential or current may be input.

[0224] In addition, signals input to the third wiring 2713, the fourth wiring 2714, and the fifth wiring 2715 The potential of the H signal is not limited to V1 and the potential of the L signal is not limited to V2. The potential is not particularly limited as long as it is higher than the potential.

[0225] A signal is output from the sixth wiring 2716. The signal is the output signal of the flip-flop and the start signal of the next flip-flop. The signal output from the sixth wiring 2716 is also The signal is input to the fifth wiring 2715. The signal output from the sixth wiring 2716 is The potential of the H signal is V1 (hereinafter referred to as the H level), and the potential of the L signal is V2 (hereinafter referred to as the L level). It is a digital signal of the same format as the digital signal.

[0226] In FIG. 28, a signal 2813 is a signal input to the third wiring 2713. 14 is a signal input to the fourth wiring 2714, and a signal 2815 is a signal input to the fifth wiring 2715. The signal 2816 is a signal output from the sixth wiring 2716. 27. Also, potential 2821 is the potential of node 2721 in FIG.

[0227] First, in the period A of FIG. 28 and the set period shown in FIG. 29(A), the signal 2813 and the signal 2 814 is at H level and signal 2815 is at L level. The first transistor 2703 and the fourth transistor 2704 are turned off, and the first transistor 270 1 is turned on. At this time, the second terminal of the first transistor 2701 becomes the source terminal. The potential of the node 2721 (potential 2821) is the potential of the fifth wiring 2715 and the potential of the first transistor. Since it is the sum of the absolute value of the threshold voltage of the transistor 2701, it becomes V2+|Vth2701| Therefore, the second transistor 2702 is turned on, and the potential of the sixth wiring 2716 becomes the third The potential of the wiring 2713 is equal to V1. The flip-flop keeps the second transistor 2702 on and outputs a high level to the sixth wiring 27 Output from 16.

[0228] During the period B in FIG. 28 and the selection period shown in FIG. 29(B), the signal 2813 is at L level. The signal 2814 remains at the H level, and the signal 2815 becomes the H level. The third transistor 2703 and the fourth transistor 2704 remain off, and the first The transistor 2701 is turned off. At this time, the second terminal of the second transistor 2702 becomes the source terminal, and the potential of the sixth wiring 2716 starts to decrease. (potential 2821) is when the node 2721 is in a floating state (hereinafter also referred to as a floating state). Therefore, the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702 is The potential of the sixth wiring 2716 is simultaneously decreased by the capacitive coupling of the amount (bootstrap operation). Therefore, the voltage Vgs between the gate and source of the second transistor 2702 is − |Vth2702|-α (Vth2702: threshold voltage of the second transistor 2702) , α: any positive number), and the potential of the sixth wiring 2716 becomes L level (V2). Thus, during the selection period, the flip-flop sets the potential of node 2721 to V2-|Vth2 702|-α, an L level can be output from the sixth wiring 2716. Cut.

[0229] During the period C in FIG. 28 and the first non-selection period shown in FIG. 29(C), the signal 2813 is at the H level. Then, the signal 2814 becomes L level, and the signal 2815 remains H level. As a result, the third transistor 2703 and the fourth transistor 2704 are turned on, and the first The transistor 2701 remains off. The node 2721 and the sixth wiring 2716 , and the second line through the third transistor 2703 and the fourth transistor 2704, respectively. The potential of the line 2712 is supplied, so that the line 2712 goes to H level.

[0230] During the period D in FIG. 28 and the second non-selection period shown in FIG. 29(D), the signal 2813 is at the H level. The signal 2814 goes high and the signal 2815 remains high. Therefore, the third transistor 2703 and the fourth transistor 2704 are turned off. Therefore, the first transistor 2701 remains off. The sixth wiring 2716 remains at H level.

[0231] During the period E in FIG. 28 and the third non-selection period shown in FIG. 29(E), the signal 2813 is at the L level. , the signal 2814 remains at the H level, and the signal 2815 remains at the H level. Therefore, the first transistor 2701, the third transistor 2703 and the fourth transistor Therefore, the node 2721 and the sixth wire 27 16 maintains H level.

[0232] From the above, the flip-flop of FIG. 27 includes the third transistor 2703 and the fourth transistor The transistor 2704 is turned on only during the first non-selection period, so the third transistor 2 The deterioration of the characteristics (shift of threshold voltage) of the second transistor 703 and the fourth transistor 2704 is suppressed. Note that the flip-flop in FIG. 27 includes a first transistor 2701 and a The second transistor 2702 is turned on only during the set period, and the second transistor 2702 is turned on only during the set period and the selection period. This causes the characteristics of the first transistor 2701 and the second transistor 2702 to deteriorate. can also be suppressed.

[0233] Furthermore, the flip-flop of FIG. 27 operates in the first non-selection period. Since V1 is supplied to the sixth wiring 2721 and the sixth wiring 2716, the flip-flop malfunctions. This is because, during the non-selection period, the Between the node 2721 and the sixth wiring 2716, V1 is supplied. This is because the potential of the sixth wiring 2716 can be stably maintained at V1.

[0234] The flip-flop of FIG. 27 includes a first transistor 2701, a second transistor 2702, the third transistor 2703 and the fourth transistor 2704 are all P-channel. Therefore, the flip-flop shown in FIG. The ROP can simplify the manufacturing process, reduce manufacturing costs and improve yields. In addition, polysilicon or single crystal silicon can be used as the semiconductor layer of the transistor. The manufacturing process can be simplified even if the above method is used.

[0235] Here, the first transistor 2701, the second transistor 2702, the third transistor The functions of the first transistor 2703 and the fourth transistor 2704 will be described. The capacitor 2701 has a function of selecting the timing of supplying a potential to the first wiring 2711. The second transistor 2702 functions as an input transistor. The timing for supplying the third potential to the sixth wiring 2716 is selected, and the potential of the node 2721 is It has a function to reduce the voltage by bootstrap operation, and a bootstrap transistor The third transistor 2703 functions as a potential of the second wiring 2712. 721 and functions as a switching transistor. The fourth transistor 2704 transfers the potential of the second wiring 2712 to the sixth wiring 271 6 and functions as a switching transistor.

[0236] If the operation is the same as that of FIG. 27, the arrangement and number of transistors may be the same as that of FIG. As can be seen from FIG. 29, which explains the operation of the flip-flop of FIG. 27, In this embodiment, a set period, a selection period, a first non-selection period, a second non-selection period, and During the non-selection periods of 3, conduction is maintained as shown by the solid lines in FIGS. 29(A) to 29(E). Therefore, the transistors and the like are arranged and operated so as to satisfy this requirement. For example, transistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches , various logic circuits, etc. may be newly arranged.

[0237] For example, as shown in FIG. 30, the gate terminal of the second transistor 2701 shown in FIG. A capacitance element 3001 may be disposed between the first terminal and the second terminal. This allows the bootstrap operation during the selection period to be performed more stably. , the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702 can be reduced. Therefore, each transistor can be switched at high speed. 1 uses a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and a gate electrode layer and a layer doped with impurities may be used as the conductive layer. Alternatively, an interlayer film (insulating film) may be used as an insulating layer and a conductive layer may be used as a conductive layer. A wiring layer and a transparent electrode layer may be used. Note that the same configuration as in FIG. 27 is the same. The symbols are used and the explanation is omitted.

[0238] The capacitor 3001 corresponds to the capacitor 401 in FIG.

[0239] The flip-flop in FIG. 31 can also perform the same operation as in FIG. 27. As shown in FIG. 27, the first transistor 2701 is diode-connected. The first transistor 2701 may be diode-connected. The line 2711 becomes unnecessary, and the number of wires and the power supply (V2) can be reduced by one. 27. The same reference numerals are used for the components common to those in FIG. 27, and the description thereof will be omitted.

[0240] In addition, the flip-flop shown in this embodiment mode may be applied to the shift registers shown in FIGS. As in the first to fourth embodiments, a three-phase clock signal can be used. In addition, the shift register of this embodiment can reduce power consumption. The third wiring 613, the fourth wiring 614, and the fifth wiring 615 are connected to the clock signal lines. The number of stages of flip-flops 601 is reduced to 2 / 3 compared to when a single-phase clock signal is used. Therefore, the load on each clock signal line can be reduced. and the potential supplied to the second wiring 612, the third wiring 613, the fourth wiring 614, and the fifth wiring 615. The signal input to the first wiring 615 and the sixth wiring 616 and the signal output to the wiring 622 are The flip-flops configured with N-channel transistors are shown in Figs. 6 and 8, respectively. Compared to when applied to a soft register, the H level and L level are inverted.

[0241] The shift register shown in this embodiment may be used in conjunction with the display devices shown in FIGS. As in the first to fourth embodiments, the present invention can be applied to a device that is formed integrally with a pixel portion. By applying this embodiment to the scanning line driving circuit, the life of the display device can be extended. This can be done.

[0242] Note that the shift registers and flip-flops shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be freely combined with the configuration of the display device shown in the embodiment. The shift register and flip-flop configurations shown in the embodiment can be freely combined and implemented. It is possible.

[0243] (Embodiment 6) In this embodiment, a P-channel transistor having a different configuration from that of the fifth embodiment is used. The flip-flop is shown in FIG. 32. The same as in the fifth embodiment is The components are shown using reference numerals, and detailed descriptions of the same components or components having similar functions are omitted.

[0244] The flip-flop shown in FIG. 32 includes a first transistor 2701, a second transistor 2702, and a 702, a third transistor 2703, a fourth transistor 2704 and a fifth transistor The flip-flop has a first wiring 2711 and a second wiring 2712. 712, the third wiring 2713, the fourth wiring 2714, the fifth wiring 2715, the sixth wiring 2 716 and the seventh wiring 3217. In this embodiment, the fifth transformer The resistor 3205 is a P-channel transistor, and the absolute value of the voltage between its gate and source is When the voltage (|Vgs|) exceeds the threshold voltage (|Vth|) (when Vgs falls below Vth When the seventh wiring 3217 is turned on, the seventh wiring 3217 is turned on. The seventh wiring 3217 is called the third signal line. That's fine.

[0245] The fifth transistor 3205 corresponds to the fifth transistor 1305 in FIG. 13. The seventh wiring 3217 corresponds to the seventh wiring 1317 in FIG.

[0246] The first terminal (one of the source terminal and the drain terminal) of the first transistor 2701 is The second terminal (the other of the source terminal and the drain terminal) is connected to the wiring 2711. The gate terminal is connected to the fifth wiring 2715. A first terminal of the third transistor 2703 is connected to a second wiring 2712. The terminal is connected to the gate terminal of the second transistor 2702, and the gate terminal is connected to the fourth wiring 2 The first terminal of the second transistor 2702 is connected to the third wiring 2713. The second terminal of the fourth transistor 27 is connected to the sixth wiring 2716. The first terminal of 04 is connected to the second wiring 2712, and the second terminal is connected to the sixth wiring 2716. The gate terminal of the fifth transistor 3205 is connected to the fourth wiring 2714. The first terminal of the second wiring 2712 is connected to the sixth wiring 2716. The gate terminal is connected to the seventh wiring 3217.

[0247] The first terminal of the third transistor 2703 and the first terminal of the fourth transistor 2704 and the first terminal of the fifth transistor 3205 is connected to the second wiring 2712. The third transistor 2703 may be connected to different wirings. The gate terminal of the fourth transistor 2704 is connected to a fourth wiring 2714. The wiring is not limited to being connected to the same wiring, and may be connected to separate wirings.

[0248] Next, regarding the operation of the flip-flop shown in Figure 32, the timing chart of Figure 33 is 33 is a diagram showing the flip-flop of FIG. 32 in relation to the flip-flop of FIG. 27. This is a timing chart for when the flop operates in the same way as the flop shown in FIG. The same parts as in the flow chart are designated by the same reference numerals and will not be described further.

[0249] A signal is input to the seventh wiring 3217. The signal input to the seventh wiring 3217 is the third clock signal. The potential of the signal is V1 (hereinafter referred to as the H level), and the potential of the L signal is V2 (hereinafter referred to as the L level). It is a digital signal.

[0250] However, it is not limited to the seventh wiring 3217 being input with the third clock signal. Other signals may be input, or a constant potential or current may be input.

[0251] In FIG. 33, a signal 3317 is a signal input to the seventh wiring 3217 .

[0252] In the flip-flop of FIG. 32, the fifth transistor is The sixth wiring 2716 is connected to the fifth transistor 3205. The potential of the second wiring 2712 is supplied via 205, so that the H level is maintained.

[0253] From the above, the flip-flop of FIG. 32 has a first non-selection period, a second non-selection period, During the first and second non-selection periods of the third non-selection period, the sixth wiring Since V1 is supplied to 2716, malfunction of the flip-flop can be further suppressed. This is because, during the non-selection period, the first non-selection period and the second non-selection period are V1 is supplied to the sixth wiring 2716 during this period, and the potential of the sixth wiring 2716 is stabilized. This is because the voltage V can be maintained at V1.

[0254] Furthermore, the flip-flop of FIG. 32 has a fifth transistor 3205 for the set period and Since the fifth transistor 3205 is turned on only during the non-selection period of the second transistor, the deterioration of the characteristics of the fifth transistor 3205 is suppressed. It is possible.

[0255] The flip-flop of FIG. 32 includes a first transistor 2701, a second transistor 2702, a third transistor 2703, a fourth transistor 2704 and a fifth transistor The transistors 3205 are all P-channel transistors. Therefore, the flip-flop of FIG. 32 can simplify the manufacturing process and reduce manufacturing costs. In addition, the semiconductor layer of the transistor can be formed by The manufacturing process can be simplified even when polysilicon or single crystal silicon is used.

[0256] Here, the function of the fifth transistor 3205 will be described. 05 selects the timing for supplying the potential of the second wiring 2712 to the sixth wiring 276. It has a function of functioning as a switching transistor.

[0257] If the operation is the same as that of FIG. 32, the arrangement and number of transistors may be the same as that of FIG. Therefore, it is not limited to transistors, other elements (resistive elements, capacitive elements, etc.), diodes, Diodes, switches, various logic circuits, etc. may be newly placed.

[0258] For example, as shown in FIG. 34, the gate terminal of the second transistor 2702 shown in FIG. A capacitor 3401 may be disposed between the first terminal and the second terminal. This allows the bootstrap operation during the selection period to be performed more stably. , the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702 can be reduced. Therefore, each transistor can be switched at high speed. 1 uses a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and a gate electrode layer and a layer doped with impurities may be used as the conductive layer. Alternatively, an interlayer film (insulating film) may be used as an insulating layer and a conductive layer may be used as a conductive layer. A wiring layer and a transparent electrode layer may be used. Note that the same configuration as in FIG. The symbols are used and the explanation is omitted.

[0259] The capacitor 3401 corresponds to the capacitor 1501 in FIG.

[0260] The flip-flop in FIG. 35 can perform the same operation as in FIG. 32. As shown in FIG. 32, the first transistor 2701 is diode-connected. The first transistor 2701 is diode-connected, 2711 is no longer necessary, and the number of wires and power supply (V2) can be reduced by one. The same reference numerals are used for the components common to those in FIG. 32, and the description thereof will be omitted.

[0261] The flip-flop shown in this embodiment may be applied to the shift registers shown in FIGS. As in the first to fifth embodiments, a three-phase clock signal can be used. Furthermore, the shift register of this embodiment can realize power saving. The clock signal lines (third wiring 613, fourth wiring 614, fifth wiring 615) are connected to the The number of stages of the flip-flop 1701 is 2 / 1 of that when a single-phase clock signal is used. 3, the load on each clock signal line can be reduced. The potential supplied to the third wiring 613 and the fourth wiring 614 is , a signal input to the fifth wiring 615 and the sixth wiring 616, and a signal output to the wiring 622 The signals are fed to flip-flops configured with N-channel transistors as shown in Figs. 17 and 18. Compared to when applied to the shift register in Figure 18, the H and L levels are inverted. .

[0262] The shift register shown in this embodiment may be used in conjunction with the display devices shown in FIGS. As in the first to fifth embodiments, the present invention can be applied to a device that is formed integrally with a pixel portion. By applying this embodiment to the scanning line driving circuit, the life of the display device can be extended. This can be done.

[0263] Note that the shift registers and flip-flops shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be freely combined with the configuration of the display device shown in the embodiment. The shift register and flip-flop configurations shown in the embodiment can be freely combined and implemented. It is possible.

[0264] (Embodiment 7) In this embodiment, a flip-flop having a different configuration from those in the fifth and sixth embodiments is used. 36. Note that the same elements as those in the fifth and sixth embodiments are designated by the same reference numerals. and detailed description of the same parts or parts having similar functions will be omitted.

[0265] The flip-flop shown in FIG. 36 includes a first transistor 2701, a second transistor 2702, and a 702, a third transistor 2703, a fourth transistor 2704, a fifth transistor a sixth transistor 3605, a seventh transistor 3606, an eighth transistor The flip-flop has a ninth transistor 3608 and a ninth transistor 3609. The first wiring 2711, the second wiring 2712, the third wiring 2713, and the fourth wiring 271 4, the fifth wiring 2715, the sixth wiring 2716 and the seventh wiring 3217. In this embodiment, the sixth transistor 3606, the seventh transistor 3607, The eighth transistor 3608 and the ninth transistor 3609 are P-channel transistors. The absolute value of the voltage between the gate and source (|Vgs|) is the threshold voltage (|Vth |) (when Vgs falls below Vth), the transistor is in a conductive state.

[0266] The first terminal (one of the source terminal and the drain terminal) of the first transistor 2701 is The second terminal (the other of the source terminal and the drain terminal) is connected to the wiring 2711. The gate terminal is connected to the fifth wiring 2715. A first terminal of the third transistor 2703 is connected to a second wiring 2712. The terminal is connected to the gate terminal of the second transistor 2702, and the gate terminal is connected to the fourth wiring 2 The first terminal of the second transistor 2702 is connected to the third wiring 2713. The second terminal of the fourth transistor 27 is connected to the sixth wiring 2716. The first terminal of 04 is connected to the second wiring 2712, and the second terminal is connected to the sixth wiring 2716. The gate terminal of the fifth transistor 3205 is connected to the fourth wiring 2714. The first terminal of the second wiring 2712 is connected to the sixth wiring 2716. The gate terminal of the sixth transistor 3606 is connected to the seventh wiring 3217. The first terminal is connected to the second wiring 2712, and the second terminal is connected to the gate of the eighth transistor 3208. The gate terminal is connected to the gate terminal of the second transistor 2701. The first terminal of the seventh transistor 3607 is connected to the first wiring 2711, and the second terminal The terminal is connected to the gate terminal of the eighth transistor 3608, and the gate terminal is connected to the first wiring 27. 11. The first terminal of the eighth transistor 3608 is connected to the third wiring 2713. The first terminal is connected to the gate terminal of the ninth transistor 3609. The first terminal of the transistor 3609 is connected to the second wiring 2712, and the second terminal of the transistor 3609 is connected to the sixth wiring 2713. The second terminal of the sixth transistor 3606 and the seventh The connection point between the second terminal of the transistor 3607 and the gate terminal of the eighth transistor 3608 The second terminal of the eighth transistor 3608 and the second terminal of the ninth transistor 3609 are connected to a node 3622. The connection point of the gate terminal of the transistor 3609 is a node 3623 .

[0267] The first terminal of the third transistor 2703 and the first terminal of the fourth transistor 2704 , the first terminal of the fifth transistor 3205, the first terminal of the sixth transistor 3606, and It is not limited that the first terminal of the ninth transistor 3609 is connected to the second wiring 2712. The gate of the third transistor 2703 may be connected to a separate wiring. The gate terminal of the fourth transistor 2704 and the gate terminal of the fourth transistor 2704 are connected to a fourth wiring 2714. The first transistor 2 may be connected to a different wiring. 701, the first terminal of the seventh transistor 3607, and the seventh transistor 36 The gate terminal of 07 is not limited to being connected to the first wiring 2711, but may be connected to a separate wiring. The first terminal of the second transistor 2702 and the eighth transistor 2703 may be connected to each other. The first terminal of the resistor 3608 is not limited to being connected to the third wiring 2713, but may be connected to a separate The wiring may be connected to the

[0268] Next, regarding the operation of the flip-flop shown in Figure 36, the timing chart of Figure 37 is 37 is a diagram showing the flip-flop of FIG. 36 shown in FIG. 27 and FIG. 32. This is a timing chart for when the flip-flop operates in the same way as the flip-flop shown in Figure 2. 8 and the timing chart of FIG. 33 are designated by the same reference numerals and the explanation thereof is omitted. do.

[0269] In FIG. 37, potential 3722 is the potential of node 3622 in FIG. 36, and potential 3723 is This is the potential of node 3623 in FIG.

[0270] In the flip-flop of FIG. 36, during the third non-selection period, the ninth transistor 360 9 is turned on. Then, the sixth wiring 2716 is connected to the Since the potential of the second wiring 2712 is supplied, the H level is maintained.

[0271] The on / off control of the ninth transistor 3609 will be specifically described. The seventh transistor 3606 and the seventh transistor 3607 constitute an inverter. When an L level is input to the gate terminal of the transistor 3606, the potential of the node 3622 (potential 3722) is approximately V1. However, the potential 3722 at this time is the sixth The resistance ratio of the first transistor 3606 to the seventh transistor 3607 is , the value is slightly lower than V1. When a signal is input, the potential of the node 3622 becomes equal to the potential of the first wiring 2711 and the potential of the seventh transistor. Since it is the sum of the absolute value of the threshold voltage of the resistor 3607, it becomes V2+|Vth3607|. Therefore, in the first non-selection period, the second non-selection period, and the third non-selection period, The node 2721 is at the H level and the node 3622 is at the L level, so that the eighth transistor Therefore, the ninth transistor 3609 is connected to the third wiring 2713. Since it is controlled by the input signal, it is turned on during the third non-selection period, and the first It is turned off during the non-selection period and the second non-selection period. In this case, the node 2721 is at L level and the node 3622 is at H level, so the eighth transistor The ninth transistor 3608 is turned off. The potential is maintained at the potential of the first non-selection period, which is the period before the set period, that is, the H level. Therefore, the ninth transistor 3609 is turned off.

[0272] From the above, the flip-flop of FIG. 36 has the first non-selection period, the second non-selection period, and During the third and fourth non-selection periods, V1 is supplied to the sixth wiring 2716, and thus the flip-flop This further suppresses malfunction of the drop. This is because V1 can be supplied to the wiring 2716. In the non-selection period, V1 is supplied to the sixth wiring 2716, and therefore, the sixth wiring 27 16 noise can be reduced.

[0273] Furthermore, the flip-flop of FIG. 36 includes a sixth transistor 3606, a seventh transistor The deterioration of the characteristics of the eighth transistor 3607, the eighth transistor 3608 and the ninth transistor 3609 is The sixth transistor 3606 can be suppressed because it is The seventh transistor 3607 is turned on only during the selection period. During the non-selection period of 1, the potential of the node 3622 decreases to V2+|Vth3607|. The eighth transistor 3608 is turned on only during the first non-selection period. During the second and third non-selection periods, the potential of the node 3623 is V2+δ(δ: This is because it is turned on only during the period when the voltage decreases to |Vth3607| + |Vth3608|. In addition, the ninth transistor 3609 is turned on only during the third non-selection period. .

[0274] The flip-flop of FIG. 36 includes a first transistor 2701, a second transistor 2702, a third transistor 2703, a fourth transistor 2704, a fifth transistor 3205, a sixth transistor 3606, a seventh transistor 3607, an eighth transistor The first transistor 3608 and the ninth transistor 3609 are all P-channel transistors. Therefore, the flip-flop of FIG. The semiconductor layer of the capacitor can be made of polysilicon or single crystal silicon, which simplifies the manufacturing process. It is possible.

[0275] Here, the sixth transistor 3606, the seventh transistor 3607, the eighth transistor The functions of the sixth transistor 3608 and the ninth transistor 3609 will be described. The timing at which the potential of the second wiring 2712 is supplied to the node 3622 is selected by the controller 3606. The seventh transistor 360 functions as a switching transistor. 7 has a function of selecting the timing for supplying the potential of the first wiring 2711 to the node 3622. The eighth transistor 3608 has a third wiring 271 and functions as a diode. The switching transistor 3621 has a function of selecting the timing at which the potential of the switching transistor 3621 is supplied to the node 3623. The ninth transistor 3609 functions as a transistor. The switching transistor has a function of selecting the timing at which the signal is supplied to the sixth wiring 2716. It functions as a register.

[0276] If the same operation as in FIG. 36 is performed, the arrangement and number of transistors may be the same as in FIG. Therefore, it is not limited to transistors, other elements (resistive elements, capacitive elements, etc.), diodes, Diodes, switches, various logic circuits, etc. may be newly placed.

[0277] For example, as shown in FIG. 38, the gate terminal of the second transistor 2702 shown in FIG. A capacitor 3801 may be disposed between the first terminal and the second terminal. This allows the bootstrap operation during the selection period to be performed more stably. , the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702 can be reduced. Therefore, each transistor can be switched at high speed. 1 uses a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and a gate electrode layer and a layer doped with impurities may be used as the conductive layer. Alternatively, an interlayer film (insulating film) may be used as an insulating layer and a conductive layer may be used as a conductive layer. A wiring layer and a transparent electrode layer may be used. Note that the same configuration as in FIG. The symbols are used and the explanation is omitted.

[0278] The flip-flop in FIG. 39 can perform the same operation as in FIG. 36. As shown in FIG. 36, the first transistor 2701 may be diode-connected. The first transistor 2701 is diode-connected, and thus the first wiring 271 Since the current flowing through the first wiring 2711 is small, the width of the first wiring 2711 can be reduced. Note that the same reference numerals are used for the components common to those in FIG. 36, and the description thereof will be omitted.

[0279] The flip-flop shown in this embodiment may be applied to the shift registers shown in FIGS. As in the first to sixth embodiments, a three-phase clock signal can be used. Furthermore, the shift register of this embodiment can realize power saving. The clock signal lines (third wiring 613, fourth wiring 614, fifth wiring 615) are connected to the The number of stages of flip-flops 1701 used is 2 / 3 of that when a single-phase clock signal is used. Therefore, the load on each clock signal line can be reduced. and the potential supplied to the second wiring 612, the third wiring 613, the fourth wiring 614, and the fifth wiring 615. The signal input to the first wiring 615 and the sixth wiring 616 and the signal output to the wiring 622 are The flip-flops configured with N-channel transistors are shown in Figs. 17 and 18, respectively. Compared to the case where this is applied to the shift register of FIG. 1, the H level and L level are inverted.

[0280] The shift register shown in this embodiment may be used in conjunction with the display devices shown in FIGS. As in the first to sixth embodiments, the present invention can be applied to a device that is formed integrally with a pixel portion. By applying this embodiment to the scanning line driving circuit, the life of the display device can be extended. This can be done.

[0281] Note that the shift registers and flip-flops shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be freely combined with the configuration of the display device shown in the embodiment. The shift register and flip-flop configurations shown in the embodiment can be freely combined and implemented. It is possible.

[0282] (Embodiment 8) In this embodiment, a function block having a configuration different from that of the fifth, sixth, and seventh embodiments is used. The flip-flop is shown in FIG. 40. Note that, as in the fifth, sixth and seventh embodiments, The same parts or parts with similar functions are shown using the same symbols. A detailed explanation will be omitted.

[0283] The flip-flop shown in FIG. 40 includes a first transistor 2701, a second transistor 2702, and a 702, a third transistor 2703, a fourth transistor 2704, a fifth transistor a sixth transistor 3605, a seventh transistor 3606, an eighth transistor the ninth transistor 3608, the ninth transistor 3609, the tenth transistor 4010, the eleventh The first transistor 4011 and the twelfth transistor 4012 are included. The flop has a first wiring 2711, a second wiring 2712, a third wiring 2713, a fourth wiring 2714, and a Connected to the wiring 2714, the fifth wiring 2715, the sixth wiring 2716 and the seventh wiring 3217 In this embodiment, the tenth transistor 4010 and the eleventh transistor The first transistor 4011 and the twelfth transistor 4012 are P-channel transistors. When the absolute value of the voltage between the gate and source (|Vgs|) exceeds the threshold voltage (|Vth|), When Vgs falls below Vth, the transistor is brought into a conductive state.

[0284] The first terminal (one of the source terminal and the drain terminal) of the first transistor 2701 is The second terminal (the other of the source terminal and the drain terminal) is connected to the wiring 2711. The gate terminal is connected to the fifth wiring 2715. A first terminal of the third transistor 2703 is connected to a second wiring 2712. The terminal is connected to the gate terminal of the second transistor 2702, and the gate terminal is connected to the fourth wiring 2 The first terminal of the second transistor 2702 is connected to the third wiring 2713. The second terminal of the fourth transistor 27 is connected to the sixth wiring 2716. The first terminal of 04 is connected to the second wiring 2712, and the second terminal is connected to the sixth wiring 2716. The gate terminal of the fifth transistor 3205 is connected to the fourth wiring 2714. The first terminal of the second wiring 2712 is connected to the sixth wiring 2716. The gate terminal of the sixth transistor 3606 is connected to the seventh wiring 3217. The first terminal is connected to the second wiring 2712, and the second terminal is connected to the gate of the eighth transistor 3608. The gate terminal of the eleventh transistor 4011 is connected to the second The gate terminal of the seventh transistor 3607 is connected to the gate terminal of the seventh transistor 3607. The first terminal is connected to the first wiring 2711, and the second terminal is connected to the gate of the eighth transistor 3608. The gate terminal of the eleventh transistor 4011 is connected to the first The first terminal of the eighth transistor 3608 is connected to the third wiring 2711. 713, and the second terminal is connected to the gate terminal of the ninth transistor 3609 and the tenth transistor The first terminal of the ninth transistor 3609 is connected to the gate terminal of the ninth transistor 3609. The terminal is connected to the second wire 2712, and the second terminal is connected to the sixth wire 2716. The first terminal of the tenth transistor 4010 is connected to the second wiring 2712, and the second terminal is connected to the gate terminal of the second transistor 2702. The first terminal of the 12th transistor 4 is connected to the seventh wiring 3217. The first terminal of the twelfth transistor 4012 is connected to the gate terminal of the second transistor 4012. The first terminal is connected to the wiring 2712 of the second transistor 2702, and the second terminal is connected to the gate terminal of the second transistor 2702. The second terminal of the eleventh transistor 4011 and the second terminal of the twelfth transistor The connection point of the gate terminal of 4012 is set as node 4024 .

[0285] The second terminal of the third transistor 2703 and the second terminal of the fourth transistor 2704 , the second terminal of the fifth transistor 3205, the second terminal of the sixth transistor 3606, the second terminal of the ninth transistor 3609, the second terminal of the tenth transistor 4010, and It is not limited to the fact that the second terminal of the transistor 4012 is connected to the second wiring 2712. The gate of the third transistor 2703 may be connected to a separate wiring. The gate terminal of the fourth transistor 2704 and the gate terminal of the fourth transistor 2704 are connected to a fourth wiring 2714. The first transistor 2 may be connected to a different wiring. 701, the first terminal of the seventh transistor 3607, and the seventh transistor 36 The gate terminal of 07 is not limited to being connected to the first wiring 2711, but may be connected to a separate wiring. The first terminal of the second transistor 2702 and the eighth transistor 2703 may be connected to each other. The first terminal of the resistor 3608 is not limited to being connected to the third wiring 2713, but may be connected to a separate The gate terminal of the fifth transistor 3205 and It is not limited to the fact that the first terminal of the 11th transistor 4011 is connected to the seventh wiring 3217. may be connected to separate wirings.

[0286] Next, regarding the operation of the flip-flop shown in Figure 40, the timing chart of Figure 41 is 41 shows the flip-flop of FIG. 40 in the same manner as in FIGS. 27, 32 and 36. 1 is a timing chart for the case where the flip-flop operates in the same manner as the flip-flop shown in FIG. 28, the same parts as those in the timing charts of Fig. 33 and Fig. 37 are explained using the same symbols. The details are omitted.

[0287] In FIG. 41, potential 4124 is the potential at node 4024 in FIG.

[0288] In the flip-flop of FIG. 40, the tenth transistor 401 0 is turned on. Then, the node 2721 is connected to the 10th transistor 4010 via the 10th transistor 4011. Since the potential of the wiring 2712 of No. 2 is supplied, the H level can be maintained more stably. In the flip-flop of FIG. 40, the twelfth transistor 401 2 is turned on. Then, the node 2721 is connected to the 12th transistor 4012 via the 13th transistor 4013. Since the potential of the wiring 2712 is supplied, the H level can be maintained more stably.

[0289] Specifically, the on / off control of the twelfth transistor 4012 will be described. The on / off control of the transistor 4010 is the same as that of the ninth transistor described in Embodiment 7. This is the same as the on / off control of the flip-flop 3609. Similarly, the sixth transistor 3606 and the seventh transistor 3607 constitute an inverter. Therefore, in the first non-selection period, the second non-selection period, and the third non-selection period, The node 2721 is at H level and the node 3622 is at L level, so the 11th transaction Therefore, the twelfth transistor 4012 is connected to the seventh wiring 3. 217, it is turned on during the second non-selection period, and the first On the other hand, the signal is turned off during the set period and the selection period. During this time, the node 2721 is at the L level and the node 3622 is at the H level. The transistor 4011 is turned off. The potential of the element is maintained at the potential of the first non-selection period, which is the period before the set period, that is, the H level. Therefore, the twelfth transistor 4012 is turned off.

[0290] From the above, the flip-flop of FIG. 40 has a first non-selection period, a second non-selection period, and During the third non-selection period, V1 is supplied to the sixth wiring 2716 and the node 2721. Therefore, malfunction of the flip-flop can be further suppressed. Between them, V1 can be supplied to the sixth wiring 2716 and the node 2721. In addition, the flip-flop in FIG. 40 has the sixth wiring 2716 and Since V1 is supplied to the sixth wiring 2716 and the node 2721, This can reduce noise.

[0291] Furthermore, the flip-flop of FIG. 40 includes a tenth transistor 4010, an eleventh transistor Therefore, deterioration of the characteristics of the first transistor 4011 and the twelfth transistor 4012 can be suppressed. This is because the tenth transistor 4010 is turned on only during the third non-selection period. The eleventh transistor 4011 is turned on during the first non-selection period, the second non-selection period, and the During the non-selection period of 3, the potential of the node 4024 is V2+ε(ε:|Vth3607|+|V This is because the voltage is turned on only during the period when the voltage decreases to th4011|. This is because the resistor 4012 is turned on only during the second non-selection period.

[0292] The flip-flop of FIG. 40 includes a first transistor 2701, a second transistor 2702, a third transistor 2703, a fourth transistor 2704, a fifth transistor 3205, a sixth transistor 3606, a seventh transistor 3607, an eighth transistor transistor 3608, ninth transistor 3609, tenth transistor 4010, first The first transistor 4011 and the twelfth transistor 4012 are all P-channel transistors. Therefore, the flip-flop of FIG. Even if polysilicon or single crystal silicon is used as the semiconductor layer of the transistor, the manufacturing process is simplified. It is possible to simplify the process.

[0293] Here, the tenth transistor 4010, the eleventh transistor 4011, and the twelfth transistor The function of the tenth transistor 4010 will be described. The potential of the wiring 2712 is supplied to the node 2721. The eleventh transistor 4011 functions as a node The 12th transistor has the function of supplying power to the 4024 and functions as a switching transistor. The transistor 4012 has a function of supplying the potential of the second wiring 2712 to the node 2721. , which functions as a switching transistor.

[0294] If the same operation as in FIG. 40 is performed, the arrangement and number of transistors may be the same as in FIG. 23 Therefore, it is not limited to transistors, other elements (resistive elements, capacitive elements, etc.), diodes, Diodes, switches, various logic circuits, etc. may be newly placed.

[0295] For example, as shown in FIG. 42, the gate terminal of the second transistor 2702 shown in FIG. A capacitor 4201 may be disposed between the first terminal and the second terminal. This allows the bootstrap operation during the selection period to be performed more stably. , the parasitic capacitance between the gate terminal and the second terminal of the second transistor 2702 can be reduced. Therefore, each transistor can be switched at high speed. 1 uses a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as conductive layers. Alternatively, a gate insulating film may be used as the insulating layer, and a gate electrode layer and a layer doped with impurities may be used as the conductive layer. Alternatively, an interlayer film (insulating film) may be used as an insulating layer and a conductive layer may be used as a conductive layer. A wiring layer and a transparent electrode layer may be used. Note that the same configuration as in FIG. The symbols are used and the explanation is omitted.

[0296] The flip-flop in FIG. 43 can also perform the same operation as in FIG. 40. As shown in FIG. 40, the first transistor 2701 may be diode-connected. The first transistor 2701 is diode-connected, and thus the first wiring 271 Since the current flowing through the first wiring 2711 is reduced, the width of the first wiring 2711 is reduced.

[0297] The flip-flop shown in this embodiment may be applied to the shift registers shown in FIGS. As in the first to seventh embodiments, a three-phase clock signal can be used. Furthermore, the shift register of this embodiment can realize power saving. The clock signal lines (third wiring 613, fourth wiring 614, fifth wiring 615) are connected to the The number of stages of the flip-flop 1701 is 2 / 1 of that when a single-phase clock signal is used. 3, the load on each clock signal line can be reduced. The potential supplied to the third wiring 613 and the fourth wiring 614 is , a signal input to the fifth wiring 615 and the sixth wiring 616, and a signal output to the wiring 622 The signals are fed to flip-flops configured with N-channel transistors as shown in Figs. 17 and 18. Compared to when applied to the shift register in Figure 18, the H and L levels are inverted. .

[0298] The shift register shown in this embodiment may be used in conjunction with the display devices shown in FIGS. As in the first to seventh embodiments, the present invention can be applied to a device that is formed integrally with a pixel portion. By applying this embodiment to the scanning line driving circuit, the life of the display device can be extended. This can be done.

[0299] Note that the shift registers and flip-flops shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be freely combined with the configuration of the display device shown in the embodiment. The shift register and flip-flop configurations shown in the embodiment can be freely combined and implemented. It is possible.

[0300] (Embodiment 9) In this embodiment, an example of a pixel included in the display device described in any of Embodiments 1 to 8 will be described. This will be described with reference to FIG.

[0301] The pixel configuration of FIG. 46 will be described. The pixel shown in FIG. 46(A) includes a transistor 4601 , a capacitor 4602, and a display element 4621. The display element 4621 is connected to the second wiring 4612 and the third wiring 4613. As shown in FIG. 46(B), the electric field between the pixel electrode 4623 and the counter electrode 4622 The case where a liquid crystal element 4631 whose light transmittance changes depending on the liquid crystal element will be described. The wiring 4611 may be called a signal line. The second wiring 4612 may be called a scan line. The third wiring 4613 may also be called a storage capacitor line.

[0302] Although the transistor 4601 is an N-channel transistor, it may be a P-channel transistor. In the first to fourth embodiments, the transistor It is preferable to use an N-channel transistor as 4601. Since amorphous silicon can be used as the semiconductor layer of the transistor, the manufacturing process This is because it is possible to simplify the manufacturing process, reduce manufacturing costs, and improve yields. Furthermore, it is possible to manufacture semiconductor devices such as large display panels. In addition, polysilicon or single crystal silicon can also be used as the semiconductor layer of the transistor. In the fifth to eighth embodiments, the manufacturing process can be simplified. It is desirable to use a P-channel transistor as the transistor 4601 because: This allows for the simplification of the manufacturing process, reducing manufacturing costs and improving yields. Because it is possible.

[0303] The first wiring 4611 is a signal wiring shown in the display devices of FIGS. The second wiring 4612 corresponds to any one of the lines S1 to Sm. 44. The scanning lines G1 to Gn correspond to any one of the scanning lines G1 to Gn shown in the display device of FIG.

[0304] Although the third wiring 4613 is not shown in FIGS. 9, 11, 12, and 44, As already mentioned, it is advisable to add to Figures 9, 11, 12 and 44 as necessary.

[0305] The capacitor 4602 serves to hold the potential of the pixel electrode 4623 of the display element 4621. Therefore, the capacitor 4602 is connected between the pixel electrode 4623 and the third wiring 4613. However, it is not limited to this. It is sufficient that the second wiring 4612 is arranged in a different row (for example, in the previous row) and is connected to the second wiring 4612 of the pixel. Alternatively, it may be connected to the counter electrode 4622 or an electrode corresponding to the counter electrode 4622. In addition, if the display element 4621 has a capacitance, the capacitor 4602 and the third The line 4613 is not necessarily required.

[0306] As an operation method, the first wiring 4611 is selected to turn on the transistor 4601. Then, a video signal is input from the first wiring 4611 to the pixel electrode 4623 and the capacitor element 4602. Then, the display element 4621 has a transmittance according to the video signal.

[0307] Here, a driving method that can improve the image quality of a display device will be described. As a driving method that can realize this, there are overdrive driving methods and a method that controls the common line (storage capacitance line). This section explains the driving method, backlight scanning, high frequency driving method, etc. The methods of operation can be freely combined.

[0308] First, the overdrive operation will be described with reference to FIG. 47. FIG. 47(A) shows the table The graph shows the time change in output luminance with respect to the input voltage of the display element. The time change in the output brightness of the display element with respect to voltage 1 is similar to output brightness 1, which is also shown by the dashed line. In other words, the voltage to obtain the desired output brightness Low is Vi, but the input voltage is If Vi is input as is, the device response time will be longer until the desired output brightness Low is reached. It takes time to match the speed.

[0309] Overdrive is a technology to speed up this response speed. By applying a voltage Vo greater than Vi to the element for a certain period of time, the response speed of the element can be increased. After the target output brightness is reached, the input voltage is returned to Vi. The input voltage is shown in Input Voltage 2 and the output brightness is shown in Output Brightness 2. The graph below shows that the time it takes to reach the target brightness Low is shorter than the graph for Output Brightness 1. are.

[0310] In addition, in FIG. 47(A), when the output luminance changes positively with respect to the input voltage, As mentioned above, the present invention also includes the case where the output luminance changes negatively with respect to the input voltage.

[0311] For a circuit for realizing such driving, see Figures 47(B) and 47(C). First, referring to FIG. 47(B), the input video signal Gi is an analog value (discrete value In the case where the output video signal Go is a signal that takes an analog value, The overdrive circuit shown in FIG. 47(B) includes an encoding circuit 4701, a frame It includes a frame memory 4702, a correction circuit 4703, and a DA conversion circuit 4704.

[0312] The input video signal Gi is first input to the encoding circuit 4701 and encoded. The analog signal is converted into a digital signal with the appropriate number of bits. The digital signal is input to a frame memory 4702 and a correction circuit 4703. The correction circuit 4703 receives the video signal of the previous frame stored in the frame memory 4702. The correction circuit 4703 then calculates the video signal of the frame and The image signal of the previous frame is corrected according to a pre-prepared numerical table. At this time, an output switching signal is input to the correction circuit 4703, and the corrected video signal is output. The video signal of the frame may be switched between the video signal of the selected frame and the video signal of the frame. The corrected video signal or the video signal of the frame is input to a DA conversion circuit 4704. Then, the value is analyzed according to the corrected video signal or the video signal of the frame. The output video signal Go, which is a log signal, is output. can be achieved.

[0313] Next, referring to FIG. 47(C), the input video signal Gi is a signal having a digital value, and the output The case where the output video signal Go is also a signal that takes a digital value will be described. The overdrive circuit includes a frame memory 4712 and a correction circuit 4713 .

[0314] The input video signal Gi is a digital signal. First, a frame memory 4712 and a correction circuit The correction circuit 4713 receives the signal from the frame memory 4712. The video signal of the previous frame that has been held is also input at the same time. In this case, a pre-prepared signal is generated from the video signal of the frame in question and the video signal of the previous frame. The correction circuit 47 outputs a corrected video signal according to the numerical value table. An output switching signal is input to 13 to switch between the corrected video signal and the video signal of the frame. In this way, overdrive driving can be realized.

[0315] The combination of the numerical table to obtain the corrected video signal is taken in 1SF. The number of possible gradations is the product of the number of gradations possible in 2SF. The smaller the value, the smaller the amount of data stored in the correction circuit 4713, which is preferable. In the embodiment, the subframe displaying the bright image is displayed in halftones up to the maximum brightness. In this case, the brightness of the dark image is 0, and the subframe displaying the bright image is at its highest brightness. Since the brightness of the bright image is constant from the first gray level to the highest gray level, the number of combinations can be significantly reduced. It can be made as small as

[0316] In the overdrive circuit of the present invention, the input video signal Gi is an analog signal. This also includes the case where the output video signal Go is a digital signal. In this case, as shown in FIG. The DA conversion circuit 4704 can be omitted from the circuit. The live circuit has an input video signal Gi as a digital signal and an output video signal Go as an analog signal. In this case, the circuit shown in FIG. 47B is replaced with the encoding circuit 4701. can be omitted.

[0317] Next, the driving for manipulating the potential of the common line will be described with reference to FIG. 48. ) is a scanning line in a display device that uses a display element with a capacitive property such as a liquid crystal element. 10 is a diagram showing a plurality of pixel circuits when one common line is arranged for each pixel circuit. The pixel circuit shown in FIG. 48A includes a transistor 4801, an auxiliary capacitor 4802, a display element 4803, and a 803, video signal lines 4804, scanning lines 4805, and common lines 4806.

[0318] The transistor 4801, the auxiliary capacitor 4802, the display element 4803, the video signal line 480 4, the scanning line 4805, and the common line 4806 are connected to the transistor 460 shown in FIG. 1, a capacitor element 4602, a display element 4621, a first wiring 4611, a second wiring 4612, This corresponds to the third wiring 4613 .

[0319] The gate terminal of the transistor 4801 is electrically connected to the scanning line 4805. Either the source terminal or the drain terminal of the capacitor 4801 is electrically connected to the video signal line 4804. The other of the source terminal and the drain terminal of the transistor 4801 is connected to the auxiliary capacitor 48 4802 and one terminal of the display element 4803. In addition, the other terminal of the auxiliary capacitor 4802 is electrically connected to a common line 4806 .

[0320] First, the pixel selected by the scan line 4805 has the transistor 4801 turned on. Therefore, the display element 4803 and the auxiliary capacitor 4802 are connected via the video signal line 4804. At this time, the video signal is applied to the common line 4806. If the minimum gray level is displayed for all connected pixels, or if the common line 4 If the maximum gray level is displayed for all pixels connected to 806, There is no need to write video signals via the video signal line 4804. Instead of writing a video signal through 4, the potential of the common line 4806 is changed to display The voltage across element 4803 can be varied.

[0321] Next, FIG. 48(B) shows a display device using a display element having a capacitive property such as a liquid crystal element. In a device, when two common lines are arranged for one scanning line, The pixel circuit shown in FIG. 48B includes a transistor 4811, an auxiliary capacitor 4 812, a display element 4813, a video signal line 4814, a scanning line 4815, and a first common line 48 16, and a second common line 4817.

[0322] The gate terminal of the transistor 4811 is electrically connected to the scan line 4815. Either the source terminal or the drain terminal of the capacitor 4811 is electrically connected to the video signal line 4814. The other of the source terminal and the drain terminal of the transistor 4811 is connected to the auxiliary capacitor 48 12 and one terminal of the display element 4813. The other terminal of the auxiliary capacitor 4812 is electrically connected to a first common line 4816. In addition, in the pixel adjacent to the pixel, the other terminal of the auxiliary capacitance 4812 is connected to the second The common line 4817 is electrically connected to the common line 4817.

[0323] The pixel circuit shown in FIG. 48(B) has a small number of pixels electrically connected to one common line. Therefore, instead of writing the video signal through the video signal line 4814, the first common line 48 By changing the potential of the common line 4816 or the second common line 4817, the voltage applied to the display element 4813 is The frequency with which the voltage can be changed is significantly increased. Inversion driving is possible. Source inversion driving or dot inversion driving improves the reliability of the device. This can reduce flicker.

[0324] Next, the scanning backlight will be described with reference to Fig. 49. Fig. 49(A) shows a cold shade. 49(A) is a diagram showing a scanning backlight in which electrode tubes are arranged side by side. The light includes a diffusion plate 4901 and N cold cathode fluorescent lamps 4902-1 to 4902-N. N cold cathode fluorescent lamps 4902-1 to 4902-N are arranged in parallel behind the diffuser plate 4901. The N cold cathode fluorescent lamps 4902-1 to 4902-N are scanned by changing their brightness. It is possible.

[0325] The change in brightness of each cold cathode tube during scanning will be explained using FIG. The brightness of the cold cathode tube 4902-1 is changed for a certain period of time. The brightness of the cold cathode fluorescent lamp 4902-2 placed next to the cold cathode fluorescent lamp 4902-1 is changed for the same period of time. As shown in Figure 4, the brightness of the cold cathode fluorescent lamps 4902-1 to 4902-N is changed in order. In 9(C), the brightness that is changed for a certain period of time is smaller than the original brightness. The brightness may be greater than that of the cold cathode fluorescent lamp 4902-1 to 4902-N. However, scanning may be performed in the reverse direction from cold cathode tube 4902-N to 4902-1.

[0326] The backlight brightness during the low brightness period is the maximum brightness of the subframe in which the dark image is inserted. Specifically, when a dark image is inserted into 1SF, the 1SF When inserting a dark image into 2SF, the maximum brightness of 2SF is Lmax 2 is preferable.

[0327] In addition, LEDs may be used as the light source of the scanning backlight. The backlight is as shown in Figure 49(B). The scanning backlight shown in Figure 49(B) is It comprises a diffusion plate 4911 and light sources 4912-1 to 4912-N in which LEDs are arranged side by side. When LEDs are used as the light source for a scanning backlight, the backlight can be made thinner and lighter. Another advantage is that the color reproduction range can be expanded. Similarly, the LEDs arranged in parallel with the light sources 4912-1 to 4912-N arranged in parallel with D are Since the backlight can be scanned, it can be a point scanning type backlight. This can further improve the image quality of moving images.

[0328] Next, high frequency driving will be explained with reference to Fig. 50. Fig. 50(A) shows the frame frequency The figure shows the case where a dark image is inserted and driven at a frequency of 60 Hz. 5002 is the dark image of the current frame, 5003 is the bright image of the next frame, 4 is the dark image of the next frame. When driving at 60Hz, the frame rate of the video signal is This has the advantage that it is easy to achieve consistency with the image processing circuit and the image processing circuit does not become complicated.

[0329] FIG. 50(B) shows the result when a dark image is inserted and the display is driven at a frame frequency of 90 Hz. 5011 is the bright image of the frame, 5012 is the dark image of the frame, and 5013 is the is a bright image of the first image created from the current frame, the next frame, and the frame after that, 5014 is a dark image of the first image created from the current frame, the next frame, and the frame after that, 5015 is the bright image of the second image created from the current frame, the next frame, and the frame after that, 5016 is the dark image of the second image created from the current frame, the next frame, and the frame after that. When driving at 0 Hz, the operating frequency of the peripheral drive circuit does not need to be increased significantly, and the efficiency is improved. This has the advantage of effectively improving the image quality of moving images.

[0330] Figure 50(C) shows the results when a dark image is inserted and the frame frequency is 120 Hz. 5021 is a bright image of the frame, 5022 is a dark image of the frame, and 502 3 is a bright image of the image created from the current frame and the next frame, and 5024 is a bright image of the current frame and the next frame. 5025 is the dark image of the image created from the frame, 5026 is the bright image of the next frame, 502 is a dark image of the frame, 5027 is a bright image of the image created from the next frame and the frame after that, 502 8 is a dark image of the image created from the next frame and the frame after that. It is driven at 120Hz. In this case, the image quality of moving images is significantly improved, and there is an advantage that there is almost no afterimage. be.

[0331] 51 to 55 show top views and cross-sectional views of the pixel shown in FIG. , the LCD operating mode is different.

[0332] First, Figure 51 shows the pixel structure of a liquid crystal display device, which is called the TN type, and which has a thin film transistor. FIG. 51(A) is a cross-sectional view and a top view of a pixel in which a TFT (thin film transistor) is combined. 51(A) is a cross-sectional view of the pixel, and FIG. 51(B) is a top view of the pixel. The cross-sectional view of the pixel corresponds to the line a-a' in the top view of the pixel shown in FIG. 51(B). By applying the present invention to a liquid crystal display device having the pixel structure shown in FIG. A display device can be manufactured.

[0333] The pixel structure of a TN liquid crystal display device will be described with reference to FIG. A display device has a key component called a liquid crystal panel, which displays images. Two substrates with this process are bonded together with a gap of a few micrometers, and liquid crystal is placed between the two substrates. In FIG. 51(A), the two substrates are a first substrate 5 The first substrate is a substrate 101, and the second substrate 5116. The first substrate is a substrate on which TFTs and pixel electrodes are formed. The second substrate is provided with a light-shielding film 5114, a color filter 5115, a fourth conductive film 5116, and a second conductive film 5118. A layer 5113, a spacer 5117, and a second alignment film 5112 may be fabricated.

[0334] It should be noted that the present invention can be implemented without forming a TFT on the first substrate 5101. When the present invention is carried out without fabricating a substrate, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0335] The TFT shown in FIG. 51 is a bottom gate type TFT using an amorphous semiconductor. However, the present invention is not limited to this. The structure of the TFT that can be used is a bottom gate type TFT. There are etch type, channel protection type, etc. Also, top gate type is also possible. Furthermore, amorphous Not only semiconductors but also polycrystalline semiconductors can be used.

[0336] It should be noted that the present invention can be implemented without forming the light-shielding film 5114 on the second substrate 5116. When the present invention is implemented without forming the light-shielding film 5114, the number of steps is reduced, and the manufacturing cost is reduced. In addition, the simple structure improves the yield. On the other hand, when the light-shielding film 5114 is fabricated and the present invention is implemented, light leakage occurs during black display. Therefore, a display device with less noise can be obtained.

[0337] The present invention can be implemented without forming the color filter 5115 on the second substrate 5116. It is possible. When the present invention is carried out without fabricating the color filter 5115, the number of steps is Since the number of electrodes is reduced, the manufacturing cost can be reduced. On the other hand, the color filter 5115 is manufactured to embody the present invention. When this is applied, a display device capable of displaying in color can be obtained.

[0338] In the present invention, the spacers 5117 are not formed on the second substrate 5116, but spherical spacers are formed on the second substrate 5116. The present invention can also be carried out by scattering spherical spacers. In this case, the number of steps is reduced, which reduces the manufacturing cost. On the other hand, the spacer 5117 is formed to When performing the lighting, the position of the spacer does not vary, so the distance between the two substrates is kept uniform. This makes it possible to obtain a display device with little display unevenness.

[0339] Next, a description will be given of processing performed on the first substrate 5101. The first substrate 5101 has a light-transmitting property. A substrate having a thickness of 100 nm or less is suitable, and may be, for example, a quartz substrate, a glass substrate or a plastic substrate. The first substrate 5101 may be a light-shielding substrate, such as a semiconductor substrate or an SOI (Silicon On Insulator) substrate. A GaN-on-Insulator (GaN on Insulator) substrate may also be used.

[0340] First, a first insulating film 5102 may be formed on a first substrate 5101. 02 is silicon oxide film, silicon nitride film, silicon oxynitride film (SiOxNy), etc. Alternatively, the insulating film may be a laminated film that combines at least two of these films. When the present invention is implemented by forming the first insulating film 5102, Prevents impurities from the substrate from affecting the semiconductor layer and changing the properties of the TFT. Therefore, a highly reliable display device can be obtained. When the present invention is implemented without forming the film of O2, the number of steps is reduced, thereby reducing the manufacturing cost. Furthermore, since the structure is simple, the yield can be improved.

[0341] Next, a first conductive layer 5103 is formed on the first substrate 5101 or the first insulating film 5102. The first conductive layer 5103 may be formed by processing its shape. The process is preferably as follows: First, the first conductive layer 5103 is formed on the entire surface. At this time, a film forming apparatus such as a sputtering apparatus or a CVD apparatus may be used. Next, a photosensitive resist material is formed on the entire surface of the first conductive layer 5103. Next, the desired shape is formed by photolithography or laser direct drawing. The resist material is then exposed to light. One of the resist materials is removed by etching to form a first conductive layer. A mask for shaping the layer 5103 can be obtained. Following the pattern, the first conductive layer 5103 is removed by etching to form a desired pattern. The first conductive layer 5103 can be shaped like a circle. There are two types of etching methods: chemical (wet etching) and physical (dry etching). However, the material of the first conductive layer 5103 and the material under the first conductive layer 5103 may be The material to be used for the first conductive layer 5103 is selected appropriately taking into consideration the properties of the material in the layer. Suitable materials are Mo, Ti, Al, Nd, Cr, etc. Alternatively, a laminated structure of these materials may be used. Furthermore, the first conductive layer 51 may be formed of these alloys in a single layer or a laminate structure. It may be formed as 03.

[0342] Next, a second insulating film 5104 is formed. At this time, a sputtering device or a CVD device is used. Any film forming apparatus may be used. The material used for the second insulating film 5104 is a thermal oxide film. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is suitable. The second semiconductor layer 5105 may have a laminated structure. It is particularly preferable that the insulating film 5104 is a silicon oxide film. This is because the trap level at the interface with the semiconductor layer 5105 is reduced when the film is made of silicon. When the first conductive layer 5103 is formed of Mo, the first conductive layer 5103 is in contact with the Mo layer. The second insulating film 5104 in the portion is preferably a silicon nitride film. This is because it does not oxidize o.

[0343] Next, a first semiconductor layer 5105 is formed. Then, a second semiconductor layer 5106 is formed in succession. It is preferable to form the first semiconductor layer 5105 and the second semiconductor layer 5106. The shape may be processed by the above-mentioned photolithography. The material used for the first semiconductor layer 5105 is Silicon or silicon germanium (SiGe) is suitable. The material used for the conductor layer 5106 is preferably silicon containing phosphorus or the like.

[0344] Next, a second conductive layer 5107 is formed. At this time, a sputtering method or a printing method is used. It is preferable that the material used for the second conductive layer 5107 is transparent. It may be reflective. If it is transparent, it may be made of, for example, indium oxide with tin oxide. Indium tin oxide (ITO) film mixed with silicon dioxide, indium tin oxide (ITO) Indium tin silicon oxide (ITSO) film mixed with zinc oxide, indium oxide mixed with zinc oxide Indium zinc oxide (IZO), zinc oxide, or tin oxide can be used. IZO is a type of ITO mixed with 2 to 20 wt% zinc oxide (ZnO). It is a transparent conductive material formed by sputtering using a target. When present, Ti, Mo, Ta, Cr, W, Al, etc. can be used. Two-layer structure of Ti, Mo, Ta, Cr, W and Al laminated together, and Al is laminated to Ti, Mo, Ta, Cr Alternatively, the second conductive layer 5107 may have a three-layer structure sandwiched between metals such as W. The shape may be formed by processing the shape. The method for processing the shape may be the above-mentioned photolithography method or the like. The etching method is preferably dry etching. Dry etching is preferably performed by ECR (Electron Cyclotron Radiation) resonance) and ICP (Inductive Coupled Plasma) This may be done by any dry etching equipment using a high density plasma source.

[0345] Next, the channel region of the TFT is formed. At this time, the second conductive layer 5107 is used as a mask. The second semiconductor layer 5106 may be etched using the mask. Since the number of the conductive second electrodes can be reduced, the manufacturing cost can be reduced. By etching the semiconductor layer 5106, the removed portion becomes the channel region of the TFT. It should be noted that the first semiconductor layer 5105 and the second semiconductor layer 5106 are not formed continuously, but are formed in a layer structure such that After the formation of the first semiconductor layer 5105, a stopper and a A film made of SiO 2 may be formed and patterned, and then the second semiconductor layer 5106 may be formed. In this way, the channel of the TFT can be formed without using the second conductive layer 5107 as a mask. This has the advantage of increasing the degree of freedom in layout patterns. In addition, when etching the second semiconductor layer 5106, the first semiconductor layer 5105 is also etched. This ensures that the TFT channel area is completely covered without causing etching defects. This has the advantage that

[0346] Next, a third insulating film 5108 is formed. The third insulating film 5108 has transparency. It is preferable that the material used for the third insulating film 5108 is an inorganic material (silicon oxide). silicon nitride, silicon oxynitride, etc.) or organic compound materials with low dielectric constant (photosensitive or non-photosensitive organic resin materials) are suitable. Also, materials containing siloxane are used. Siloxane has a skeleton structure made up of bonds between silicon (Si) and oxygen (O). The material is an organic group containing at least hydrogen as a substituent (e.g., alkyl group, aromatic carbon, etc.). A fluoro group may be used as a substituent. Alternatively, the following may be used as a substituent: An organic group containing at least hydrogen and a fluoro group may be used. It may have a laminated structure. The third insulating film 5108 may be formed by processing its shape. The method for processing the shape is preferably the above-mentioned photolithography method or the like. At this time, the second insulating film 5104 is also etched at the same time, so that the third insulating film 5108 In addition, a contact hole with the first conductive layer 5103 can be formed. It is preferable that the surface of the third insulating film 5108 is as flat as possible. This is because the alignment of the liquid crystal molecules is affected by the unevenness of the surface that the liquid crystal comes into contact with.

[0347] Next, a third conductive layer 5109 is formed. At this time, a sputtering method or a printing method is used. The material used for the third conductive layer 5109 is preferably the same as that used for the second conductive layer 5107. Similarly, the third conductive layer 510 may be transparent or reflective. The material that can be used for the third conductive layer 9 may be the same as that for the second conductive layer 5107. The second conductive layer 51 may be formed by processing the shape. It can be the same as 07.

[0348] Next, a first alignment film 5110 is formed. The alignment film 5110 is made of a polymer such as polyimide. After the first alignment film 5110 is formed, the alignment of the liquid crystal molecules can be controlled. To achieve this, rubbing may be performed by rubbing the alignment film with a cloth. This is the process of making lines on the alignment film. By rubbing, alignment is given to the alignment film. You can have it.

[0349] The first substrate 5101, the light-shielding film 5114, and the color filter 511 are then combined. 5. A fourth conductive layer 5113, a spacer 5117, and a second alignment film 5112 were fabricated. The second substrate 5116 is attached with a sealant with a gap of several μm. A liquid crystal panel can be fabricated by injecting liquid crystal material between the substrates. In such a TN type liquid crystal panel, the fourth conductive layer 5113 is It may be formed on the entire surface.

[0350] Next, we will explain the characteristics of the pixel structure of a TN liquid crystal panel shown in Figure 51. The liquid crystal molecule 5118 shown in (A) is a long and thin molecule with a long axis and a short axis. In order to indicate the direction of 118, it is expressed by its length in FIG. That is, the long axis of the liquid crystal molecule 5118 is parallel to the paper surface, and the short axis is parallel to the paper surface. The orientation of the long axis of the liquid crystal molecule 5118 is closer to the normal direction of the paper. In other words, the liquid crystal molecules 5118 shown in FIG. 51(A) are close to the first substrate 5101. The direction of the long axis of the first substrate 5116 is different by 90 degrees from that of the second substrate 5116. The liquid crystal molecule 5118 located between them has its long axis oriented in such a way that it smoothly connects them. That is, the liquid crystal molecules 5118 shown in FIG. The liquid crystal molecules are oriented in a state where they are twisted by 90 degrees between the first substrate 5116 and the second substrate 5116.

[0351] Next, referring to FIG. 51(B), the image quality when the present invention is applied to a TN type liquid crystal display device will be described. An example of the layout of the pixel of a TN type liquid crystal display device to which the present invention is applied will be described. The element includes a scanning line 5121, a video signal line 5122, a capacitance line 5123, and a TFT 5124. , a pixel electrode 5125 and a pixel capacitor 5126 .

[0352] The scanning line 5121 is electrically connected to the gate terminal of the TFT 5124, and therefore, the first conductive Preferably, it is made up of layer 5103.

[0353] The video signal line 5122 is electrically connected to the source terminal or the drain terminal of the TFT 5124. Therefore, it is preferable that the scanning line 51 is made of the second conductive layer 5107. 21 and the video signal lines 5122 are arranged in a matrix, so that at least the It is preferably formed from a conductive layer.

[0354] The capacitance line 5123 is arranged in parallel with the pixel electrode 5125 to form a pixel capacitance 5126. It is preferable that the wiring is made of the first conductive layer 5103. As shown in FIG. 51(B), the capacitance line 5123 is connected to the video signal line 5122. The video signal line 5122 may be extended to surround the video signal line 5122. The phenomenon where the potential of the electrode that should maintain the potential changes as the potential of the electrode changes. It is possible to reduce crosstalk. Therefore, as shown in FIG. 51(B), the first semiconductor layer 5105 is connected to the capacitance line 5123 and the video signal line. It may also be installed in the intersection area of ​​Route 5122.

[0355] The TFT 5124 acts as a switch that connects the video signal line 5122 and the pixel electrode 5125. As shown in FIG. 51(B), the source region or drain region of the TFT5124 The source and drain regions may be arranged to surround each other. This allows for a large channel width in a small area, improving switching As shown in Figure 51(B), the gate of the TFT5124 The port terminal may be disposed so as to surround the first semiconductor layer 5105 .

[0356] The pixel electrode 5125 is electrically connected to either the source terminal or the drain terminal of the TFT 5124. The pixel electrode 5125 is connected to the liquid crystal panel 5121. It is an electrode for supplying a voltage to the liquid crystal element. In addition, a capacitance line 5123 and a pixel capacitance 5126 are formed. This may serve to hold the signal voltage transmitted by the video signal line 5122. As shown in FIG. 51(B), the pixel electrode 5125 can have a rectangular shape. By doing so, the aperture ratio of the pixel can be increased, so that the liquid crystal display In addition, when the pixel electrode 5125 is made of a transparent material, A transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has excellent color reproducibility. In addition, the pixel electrode 5125 can be formed as a reflective When the display device is made of a material having such a property, a reflective liquid crystal display device can be obtained. LCD displays have high visibility in bright environments such as outdoors, and are suitable for applications where backlighting is not required. Since the pixel electrode 5125 is made of a transparent material, the power consumption can be reduced. When made using both a material with a transparent property and a material with a reflective property, the advantages of both can be combined. A semi-transmissive liquid crystal display device having the pixel electrode 5125 can be obtained. If the pixel electrode 5125 is made of a material having a rough surface, the surface of the pixel electrode 5125 may be roughened. This has the advantage that the reflected light is diffused, reducing the angle dependency of the intensity distribution of the reflected light. In other words, it is possible to obtain a reflective liquid crystal display device that has a constant brightness regardless of the viewing angle. This can be done.

[0357] Next, referring to Figure 52, the liquid crystal display in VA (Vertical Alignment) mode The case where the present invention is applied to a display device will be described. The pixel structure uses protrusions for alignment control, which allows the liquid crystal molecules to be oriented in various directions. This allows for a wider viewing angle, known as MVA (Multi-domain Vertic The cross-sectional view and top view of a pixel when the present invention is applied to the LC alignment method are shown in Fig. FIG. 52(A) is a cross-sectional view of a pixel, and FIG. 52(B) is a top view of the pixel. In addition, the cross-sectional view of the pixel shown in FIG. 52(A) is a cross-sectional view of the pixel shown in FIG. 52(B). The present invention can be applied to a liquid crystal display device having a pixel structure shown in FIG. Thus, a liquid crystal display device having a wide viewing angle, a fast response speed, and a high contrast can be obtained. It is possible.

[0358] The pixel structure of an MVA liquid crystal display device will be described with reference to Figure 52(A). A display device has a key component called a liquid crystal panel that displays images. Two processed substrates are bonded together with a gap of several micrometers, and liquid is placed between the two substrates. In FIG. 52(A), the two substrates are a first substrate and a second substrate. The first substrate is a substrate 5201, and the second substrate is a substrate 5216. The first substrate is provided with TFTs and pixel electrodes. The second substrate is provided with a light-shielding film 5214, a color filter 5215, a fourth conductive film 5216, and a second conductive film 5217. The electrode layer 5213, the spacer 5217, the second alignment film 5212, and the alignment control protrusion 521 9 may be made.

[0359] It should be noted that the present invention can be implemented without forming a TFT on the first substrate 5201. When the present invention is carried out without fabricating a substrate, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0360] The TFT shown in FIG. 52 is a bottom gate type TFT using an amorphous semiconductor. However, the present invention is not limited to this. The structure of the TFT that can be used is a bottom gate type TFT. There are etch type, channel protection type, etc. Also, top gate type is also possible. Furthermore, amorphous Not only semiconductors but also polycrystalline semiconductors can be used.

[0361] It should be noted that the present invention can be implemented without forming the light-shielding film 5214 on the second substrate 5216. When the present invention is implemented without forming the light-shielding film 5214, the number of steps is reduced, and the manufacturing cost is reduced. In addition, the simple structure improves the yield. On the other hand, when the light-shielding film 5214 is fabricated and the present invention is implemented, light leakage occurs during black display. Therefore, a display device with less noise can be obtained.

[0362] The present invention can be implemented without forming the color filter 5215 on the second substrate 5216. It is possible to carry out the present invention without fabricating the color filter 5215. Since the number of electrodes is reduced, the manufacturing cost can be reduced. On the other hand, the color filter 5215 is manufactured to embody the present invention. When this is applied, a display device capable of displaying in color can be obtained.

[0363] In the present invention, the spacers 5217 are not formed on the second substrate 5216, but spherical spacers are formed. The present invention can also be carried out by scattering spherical spacers. In this case, the number of steps is reduced, which reduces the manufacturing cost. On the other hand, the spacer 5217 is formed to When performing the lighting, the position of the spacer does not vary, so the distance between the two substrates is kept uniform. This makes it possible to obtain a display device with little display unevenness.

[0364] Next, the first substrate 5201 may be processed using the method described in FIG. Here, a first substrate 5201, a first insulating film 5202, a first conductive layer 5 203, a second insulating film 5204, a first semiconductor layer 5205, a second semiconductor layer 5206, The second conductive layer 5207, the third insulating film 5208, the third conductive layer 5209, the first alignment film 52 10 respectively correspond to the first substrate 5101, the first insulating film 5102, and the first A conductive layer 5103, a second insulating film 5104, a first semiconductor layer 5105, a second semiconductor layer 51 06, a second conductive layer 5107, a third insulating film 5108, a third conductive layer 5109, a first wiring Although not shown, the alignment control protrusions are also provided on the first substrate side. By doing so, the alignment of the liquid crystal molecules can be controlled more reliably. The first alignment film 5210 and the second alignment film 5212 may be vertical alignment films. This allows the liquid crystal molecules 5218 to be aligned vertically.

[0365] The first substrate 5201, the light-shielding film 5214, and the color filter 521 are then combined. 5. A fourth conductive layer 5213, a spacer 5217, and a second alignment film 5212 were fabricated. The second substrate 5216 is attached with a sealant with a gap of several μm. A liquid crystal panel can be fabricated by injecting liquid crystal material between the substrates. In such an MVA type liquid crystal panel, the fourth conductive layer 5213 is connected to the second substrate 5216. Alternatively, the alignment control protrusion may be formed on the entire surface of the fourth conductive layer 5213. The shape of the alignment control protrusion 5219 is not limited, but a smooth surface is preferable. It is preferable that the shape has a slightly curved surface. Since the orientation of the second alignment film 5212 is very close to that of the first alignment film 5212, the alignment defects are reduced. The alignment control protrusion 5219 may cause a step cut, resulting in a defect in the alignment film. can be reduced.

[0366] Next, we will explain the characteristics of the pixel structure of the MVA liquid crystal panel shown in Figure 52. The liquid crystal molecule 5218 shown in Fig. 2(A) is a long and thin molecule with a long axis and a short axis. In order to indicate the direction of the element 5218, the element 5218 is expressed by its length in FIG. That is, the liquid crystal molecules 5218 are depicted with their long axes parallel to the paper surface. The shorter the liquid crystal molecule 5218, the closer its long axis is to the normal direction of the paper. In other words, the liquid crystal molecules 5218 shown in FIG. 52A are aligned such that the direction of their long axes is Therefore, the part where the alignment control protrusion 5219 is located is oriented so as to face the normal direction of the film. The liquid crystal molecules 5218 are aligned radially around the alignment control protrusion 5219. By adopting this state, a liquid crystal display device with a wide viewing angle can be obtained.

[0367] Next, referring to FIG. 52(B), the following will explain the case where the present invention is applied to an MVA type liquid crystal display device. An example of a pixel layout will now be described. The pixel in the position is composed of a scanning line 5221, a video signal line 5222, a capacitance line 5223, and a TFT 52. 24, a pixel electrode 5225, a pixel capacitor 5226, and an alignment control protrusion 5219. It may be possible.

[0368] The scanning line 5221 is electrically connected to the gate terminal of the TFT 5224, and therefore, the first conductive Preferably, it is made up of layer 5203.

[0369] The video signal line 5222 is electrically connected to the source terminal or the drain terminal of the TFT 5224. Therefore, it is preferable that the scanning line 52 is made of the second conductive layer 5207. 21 and the video signal lines 5222 are arranged in a matrix, so that at least the It is preferably formed from a conductive layer.

[0370] The capacitance line 5223 is arranged in parallel with the pixel electrode 5225 to form a pixel capacitance 5226. It is preferable that the wiring is made of the first conductive layer 5203. As shown in FIG. 52(B), the capacitance line 5223 is connected to the video signal line 5222. The signal line 5222 may be extended to surround the signal line 5222. The phenomenon where the potential of the electrode that should maintain the potential changes as the potential of the electrode changes. It is possible to reduce crosstalk. 52(B), the first semiconductor layer 5205 is connected to a capacitor line 5223 and a video signal line. It may also be installed in the intersection area of ​​Route 5222.

[0371] The TFT 5224 serves as a switch for connecting the video signal line 5222 and the pixel electrode 5225. As shown in FIG. 52(B), the source region or drain region of the TFT5224 The source and drain regions may be arranged to surround each other. This allows for a large channel width in a small area, improving switching As shown in FIG. 52(B), the gate of the TFT5224 The port terminal may be disposed so as to surround the first semiconductor layer 5205 .

[0372] The pixel electrode 5225 is electrically connected to either the source terminal or the drain terminal of the TFT 5224. The pixel electrode 5225 is connected to the liquid crystal panel 5221. It is an electrode for supplying a signal to the liquid crystal element. In addition, a capacitance line 5223 and a pixel capacitance 5226 are formed. This may serve to hold the signal voltage transmitted by the video signal line 5222. As shown in FIG. 52(B), the pixel electrode 5225 can have a rectangular shape. By doing so, the aperture ratio of the pixel can be increased, so that the liquid crystal display In addition, when the pixel electrode 5225 is made of a transparent material, A transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has excellent color reproducibility. In addition, the pixel electrode 5225 can be formed as a reflective When the display device is made of a material having such a property, a reflective liquid crystal display device can be obtained. LCD displays have high visibility in bright environments such as outdoors, and are suitable for applications where backlighting is not required. Since the pixel electrode 5225 is made of a transparent material, the power consumption can be reduced. When made using both a material with a transparent property and a material with a reflective property, the advantages of both can be combined. A semi-transmissive liquid crystal display device having the pixel electrode 5225 can be obtained. When the pixel electrode 5225 is made of a material having a rough surface, the surface of the pixel electrode 5225 may be made uneven. This has the advantage that the reflected light is diffused, reducing the angle dependency of the intensity distribution of the reflected light. In other words, it is possible to obtain a reflective liquid crystal display device that has a constant brightness regardless of the viewing angle. This can be done.

[0373] Next, referring to Figure 53, the liquid crystal display in VA (Vertical Alignment) mode Another example of the application of the present invention to a display device will be described. In the pixel structure of the display device, the fourth conductive layer 5313 is patterned to form a liquid crystal layer. This is called PVA (Paper Backlighting) which controls the orientation of the object to increase the viewing angle. When the present invention is applied to the NEMA Vertical Alignment method, 53(A) is a cross-sectional view of a pixel, and FIG. 53(B) is a top view of a pixel. 53(A) is a top view of the pixel shown in FIG. 53(B). This corresponds to the line a-a' in the top view of the liquid crystal display device having the pixel structure shown in FIG. By applying the present invention, a wide viewing angle, a fast response speed, and a high contrast can be achieved. Therefore, a liquid crystal display device can be obtained.

[0374] The pixel structure of a PVA liquid crystal display device will be described with reference to Figure 53(A). A display device has a key component called a liquid crystal panel that displays images. Two processed substrates are bonded together with a gap of several micrometers, and liquid is placed between the two substrates. In FIG. 53(A), the two substrates are a first substrate and a second substrate. The first substrate is a substrate 5301, and the second substrate is a substrate 5316. The first substrate is provided with TFTs and pixel electrodes. The second substrate is provided with a light-shielding film 5314, a color filter 5315, a fourth conductive film 5316, and a second conductive film 5317. An electrode layer 5313, a spacer 5317, and a second alignment film 5312 may be fabricated.

[0375] It should be noted that the present invention can be implemented without forming a TFT on the first substrate 5301. When the present invention is carried out without fabricating a substrate, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0376] The TFT shown in FIG. 53 is a bottom gate type TFT using an amorphous semiconductor. However, the present invention is not limited to this. The structure of the TFT that can be used is a bottom gate type TFT. There are etch type, channel protection type, etc. Also, top gate type is also possible. Furthermore, amorphous Not only semiconductors but also polycrystalline semiconductors can be used.

[0377] It should be noted that the present invention can be implemented without forming the light-shielding film 5314 on the second substrate 5316. When the present invention is implemented without forming the light-shielding film 5314, the number of steps is reduced, and the manufacturing cost is reduced. In addition, the simple structure improves the yield. On the other hand, when the present invention is implemented by forming the light-shielding film 5314, light leakage occurs during black display. Therefore, a display device with less noise can be obtained.

[0378] It should be noted that the present invention can be implemented without forming the color filter 5315 on the second substrate 5316. It is possible to carry out the present invention without fabricating the color filter 5315. Since the number of electrodes is reduced, the manufacturing cost can be reduced. On the other hand, the color filter 5315 is manufactured to embody the present invention. When this is applied, a display device capable of displaying in color can be obtained.

[0379] In the present invention, the spacers 5317 are not formed on the second substrate 5316, but spherical spacers are formed. The present invention can also be carried out by scattering spherical spacers. In this case, the number of steps is reduced, which reduces the manufacturing cost. On the other hand, the spacer 5317 is fabricated to improve the yield. When performing the lighting, the position of the spacer does not vary, so the distance between the two substrates is kept uniform. This makes it possible to obtain a display device with little display unevenness.

[0380] Next, the first substrate 5301 may be processed using the method described in FIG. Here, a first substrate 5301, a first insulating film 5302, a first conductive layer 5 303, a second insulating film 5304, a first semiconductor layer 5305, a second semiconductor layer 5306, The second conductive layer 5307, the third insulating film 5308, the third conductive layer 5309, and the first alignment film 53 10 respectively correspond to the first substrate 5101, the first insulating film 5102, and the first A conductive layer 5103, a second insulating film 5104, a first semiconductor layer 5105, a second semiconductor layer 51 06, a second conductive layer 5107, a third insulating film 5108, a third conductive layer 5109, a first wiring The third conductive layer 5309 on the first substrate 5301 side corresponds to the opposite film 5110. A polar cutout may be provided. This allows for more reliable control of the alignment of the liquid crystal molecules. In addition, the first alignment film 5310 and the second alignment film 5312 are vertical alignment films. This allows the liquid crystal molecules 5318 to be aligned vertically.

[0381] The first substrate 5301, the light-shielding film 5314, and the color filter 531 are formed as described above. 5. A fourth conductive layer 5313, a spacer 5317, and a second alignment film 5312 were fabricated. The second substrate 5316 is attached with a sealant with a gap of several μm. A liquid crystal panel can be fabricated by injecting liquid crystal material between the substrates. In such a PVA type liquid crystal panel, the fourth conductive layer 5313 is patterned. The electrode cutout 5319 may be formed by the above method. Although there is no limitation, a shape that combines multiple rectangles with different orientations is preferable. This allows for the creation of multiple regions with different orientations, resulting in a liquid crystal display with a wide viewing angle. In addition, the boundary between the electrode cutout portion 5319 and the fourth conductive layer 5313 can be obtained. The shape of the fourth conductive layer 5313 in this case is preferably a smooth curve. By doing so, the alignment of the adjacent liquid crystal molecules 5318 becomes very close, and therefore alignment defects are reduced. In addition, the second alignment film 5312 is cut off by the electrode notch 5319. This also reduces defects in the alignment film caused by the liquid crystal display panel being closed.

[0382] Next, we will explain the characteristics of the pixel structure of the PVA liquid crystal panel shown in Figure 53. The liquid crystal molecule 5318 shown in Figure 3(A) is a long and thin molecule with a long axis and a short axis. To indicate the orientation of 5318, it is expressed by its length in FIG. 53(A). That is, the long axis of the liquid crystal molecule 5318 is parallel to the paper surface, and the short axis is parallel to the paper surface. The shorter the liquid crystal molecule 5318, the closer its long axis is to the normal direction of the paper. In other words, the liquid crystal molecules 5318 shown in FIG. 53A are aligned such that the direction of their long axes is the same as that of the alignment film. Therefore, the liquid crystal in the part where the electrode cutout portion 5319 is located is oriented in the normal direction. The molecules 5318 are emitted from the boundary between the electrode cutout 5319 and the fourth conductive layer 5313. By achieving this state, a liquid crystal display device with a wide viewing angle can be obtained. can be done.

[0383] Next, referring to FIG. 53(B), when the present invention is applied to a PVA type liquid crystal display device, An example of a pixel layout will be described. A PVA type liquid crystal display device to which the present invention is applied. The pixel is composed of a scanning line 5321, a video signal line 5322, a capacitance line 5323, and a TFT 532. 4, a pixel electrode 5325, a pixel capacitor 5326, and an electrode notch portion 5319. It's fine.

[0384] The scanning line 5321 is electrically connected to the gate terminal of the TFT 5324, and therefore, the first conductive Preferably, it is made up of layer 5303.

[0385] The video signal line 5322 is electrically connected to the source terminal or the drain terminal of the TFT 5324. Therefore, it is preferable that the scanning line 53 is made of the second conductive layer 5307. 21 and the video signal line 5322 are arranged in a matrix, so that at least the It is preferably formed from a conductive layer.

[0386] The capacitance line 5323 is arranged in parallel with the pixel electrode 5325 to form a pixel capacitance 5326. It is preferable that the wiring is made of the first conductive layer 5303. As shown in FIG. 53(B), the capacitance line 5323 is connected to the video signal line 5322. The signal line 5322 may be extended to surround the signal line 5322. The phenomenon where the potential of the electrode that should maintain the potential changes as the potential of the electrode changes. It is possible to reduce crosstalk. Therefore, as shown in FIG. 53(B), the first semiconductor layer 5305 is connected to the capacitance line 5323 and the image It may be provided in the crossing region of the signal line 5322 .

[0387] The TFT 5324 acts as a switch that connects the video signal line 5322 and the pixel electrode 5325. As shown in FIG. 53(B), the source region or drain region of the TFT5324 The source and drain regions may be arranged to surround each other. This allows for a large channel width in a small area, improving switching As shown in FIG. 53(B), the capacity of the TFT5324 can be increased. The gate terminal may be disposed to surround the first semiconductor layer 5305 .

[0388] The pixel electrode 5325 is electrically connected to either the source terminal or the drain terminal of the TFT 5324. The pixel electrode 5325 is connected to the liquid crystal panel 5321. It is an electrode for supplying a signal to the liquid crystal element. In addition, a capacitance line 5323 and a pixel capacitance 5326 are formed. This may serve to hold the signal voltage transmitted by the video signal line 5322. As shown in FIG. 53(B), the pixel electrode 5325 can have a fourth The electrode cutout 53 is formed to match the shape of the electrode cutout 5319 provided in the conductive layer 5313. It is preferable to form a cutout portion of the pixel electrode 5325 in the portion where the pixel electrode 5325 is not present. By doing so, it is possible to form a plurality of regions in which the liquid crystal molecules 5318 have different orientations. A liquid crystal display device with a wide viewing angle can be obtained. When the liquid crystal display device is made of a material having the above properties, a transmission type liquid crystal display device can be obtained. The display device is capable of displaying images with high color reproducibility and high image quality. When the base electrode 5325 is made of a reflective material, a reflective liquid crystal display device can be obtained. Reflective LCD devices have high visibility in bright environments such as outdoors, In addition, since a backlight is not required, power consumption can be reduced significantly. When the base electrode 5325 is made using both a transparent material and a reflective material, In this case, it is possible to obtain a semi-transmissive liquid crystal display device that combines the advantages of both. When the electrode 5325 is made of a reflective material, the surface of the pixel electrode 5325 is made uneven. By doing so, the reflected light is diffused, so the intensity distribution of the reflected light is angle-dependent. In other words, reflective type has a constant brightness regardless of the angle at which it is viewed. A liquid crystal display device having the above structure can be obtained.

[0389] Next, with reference to FIG. 54, a case where the present invention is applied to a liquid crystal display device of the lateral electric field type will be described. Figure 54 shows a liquid crystal display that switches so that the orientation of the liquid crystal molecules is always horizontal to the substrate. In order to achieve this, in the pixel structure of a liquid crystal display device in which an electric field is applied in the horizontal direction, the pixel electrode 542 A method of applying an electric field in the horizontal direction by applying a comb-like pattern to the 5 and common electrode 5423. The present invention is applied to the so-called IPS (In-Plane-Switching) method. 54(A) is a cross-sectional view of a pixel, and FIG. 54(B) is a top view of a pixel. 54(B) is a top view of the pixel. Also, the cross-sectional view of the pixel shown in FIG. 54(A) is shown in FIG. 54(B). 54) in the top view of the pixel shown in FIG. By applying the present invention to a liquid crystal display device, the viewing angle is in principle large and the response speed is high. A liquid crystal display device with small dependency can be obtained.

[0390] The pixel structure of an IPS liquid crystal display device will be described with reference to Figure 54(A). A display device has a key component called a liquid crystal panel that displays images. Two processed substrates are bonded together with a gap of several micrometers, and liquid is placed between the two substrates. In FIG. 54(A), the two substrates are a first substrate and a second substrate. The first substrate is a substrate 5401, and the second substrate is a substrate 5416. The first substrate is provided with TFTs and pixel electrodes. The second substrate is provided with a light-shielding film 5414, a color filter 5415, a spacer 5417 and a second alignment film 5412 may be fabricated.

[0391] It should be noted that the present invention can be implemented without forming a TFT on the first substrate 5401. When the present invention is carried out without fabricating a substrate, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0392] The TFT shown in FIG. 54 is a bottom gate type TFT using an amorphous semiconductor. However, the present invention is not limited to this. The structure of the TFT that can be used is a bottom gate type TFT. There are etch type, channel protection type, etc. Also, top gate type is also possible. Furthermore, amorphous Not only semiconductors but also polycrystalline semiconductors can be used.

[0393] It should be noted that the present invention can be implemented without forming the light-shielding film 5414 on the second substrate 5416. When the present invention is implemented without forming the light-shielding film 5414, the number of steps is reduced, and the manufacturing cost is reduced. In addition, the simple structure improves the yield. On the other hand, when the light-shielding film 5414 is fabricated and the present invention is implemented, light leakage occurs during black display. Therefore, a display device with less noise can be obtained.

[0394] The present invention can be implemented without forming the color filter 5415 on the second substrate 5416. It is possible to carry out the present invention without fabricating the color filter 5415. Since the number of electrodes is reduced, the manufacturing cost can be reduced. On the other hand, the color filter 5415 is manufactured to embody the present invention. When this is applied, a display device capable of displaying in color can be obtained.

[0395] In the present invention, the spacers 5417 are not formed on the second substrate 5416, but spherical spacers are formed. The present invention can also be carried out by scattering spherical spacers. In this case, the number of steps is reduced, which reduces the manufacturing cost. On the other hand, the spacer 5417 is formed to When performing the lighting, the position of the spacer does not vary, so the distance between the two substrates is kept uniform. This makes it possible to obtain a display device with little display unevenness.

[0396] Next, the first substrate 5401 may be processed using the method described in FIG. Here, a first substrate 5401, a first insulating film 5402, a first conductive layer 5403, and a 403, a second insulating film 5404, a first semiconductor layer 5405, a second semiconductor layer 5406, The second conductive layer 5407, the third insulating film 5408, the third conductive layer 5409, and the first alignment film 54 10 respectively correspond to the first substrate 5101, the first insulating film 5102, and the first A conductive layer 5103, a second insulating film 5104, a first semiconductor layer 5105, a second semiconductor layer 51 06, a second conductive layer 5107, a third insulating film 5108, a third conductive layer 5109, a first wiring The third conductive layer 5409 on the first substrate 5401 side corresponds to the first conductive layer 5110. The two teeth may be formed into a comb-like shape by applying a cutting process to the two teeth. The comb-shaped electrode is electrically connected to either the source terminal or the drain terminal of the TFT5424. The other comb-shaped electrode may be electrically connected to the common electrode 5423. By doing so, a horizontal electric field can be effectively applied to the liquid crystal molecules 5418 .

[0397] The first substrate 5401, the light-shielding film 5414, and the color filter 541 are formed as described above. 5, the spacer 5417, and the second substrate 5416 on which the second alignment film 5412 was formed, The two substrates are bonded together with a gap of a few microns using a sealant, and liquid crystal material is injected between them. Although not shown, a liquid crystal panel can be fabricated by inserting the second substrate 5416 side. By forming a conductive layer on the second substrate 5416 side, This makes it possible to make the device less susceptible to the effects of electromagnetic noise.

[0398] Next, we will explain the characteristics of the pixel structure of an IPS-type liquid crystal panel shown in Figure 54. The liquid crystal molecule 5418 shown in Figure 4(A) is a long and thin molecule with a long axis and a short axis. To indicate the orientation of 5418, it is expressed by its length in FIG. 54(A). That is, the liquid crystal molecule 5418 shown as long has its long axis oriented parallel to the paper surface, and its short axis oriented parallel to the paper surface. The shorter the liquid crystal molecule 5418, the closer its long axis is to the normal direction of the paper. In other words, the liquid crystal molecules 5418 shown in FIG. 54A are always aligned such that their long axes are aligned with the substrate. In Figure 54(A), in the absence of an electric field, When an electric field is applied to the liquid crystal molecules 5418, the direction of their long axes changes to It rotates in a horizontal plane while always maintaining a horizontal orientation to the substrate. This makes it possible to obtain a liquid crystal display device with a wide viewing angle.

[0399] Next, referring to FIG. 54(B), when the present invention is applied to an IPS type liquid crystal display device, An example of a pixel layout will be described. An IPS-type liquid crystal display device to which the present invention is applied. The pixel is composed of a scanning line 5421, a video signal line 5422, a common electrode 5423, and a TFT 54. 24 and a pixel electrode 5425.

[0400] The scanning line 5421 is electrically connected to the gate terminal of the TFT 5424, and therefore, the first conductive Preferably, it is made up of layer 5403.

[0401] The video signal line 5422 is electrically connected to the source terminal or the drain terminal of the TFT 5424. Therefore, it is preferable that the scanning line 54 is made of the second conductive layer 5407. 21 and the video signal line 5422 are arranged in a matrix, so that at least the It is preferable that the image signal line 54 is formed of a conductive layer. 22 is bent in the pixel so as to fit the shape of the pixel electrode 5425 and the common electrode 5423. It may be curved, which increases the aperture ratio of the pixel. Therefore, the efficiency of the liquid crystal display device can be improved.

[0402] The common electrode 5423 is arranged parallel to the pixel electrode 5425 to generate a horizontal electric field. The electrode is made up of a first conductive layer 5403 and a third conductive layer 5409. As shown in FIG. 54(B), the common electrode 5423 is The wiring may extend along the video signal line 5422 so as to surround the video signal line 5422. By this, the potential of the electrode that should hold the potential changes in accordance with the change in the potential of the video signal line 5422. This can reduce the phenomenon of crosstalk, which occurs when the video signal line 5 In order to reduce the cross capacitance with the first semiconductor layer 54, as shown in FIG. 05 may be provided in the intersection area of ​​the common electrode 5423 and the video signal line 5422.

[0403] The TFT 5424 serves as a switch for connecting the video signal line 5422 and the pixel electrode 5425. As shown in FIG. 54(B), the source region or drain region of the TFT 5424 The source and drain regions may be arranged to surround each other. This allows for a large channel width in a small area, improving switching As shown in FIG. 54(B), the gate of the TFT5424 The port terminal may be disposed so as to surround the first semiconductor layer 5405 .

[0404] The pixel electrode 5425 is electrically connected to either the source terminal or the drain terminal of the TFT 5424. The pixel electrode 5425 is connected to the liquid crystal panel 5421. It is an electrode for supplying a voltage to the liquid crystal element. It may also form a pixel capacitor together with the common electrode 5423. This also serves to hold the signal voltage transmitted by the video signal line 5422. The pixel electrode 5425 and the comb-shaped common electrode 5423 are shown in FIG. As shown in B), it is preferable to form the shape of a bent comb. Therefore, a plurality of regions in which the liquid crystal molecules 5418 are aligned differently can be formed, and the viewing angle can be changed. A large liquid crystal display device can be obtained. If the electrode 5423 is made of a transparent material, a transmission type liquid crystal display device can be obtained. Transmissive LCD displays have high color reproducibility and display high-quality images. In addition, the pixel electrode 5425 and the comb-shaped common electrode 5423 can be made reflective. When the liquid crystal display device is made of such a material, a reflective liquid crystal display device can be obtained. The device has high visibility in bright environments such as outdoors, and does not require a backlight. The pixel electrode 5425 and the comb-shaped The common electrode 5423 is made of both transparent and reflective materials. In this case, a semi-transmissive liquid crystal display device can be obtained that has the advantages of both. When the element electrode 5425 and the comb-shaped common electrode 5423 are made of a reflective material, The surfaces of the pixel electrode 5425 and the comb-shaped common electrode 5423 may be uneven. This has the advantage that the reflected light is diffused, reducing the angle dependency of the intensity distribution of the reflected light. In other words, it is possible to obtain a reflective LCD display that has a constant brightness regardless of the viewing angle. It is possible.

[0405] The comb-shaped pixel electrode 5425 and the comb-shaped common electrode 5423 are both made of the third conductive layer. However, the pixel configuration to which the present invention can be applied is not limited to this. For example, a comb-shaped pixel electrode 5425 and a comb-shaped common electrode 54 23 may both be formed of the second conductive layer 5407 or both of the first conductive layer 5403 Alternatively, one of the electrodes may be formed from the third conductive layer 5409 and the other from the second conductive layer. Alternatively, one of the electrodes may be formed from the third conductive layer 5409 and the other may be formed from the third conductive layer 5407. It may be formed of the first conductive layer 5403, or either one may be formed of the second conductive layer 5407. The other may be formed of the first conductive layer 5403 .

[0406] Next, with reference to FIG. 55, a case where the present invention is applied to another in-plane switching type liquid crystal display device will be described. Figure 55 shows a liquid crystal display that switches so that the orientation of the liquid crystal molecules is always horizontal to the substrate. 10 is a diagram showing another pixel structure of a liquid crystal display device in which an electric field is applied in the lateral direction to perform the above-mentioned operation. More specifically, either the pixel electrode 5525 or the common electrode 5523 has a comb-shaped By applying pattern processing to one side and forming an electrode uniformly in the area where it overlaps with the comb-tooth shape, A method of applying an electric field in the horizontal direction, known as FFS (Fringe Field Switch 55(A) is a cross-sectional view and a top view of a pixel when the present invention is applied to the OLED display method. FIG. 55(A) is a cross-sectional view of the pixel, and FIG. 55(B) is a top view of the pixel. The cross-sectional view of the pixel shown in FIG. 55(B) corresponds to the line a-a' in the top view of the pixel shown in FIG. By applying the present invention to a liquid crystal display device having the pixel structure shown in FIG. A liquid crystal display device having a wide viewing angle and a small grayscale dependency of response speed can be obtained.

[0407] The pixel structure of an FFS liquid crystal display device will be described with reference to Figure 55(A). A display device has a key component called a liquid crystal panel that displays images. Two processed substrates are bonded together with a gap of several micrometers, and liquid is placed between the two substrates. In FIG. 55(A), the two substrates are a first substrate and a second substrate. The first substrate is a substrate 5501, and the second substrate is a substrate 5516. The first substrate is provided with TFTs and pixel electrodes. The second substrate is provided with a light-shielding film 5514, a color filter 5515, a spacer 5517 and a second alignment film 5512 may be fabricated.

[0408] It should be noted that the present invention can be implemented without forming a TFT on the first substrate 5501. When the present invention is carried out without fabricating a substrate, the number of steps is reduced, and therefore the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. When the present invention is implemented by fabricating TFTs, a larger display device can be obtained.

[0409] The TFT shown in FIG. 55 is a bottom gate type TFT using an amorphous semiconductor. However, the present invention is not limited to this. The structure of the TFT that can be used is a bottom gate type TFT. There are etch type, channel protection type, etc. Also, top gate type is also possible. Furthermore, amorphous Not only semiconductors but also polycrystalline semiconductors can be used.

[0410] It should be noted that the present invention can be implemented without forming the light-shielding film 5514 on the second substrate 5516. When the present invention is carried out without forming the light-shielding film 5514, the number of steps is reduced, and the manufacturing cost is reduced. In addition, the simple structure improves the yield. On the other hand, when the light-shielding film 5514 is fabricated and the present invention is implemented, light leakage occurs during black display. Therefore, a display device with less noise can be obtained.

[0411] The present invention can be implemented without forming the color filter 5515 on the second substrate 5516. It is possible to carry out the present invention without fabricating the color filter 5515. Since the number of electrodes is reduced, the manufacturing cost can be reduced. On the other hand, the color filter 5515 is manufactured to embody the present invention. When this is applied, a display device capable of displaying in color can be obtained.

[0412] In the present invention, the spacers 5517 are not formed on the second substrate 5516, but spherical spacers are formed. The present invention can also be carried out by scattering spherical spacers. In this case, the number of steps is reduced, which reduces the manufacturing cost. On the other hand, the spacer 5517 is fabricated to improve the yield. When performing the lighting, the position of the spacer does not vary, so the distance between the two substrates is kept uniform. This makes it possible to obtain a display device with little display unevenness.

[0413] Next, the first substrate 5501 may be processed using the method described in FIG. Here, a first substrate 5501, a first insulating film 5502, a first conductive layer 5 503, a second insulating film 5504, a first semiconductor layer 5505, a second semiconductor layer 5506, The second conductive layer 5507, the third insulating film 5508, the third conductive layer 5509, and the first alignment film 55 10 respectively correspond to the first substrate 5101, the first insulating film 5102, and the first A conductive layer 5103, a second insulating film 5104, a first semiconductor layer 5105, a second semiconductor layer 51 06, a second conductive layer 5107, a third insulating film 5108, a third conductive layer 5109, a first wiring It corresponds to the membrane 5110.

[0414] However, the difference from FIG. 51 is that a fourth insulating film 5519 and a fourth insulating film 5518 are provided on the first substrate 5501 side. The fourth conductive layer 5513 may be formed. More specifically, the third conductive layer 55 After patterning the 09, a fourth insulating film 5519 is formed and patterned. After forming contact holes, a fourth conductive layer 5513 is formed and patterned in the same manner. After the above-mentioned process, the first alignment film 5510 may be formed. The materials and processing methods that can be used for the third insulating film 5508 and the fourth conductive layer 5513 are the same as those for the third insulating film 5508 and the fourth conductive layer 5513. The same material as that used for the third conductive layer 5509 can be used. The electrode is electrically connected to either the source terminal or the drain terminal of the TFT5524, The uniform electrode may be electrically connected to a common electrode 5523. A lateral electric field can be effectively applied to the crystal molecules 5518.

[0415] The first substrate 5501, the light-shielding film 5514, and the color filter 551 are then combined. 5, the spacer 5517, and the second substrate 5516 on which the second alignment film 5512 was formed, The two substrates are bonded together with a gap of a few microns using a sealant, and liquid crystal material is injected between them. Although not shown, a liquid crystal panel can be fabricated by inserting the second substrate 5516 side. By forming a conductive layer on the second substrate 5516 side, This makes it possible to make the device less susceptible to the effects of electromagnetic noise.

[0416] Next, we will explain the characteristics of the pixel structure of the FFS type liquid crystal panel shown in Figure 55. The liquid crystal molecule 5518 shown in 5(A) is a long and thin molecule with a long axis and a short axis. To indicate the orientation of 5518, it is expressed by its length in FIG. 55(A). That is, the liquid crystal molecules 5518 shown as long have their long axes parallel to the paper surface, and their short axes parallel to the paper surface. The shorter the liquid crystal molecule 5518, the closer its long axis is to the normal direction of the paper. In other words, the liquid crystal molecules 5518 shown in FIG. 55(A) are always aligned such that their long axes are aligned with the substrate. In Figure 55(A), in the absence of an electric field, When an electric field is applied to the liquid crystal molecules 5518, the direction of their long axes changes to It rotates in a horizontal plane while always maintaining a horizontal orientation to the substrate. This makes it possible to obtain a liquid crystal display device with a wide viewing angle.

[0417] Next, referring to FIG. 55(B), when the present invention is applied to an FFS type liquid crystal display device, An example of a pixel layout will be described. An FFS type liquid crystal display device to which the present invention is applied. The pixel includes a scanning line 5521, a video signal line 5522, a common electrode 5523, and a TFT 55. 24 and a pixel electrode 5525.

[0418] The scanning line 5521 is electrically connected to the gate terminal of the TFT 5524, and therefore, the first conductive Preferably, it is made up of layer 5503.

[0419] The video signal line 5522 is electrically connected to the source terminal or the drain terminal of the TFT 5524. Therefore, it is preferable that the scanning line 55 is made of the second conductive layer 5507. 21 and the video signal line 5522 are arranged in a matrix, so that at least the It is preferable that the image signal line 55 is formed of a conductive layer. 22 may be bent within the pixel to fit the shape of the pixel electrode 5525. This makes it possible to increase the aperture ratio of the pixel, thereby improving the efficiency of the liquid crystal display device. The rate can be improved.

[0420] The common electrode 5523 is arranged parallel to the pixel electrode 5525 to generate a horizontal electric field. The electrode is made up of a first conductive layer 5503 and a third conductive layer 5509. As shown in FIG. 55(B), the common electrode 5523 is The image signal line 5522 may be formed in a shape that conforms to the image signal line 552. The phenomenon in which the potential of the electrode that should maintain the potential changes as the potential of 2 changes. It is possible to reduce crosstalk. In order to achieve this, as shown in FIG. 55(B), the first semiconductor layer 5505 is projected as a common electrode 5523. It may be provided in the crossing region of the image signal line 5522.

[0421] The TFT 5524 acts as a switch that connects the video signal line 5522 and the pixel electrode 5525. As shown in FIG. 55(B), the source region or drain region of the TFT5524 The source and drain regions may be arranged to surround each other. This allows for a large channel width in a small area, improving switching As shown in Figure 55(B), the gate of the TFT5524 The port terminal may be disposed so as to surround the first semiconductor layer 5505 .

[0422] The pixel electrode 5525 is electrically connected to either the source terminal or the drain terminal of the TFT 5524. The pixel electrode 5525 is connected to the liquid crystal panel 5521. It is an electrode for supplying a signal to the liquid crystal element. It may also form a pixel capacitor together with the common electrode 5523. This also serves to hold the signal voltage transmitted by the video signal line 5522. The pixel electrode 5525 can be formed in a bent comb shape as shown in FIG. It is preferable to form the liquid crystal molecules 5518 in a tooth-like shape. Since a plurality of different regions can be formed, a liquid crystal display device with a wide viewing angle can be obtained. In addition, the pixel electrode 5525 and the comb-shaped common electrode 5523 are made of a transparent material. When the liquid crystal display device is fabricated using the above material, a transmission type liquid crystal displa...

Claims

1. A gate driver is provided. the gate driver includes first to ninth transistors; one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to an output signal line; one of the source and the drain of the second transistor is always electrically connected to the output signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the gate of the third transistor is always electrically connected to the first wiring; one of the source and the drain of the fourth transistor is always electrically connected to the output signal line; the other of the source and the drain of the fourth transistor is always electrically connected to the power supply line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; a gate of the fifth transistor is always electrically connected to a gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; a gate of the sixth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the seventh transistor; the other of the source and the drain of the eighth transistor is always electrically connected to a second wiring; the gate of the eighth transistor is always electrically connected to the second wiring; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the seventh transistor; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; when the other of the source and the drain of the third transistor is in a conductive state with the gate of the first transistor through at least a channel formation region of the third transistor, a potential at which the first transistor is turned on is input to the gate of the first transistor through at least a channel formation region of the third transistor, when the other of the source and the drain of the sixth transistor is in a conductive state with the gate of the first transistor through at least a channel formation region of the sixth transistor, a potential at which the first transistor is turned off is input to the gate of the first transistor through at least a channel formation region of the sixth transistor, when the other of the source or the drain of the seventh transistor is in a conductive state with the gate of the second transistor and the gate of the sixth transistor via at least a channel formation region of the seventh transistor, a potential for controlling a potential of the gate of the second transistor and a potential for controlling a potential of the gate of the sixth transistor are input to the gate of the second transistor and the gate of the sixth transistor via at least a channel formation region of the seventh transistor, a signal input to the other of the source and the drain of the seventh transistor is not input to the other of the source and the drain of the third transistor; when a potential of a third wiring is applied to at least a gate of the fourth transistor and a gate of the fifth transistor, a potential of the gate of the fourth transistor and a potential of the gate of the fifth transistor are controlled in accordance with at least the potential of the third wiring; the seventh transistor is turned on and off by the eighth and ninth transistors; the first transistor has a larger channel width than the third transistor; the first transistor has a larger channel width than the fourth transistor; The display device, wherein the first transistor has a channel width larger than that of the fifth transistor.

2. In claim 1, A pixel portion is provided. the pixel portion includes a tenth transistor, One of the source and the drain of the tenth transistor is always electrically connected to a pixel electrode; the other of the source and the drain of the tenth transistor is always electrically connected to a video signal line; the gate of the tenth transistor is always electrically connected to the output signal line; one of a source and a drain of the tenth transistor has a region sandwiched by the other of the source and the drain of the tenth transistor in a plan view; The pixel electrode has a plurality of cutout portions.

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