Transistor

Abstract

To provide a planar type transistor having stable semiconductor characteristics and high reliability, and including an oxide semiconductor film formed by a simple manufacturing process.SOLUTION: In a semiconductor device, a transistor 150 includes a first insulating film 102a including a first conductive film 104a and a film containing hydrogen, a second insulating film 102b including an oxide insulating film, a first region 106 overlapping with the first conductive film, an oxide semiconductor film 126 including a pair of second regions 107a, b with the first region therebetween, a pair of electrodes 116a, b, a gate insulating film 112a, a second conductive film 114a, and a fifth insulating film 108 containing hydrogen. A capacitor element includes a lower electrode 104b containing the same material as that of the first conductive film, an interelectrode insulating film 102a containing the same material as that of the first insulating film, an insulating film 112b containing the same material as that of the gate insulating film, and an upper electrode 114b containing the same material as that of the second conductive film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film, a method for manufacturing the semiconductor device, Related to modules and electronic devices.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. process, machine, manufacture, or composition of matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called thin-film transistors (TFTs)) is attracting attention. It is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Semiconductor materials such as silicon are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as another material.

[0005] For example, amorphous oxides containing In, Zn, Ga, Sn, etc. are used as oxide semiconductors. A technique for fabricating a transistor using this method is disclosed in Patent Document 1. A technique for producing a star is disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2006-165529 A [Patent Document 2] JP 2009-278115 A Summary of the Invention [Problem to be solved by the invention]

[0007] As a transistor using an oxide semiconductor film, for example, an inverted staggered type (bottom gate structure) The oxide semiconductor is a planar type (also called a top gate structure) or a planar type (also called a top gate structure). When a transistor using a conductor film is applied to a display device, it is more effective than a planar type transistor. However, the manufacturing process of the inverted staggered transistor is relatively simple and the manufacturing cost can be reduced. However, as the screen size of display devices increases, High definition image quality of the device (for example, 4k x 2k (horizontal pixel count = 3840 pixels, vertical pixel count = 3840 pixels) Prime number = 2048 pixels) or 8k x 4k (horizontal pixels = 7680 pixels, vertical pixels As the development of high-resolution display devices (represented by displays with 4320 pixels) progresses, the use of inverted staggered transistors In the case of a transistor, there is a parasitic capacitance between the gate electrode and the source electrode and between the gate electrode and the drain electrode. There is a problem in that signal delays and the like increase depending on the capacitance, deteriorating the image quality of the display device. In addition, in the case of an inverted staggered transistor, the transistor Therefore, a transistor using an oxide semiconductor film is used. The structure of the Renner-type transistor has stable semiconductor characteristics and high reliability. Furthermore, there is a demand for the development of a transistor that can be formed through a simple manufacturing process.

[0008] In addition, as the screen size of a display device increases or the image quality of a display device increases, The configuration of the transistor formed in the pixel and the capacitance element connected to the transistor is important. The capacitor element functions as a storage capacitor that stores data written to the pixel. Depending on the configuration of the capacitance element, the data written to the pixel may not be retained, and the image of the display device may not be displayed. There was a problem of quality deterioration.

[0009] In view of the above problems, one embodiment of the present invention provides a novel semiconductor device including an oxide semiconductor. In particular, a planar semiconductor device using an oxide semiconductor is provided, or To provide a semiconductor device with a large on-state current using an oxide semiconductor, or to provide a semiconductor device with a large off-state current using an oxide semiconductor To provide a semiconductor device with a small current, or a semiconductor device with a small occupancy area using an oxide semiconductor To provide a semiconductor device using an oxide semiconductor and having stable electrical characteristics. To provide a highly reliable semiconductor device using an oxide semiconductor, or to provide a novel semiconductor One of the objectives is to provide a body device.

[0010] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above may be solved by the specification. The above problems are obvious from the description of the specification, etc., and no other problems can be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0011] One embodiment of the present invention includes a transistor and a capacitor. a first insulating film on the first conductive film, a second insulating film on the first insulating film, and a second insulating film on the first insulating film. An oxide semiconductor film on an insulating film, a pair of electrodes in contact with the oxide semiconductor film, a gate insulating film and a second conductive film overlapping with the oxide semiconductor film with the gate insulating film interposed therebetween; the first insulating film includes a film containing hydrogen, the second insulating film includes an oxide insulating film, The oxide semiconductor film includes a first region overlapping with the first conductive film and a pair of insulating films sandwiching the first region. and a second region, the first region and the second region having different concentrations of impurity elements, The element has a lower electrode, an interelectrode insulating film on the lower electrode, and an upper electrode on the interelectrode insulating film. The lower electrode includes the same material as the first conductive film, and the interelectrode insulating film includes the first A third insulating film containing the same material as the insulating film, and a gate insulating film containing the same material as the gate insulating film. and a fourth insulating film containing a material, and the upper electrode is made of the same material as the second conductive film. and a fifth insulating film on the transistor, the fifth insulating film including a film containing hydrogen. The semiconductor device is characterized in that

[0012] In the above structure, the film containing hydrogen preferably includes a silicon nitride film.

[0013] In the above structure, the oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. It is preferable to have a region containing oxygen.

[0014] In the above structure, the second region has a higher concentration of the impurity element than the first region.

[0015] In the above structure, the impurity element is hydrogen, boron, carbon, nitrogen, fluorine, or aluminum. The element has any one selected from the group consisting of nium, silicon, phosphorus and chlorine.

[0016] In the above configuration, the first region may have a region having a thickness larger than that of the second region. good.

[0017] In another embodiment of the present invention, the first gate electrode and the lower electrode are formed from the same conductive film. Then, a first insulating film is formed on the first gate electrode and the lower electrode, and a second insulating film is formed on the first insulating film. An insulating film is formed, a detachment-inhibiting film is formed on the second insulating film, and the second insulating film is formed through the detachment-inhibiting film. Oxygen is added to the film, the detachment suppression film is removed, and the area of ​​the second insulating film that overlaps with the lower electrode is The first insulating film is exposed by processing, an oxide semiconductor film is formed over the second insulating film, and an oxide semiconductor A third insulating film is formed on the conductor film, the first insulating film, and the second insulating film. A first conductive film is formed on the first gate electrode and the first conductive film is processed to form a second gate electrode and an upper electrode. The third insulating film is processed to form a gate insulating film and a fourth insulating film, and the second gate The electrode is used as a mask to add impurities to the oxide semiconductor film, forming a first gate electrode overlapping the second gate electrode. a pair of second regions sandwiching the first region; and an oxide semiconductor is formed on the second insulating film. A fifth insulating film is formed on the conductive film, the second gate electrode and the upper electrode. The pair of second regions and the region overlapping with each other are processed to expose the pair of second regions, and a fifth insulating layer is formed. A source electrode is formed on the insulating film and on one of the pair of second regions, and a fifth insulating film is formed on the fifth insulating film and A drain electrode is formed on the other of the pair of second regions, and the fifth insulating film is a film containing hydrogen. The first insulating film and the fourth insulating film have a function as an inter-electrode insulating film. The present invention relates to a method for manufacturing a semiconductor device.

[0018] Another embodiment of the present invention is a semiconductor device including the above-described semiconductor device and a printed circuit board. This is a module that features:

[0019] Another embodiment of the present invention is a semiconductor device including the above-described semiconductor device or the above-described module and a spindle. The electronic device is characterized by having a camera, an operation key, or a battery. Effect of the Invention

[0020] According to one embodiment of the present invention, a novel semiconductor device including an oxide semiconductor can be provided. In particular, a planar semiconductor device using an oxide semiconductor can be provided. A semiconductor device including an oxide semiconductor and having a large on-state current can be provided. It is possible to provide a semiconductor device which uses an oxide semiconductor and has low off-state current. A semiconductor device using an oxide semiconductor and having a small area can be provided. It is possible to provide a semiconductor device using a nitride semiconductor and having stable electrical characteristics. It is possible to provide a highly reliable semiconductor device using an oxide semiconductor. A semiconductor device can be provided.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 4] 1A to 1C are diagrams illustrating a structure of a transistor. [Diagram 5] 1A to 1C are diagrams illustrating a structure of a transistor. [Figure 6] 1A to 1C are diagrams illustrating a structure of a transistor. [Figure 7] 1A to 1C are diagrams illustrating a structure of a transistor. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 18] 1A and 1B are a cross-sectional view and a band structure of a transistor that is a semiconductor device of one embodiment of the present invention. [Figure 19]1A to 1C are cross-sectional views of a semiconductor device. [Figure 20] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 21] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 22] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 23] Electron diffraction pattern of CAAC-OS. [Figure 24] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 25] 1A and 1B are diagrams illustrating a structure of a pixel portion of a light-emitting device. [Figure 26] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 27] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 28] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 29] 1A to 1C are diagrams illustrating a structure of a transistor. [Diagram 30] FIG. 1 is a diagram for explaining a computational model. [Diagram 31] FIG. 1 is a diagram for explaining an initial state and a final state. [Diagram 32] FIG. 1 is a diagram illustrating the activation barrier. [Diagram 33] FIG. 1 is a diagram for explaining the initial state and the final state. [Diagram 34] FIG. 1 is a diagram illustrating the activation barrier. [Diagram 35] A diagram explaining VoH transition levels. [Diagram 36] 1A and 1B are a top view and a circuit diagram of a display device using a semiconductor device according to one embodiment of the present invention. [Figure 37] 1A and 1B are a circuit diagram and a timing chart of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 38] 1A and 1B are a circuit diagram and a timing chart of a display device including a semiconductor device according to one embodiment of the present invention. [Figure 39]1A and 1B are a circuit diagram and a timing chart of a display device including a semiconductor device according to one embodiment of the present invention. [Diagram 40] 1A and 1B are a circuit diagram and a timing chart of a display device including a semiconductor device according to one embodiment of the present invention. [Diagram 41] FIG. 2 is a diagram illustrating a display module. [Diagram 42] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 43] FIG. 1 is a diagram showing an embodiment of a band structure. [Diagram 44] 1A to 1C are diagrams illustrating electronic devices. [Diagram 45] FIG. 4 is a diagram illustrating the temperature dependence of resistivity. [Diagram 46] Schematic diagram illustrating a film formation model of CAAC-OS, and cross-sectional views of a pellet and CAAC-OS. [Figure 47] Schematic diagram explaining a film formation model of nc-OS and a figure showing a pellet. [Figure 48] FIG. [Figure 49] 4A to 4C are diagrams illustrating the force applied to a pellet on a formation surface. [Figure 50] 4A to 4C are diagrams illustrating the movement of pellets on a formation surface. [Figure 51] A diagram explaining the InGaZnO4 crystal. [Figure 52] A diagram explaining the structure of InGaZnO4 before atoms collide. [Diagram 53] A diagram explaining the structure of InGaZnO4 after atomic collisions. [Figure 54] A diagram explaining the trajectory of atoms after they collide. [Figure 55] Cross-sectional HAADF-STEM images of CAAC-OS and the target. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the present invention in various forms without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0024] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. and are not limited to the shapes or values ​​shown in the drawings.

[0025] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0026] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0027] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0028] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0029] In this specification, the terms "film" and "layer" are interchangeable. In addition, the term "insulator" and "insulating film (or insulating layer)" can be used interchangeably. The expressions "conductor" and "electroconductor" can be interchanged. The term "conductive film (or conductive layer)" can be interchanged with the term "conductive film (or conductive layer)". The term "semiconductor" can be used interchangeably with the term "semiconductor film (or semiconductor layer)." It is possible to replace it.

[0030] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region refers to a region through which a current mainly flows. The flow area.

[0031] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain can be used interchangeably. Let us assume that.

[0032] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0033] Note that in this specification, the channel length refers to, for example, A semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and a gate The source (source electrode) in the region where the source electrode and the source electrode overlap each other or in the region where the channel is formed The distance between the source region (or source electrode) and the drain (drain region or drain electrode) In addition, if the channel length of a single transistor is the same in all regions, That is, the channel length of a transistor may not be determined to a single value. Therefore, in this specification, the channel length is defined as any one of the lengths of the regions in which the channel is formed. The value may be any one of the following: maximum, minimum or average value.

[0034] In this specification, the channel width is, for example, the width of a semiconductor (or transistor) when it is in an on-state. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the This refers to the width of the source or drain in the region where the channel is formed. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of the transistor may not be determined to a single value. In the above, the channel width is any one value, maximum value, or maximum in the region where the channel is formed. The minimum or average value.

[0035] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in a transistor with a fine and three-dimensional structure, The percentage of the channel region formed on the side of the semiconductor compared to the percentage of the channel region formed on the inside of the semiconductor. In that case, the apparent channel width shown in the top view may be In this case, the effective channel width where the channel is actually formed is larger than the actual channel width.

[0036] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width unless the exact channel conditions are known. .

[0037] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the source and drain facing each other in the overlapping region. The above channel width is called "Surrounded Channel Width (SCW)". In this specification, it is simply referred to as the channel width. In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when the term "channel width" is used simply, it may refer to the effective channel width. In addition, the channel length, channel width, effective channel width, apparent channel width, and The width of the interstitial channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0038] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0039] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to the drawings. Reveal.

[0040] <Configuration of Semiconductor Device> FIG. 1 shows a top-gate transistor as an example of a transistor included in a semiconductor device. 1 shows a capacitor that can be manufactured in the same process as a transistor.

[0041] FIG. 1 shows a cross-sectional view of a transistor 150 and a capacitor 160 included in the semiconductor device. FIG. 2A shows a top view and a cross-sectional view of the transistor 150. 2(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 2(A). 2(C) is a cross-sectional view taken along the dashed line A3-A4 in FIG. 2(A). For clarity, the substrate 100, the insulating film 101, the insulating film 102, and the gate insulating film 112a are shown. , the insulating film 108, the insulating film 118, the insulating film 128, etc. are omitted. In the top view of this figure, one of the components is shown as transistor 150, as in the subsequent figures. In addition, the direction of the dashed line A1-A2 is the channel length direction, The direction of the dotted chain line A3-A4 may be referred to as the channel width direction.

[0042] The transistor 150 includes a gate electrode 104 on an insulating film 101 formed on a substrate 100. a, an insulating film 102 on the gate electrode 104a, a first region 106 on the insulating film 102, and an oxide semiconductor film 126 including a pair of second regions 107a and 107b sandwiching a first region therebetween; The gate insulating film 112a in contact with the oxide semiconductor film 126 and the gate insulating film 112a The gate electrode 114a, the oxide semiconductor film 126, and the insulating film 108 that covers the gate electrode 114a and the insulating film 118, and the insulating film 108 and the openings provided in the insulating film 118. A source electrode 116a contacting the region 107a and a drain electrode 116b contacting the second region 107b. 116b.

[0043] The capacitance element 160 includes a lower electrode 104b on an insulating film 101 formed on a substrate 100, The insulating film 102a and the insulating film 112b functioning as interelectrode insulating films on the lower electrode 104b. , and an upper electrode 114b on the insulating film 112b.

[0044] In the oxide semiconductor film 126, a pair of second gate electrodes 114a and 114b are not overlapped with each other. The regions 107a and 107b contain elements that form oxygen vacancies. The elements that cause the impurity are described as impurity elements. Representative examples of impurity elements are hydrogen, boron, These include carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, and rare gas elements. Representative examples of gas elements are helium, neon, argon, krypton, and xenon. .

[0045] When an impurity element is added to an oxide semiconductor film, the metal element and oxygen in the oxide semiconductor film are The bond is broken, and oxygen vacancies are formed. Alternatively, an impurity element is added to the oxide semiconductor film. When the oxide semiconductor film is heated, oxygen that has been bonded to a metal element in the oxide semiconductor film is bonded to an impurity element, and the metal element is As a result, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The carrier density increases and the conductivity becomes higher.

[0046] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, oxygen Hydrogen enters the vacancy site and a donor level is formed near the conduction band. As a result, the oxide semiconductor The conductivity of the oxide semiconductor increases and it becomes a conductor. The oxide semiconductor that becomes a conductor is called an oxide conductor. In general, oxide semiconductors have a large energy gap and are therefore sensitive to visible light. On the other hand, an oxide conductor is an oxide having a donor level near the conduction band. Therefore, the effect of absorption due to the donor level is small, and the material is oxidized to visible light. It has the same level of light transmittance as nitride semiconductors.

[0047] Here, the resistance of a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film) The temperature dependency of resistivity will be explained with reference to the drawings.

[0048] Here, a sample having an oxide conductor film was prepared. The oxide conductor film (OC_SiN x ) In the doping apparatus, argon is added to the oxide semiconductor film, and the silicon nitride film is The oxide conductor film (OC_Ar dope+SiN x ), or In the plasma processing apparatus, the oxide semiconductor film is exposed to argon plasma, and silicon nitride is The oxide conductive film formed by contacting with the film (OC_Ar plasma + SiN x )of The silicon nitride film contains hydrogen.

[0049] Oxide conductive film (OC_SiN x The method for preparing the sample containing the ZnO film is as follows. A silicon oxynitride film with a thickness of 400 nm was formed on the substrate by plasma CVD, and then oxygen was pumped. By exposing the silicon oxynitride film to plasma and adding oxygen ions to it, oxygen is released by heating. Next, a silicon oxynitride film that releases oxygen when heated was formed. A sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2 was placed on the silicon film. A 100 nm thick In-Ga-Zn oxide film was formed by sputtering using Heat treatment in a nitrogen atmosphere at 50℃, then heat treatment in a nitrogen and oxygen mixed gas atmosphere at 450℃ Next, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD. Then, the sample was heat-treated at 350° C. in a mixed gas atmosphere of nitrogen and oxygen.

[0050] Oxide conductor film (OC_Ar doped + SiN x The method for preparing the sample containing A 400 nm thick silicon oxynitride film is formed on a glass substrate by plasma CVD. After the formation of the silicon oxynitride film, it is exposed to oxygen plasma to add oxygen ions to the silicon oxynitride film. A silicon oxynitride film that releases oxygen by heating was formed. On the silicon oxynitride film, a sputtering layer with an atomic ratio of In:Ga:Zn=1:1:1.2 was formed. Using a 100 nm thick In-Ga-Zn oxide film, a sputtering method was used. After forming a nitride film, it was heat-treated in a nitrogen atmosphere at 450°C, and then heated in a mixture of nitrogen and oxygen at 450°C. The substrate was then heat-treated in a mixed gas atmosphere. Next, a doping device was used to dope the In-Ga-Zn oxide The film was irradiated with 5×10 ions at an acceleration voltage of 10 kV. 14 / cm 2 of argon was added. Next, oxygen vacancies were formed in the In-Ga-Zn oxide film by plasma CVD. A silicon nitride film of 00 nm was formed. Next, a nitrogen and oxygen mixed gas atmosphere at 350° C. was used. It was heat treated.

[0051] Oxide conductive film (OC_Ar plasma + SiN x The preparation method of the sample including A silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate by plasma CVD. After forming the silicon oxynitride film, it is exposed to oxygen plasma to produce a silicon oxynitride film that releases oxygen when heated. Next, a silicon oxynitride film with an atomic ratio of I was formed on the silicon oxynitride film, which releases oxygen when heated. Sputtering was performed using a sputtering target of n:Ga:Zn=1:1:1.2. A 100 nm thick In-Ga-Zn oxide film was formed by the CVD method, and then heated at 450°C in a nitrogen atmosphere. After the heat treatment, the plate was heated at 450°C in a mixed gas atmosphere of nitrogen and oxygen. In the Zuma processing device, argon plasma is generated and accelerated argon ions are ionized into In The oxygen vacancies were created by colliding the Zn-Ga oxide film with the Zn-Ga oxide film. A silicon nitride film with a thickness of 100 nm was formed by evaporating the nitrogen and oxygen mixture at 350° C. The heat treatment was carried out in a gas atmosphere.

[0052] Next, the results of measuring the resistivity of each sample are shown in Figure 45. Here, the resistivity was measured using a four-terminal In FIG. 45, the horizontal axis indicates the measurement temperature, and the vertical axis indicates indicates resistivity. Also, the oxide conductor film (OC_SiN x ) measurement results are indicated by square marks, Oxide conductor film (OC_Ar doped + SiN x The measurement results of oxide conductors are shown with circles. Electrical film (OC_Ar plasma+SiN x ) The measurement results are indicated by triangles.

[0053] Although not shown, the oxide semiconductor film that is not in contact with the silicon nitride film has a high resistivity. Therefore, it is considered that the oxide conductor film has a higher resistivity than the oxide semiconductor film. It is clear that it is low.

[0054] As can be seen from FIG. 45, the oxide conductor film (OC_Ar doped + SiN x ) and acid Compound conductor film (OC_Ar plasma+SiN x ) contains oxygen vacancies and hydrogen The resistivity fluctuation is small. Typically, the resistivity fluctuation is small at temperatures between 80K and 290K. The resistivity variation is less than ±20% between 150K and 250K. The rate is less than ±10%. In other words, oxide conductors are degenerate semiconductors, and the conduction band edge and the ferroelectric It is estimated that the luminescence level of the oxide conductor film is equal to or approximately equal to the luminescence level of the oxide conductor film. By using it as the source and drain regions of a transistor, the oxide conductor film and the source The contact with the conductive film that functions as the electrode and drain electrode is an ohmic contact, and the oxide conductive The contact resistance between the conductive film and the conductive film functioning as the source electrode and the drain electrode can be reduced. In addition, since the resistivity of the oxide conductor has low temperature dependence, the oxide conductor film and the source electrode and drain electrode can be easily formed. The variation in contact resistance with the conductive film that functions as the drain electrode is small, resulting in highly reliable transistors. It is possible to create a star.

[0055] The pair of second regions 107a and 107b function as a source region and a drain region. The source electrode 116a and the drain electrode 116b are made of tungsten, titanium, or aluminum. Conductors that easily combine with oxygen, such as copper, molybdenum, chromium, or tantalum alone or in alloys In the case where the oxide semiconductor film is formed using an insulating material, oxygen contained in the oxide semiconductor film and the source electrode 116a and The conductive material contained in the drain electrode 116b is bonded to the oxide semiconductor film. In addition, the source electrode 116a and the drain electrode 116 In some cases, some of the constituent elements of the conductive material that forms b may be mixed in. As a result, A pair of second regions 107a, 107b in contact with the electrode 116a and the drain electrode 116b are The conductivity increases and they act as source and drain regions.

[0056] The impurity element is a rare gas element, and the oxide semiconductor film 126 is formed by a sputtering method. In this case, the pair of second regions 107a and 107b each contain a rare gas element, and the first The pair of second regions 107a and 107b has a higher concentration of rare gas elements than the region 106. This is because, when the oxide semiconductor film 126 is formed by a sputtering method, Since a rare gas element is used as the ring gas, the rare gas is contained in the oxide semiconductor film 126. and in order to form oxygen vacancies in the pair of second regions 107a and 107b, This is because rare gas elements are intentionally added. In the first region 107b, a rare gas element different from that in the first region 106 may be added.

[0057] Impurity elements are boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, or In the case of chlorine, the impurity element is contained only in the pair of second regions 107a and 107b. Therefore, the pair of second regions 107a and 107b has a higher impurity content than the first region 106. In the pair of second regions 107a and 107b, the secondary ion mass Analysis method (SIMS: Secondary Ion Mass Spectrometry) The concentration of impurity elements obtained by 18 atoms / cm 3 More than 1×10 2 2 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 More than 1×10 21 a toms / cm 3 or less, or 5×10 19 atoms / cm 3 5×10 or more 20 ato ms / cm 3 It can be as follows:

[0058] When the impurity element is hydrogen, the pair of second regions 107a The pair of second regions 107a and 107b has a higher concentration of the impurity element. The hydrogen concentration obtained by secondary ion mass spectrometry is 8×10 19 atoms / cm 3 or more, or 1×10 20 atoms / cm 3 or more, or 5×10 20 ato ms / cm 3 It can be more than that.

[0059] Since the pair of second regions 107a and 107b contains an impurity element, oxygen vacancies are increased. The carrier density increases. As a result, the pair of second regions 107a and 107b become conductive. This increases the resistance and acts as a low resistance region.

[0060] The impurity elements are hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, It may be a combination of one or more of phosphorus or chlorine and one or more of a rare gas. In this case, a pair of In the second regions 107a and 107b, oxygen vacancies formed by a rare gas element, and Hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus added to the region or chlorine, the pair of second regions 107a, 107b become conductive. The electrical conductivity may increase further.

[0061] The first region 106 functions as a channel. An enlarged view is shown in FIG. 3. When the gate electrode 114a is formed, a pair of oxide semiconductor films 126 Since the regions that will become the second regions 107a and 107b are etched, as shown in FIG. The first region 106 has a larger film thickness than the pair of second regions 107a and 107b. Specifically, the first region 106 is 0.1 n thicker than the pair of second regions 107 a and 107 b. It has an area larger than m and smaller than 5 nm.

[0062] The transistor 150 described in this embodiment has a first region functioning as a channel formation region. a pair of second regions 107a, 107b functioning as a source region and a drain region; The pair of second regions 107a and 107b have high electrical conductivity, and therefore the pair of first regions 107a and 107b have high electrical conductivity. The contact resistance between the second region 107a, 107b and the source electrode 116a and the drain electrode 116b is It is possible to reduce the resistance and increase the on-state current of the transistor. .

[0063] In addition, in the transistor 150, an impurity element is introduced by using the gate electrode 114a as a mask. That is, the impurity region (source A source region and a drain region can be formed.

[0064] In addition, the capacitor 160 can be manufactured simultaneously with the manufacturing process of the transistor 150. . The gate electrode 104a of the transistor 150 and the lower electrode 104b of the capacitance element 160 are the same. Also, the gate insulating film 112a of the transistor 150 and the capacitor element 160 The insulating film 112b of the transistor 150 is formed at the same time. a and the upper electrode 114b of the capacitance element 160 are formed at the same time.

[0065] The configuration shown in FIG. 1 will be described in detail below.

[0066] Various substrates can be used as the substrate 100, and it is not limited to a specific one. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), a SO I substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate , Substrate with Stainless Steel Foil, Tungsten Substrate, Tungsten Foil A substrate having a fibrous material, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film Examples of glass substrates include barium borosilicate glass and aluminophore. silicate glass, or soda lime glass. Flexible substrates, lamination films Examples of the materials and base films are as follows: Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulf For example, there are plastics such as polyether ether sulphate (PES). Synthetic resins, etc. Examples include polypropylene, polyester, and polyfluorine. Examples of such materials include polyvinyl chloride, polyvinyl chloride, and polyamide. Imide, aramid, epoxy, inorganic deposition film, paper, etc. In particular, semiconductor By manufacturing transistors using substrates, single crystal substrates, or SOI substrates, etc. , small variation in characteristics, size, or shape, high current capability, small size It is possible to manufacture transistors. Circuits are constructed using such transistors. As a result, it is possible to reduce the power consumption of the circuit or to increase the degree of integration of the circuit.

[0067] In addition, a flexible substrate is used as the substrate 100, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 100 and the transistor. After a semiconductor device is partially or entirely completed on the substrate, the semiconductor device is separated from the substrate 100 and another In this case, the transistors are transferred to a substrate with poor heat resistance or a flexible substrate. The transfer can also be performed on a flexible substrate. The above-mentioned release layer may be, for example, a tungsten film and a silicon oxide film. The laminated structure of the inorganic film with the silicon film, or the organic resin film such as polyimide is formed on the substrate. The above configuration can be used.

[0068] An example of a substrate on which a transistor is transferred is a substrate on which the above-mentioned transistor is formed. In addition to the substrates that can be used, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, Rubber substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, hemp), synthetic fibers (nylon) , polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, These substrates include recycled polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and low power consumption. It is possible to form, manufacture devices that are less likely to break, are heat resistant, or are lighter or thinner. .

[0069] The insulating film 101 functions as a base insulating film. The insulating film 101 has a role of preventing the diffusion of substances. Sium, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide Thorium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and thorium oxide Oxide insulating film such as tantalum, silicon nitride, silicon nitride oxide, aluminum nitride, nitride The insulating film can be formed using a nitride insulating film such as aluminum oxide or a mixture of these materials. Also, the material may be a laminate of the above materials.

[0070] The gate electrode 104a is a stack of a conductive film 104a1 and a conductive film 104a2. The lower electrode 104b is a laminate of a conductive film 104b1 and a conductive film 104b2. 4a1, the conductive film 104a2, the conductive film 104b1 and the conductive film 104b2 are made of aluminum, Chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, tungsten or an alloy containing the above-mentioned metal elements or the above-mentioned metal elements. It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. The gate electrode 104a may be formed of one or more metal elements selected from the above. The lower electrode 104b may have a single-layer structure or a laminated structure of three or more layers. Single layer structure of aluminum film containing silicon, single layer structure of copper film containing manganese, aluminum A two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, A two-layer structure in which a tungsten film is laminated on a titanium nitride film, a tantalum nitride film or a tungsten nitride film A two-layer structure in which a tungsten film is laminated on a tungsten film, and a copper film is laminated on a copper film containing manganese Two-layer structure: titanium film, aluminum film laminated on top of the titanium film, and titanium on top of that. A three-layer structure that forms a manganese film, a copper film is laminated on a copper film containing manganese, and a manganese film is further laminated on top of that. There are also three-layer structures in which a copper film containing titanium, tantalum, A single branch of an element selected from tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film in which a plurality of layers are combined, or a nitride film may be used.

[0071] The gate electrode 104a and the lower electrode 104b are made of indium tin oxide or tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light transmission properties, such as indium tin oxide containing silicon oxide, is used. In addition, the conductive material having light transmitting properties and the metal element may be laminated. It is also possible.

[0072] In this embodiment, the conductive film 104a1 and the conductive film 104b1 are made of titanium film, and the conductive film 104 The conductive film 104a2 and the conductive film 104b2 are made of copper. It is preferable to use a low-resistance conductive material such as aluminum. By using conductive materials, signal delay can be reduced.

[0073] The insulating film 102 is a stack of an insulating film 102a and an insulating film 102b.

[0074] The insulating film 102a is a blocking agent for oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. The film has a blocking effect and preferably contains hydrogen. The insulating film 102b can be formed of an oxide semiconductor film, an aluminum nitride oxide film, or the like. In order to improve the interface characteristics with 126, it is preferable to form the insulating film with an oxide. It is preferable that the material contains an oxide material which releases a part of oxygen by heating, and the stoichiometric composition is not satisfied. It is more preferable to use an oxide containing more oxygen than oxygen that is not included in the insulating film 102b. By using the oxide insulating film which releases oxygen by heating as described above, Oxygen contained in the insulating film 102b can be moved to the oxide semiconductor film 126. .

[0075] The thickness of the insulating film 102b is 50 nm or more, or 100 nm or more and 3000 nm or less, or Alternatively, the thickness of the insulating film 102b can be set to 200 nm or more and 1000 nm or less. As a result, the amount of oxygen released from the insulating film 102b can be increased. The interface state at the interface with the oxide semiconductor film 126 and the first It is possible to reduce the oxygen vacancies contained in the region 106 .

[0076] The insulating film 102b may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The material may be a single layer or a multilayer.

[0077] The oxide semiconductor film 126 is typically made of In-Ga oxide, In-Zn oxide, or In- M-Zn oxide (M is Mg, Al, Ti, Ga, Y, Zr, La, Ce, Nd, or The oxide semiconductor film 126 is formed using a metal oxide such as Hf. Note that the oxide semiconductor film 126 has a light-transmitting property.

[0078] In the case where the oxide semiconductor film 126 is an In-M-Zn oxide, I excluding Zn and O The atomic ratio of n and M is 25% In when the sum of In and M is 100 atomic %. atomic% or more, M is less than 75 atomic%, or In is 34 atomic% or more Above, M is less than 66 atomic%.

[0079] The oxide semiconductor film 126 has an energy gap of 2 eV or more, or 2.5 eV or more. Or it is 3 eV or more.

[0080] The thickness of the oxide semiconductor film 126 is 3 nm to 200 nm, or The thickness can be 3 nm or less, or 3 nm to 50 nm.

[0081] In the case where the oxide semiconductor film 126 is an In-M-Zn oxide, the In-M-Zn oxide is formed. The atomic ratio of the metal elements in the sputtering target used for this purpose is In≧M, Zn≧M. It is preferable that the atomic ratio of the metal elements in such a sputtering target and In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn =2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, I The atomic ratio of n:M:Zn to Zn is preferably 3:1:2. The atomic ratios are calculated based on the atomic ratio of the metal elements contained in the sputtering target. This includes a fluctuation of plus or minus 40% in numerical ratios.

[0082] In addition, the oxide semiconductor film 126 contains silicon or carbon, which is one of the Group 14 elements. When the oxide semiconductor film 126 is filled with oxygen, oxygen vacancies are increased in the oxide semiconductor film 126, and the oxide semiconductor film 126 becomes n-type. Therefore, the oxide semiconductor film 126, particularly the first region 106, is made of silicon or carbon. The concentration of (obtained by secondary ion mass spectrometry) is 2 × 10 18 atoms / cm 3 or less, or 2×10 17 atoms / cm 3 As a result, A transistor has electrical characteristics in which the threshold voltage is positive (also called normally-off characteristics). has.

[0083] In addition, in the oxide semiconductor film 126, particularly in the first region 106, the secondary ion species The concentration of alkali metals or alkaline earth metals obtained by quantitative analysis is 1×10 18 a toms / cm 3 or less, or 2×10 16 atoms / cm 3 It can be Alkali metals and alkaline earth metals generate carriers when bonded to oxide semiconductors. In some cases, the off-state current of the transistor may increase. It is preferable to reduce the concentration of alkali metals or alkaline earth metals in region 106. As a result, the transistor has normally-off characteristics.

[0084] In addition, when the oxide semiconductor film 126 contains nitrogen, particularly in the first region 106, In this case, electrons acting as carriers are generated, the carrier density increases, and the material becomes n-type. As a result, a transistor using an oxide semiconductor film containing nitrogen has normally-on characteristics. Therefore, in the oxide semiconductor film, particularly in the first region 106, For example, the amount of the ionized water obtained by secondary ion mass spectrometry is preferably as small as possible. The nitrogen concentration is 5×10 18 atoms / cm 3 It can be the following:

[0085] The oxide semiconductor film 126 is formed by reducing impurity elements, particularly in the first region 106. By this, the carrier density of the oxide semiconductor film can be reduced. The conductor film 126, particularly in the first region 106, has a carrier density of 1×10 17 pieces / cm 3 or less, or 1×1015 pieces / cm 3 or less, or 1×10 13 pieces / cm 3 Below Down, or 1×10 11 pieces / cm 3 It can be as follows:

[0086] The oxide semiconductor film 126 is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using such a material, a transistor having better electrical characteristics can be manufactured. Here, the low impurity concentration and low defect level density (few oxygen vacancies) are referred to as high purity pure silicon. High-purity intrinsic or substantially high-purity intrinsic oxides Semiconductors have few carrier generation sources, so it is sometimes possible to reduce the carrier density. Therefore, the transistor in which the channel region is formed in the oxide semiconductor film is a normally In addition, high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors are prone to loss-of-temperature characteristics. Since the defect level density of the thin film is low, the trap level density may also be low. A highly intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current and When the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V, The current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 Below A Therefore, a channel region is formed in the oxide semiconductor film. Such a transistor may have small fluctuations in electrical characteristics and become a highly reliable transistor. do.

[0087] The oxide semiconductor film 126 may have a non-single crystal structure, for example. For example, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline, microcrystalline, or amorphous Among non-single crystal structures, the amorphous structure has the highest defect level density and CAAC- The OS has the lowest defect state density.

[0088] Note that the oxide semiconductor film 126 may have an amorphous structure, a microcrystalline structure, or a polycrystalline structure. A mixed film having two or more of the following regions may be used: a region of a CAAC-OS structure, a region of a single crystal structure, and a region of a crystalline structure. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CA In the case of a single-layer structure having two or more regions of either AC-OS or single crystal structure In addition, the mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, and the like. A structure in which two or more of the following are stacked: a CAAC-OS region, a CAAC-OS region, and a single crystal structure region. There are cases.

[0089] Note that in the oxide semiconductor film 126, the pair of second regions 107 a and 107 b and the first The crystallinity of the pair of second regions 107a, 106 may be different from that of the pair of second regions 107b, 10 When an impurity element is added to the second region 107a and the second region 107b, damage is caused to the pair of second regions 107a and 107b. This is because the crystallinity decreases due to the inclusion of the ions.

[0090] In this embodiment, the oxide semiconductor film 126 has a multilayer structure (here, The lower layer is a channel formation region 106a, a low resistance region 107a1, and a low resistance A channel forming region 106b, a low resistance region 107a2, and It has a low resistance region 107b2.

[0091] In addition, a channel region is formed in the lower layer of the oxide semiconductor film having a two-layer structure. The upper layer of the oxide semiconductor film is typically an In-Ga oxide, an In-Zn oxide, or an In- Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Mg, Al, Ti, Ga , Y, Zr, La, Ce, Nd, or Hf) and have a lower energy level at the conduction band edge than the lower layer. The energy level is close to the vacuum level, and typically, the energy level at the bottom of the conduction band of the oxide semiconductor film (upper layer) is The difference between the energy of the conduction band of the oxide semiconductor film (lower layer) and the energy of the conduction band of the oxide semiconductor film (lower layer) is 0.05 eV or more. 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or more The energy difference between the vacuum level and the conduction band edge is 0.5 eV or less, or 0.4 eV or less. The energy difference is also called electron affinity.

[0092] The oxide semiconductor film (upper layer) is In-M-Zn oxide (M is Mg, Al, Ti, Ga, Y , Zr, La, Ce, Nd, or Hf) to form an oxide semiconductor film (upper layer). The atomic ratio of the metal elements in the target used for this purpose is In:M:Zn=x1:y1:z If we set it to 1, 、 x1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z1 / It is preferable that y1 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. When y1 is 1 to 6, a CAAC-OS film is formed as the oxide semiconductor film (upper layer). A typical example of the atomic ratio of the metal elements in the target is In:M:Zn. =1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, I n:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1 :There are 2nd and 3rd place.

[0093] The atomic ratios of the oxide semiconductor film (upper layer) and the oxide semiconductor film (lower layer) are each determined with an error of The atomic ratios above may vary by ±40%.

[0094] The atomic ratio is not limited to these, and an appropriate atomic ratio may be selected according to the required semiconductor characteristics. Just use what you have.

[0095] The gate insulating film 112a and the insulating film 112b are each a single layer of an oxide insulating film or a nitride insulating film. Alternatively, the oxide semiconductor film 126 may be formed by stacking the oxide semiconductor film 126. In order to achieve this, at least a region in contact with the oxide semiconductor film 126 is formed using an oxide insulating film. It is preferable that the gate insulating film 112a and the insulating film 112b are made of, for example, silicon oxide. Silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, halide The material can be a single layer or a multilayer. It can be established.

[0096] The gate insulating film 112a and the insulating film 112b are formed of a material containing a blocker such as oxygen, hydrogen, or water. By providing the insulating film having a blocking effect, oxygen from the oxide semiconductor film 126 to the outside can be prevented from diffusing. This can prevent hydrogen, water, and the like from entering the oxide semiconductor film 126 from the outside. Examples of insulating films that have a blocking effect against hydrogen, water, etc. include aluminum oxide and aluminum oxynitride. Aluminum, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride Examples include hafnium oxide, hafnium oxynitride, etc.

[0097] The gate insulating film 112a and the insulating film 112b are made of hafnium silicate (Hf Sx O y ), nitrogen-doped hafnium silicate (HfSi x O y ), nitrogen is added Hafnium aluminate (HfAl x O y ), hafnium oxide, yttrium oxide The use of high-k materials such as these can reduce gate leakage of transistors.

[0098] The gate insulating film 112a and the insulating film 112b are formed by using a material that releases part of oxygen by heating. Preferably, the oxide material contains more oxygen than the stoichiometric composition. It is preferable to use an oxide insulating film containing By using an oxide insulating film that releases oxygen by heating as described above as b, As a result, oxygen contained in the gate insulating film 112a is transferred to the oxide semiconductor film 126. is possible.

[0099] The gate insulating film 112a and the insulating film 112b are made of silicon oxynitride having few defects. A silicon oxynitride film having few defects can be used after the heat treatment. In the spectrum obtained by ESR measurement at 100K or less, the g value is 2.037 or more. a first signal with a g value of 0.39 or less, a second signal with a g value of 2.001 to 2.003 or less, And the spin density of a third signal having a g value of 1.964 or more and 1.966 or less is observed. In addition, the split width of the first signal and the second signal, and the split width of the second signal and The split width of the signal 3 is about 5 mT in the X-band ESR measurement. The first signal has a g value between 2.037 and 2.039, and the second signal has a g value between 2.001 and 2.00. 3 or less for the second signal, and g-values ​​between 1.964 and 1.966 or less for the third signal. The total density of spins is 1×10 18 spins / cm 3 is less than 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 is less than.

[0100] In addition, the g value in the ESR spectrum below 100K is 2.037 to 2.039. The first signal has a g value of 2.001 to 2.003, and the second signal has a g value of 1 The third signal, between .964 and 1.966, is nitrogen oxide (NO x , x is 0 to 2 This corresponds to signals caused by g values ​​of 2.037 or more and 2.038 or less. a first signal with a g value of 0.39 or less, a second signal with a g value of 2.001 to 2.003 or less, And the sum of the spin densities of the third signals with g values ​​between 1.964 and 1.966 is small. It can be said that the smaller the concentration of nitrogen oxide in the silicon oxynitride film, the smaller the content of nitrogen oxide in the silicon oxynitride film.

[0101] In addition, the silicon oxynitride film with few defects has a nitrogen concentration measured by secondary ion mass spectrometry. Degrees are 6 x 10 20 atoms / cm 3 The gate insulating film 112a and the insulating film 1 By using a silicon oxynitride film with few defects as 12b, nitrogen oxide is not generated. This reduces carrier traps at the interface between the oxide semiconductor film 126 and the insulating film. In addition, it is possible to prevent a shift in the threshold voltage of a transistor included in a semiconductor device. It is possible to reduce the variation in electrical characteristics of the transistor.

[0102] The gate electrode 114a is a stack of a conductive film 114a1 and a conductive film 114a2. The upper electrode 114b is a laminate of a conductive film 114b1 and a conductive film 114b2. The materials of the conductive film 4a1, the conductive film 114a2, the conductive film 114b1, and the conductive film 114b2 are 104a1, conductive film 104a2, conductive film 104b1, and conductive film 104b2 are referred to. can be done.

[0103] In this embodiment, the conductive film 114a1 and the conductive film 114b1 are formed of a tantalum nitride film and a conductive film A tungsten film is used for the conductive film 114a2 and the conductive film 114b2.

[0104] In addition, as shown in FIG. 1, in the cross section in the channel length direction, The portion is located outside the end of the conductive film 114a2, and the conductive film 114a1 has a tapered shape. That is, the surface where the gate insulating film 112a and the conductive film 114a1 are in contact with each other and the conductive film 114a1 may be formed as follows. The angle between the side faces of the film 114a1 is less than 90°, or is 5° to 45°, or is 5° or more. The angle between the end of the conductive film 114b1 and the end of the conductive film 114b2 may be 30° or less. The insulating film 114b1 may be located on the outer side and may have a tapered shape. The angle between the surface where the conductive film 114b1 and the conductive film 114b1 are in contact with each other is 90°. The angle may be less than 5°, or may be greater than 5° and less than 45°, or greater than 5° and less than 30°.

[0105] Furthermore, the end of the gate insulating film 112a is located outside the end of the conductive film 114a1. In addition, the end of the insulating film 112b may be located outside the end of the conductive film 114b1. Good too.

[0106] Furthermore, the side surfaces of the gate insulating film 112a and the insulating film 112b may be curved.

[0107] Furthermore, the gate insulating film 112a may have a tapered shape. The angle between the surface where the film 126 and the gate insulating film 112a contact each other and the side surface of the gate insulating film 112a The angle may be less than 90°, preferably greater than or equal to 30° and less than 90°.

[0108] The material of the insulating film 108 may be the same as that of the insulating film 102a.

[0109] The insulating film 118 can be made of the same material as the insulating film 102b.

[0110] The source electrode 116a is a laminate of a conductive film 116a1 and a conductive film 116a2. The drain electrode 116b is a stack of a conductive film 116b1 and a conductive film 116b2. The materials of the conductive film 116a1, the conductive film 116a2, the conductive film 116b1, and the conductive film 116b2 are conductive. The conductive film 104a1, the conductive film 104a2, the conductive film 104b1, and the conductive film 104b2 are referred to. It is possible.

[0111] In this embodiment, the conductive film 116a1 and the conductive film 116b1 are formed of a tungsten film and a conductive film A copper film is used for the conductive film 116a2 and the conductive film 116b2. It is preferable to use a low resistance conductive material such as copper or aluminum for 2. By using a highly conductive material, signal delay can be reduced.

[0112] The insulating film 128 is preferably a film that functions as a barrier film against hydrogen, water, and the like from the outside. The insulating film 128 may be made of, for example, silicon nitride, silicon oxynitride, or aluminum oxide. The above may be used, and the layer may be formed as a single layer or a multilayer.

[0113] Here, modified examples of the transistor will be described with reference to FIGS. The transistor illustrated in FIG. 4 includes an oxide semiconductor film formed over an insulating film 453 over a substrate 400. 455, an insulating film 457 in contact with the oxide semiconductor film 455, The insulating film 457 includes a conductive film 459 overlapping the nitride semiconductor film 455. The conductive film 459 functions as a gate insulating film. The substrate 400 may be the substrate 100. The insulating film 453 may be an insulating film. The oxide semiconductor film 126 can be used as the oxide semiconductor film 455. The insulating film 457 can be formed using the gate insulating film 112a. , the gate electrode 114a can be used.

[0114] The nitride insulating film 465 in contact with the oxide semiconductor film 455 and the nitride insulating film 465 The insulating film 467 is provided in contact with the transistor. In the opening of the insulating film 467, the conductive films 468 and 469 in contact with the oxide semiconductor film 455 are The conductive films 468 and 469 are provided as source and drain electrodes. The nitride insulating film 465 functions as a gate electrode. The insulating film 118 can be used as the insulating film 467. The conductive films 468 and 469 are , a source electrode 116a, and a drain electrode 116b can be used.

[0115] In the transistor illustrated in FIG. 4A, the oxide semiconductor film 455 overlaps with the conductive film 459. A channel region 455a is formed in the region having impurities. The conductive film 46 has regions containing organic elements, i.e., low resistance regions 455b and 455c. The conductive films 468 and 469 are in contact with the low resistance regions 455b and 455c. , and functions as wiring.

[0116] Alternatively, in the transistor illustrated in FIG. 4B, The regions 455d and 455e in contact with the conductive films 468 and 469 are not doped with impurity elements. In this case, the regions 455d and 455e in contact with the conductive films 468 and 469 and the channel Between the region 455a, there are regions having impurity elements, i.e., low resistance regions 455b and 455c. Note that the regions 455d and 455e are formed by applying a voltage to the conductive films 468 and 469. Since the SiO 2 layer has electrical conductivity, it functions as a source region and a drain region.

[0117] Note that in the transistor shown in FIG. 4B, after the conductive films 468 and 469 are formed, An impurity element is added to the oxide semiconductor film using the conductive films 459 and 468 and 469 as masks. It can be formed by

[0118] The conductive film 459 may have a tapered end. The angle θ1 between the surface where the insulating film 457 and the conductive film 459 are in contact and the side surface of the conductive film 459 is 90 Less than °, 10° to 85°, or 15° to 85°, or 30° to 85° or less than 45°, or less than 85°, or less than 60°. θ1 is set to less than 90°, 10° to 85°, 15° to 85°, or 30°. 45° to 85°, or 60° to 85°. This improves the coverage of the side surfaces of the insulating film 457 and the conductive film 459 with the nitride insulating film 465. It is possible.

[0119] Next, a modified example of the low resistance regions 455b and 455c will be described. 4F is an enlarged view of the oxide semiconductor film 455 and its vicinity shown in FIG. The channel length L is the distance between a pair of low resistance regions.

[0120] As shown in FIG. 4C, in the cross section in the channel length direction, the channel region 455a The boundary between the low resistance regions 455b and 455c is the edge of the conductive film 459 via the insulating film 457. That is, in the top view, the channel region 455a and The boundaries of the low resistance regions 455b and 455c coincide or approximately coincide with the ends of the conductive film 459. is.

[0121] Alternatively, as shown in FIG. 4D, in a cross-sectional shape in the channel length direction, the channel region The conductive film 455a has a region that does not overlap with the conductive film 459. The region functions as an offset region. The length of the offset region in the channel length direction is L off In addition, the offset If there are multiple offset areas, the length of one offset area is L. off That is said. off teeth , which is included in the channel length L. Also, L off is less than 20% of the channel length L, or 10 %, or less than 5%, or less than 2%.

[0122] Alternatively, as shown in FIG. 4E, in the cross-sectional shape in the channel length direction, the low resistance region 4 The insulating film 457 is disposed between the conductive film 459 and the insulating film 457. The overlap region in the channel length direction Length L ov L ov is less than 20% of the channel length L, or less than 10%, or Less than 5% or less than 2%.

[0123] Alternatively, as shown in FIG. 4(F), in the cross section in the channel length direction, A low resistance region 455f is provided between the channel region 455a and the low resistance region 455b. The low resistance region 455g is between the low resistance region 455f and the low resistance region 455c. g has a lower concentration of impurity elements and a higher resistivity than the low resistance regions 455b and 455c. In this case, the low resistance regions 455f and 455g overlap the insulating film 457, but the insulating film 457 and the conductive It may overlap with the conductive film 459 .

[0124] Note that in FIGS. 4C to 4F, the transistor in FIG. However, the transistor shown in FIG. 4B may have the structures shown in FIGS. It can be applied as appropriate.

[0125] In the transistor illustrated in FIG. 5A, an edge of the insulating film 457 is located outside an edge of the conductive film 459. That is, the insulating film 457 is located on the conductive film 459 side. Since the nitride insulating film 465 can be kept away from the panel region 455a, the nitride insulating film 465 can be formed in a thin film. To prevent nitrogen, hydrogen, etc. contained in the film 465 from entering the channel region 455a. can be done.

[0126] In the transistor shown in FIG. 5B, the insulating film 457 and the conductive film 459 have a tapered shape. In other words, the insulating film 457 and the conductive film 459 have different taper angles. The angle θ1 between the contact surface and the side surface of the conductive film 459 and the oxide semiconductor film 455 and the insulating film 4 The angle θ2 between the surface of the insulating film 457 and the side of the insulating film 457 is different. It may be less than 90°, or between 30° and 85°, or between 45° and 70°. For example, when the angle θ2 is greater than the angle θ1, the transistor can be miniaturized.

[0127] Next, regarding modified examples of the low resistance regions 455b and 455c, FIG. 5(C) to FIG. 5(F) will be described. 5C to 5F are diagrams illustrating the oxide semiconductor film This is an enlarged view of the vicinity of 455.

[0128] As shown in FIG. 5C, in the cross section in the channel length direction, the channel region 455a The boundary between the low resistance regions 455b and 455c is a boundary between the end of the conductive film 459 and the insulating film 457. That is, in terms of the top view, the channel region 455a and The boundaries of the low resistance regions 455b and 455c coincide or nearly coincide with the ends of the conductive film 459. is doing.

[0129] Alternatively, as shown in FIG. 5D, in a cross-sectional shape in the channel length direction, the channel region The conductive film 455a has a region that does not overlap with the conductive film 459. The region functions as an offset region. That is, in the top view, the ends of the low resistance regions 455b and 455c are in contact with the insulating film 45. 7 and does not overlap with the edge of the conductive film 459.

[0130] Alternatively, as shown in FIG. 5E, in the cross-sectional shape in the channel length direction, the low resistance region 4 The insulating film 457 is disposed between the conductive film 459 and the insulating film 457. In other words, in the top view, the low resistance regions 455b and 455 An end of c overlaps with the conductive film 459 .

[0131] Alternatively, as shown in FIG. 5(F), in the cross section in the channel length direction, A low resistance region 455f is provided between the channel region 455a and the low resistance region 455b. The low resistance region 455g is between the low resistance region 455f and the low resistance region 455c. g has a lower concentration of impurity elements and a higher resistivity than the low resistance regions 455b and 455c. In this case, the low resistance regions 455f and 455g overlap the insulating film 457, but the insulating film 457 and the conductive It may overlap with the conductive film 459 .

[0132] Note that in FIGS. 5C to 5F, the transistor shown in FIG. However, the transistor shown in FIG. 5B may have the structures shown in FIGS. It is possible to apply it appropriately.

[0133] In the transistor illustrated in FIG. 6A, a conductive film 459 is in contact with an insulating film 457. A conductive film 459a is in contact with the conductive film 459a, and a conductive film 459b is in contact with the conductive film 459a. The end of the conductive film 459a is located outside the end of the conductive film 459b. The portion a protrudes from the conductive film 459b.

[0134] Next, a modified example of the low resistance regions 455b and 455c will be described. 6E to 7A and 7B show the oxide semiconductor film 455 shown in FIG. FIG.

[0135] As shown in FIG. 6B, in the cross section in the channel length direction, the channel region 455a The boundary between the low resistance regions 455b and 455c is the conductive film 459a included in the conductive film 459. The end portion is aligned or approximately aligned with the insulating film 457. The boundary between the channel region 455a and the low resistance regions 455b and 455c is the end of the conductive film 459. It matches or nearly matches.

[0136] Alternatively, as shown in FIG. 6C, in the cross-sectional shape in the channel length direction, the channel region The conductive film 455a has a region that does not overlap with the conductive film 459. The region functions as an offset region. That is, in the top view, the ends of the low resistance regions 455b and 455c are Does not overlap with the end of 9.

[0137] Alternatively, as shown in FIG. 6D, in the cross-sectional shape in the channel length direction, the low resistance region 4 The conductive film 459 includes a region overlapping the conductive film 459a. The regions are called overlap regions. That is, in the top view, the low resistance regions 455b and 45 An end of 5c overlaps with the conductive film 459a.

[0138] Alternatively, as shown in FIG. 6E, in a cross-sectional shape in the channel length direction, the channel region A low resistance region 455f is provided between the channel region 455a and the low resistance region 455b. The impurity element is a conductive film 459. a and is added to the low resistance regions 455f and 455g. The region 55g has a lower concentration of impurity elements and a higher resistivity than the low-resistance regions 455b and 455c. Here, the low resistance regions 455f and 455g overlap with the conductive film 459a. The conductive film 459a and the conductive film 459b may overlap with each other.

[0139] Alternatively, as shown in FIG. 7A, in the cross section in the channel length direction, the conductive film 459 The end of the conductive film 459a is located outside the end of the conductive film 459b, and the conductive film 459a has a tapered shape. That is, the surface where the insulating film 457 and the conductive film 459a are in contact with each other and the conductive film 459 may be in a shape similar to that of the insulating film 457. The angle between the sides of a is less than 90°, or is between 5° and 45°, or between 5° and 30° may be also possible.

[0140] Furthermore, the edge of the insulating film 457 may be located outside the edge of the conductive film 459a.

[0141] Furthermore, the side surface of the insulating film 457 may be curved.

[0142] Furthermore, the insulating film 457 may have a tapered shape. The angle between the surface of the insulating film 457 and the side of the insulating film 457 is preferably less than 90°. may be greater than or equal to 30° and less than 90°.

[0143] The oxide semiconductor film 455 illustrated in FIG. 7A includes a channel region 455a and a channel region 455b. The low resistance regions 455f and 455g sandwich the channel region 455a and the low resistance region 45 5f, 455g are sandwiched between low resistance regions 455h, 455i, a channel region 455a, and a low resistance The low resistance regions 455f and 455g are sandwiched between the low resistance regions 455h and 455i. The impurity element passes through the insulating film 457 and the conductive film 459a and is a low-resistance insulating film. Since it is added to the resistance regions 455f, 455g, 455h, and 455i, the low resistance region 455f , 455g, 455h, and 455i are regions with higher impurity element concentrations than the low resistance regions 455b and 455c. It has low resistance and high resistivity.

[0144] The oxide semiconductor film 455 illustrated in FIG. 7B includes a channel region 455a and a channel region 455b. The low resistance regions 455h and 455i sandwich the channel region 455a and the low resistance region 45 The impurity element is an insulating film. Since it passes through 457 and is added to the low resistance regions 455h and 455i, the low resistance region 455h , 455i has a lower concentration of impurity elements than the low resistance regions 455b, 455c, and has a higher resistivity. stomach.

[0145] In the channel length direction in FIG. 7A, the channel region 455a is The low resistance regions 455f and 455g are conductive regions that protrude outside the conductive film 459b. The low resistance regions 455h and 455i overlap the conductive film 459a. The low resistance regions 455b and 455c are located outside the insulating film 457. It is out.

[0146] As shown in FIG. 7A, the oxide semiconductor film 455 is , Low-resistance region 455f, 455g, 455h, 4 By having 55i, the electric field in the drain region can be relaxed. This makes it possible to reduce degradation such as the fluctuation of the threshold voltage of transistors caused by the electric field of be.

[0147] The transistor shown in FIG. 29A has a channel region 455a, a low-resistance region 455b, The low-resistance regions 455b and 455c are formed in the oxide semiconductor film 455. Typically, the low resistance regions 455b and 455c are made of low-resistance material. 5c has a region that is 0.1 nm to 5 nm thinner than the channel region 455a. .

[0148] The transistor in FIG. 29B includes insulating films 453 and 4 At least one of the insulating films 453a and 57 has a multilayer structure. The insulating film 453b is in contact with the oxide semiconductor film 455 and the insulating film 453a. The insulating film 457 includes an insulating film 457a in contact with the oxide semiconductor film 455 and an insulating film 457b in contact with the insulating film 457a. The insulating film 457b is formed on the insulating film 457.

[0149] The insulating films 453b and 457a have an upper energy (E v_ os ) and the conduction band edge energy (E c_os ) between the nitrogen oxides and the acid with low level density The insulating film can be formed of a carbide. v_os and E c_os During As an oxide insulating film with a low density of states, a silicon oxynitride film that emits a small amount of nitrogen oxide, Alternatively, an aluminum oxide nitride film that emits less nitrogen oxide can be used. The insulating films 453b and 457a have an average film thickness of 0.1 nm or more and 50 nm or less, or 0. Between .5nm and 10nm.

[0150] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectrometry (TD In Thermal Desorption Spectroscopy (S), This is a membrane that releases more ammonia than nitrogen oxides, and is typically Output is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is the case. The amount of a released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. The amount released due to the following heat treatment is considered.

[0151] The insulating films 453a and 457b are formed using an oxide insulating film which releases oxygen by heating. The insulating films 453a and 457b have an average film thickness of 5 nm or more and 1000 nm or less. m or less, or between 10 nm and 500 nm.

[0152] Typical examples of oxide insulating films that release oxygen when heated include silicon oxynitride films and oxide Examples include an aluminum nitride film.

[0153] Nitrogen oxides (NO x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO 2 or NO forms a level in the insulating film 453 and the insulating film 457. The nitroxide is located within the energy gap of the nitride semiconductor film 455. When the insulating film 453 and the oxide semiconductor film 457 are diffused to the interface between the insulating film 453 and the oxide semiconductor film 455, the level is 3, 457 side may trap electrons. As a result, the trapped electrons Since the insulating film 453 and the insulating film 457 and the oxide semiconductor film 455 are located near the interface, the transistor This causes the threshold voltage to shift in the positive direction.

[0154] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxides contained in the insulating films 453b and 457a are deposited on the insulating films 453b and 457a during the heat treatment. The nitrogen oxides contained in the insulating films 453a and 457b react with the ammonia contained therein. As a result, at the interface between the insulating films 453 and 457 and the oxide semiconductor film 455, , electrons are less likely to be trapped.

[0155] The insulating films 453b and 457a are made of E v_os and E c_os The density of nitrogen oxides is By using an oxide insulating film with a low thermal conductivity, the shift in the threshold voltage of a transistor is reduced. This makes it possible to reduce fluctuations in the electrical characteristics of the transistor.

[0156] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher but below the substrate distortion point. By the heat treatment, the insulating films 453 and 457 have the following properties as measured by ESR at 100K or less: The first signal in the spectrum has a g value between 2.037 and 2.039, and the g value is 2.0 A second signal with a g value between 1.01 and 2.003, and a g value between 1.964 and 1.966 The third signal is observed. Note that the split width of the first and second signals is , and the split widths of the second and third signals are set to the values ​​for the X-band ESR measurement. The g-value is about 5 mT at 2.037 to 2.039. The second signal has a g value between 2.001 and 2.003, and the g value between 1.964 and 1.96 The sum of the spin densities of the 6 or fewer tertiary signals is 1×10 18 spins / cm 3 Less than Typically, 1×10 17 spins / cm3 More than 1×10 18 spins / cm 3 is less than.

[0157] In addition, the g value in the ESR spectrum below 100K is 2.037 to 2.039. The first signal has a g value of 2.001 to 2.003, and the second signal has a g value of 1 The third signal, between .964 and 1.966, corresponds to the signal due to nitrogen dioxide. That is, the first signal has a g value of 2.037 or more and 2.039, and the second signal has a g value of 2.001 or more and 2. A second signal with a g value of 0.003 or less, and a third signal with a g value of 1.964 to 1.966 or less. The lower the total spin density of the spins, the lower the nitrogen dioxide content in the oxide insulating film. It can be said that there is no such thing.

[0158] In addition, the heat treatment in the manufacturing process of the transistor is typically performed at temperatures of 300°C or higher but below the substrate distortion point. The oxide insulating film containing nitrogen and having few defects during the heat treatment was analyzed by SIMS (Sec The nitrogen concentration measured by ondary ion mass spectrometry 6×10 20 atoms / cm 3 The following is the result.

[0159] The substrate temperature is 220°C or higher, 280°C or higher, or 350°C or higher, and silane and Using the plasma CVD method using nitrous oxide and dinitrogen monoxide, an oxide containing nitrogen and with few defects was produced. By forming a nitride insulating film, a dense film having high hardness can be formed.

[0160] The transistor in FIG. 29C includes an oxide semiconductor film 455, an insulating film 457, and a conductive An insulating film 475 is provided between the film 459 and the nitride insulating film 465. The insulating film 475 is The oxides shown in the insulating films 453b and 457a in FIG. 29(B) contain nitrogen and have few defects. The insulating film can be used.

[0161] In addition, in the cross-sectional shape in the channel length direction, the channel region 455a and the low resistance region 45 5b, and the channel region 455a and the low resistance region 455c are disposed between the low resistance region 455f and the low resistance region 455c. The low resistance regions 455f and 455g are the low resistance region 455 The concentration of impurities is lower than in b and c, and the resistivity is higher. The insulating film 455f and the insulating film 475 are in contact with the side surfaces of the insulating film 457 and the conductive film 459. The low resistance regions 455f and 455g are formed by insulating film 457 and conductive film 45 May overlap with 9.

[0162] In the transistor illustrated in FIG. 29D, the insulating film 457 is formed on the channel of the oxide semiconductor film 455. The insulating layer 455a is in contact with the low resistance regions 455b and 455c. The film 457 has low resistance regions 455b and 455c compared to the region in contact with the channel region 455a. The film thickness in the area in contact with 5c is thin, typically with an average film thickness of 0.1 nm to 50 nm. As a result, the oxide An impurity element can be added to the semiconductor film 455, and the nitride insulating film 465 can be formed by adding an impurity element to the semiconductor film 455. The contained hydrogen can be transferred to the oxide semiconductor film 455 through the insulating film 457. As a result, low resistance regions 455b and 455c can be formed.

[0163] Furthermore, the insulating film 453 has a multi-layer structure of insulating films 453a and 453b, and is heated to remove oxygen. The insulating film 453a is formed using an oxide insulating film that emits nitrogen and has few defects. The insulating film 453b is formed using a thin oxide insulating film. The insulating film 457 is formed using an oxide insulating film having a small amount of defects. The oxide semiconductor film 455 can be covered with a small amount of the oxide insulating film. The oxygen contained in the oxide semiconductor film 53a is transferred to the oxide semiconductor film 455 by heat treatment. While reducing oxygen vacancies in the channel region 455a of the body film 455, the insulating film 453b, The number of carrier traps at the interface between the oxide semiconductor film 457a and the oxide semiconductor film 455 is reduced. As a result, the shift in the threshold voltage of the transistor can be reduced. As a result, the fluctuation in the electrical characteristics of the transistor can be reduced.

[0164] <(1). V o Ease of formation and stability of H> When the oxide semiconductor film (hereinafter referred to as IGZO) is a perfect crystal, H is dominant at room temperature. During heat treatment at 450°C, H diffuses primarily along the ab plane. In this study, oxygen vacancies in IGZO are o If there is In this case, H is oxygen vacancy V o Here, we will explain whether it is easy to enter the oxygen vacancy V o Medium The state where there is H in V o It is written as H.

[0165] For the calculation, the InGaZnO4 crystal model shown in Figure 30 was used. Here, V o H in H V o The activation barrier (E a ) to NEB (Nud The calculation conditions are shown in Table 1.

[0166] [Table 1]

[0167] In addition, in the InGaZnO4 crystal model, the difference in the number of metal elements to which oxygen is bonded Therefore, there are oxygen sites 1 to 4 as shown in FIG. V o The calculations were performed for oxygen site 1 and oxygen site 2, which are prone to form

[0168] First, oxygen deficiency V o As oxygen site 1, which is likely to form The calculations were performed for the oxygen sites bonded to the

[0169] The model of the initial state is shown in FIG. 31(A), and the model of the final state is shown in FIG. 31(B). In addition, the calculated activation barrier (E a ) is shown in Figure 32. Here, the initial state is oxygen vacancy V o There is an H inside (V o H) and the final state is is oxygen deficiency V o and the state where oxygen bound to one Ga atom and two Zn atoms is bound to H ( It is a structure having a HO.

[0170] As a result of the calculation, oxygen deficiency V o It takes about 1.52 eV of energy for the H in the molecule to bond with another O. is required, whereas H bonded to O is oxygen vacant V o It takes about 0.46 eV to enter Energy was needed.

[0171] Here, the calculated activation barrier (Ea ) and equation 1 to calculate the reaction frequency (Γ) In addition, in the formula 1, k B is the Boltzmann constant and T is the absolute temperature.

[0172]

number

[0173] Frequency factor ν=10 13 [1 / sec] and the reaction frequency at 350°C was calculated. The frequency of H transfer from the model shown in Figure 31(A) to the model shown in Figure 31(B) is 5.5 2×10 0 [1 / sec]. Also, from the model shown in FIG. 31(B), The frequency of H transfer to the model shown in is 1.82×10 9 [1 / sec]. Therefore, H diffusing in IGZO is near the oxygen vacancy V. o There is V o It is easy to form H, Once V o H forms oxygen vacancy V o It is thought that it is difficult to release from

[0174] Next, oxygen deficiency V o The oxygen site 2, which is likely to form a bond with one Ga and two Zn, Calculations were performed for the combined oxygen sites.

[0175] The model of the initial state is shown in FIG. 33(A), and the model of the final state is shown in FIG. 33(B). In addition, the calculated activation barrier (E a ) is shown in Figure 34. Here, the initial state is oxygen vacancy V o There is an H inside (V o H) and the final state is is oxygen deficiency V oand the state where oxygen bound to one Ga atom and two Zn atoms is bound to H ( It is a structure having a HO.

[0176] As a result of the calculation, oxygen deficiency V o It takes about 1.75 eV of energy for the H in the molecule to bond with another O. is required, whereas H bonded to O is oxygen vacant V o It takes about 0.35 eV to enter Energy was needed.

[0177] In addition, the calculated activation barrier (E a ) and the above formula 1, the reaction frequency (Γ) is Calculated.

[0178] Frequency factor ν=10 13 [1 / sec] and the reaction frequency at 350°C was calculated. The frequency of H transfer from the model shown in Figure 33(A) to the model shown in Figure 33(B) is 7.5 3×10 -2 [1 / sec]. Also, from the model shown in FIG. 33(B), The frequency of H transfer to the model shown in 10 [1 / sec]. Therefore, for now, V o H forms oxygen vacancy V o It is thought that H is unlikely to be released from

[0179] From the above, it can be seen that H in IGZO is easily diffused during annealing, and oxygen vacancies V o If there is is oxygen deficiency V o Enter V o It was found that it is likely to become H.

[0180] <(2). V o H transition level > Oxygen vacancy in IGZO V o If and H exists, then <(1). V o H formation From the calculation using the NEB method shown in the section on Difficulty and Stability, oxygen vacancies V o and H is V o H shape It is easy to achieve and V o H is considered stable. Therefore, V o H is a career tracker To investigate whether V o The transition levels of H were calculated.

[0181] The calculation was performed using an InGaZnO4 crystal model (112 atoms). V for oxygen site 1 and oxygen site 2 o The H model was created and the transition level was calculated. The conditions are shown in Table 2.

[0182] [Table 2]

[0183] By adjusting the mixing ratio of the exchange terms to obtain a band gap close to the experimental value, The band gap of the new InGaZnO4 crystal model is 3.08 eV, which is lower than the experimental value of 3.1 The result was close to 5 eV.

[0184] The transition level (ε(q / q')) of the model with defect D is calculated by the following formula 2. In addition, ΔE(D q ) is the formation energy of defect D at charge q, calculated from Eq. It is served.

[0185]

number

[0186]

number

[0187] In Formula 2 and Formula 3, E tot (D q ) is the charge q of the model including the defect D. Total energy, E tot (bulk) is the total energy of a defect-free model (perfect crystal), Δn i is the increase or decrease in the number of atoms i related to the defect, μ i is the chemical potential of atom i, ε VBM Missing The energy of the top of the valence band in the defect-free model, ΔV q is related to the electrostatic potential Correction term, E F is the Fermi energy.

[0188] Calculated V o The transition levels of H are shown in Figure 35. The values ​​in Figure 35 indicate the depth from the bottom of the conduction band. From Figure 35, V for oxygen site 1 o The transition level of H is 0.0 below the conduction band edge. 5 eV, and V for oxygen site 2 o The transition level of H is 0.11e below the conduction band edge. V, so each V o H is thought to be involved in electron trapping. , V o It was revealed that H acts as a donor. o IGZO with H It was revealed that the material has electrical conductivity.

[0189] <Band structure> The band structure in an arbitrary cross section of the above-mentioned transistor will be described below.

[0190] FIG. 18A is a cross-sectional view of a transistor that is a semiconductor device according to one embodiment of the present invention. .

[0191] The transistor shown in FIG. 18A is similar to the transistor 150 shown in FIG. do.

[0192] FIG. 18B shows a line A-A' including a channel formation region of the transistor shown in FIG. The band structure in the cross section is shown. The energy gap of the oxide semiconductor layer is slightly larger than that of the oxide semiconductor layer including the channel formation region 106b. The insulating film 102a, the insulating film 102b and the gate insulating film 112a are formed in a channel shape. The oxide semiconductor including the channel formation region 106a and the oxide semiconductor including the channel formation region 106b The energy gap is sufficiently larger than that of the channel formation region 106a. An oxide semiconductor, an oxide semiconductor including a channel formation region 106b, an insulating film 102a, and an insulating film The Fermi levels (Ef) of the gate insulating film 102b and the gate insulating film 112a are The position of the intrinsic Fermi level (denoted as Ei) is also defined as the position of the gate electrode 104a and the gate The work function of the gate electrode 114a is set to be at the same position as the Fermi level.

[0193] When the gate voltage is set to be equal to or higher than the threshold voltage of the transistor, the channel forming region 106a and the oxide semiconductor including the channel formation region 106b. Due to the difference in energy between the two, the electrons preferentially pass through the oxide semiconductor including the channel formation region 106a. That is, when electrons are embedded in the oxide semiconductor including the channel formation region 106a, The energy at the bottom of the conduction band is denoted as Ec, and the energy at the top of the valence band is denoted as Energy is written as Ev.

[0194] Therefore, in the transistor which is a semiconductor device according to one embodiment of the present invention, the electron embedding Therefore, the influence of interface scattering is reduced. A transistor having such a structure has a small channel resistance.

[0195] Next, in FIG. 18(C), a B-B' region including a source region or a drain region of a transistor is shown. The band structure in the cross section is shown. The low resistance region 107a2 and the low resistance region 107b2 are in a degenerated state. In the region 107b1, the Fermi level of the oxide semiconductor including the channel formation region 106a is The energy of the channel in the low-resistance region 107b2 is approximately equal to the energy of the bottom of the conductive band. The Fermi level of the oxide semiconductor including the formation region 106b is approximately equal to the energy of the bottom of the conduction band. The same applies to the low resistance region 107a1 and the low resistance region 107a2.

[0196] At this time, the energy barrier between the drain electrode 116b and the low resistance region 107b2 is sufficiently large. Since the low resistance region 107b2 is smaller than the low resistance region 107b3, the low resistance region 107b2 is in ohmic contact. Similarly, the source electrode 116a and the low resistance region 107 are in ohmic contact with each other. The energy barrier between a2 and a1 is small enough that they form an ohmic contact. The low-resistance region 107a1 and the low-resistance region 107a2 are in ohmic contact with each other. The oxide semiconductor including the electrode 116a, the drain electrode 116b, and the channel forming region 106a Electrons can be smoothly exchanged between the oxide semiconductor layer and the channel formation region 106b. I know it will be done.

[0197] As described above, the transistor which is a semiconductor device according to one embodiment of the present invention has a source Electrons are smoothly exchanged between the drain electrode and the channel forming region, In addition, it is a transistor with a small channel resistance, i.e., it has excellent switching characteristics. It is clear that this is a transistor.

[0198] In addition, a transistor having a three-layer oxide semiconductor film such as the transistor shown in FIG. The band structure of the transistor with two oxide semiconductor layers, as shown in Figure 1, The band structure of the transistor shown in FIG. FIG. 43(B) is a band structure of the transistor 150 shown in FIG. For ease of understanding, the insulating film 102, the first region 106, and the gate insulating film 112a are The energy (Ec) of the conduction band edge of

[0199] As shown in FIG. 43A, a channel formation region 106a, a channel formation region 106b, In the channel formation region 106c, the energy of the conduction band minimum changes continuously. This is a channel formation region 106a, a channel formation region 106b, and a channel formation region This is also understood from the fact that the elements that make up 106c are the same, and oxygen easily diffuses between them. Therefore, the channel formation region 106a, the channel formation region 106b, and the channel The panel-forming region 106c is a laminate of films with different compositions, but is physically continuous. It is also possible.

[0200] The oxide semiconductor film, which is laminated with a common main component, is not simply laminated, but is formed continuously. Junction (here, specifically, a U-shaped well in which the energy of the conduction band edge changes continuously between layers) The U-shape well structure is formed at the boundary between the layers. In the oxide semiconductor, defect states such as trap centers and recombination centers, or carrier The laminated structure is formed so that there are no impurities that can impede the flow of oxygen. When impurities are present between the layers of a semiconductor film, the continuity of the energy band is lost, and the boundary At this surface, carriers disappear due to trapping or recombination.

[0201] In FIG. 43A, the E Although the cases where c is the same are shown, they may be different.

[0202] As shown in FIG. 43A, the channel formation region 106a serves as a well, and the transistor It can be seen that a channel is formed in the channel formation region 106a. The panel forming region 106a, the channel forming region 106b, and the channel forming region 106c are conductive. Since the energy at the lower band edge changes continuously, a U-shaped well structure is embedded in the channel. It can also be called a channel.

[0203] As shown in FIG. 43B, the channel formation region 106a and the channel formation region 10 In 6b, the energy of the conduction band minimum may change continuously.

[0204] As shown in FIG. 43B, the channel formation region 106a becomes a well, and the transistor It can be seen that a channel is formed in the channel formation region 106a.

[0205] The transistor shown in FIG. 42 includes one or more metal elements constituting the channel formation region 106a. Since the channel forming region 106b and the channel forming region 106c are included in the , the interface between the channel formation region 106a and the channel formation region 106c, and Therefore, an interface state is unlikely to be formed at the interface between the region 106a and the channel formation region 106b. By providing the channel forming region 106b and the channel forming region 106c, This can reduce variations and fluctuations in electrical characteristics such as the threshold voltage of a transistor.

[0206] The transistor shown in FIG. 1 includes one or more metal elements constituting the channel formation region 106a. Since the channel forming region 106b includes the channel forming region 106a, Therefore, the interface state is hardly formed at the interface with the channel formation region 106b. By providing the region 106b, the variation in electrical characteristics such as the threshold voltage of the transistor is reduced. This can reduce noise and fluctuations.

[0207] <Method for manufacturing semiconductor device> Next, a method for manufacturing the transistor 150 and the capacitor 160 shown in FIG. This will be explained with reference to FIG.

[0208] The transistor 150 and the capacitor 160 are made of films (insulating film, oxide semiconductor film, conductive film, The deposition method (film, etc.) can be achieved by sputtering, chemical vapor deposition (CVD), vacuum deposition, pulse laser, etc. It can be formed using a deposition (PLD) method, or it can be formed by a coating method or a printing method. The deposition method includes sputtering, plasma enhanced chemical vapor deposition (PECV), The most typical method is the MOCVD (metal organic chemical vapor deposition) method, but the thermal CVD method may also be used. Alternatively, an organic metal chemical vapor deposition (AMCVD) method or an ALD (atomic layer deposition) method may be used.

[0209] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0210] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating the gas introduction sequence. For example, By switching each switching valve (also called high-speed valve), two or more types of raw materials can be The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so that multiple source gases do not mix. Simultaneously with or after the second gas, an inert gas (such as argon or nitrogen) is introduced. Introduce the raw material gas. If an inert gas is introduced at the same time, the inert gas is used as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first monoatomic layer. The second monoatomic layer is formed by reacting with the second source gas introduced later. Layer upon layer is laminated to form a thin film.

[0211] This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. This allows precise film thickness control, making it possible to fabricate minute transistors. It is suitable for fabrication.

[0212] First, an insulating film 101 is formed on a substrate 100, and a gate electrode 104a and Then, the lower electrode 104b is formed (see FIG. 8).

[0213] The gate electrode 104a and the lower electrode 104b are formed by sputtering, vacuum deposition, pulse deposition, or the like. It can be formed by using a laser deposition (PLD) method, a thermal CVD method, etc. Instead of the above-mentioned method, the gate electrode 104a and the gate electrode 104b are formed by electrolytic plating, printing, inkjet printing, or the like. A lower electrode 104b may be formed.

[0214] Next, the insulating film 102a and the insulating film 102b are formed on the insulating film 101, the gate electrode 104a and the lower electrode 104b. Then, a laminate of the insulating film 132 is formed (see FIG. 9).

[0215] The insulating film 102a and the insulating film 132 are formed by a sputtering method, a CVD method, a vapor deposition method, a pulse laser method, or the like. The layer can be formed by appropriately using a laser deposition (PLD) method, a printing method, a coating method, or the like. The material of the insulating film 132 may be the same as that of the insulating film 102b.

[0216] Next, a desorption suppression film 113 for suppressing desorption of oxygen is formed on the insulating film 132. Oxygen 140 is added to the insulating film 132 through the release inhibitor film 113 (see FIG. 10).

[0217] The detachment suppression film 113 is made of aluminum, chromium, tantalum, titanium, molybdenum, nickel, etc. A metal element selected from the group consisting of ruthenium, iron, cobalt, and tungsten, Alloys, alloys combining the above-mentioned metal elements, metal nitrides having the above-mentioned metal elements, Conductive materials such as metal oxides having the above-mentioned metal elements and metal nitride oxides having the above-mentioned metal elements It is formed using a material having such properties.

[0218] The thickness of the detachment-inhibiting film 113 can be set to be not less than 0.1 nm and not more than 10 nm.

[0219] As a method for adding oxygen 140 to the insulating film 132 through the detachment suppression film 113, ion The methods include a doping method, an ion implantation method, a plasma treatment method, etc. By providing the insulating film 13 and adding oxygen, the detachment suppression film 113 prevents oxygen from being detached from the insulating film 132. Therefore, the insulating film 132 is doped with a large amount of oxygen. It can be added.

[0220] In addition, when oxygen is introduced in plasma processing, the oxygen is excited by microwaves to produce high-density oxygen. By generating atomic plasma, the amount of oxygen introduced into the insulating film 132 can be increased. .

[0221] Next, the detachment suppression film 113 is removed to form the insulating film 132 to which oxygen is added. This is possible (see Figure 11).

[0222] The insulating film 132 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The insulating film 132 can be formed by appropriately using a photolaser laser deposition (PLD) method, a printing method, a coating method, or the like. After the insulating film is formed, oxygen may be added to the insulating film. Radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. The methods include ion doping, ion implantation, plasma treatment, and the like.

[0223] In addition, the substrate placed in the evacuated processing chamber of the plasma CVD device is heated to 180°C or higher. The temperature is kept at 280°C or below, or between 200°C and 240°C, and the raw material gas is introduced into the treatment chamber. The pressure in the processing chamber should be between 100 Pa and 250 Pa, or between 100 Pa and 200 Pa. a or less, and the electrode installed in the treatment chamber is 0.17 W / cm 2 More than 0.5W / cm 2 below , or 0.25 W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: Therefore, a silicon oxide film or a silicon oxynitride film capable of releasing oxygen by heat treatment is formed. A silicon film can be formed as the insulating film 132.

[0224] Next, a mask is formed on the insulating film 132 by a lithography process, and then the mask is used to By etching a part of the insulating film 132 that overlaps with the lower electrode 104b, Form 102b.

[0225] Next, the oxide semiconductor film 126a and the oxide semiconductor film 126b are stacked over the insulating film 102b. Then, an oxide semiconductor film 126 containing the above compound is formed (see FIG. 12).

[0226] A method for forming the oxide semiconductor film 126 is described below. Tarring method, coating method, pulsed laser deposition method, laser ablation method, thermal CVD method, etc. Thus, the oxide semiconductor films 126a and 126b are formed. Next, a mask is formed over the oxide semiconductor film by a lithography process. By etching a part of the oxide semiconductor film using a The conductive film 126 can be formed. After that, the mask is removed. After the oxide semiconductor film 126 is formed by etching part of the film, heat treatment may be performed. .

[0227] In addition, by using a printing method for the oxide semiconductor film 126, an oxide semiconductor film having element separation can be formed. The membrane 126 can be formed directly.

[0228] When an oxide semiconductor film is formed by a sputtering method, a power source for generating plasma The device may be an RF power supply device, an AC power supply device, a DC power supply device, or the like. CAAC-OS films can be formed by using an AC or DC power supply. It is also possible to form an oxide semiconductor film by sputtering using an RF power supply. In contrast, an oxide semiconductor film is formed by a sputtering method using an AC power supply or a DC power supply. It is preferable to form the film having a uniform thickness, composition, or crystallinity. stomach.

[0229] The sputtering gas is a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen. In the case of a mixture of rare gas and oxygen, the amount of oxygen gas is appropriately adjusted relative to the amount of rare gas. A higher ratio is preferred.

[0230] The target may be appropriately selected depending on the composition of the oxide semiconductor film to be formed. .

[0231] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, Temperature: 150℃ to 750℃, 150℃ to 450℃, or 200℃ An oxide semiconductor film is formed at a temperature of 350° C. or lower to form a CAAC-OS film. In addition, by setting the substrate temperature at 25° C. or higher and lower than 150° C., it is possible to form a microcrystalline oxide semiconductor. A conductive film can be formed.

[0232] In order to form a CAAC-OS film, which will be described later, it is preferable to apply the following conditions: It is.

[0233] By suppressing the inclusion of impurities during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower or -100°C or lower is used.

[0234] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, or 100% by volume or more. %.

[0235] In addition, after the oxide semiconductor film is formed, heat treatment is performed to dehydrogenate or The temperature of the heat treatment is typically 150° C. or higher and lower than the substrate distortion point. Or, 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower.

[0236] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or The heating is performed in an inert gas atmosphere containing nitrogen, or after heating in an inert gas atmosphere, the heating is performed in an oxygen atmosphere. The inert atmosphere and oxygen atmosphere may contain hydrogen, water, etc. The treatment time is preferably from 3 minutes to 24 hours.

[0237] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0238] The oxide semiconductor film is formed while being heated, and after the oxide semiconductor film is formed, By performing heat treatment, the oxide semiconductor film is The hydrogen concentration is 5×10 19 atoms / cm 3 or less, or 1×10 19 atoms / c m 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 or less, or 5×10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 It can be as follows:

[0239] The deposition equipment using ALD can be used to form oxide semiconductor films, such as InGaZnO X (X>0) When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form InO Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gas are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, the InGaO2 layer InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. Alternatively, instead of O3 gas, H2O gas bubbled with an inert gas such as Ar may be used. However, it is preferable to use O3 gas that does not contain H. In(CH3) Instead of the gas In(C2H5)3, gas Ga(CH3)3 may be used. Alternatively, Ga(C2H5)3 gas may be used. Zn(CH3)2 gas may also be used. This is also fine.

[0240] Here, an oxide semiconductor film having a thickness of 35 nm is formed by a sputtering method. Heat treatment is performed to move oxygen contained in the insulating film 102b to the oxide semiconductor film. A mask is formed over the oxide semiconductor film, and part of the oxide semiconductor film is selectively etched. In this way, the oxide semiconductor film 126 is formed.

[0241] The heat treatment should be performed at a temperature between 350℃ and 650℃, or between 450℃ and 600℃. By performing the above process, it is possible to obtain an oxide semiconductor film in which the contents of hydrogen, water, and the like are reduced. That is, an oxide semiconductor film having a low impurity concentration and a low density of defect states can be formed. Cut.

[0242] Next, an insulating film and two conductive films are formed over the oxide semiconductor film 126 and the insulating film 102a. A mask is formed on the two conductive layers by a lithography process, and then the two conductive layers are formed by using the mask. By etching a part of the conductive film and insulating film of the layer, the gate electrode 114a and the upper electrode 1 14b, a gate insulating film 112a and an insulating film 112b are formed (see FIG. 13).

[0243] The insulating films that become the gate insulating film 112a and the insulating film 112b are formed by sputtering, CVD, etc. The gate electrode is formed by a method such as vacuum deposition, pulsed laser deposition (PLD), or thermal CVD. The two conductive layers that become the electrode 114a and the upper electrode 114b are formed by sputtering or vacuum deposition. The two-layer conductive film is formed by the above-mentioned pulsed laser deposition (PLD) method, thermal CVD method, etc. Instead of the forming method, electrolytic plating, printing, ink jet method, etc. may be used.

[0244] In addition, a tungsten film is formed as a two-layer conductive film using a deposition device that uses ALD. In this case, WF6 gas and B2H6 gas are repeatedly introduced in sequence to obtain the initial temperature. Then, WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. It should be noted that SiH4 gas may be used instead of B2H6 gas.

[0245] Although not shown, after the insulating film that becomes the gate insulating film 112a and the insulating film 112b is formed, An opening is provided in the insulating film and the insulating film 102, and the gate electrode 114a and the upper part are exposed through the opening. A two-layer conductive film that will become the electrode 114b is formed and etched to form the gate electrode 104a and the gate The electrodes 114a may be electrically connected.

[0246] Next, as shown in FIG. 13, the oxide semiconductor film 12 is formed by using the gate electrode 114a as a mask. As a result, the impurity element 142 is added to the gate electrode 114 in the oxide semiconductor film. The impurity element is added to the region not covered by a. In the oxide semiconductor film that is damaged by the above, defects, typically oxygen vacancies, are formed. When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed, hydrogen enters the oxygen vacancy sites and the conduction band is reduced. A donor level is formed adjacent to the first region 106, and a pair of second regions sandwiching the first region 106 are In the first region 106, the impurity This is a region to which no elements are added, and can be made to be highly pure intrinsic.

[0247] The impurity element 142 can be added by ion doping, ion implantation, plasma There are various processing methods.

[0248] The addition of the impurity element 142 is controlled by appropriately setting implantation conditions such as acceleration voltage and dose amount. For example, when argon is added by ion implantation, the acceleration voltage is 10 kV and the doping The amount of sugar is 1×10 13 ions / cm 2 More than 1×10 16 ions / cm 2 If we use the following Well, for example, 1 x 10 14 ions / cm 2 In addition, phosphorus can be implanted by ion implantation. When ions are added, the acceleration voltage is 30 kV and the dose is 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 For example, 1×10 15 ions / cm 2 This can be done as follows.

[0249] Note that instead of the impurity element 142, the oxide semiconductor film 126 is irradiated with ultraviolet light or the like to form an oxide semiconductor film. Alternatively, oxygen vacancies may be formed in the oxide semiconductor film 126. Oxygen vacancies may be formed in the oxide semiconductor film 126 by irradiation with xenon light.

[0250] Next, the insulating film 138 and the insulating film 148 are formed (see FIG. 15). The insulating film 148 may be produced by the same method as the insulating film 102a, the insulating film 132, etc. This can be done.

[0251] Next, a mask is formed on the insulating film 148 by a lithography process, and then the insulating film 138 and and a part of the insulating film 148 is etched to form a pair of second regions 107a and 107b. Two openings are formed to expose the insulating film 108 and the insulating film 118. (See Figure 16.)

[0252] Next, two layers of conductive films are formed on the insulating film 118 and the pair of second regions 107a and 107b. A mask is formed on the upper conductive film of the two conductive films by a lithography process, and then the two conductive films are The conductive film of the layer is partially etched to form the source electrode 116a and the drain electrode 116b. (See Figure 17.)

[0253] Next, an insulating film 128 is formed on the insulating film 118, the source electrode 116a, and the drain electrode 116b. Form.

[0254] Through the above steps, the transistor 150 and the capacitor 160 can be formed at the same time. Cut.

[0255] In addition, the connection of each wiring of the semiconductor device according to one embodiment of the present invention will be described below. do.

[0256] As shown in FIG. 19A, a gate electrode serving as a back gate electrode of a transistor 150 is The wiring 204 (conductive film 204a and conductive film 204) is formed in the same process as the gate electrode 104a. a stack of insulating films 102 and 112b) formed on the insulating film 102 and the insulating film 112a that will become the gate insulating film 112a; A mask is formed on the insulating layer by a lithography process, and then a part of the insulating layer is laminated using the mask. The wiring 204 is then etched to form an opening that reaches the wiring 204. The transistor 150 is A conductive film that will become the gate electrode 114a is formed, and a mask is formed on the conductive film by a lithography process. After forming the mask, the conductive film and a part of the insulating film that will become the gate insulating film 112a are The wiring 214 (a laminate of the conductive film 214a and the conductive film 214b) and the insulating film are removed by etching the wiring 214 (a laminate of the conductive film 214a and the conductive film 214b). Further, the insulating film 108 and the insulating film 118 are formed on the wiring 214 to form an insulating film. After forming a mask on the film 118 by a lithography process, the insulating film 10 is 8 and a part of the insulating film 118 are etched to provide an opening that reaches the wiring 214. A conductive film that will become the source electrode or drain electrode of the transistor 150 is formed through the conductive film. A mask is formed on the conductive film by a lithography process, and then a part of the conductive film is The resulting film is etched to form the wiring 216 (a stack of a conductive film 216a and a conductive film 216b). Through the above steps, the wiring 204 as shown in FIG. 19(A) is formed via the wiring 214. 216. In addition, a lithography process may be performed on the insulating layer. After forming a mask by a photolithography process, the insulating film 102b and the gate insulating film are After etching a part of the insulating film that will become 112a, the insulating film 102a, the insulating film 102b, and After forming a mask by a lithography process on the insulating film that will become the gate insulating film 112a, A part of the insulating film 102a is etched using a mask to provide an opening reaching the wiring 204. Good too.

[0257] In addition, the upper layer of the wiring 204 (conductive film 204b) and the upper layer of the wiring 216 (conductive film 216b) It is preferable to use a low resistance conductive material such as copper or aluminum. By using a highly conductive material, signal delay can be reduced.

[0258] Also, as shown in FIG. 19B, the wiring 214 is formed by the above-mentioned process on the insulating film 108 and The portion electrically connected to the wiring 216 through the opening provided in the insulating film 118 and the portion shown in FIG. As shown in FIG. 2, the wiring 204 is formed through the opening provided in the laminate of the insulating layers by the above-mentioned process. 12 and 13, the wiring 214 may be electrically connected to the wiring 214. The method of electrically connecting the gate electrode 104a and the gate electrode 114a described in FIG. The connection method in 9(C) can be used.

[0259] In this embodiment, the wiring 214 is wired through an opening provided in the laminate of the insulating layers. 204, and the wiring 204 and the wiring 216 are configured to cross each other. Therefore, as shown in FIG. 19(D), the insulating film 102 and the insulating film 103 are provided between the wiring 204 and the wiring 216. 108 and the insulating film 118, the parasitic capacitance at the intersection of the wirings is As a result, the signal delay due to the parasitic capacitance can be reduced. .

[0260] In this embodiment, when an oxide semiconductor film is used for a channel or the like, Although an example has been given, one aspect of the embodiment of the present invention is not limited thereto. For example, a channel or In the vicinity thereof, in the source region, the drain region, etc., depending on the circumstances, Therefore, Si (silicon), Ge (germanium), SiGe (silicon germanium), It may be formed of a material having, for example, GaAs (gallium arsenide).

[0261] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0262] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor included in a semiconductor device of one embodiment of the present invention will be described. He explains.

[0263] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, etc.

[0264] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductor, and nc-OS.

[0265] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. In other words, it is a structure that has discrete order but does not have long-range order.

[0266] On the other hand, in the case of an essentially stable oxide semiconductor, In addition, it cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor is then turned into a completely amorphous oxide semiconductor (e.g., a semiconductor having a periodic structure in a microscopic region). However, a-like OS is a semiconductor that can be used in a small area. Although it has a periodic structure, it has voids and is an unstable structure. In terms of physical properties, it can be said that the semiconductor is close to an amorphous oxide semiconductor.

[0267] <caac-os> First, let me explain about CAAC-OS.

[0268] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0269] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly confirm the presence of the CAAC-OS at the grain boundaries. It can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0270] The following describes the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. , specifically called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images are obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0271] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 20(A) is shown in Figure 20(B). From FIG. 20(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0272] As shown in FIG. 20(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of a single pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the inclination between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS is also used as a C-Axis Aligned Nanoclip The semiconductor may also be referred to as an oxide semiconductor having metal ions.

[0273] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 6120 were The layout of the 6100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 20(D)). Between the pellets observed in FIG. 20(C), The portion where the inclination occurs corresponds to the area 6161 shown in FIG.

[0274] FIG. 21(A) shows the C 21(A) shows the s-corrected high-resolution TEM images of regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 21(B), (C) and (D), respectively. As shown in Figure 21(D), Figure 21(B), Figure 21(C) and Figure 21(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0275] Next, C was analyzed by X-ray diffraction (XRD). We will explain AAC-OS. For example, CAAC-O with InGaZnO4 crystals When the out-of-plane structural analysis is performed on S, the result is as shown in Figure 22(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal has a c-axis orientation. It can be seen that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface on which the crystal is formed or to the upper surface.

[0276] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0277] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I It is attributed to the (110) plane of the crystal of nGaZnO4. In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in FIG. On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 22(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0278] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the InGaZnO4 The spots due to the (009) plane of the crystal are included. Therefore, even by electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. 3(B), a ring-shaped diffraction pattern is confirmed. Therefore, electron diffraction also It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. In addition, the first ring in FIG. 23(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface, etc.

[0279] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0280] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0281] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0282] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than 100 Such an oxide semiconductor can be a high-purity intrinsic or The CAAC-OS is essentially a high-purity intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0283] <nc-os> Next, we will explain nc-OS.

[0284] In the high-resolution TEM image, the nc-OS is divided into two regions: one where the crystals can be confirmed, and the other where the clear The crystalline parts in nc-OS are In most cases, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible in the pellets of CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0285] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, the nc-OS may be a pellet with a larger diameter than the pellet. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, the probe diameter is larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction was performed on nc-OS, high brightness regions were observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. There may be cases where this occurs.

[0286] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0287] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0288] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0289] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen, and areas where crystals can be seen. and areas where it is not possible to

[0290] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0291] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0292] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0293] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the crystals is 0.28 nm to 0.30 nm are considered to be crystal parts of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0294] Figure 24 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in FIG. 24, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was 4.2×10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 24, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that.

[0295] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0296] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0297] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0298] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density equivalent to that of a single crystal of the desired composition can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate the size of the single crystal by combining different types of single crystals.

[0299] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0300] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0301] (Embodiment 3) In this embodiment, a deposition model of the CAAC-OS and the nc-OS will be described.

[0302] FIG. 46A shows a process of forming a CAAC-OS film by a sputtering method. FIG. 1 is a schematic diagram of the inside of a membrane chamber.

[0303] The target 630 is bonded onto a backing plate. A plurality of magnets are disposed under the backing plate. A magnetic field is generated above the target 630. The film deposition rate is increased by using the magnetic field of the magnet. The sputtering method that enhances this is called magnetron sputtering.

[0304] The target 630 has a polycrystalline structure, and each crystal grain includes a cleavage plane. The cleavage plane will be described in detail later.

[0305] The substrate 620 is disposed so as to face the target 630, and the distance therebetween is d ( The get-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the deposition chamber is 0.02m to 0.5m. Most of the deposition gas (e.g., oxygen) is , argon, or a mixture of gases containing 50% or more by volume of oxygen) and The pressure is controlled to be 0.1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage or more to the target 630, discharge begins and plasma is observed. In addition, a high density plasma region is formed by the magnetic field above the target 630. In the high density plasma region, the deposition gas is ionized to generate ions 601. The ion 601 is, for example, an oxygen cation (O + ) and argon cations (Ar + ) etc. do.

[0306] The ions 601 are accelerated toward the target 630 by the electric field, and eventually reach the target 63 At this time, pellets, which are sputtered particles in the shape of plates or pellets, are ejected from the cleavage plane. The pellet 600a and the pellet 600b are peeled off and knocked out. The pellet 600b may be distorted in structure due to the impact of the ion 601. There is.

[0307] The pellet 600a is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. The pellet 600b is a sputtered particle. The pellet 600b has a hexagonal, for example, regular hexagonal, plane. The pellets 600a and 600b are sputtered particles in the form of flat plates or pellets. The plate-like or pellet-like sputtered particles such as 600b are collectively referred to as pellets 600. The planar shape of the pellet 600 is not limited to a triangle or a hexagon. For example, For example, two triangles (equilateral triangles) may be combined to form a shape with six or fewer elements. Sometimes it may be a rectangular shape (diamond).

[0308] The thickness of the pellet 600 is determined according to the type of deposition gas, etc. The reason for this will be described later. It is preferable that the thickness of the pellet 600 is uniform. Pellets are preferred over thick cubes.

[0309] The pellet 600 receives an electric charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 600 has oxygen atoms on the side, and the oxygen atoms are negatively charged. For example, pellet 600a may have negatively charged oxygen atoms on its sides. An example of this is shown in Figure 48. In this way, the sides are charged with the same polarity, This causes a repulsion between the two, allowing the plate-like shape to be maintained. In the case of In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. Or, oxygen bonded to an indium atom, a gallium atom, or a zinc atom Atoms can become negatively charged.

[0310] As shown in FIG. 46(A), for example, a pellet 600 flies like a kite through the plasma. The pellet 600 then flutters up onto the substrate 620. Therefore, when an area where other pellets 600 are already deposited approaches, a repulsive force is generated. On the upper surface of the substrate 620, a magnetic field is generated in a direction parallel to the upper surface of the substrate 620. A potential difference is applied between the plate 620 and the target 630, so that the A current flows toward the target 630. Thus, the pellet 600 is immersed in the substrate 62. The upper surface of 0 is subjected to a force (Lorentz force) due to the action of a magnetic field and an electric current (Figure 4 9.) This can be understood by Fleming's left-hand rule. In order to increase the force applied to the substrate 600, the upper surface of the substrate 620 is The magnetic field parallel to the magnet should be 10 G or more, preferably 20 G or more, and more preferably 30 G or more. More preferably, a region where the resistance is 50 G or more is provided. In this case, the magnetic field parallel to the upper surface of the substrate 620 is larger than the magnetic field perpendicular to the upper surface of the substrate 620. 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more It is a good idea to set up an upper area.

[0311] In addition, the substrate 620 is heated, and friction between the pellet 600 and the substrate 620 is prevented. As a result, as shown in FIG. 50(A), the pellet 600 The pellet 600 glides over the top surface of the substrate 620. This occurs in a state facing the plate 620. Then, as shown in FIG. 50(B), When the pellet reaches the side of another pellet 600, the sides join together. The oxygen atom on the side of 600 is released. The released oxygen atom causes the Since the oxygen vacancies in the CAAC-OS can be filled, the CAAC-OS has a low density of defect states.

[0312] In addition, when the pellet 600 is heated on the substrate 620, the atoms are rearranged and the ions are The distortion of the structure caused by the collision of the pellet 601 is relieved. The pellet 600 with the relieved distortion is The pellets 600 become almost single crystals. Even if the pellet 600 is heated after bonding, the pellet itself is unlikely to expand or contract. Therefore, the gaps between the pellets 600 widen, forming defects such as grain boundaries, and the cracks The gaps are filled with elastic metal atoms, It is thought that the sides of the misaligned pellets 600 are connected together like a highway.

[0313] Based on the above model, it is considered that the pellet 600 accumulates on the substrate 620. Therefore, unlike epitaxial growth, when the surface on which the film is to be formed does not have a crystal structure, For example, the CAAC-OS film can be formed on the upper surface of the substrate 620. Even if the structure of the surface to be formed is amorphous, it is possible to form a CAAC-OS film. do.

[0314] In addition, the CAAC-OS can be formed not only on a flat surface but also on the top surface of the substrate 620. Even if the surface is uneven, the pellets 600 are aligned along the surface shape. For example, if the top surface of the substrate 620 is atomically flat, the pellet 600 will have a flat surface parallel to the ab plane. The flat surfaces are arranged side by side with the plate surface facing downwards, resulting in a uniform thickness, flatness, and high crystallinity. A layer is formed. Then, the layers are stacked n levels (n is a natural number), and the CAAC- The OS can be obtained (see FIG. 46(B)).

[0315] On the other hand, even if the upper surface of the substrate 620 has unevenness, the CAAC-OS can form the pellet 600 The structure is made up of n layers (n is a natural number) of layers arranged side by side along the convex surface. Since the surface of the pellet 600 is uneven, gaps may easily occur between the pellets 600 in the CAAC-OS. However, intermolecular forces act between the pellets 600, so even if there are irregularities, there are no gaps between the pellets. Therefore, CA has high crystallinity even if it has unevenness. This can be AC-OS (see Figure 46(C)).

[0316] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if the thickness is small, a uniform film can be formed.

[0317] Since the CAAC-OS film is formed by such a model, the sputtered particles are distributed evenly throughout the film. It is preferable that the sputtered particles are in the form of thick pellets. In this case, the surface facing the substrate 620 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0318] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface having an amorphous structure. Thus, a CAAC-OS having the above properties can be obtained.

[0319] In addition to the pellet 600, CAAC-OS also has a coating model with zinc oxide particles. This can also be explained.

[0320] The zinc oxide particles have a smaller mass than the pellets 600 and therefore reach the substrate 620 first. On the upper surface of the substrate 620, zinc oxide particles grow preferentially in the horizontal direction. A thin zinc oxide layer is formed. The zinc oxide layer has a c-axis orientation. The c-axis of the crystal is oriented parallel to the normal vector of the substrate 620. The crystallinity of CAAC-OS was improved by acting as a seed layer for the growth of AC-OS. The zinc oxide layer has a thickness of 0.1 nm to 5 nm, and is almost The zinc oxide layer is thin enough that the grain boundaries are almost completely defined. It cannot be acknowledged.

[0321] Therefore, in order to form a CAAC-OS film with high crystallinity, the composition should be more favorable than the stoichiometric composition. It is preferred to use a target containing a high percentage of zinc.

[0322] Similarly, the nc-OS can be understood by the film formation model shown in FIG. The only difference between FIG. 47 and FIG. 46(A) is whether or not the substrate 620 is heated.

[0323] Therefore, the substrate 620 is not heated, and friction between the pellet 600 and the substrate 620 occurs. As a result, the pellet 600 is in a state where the resistance to friction and the like is large. Since it cannot glide across the surface, it accumulates irregularly. -OS can be obtained.

[0324] <cleavage plane> Below, we explain the cleavage plane of the target described in the CAAC-OS deposition model. Reveal.

[0325] First, the cleavage plane of the target will be explained using FIG. 51. The crystal structure of nO4 is shown in Fig. 51(A). Note that the c-axis is oriented upward and parallel to the b-axis. The structure of the InGaZnO4 crystal is shown when observed from the c direction. The structure of an InGaZnO4 crystal observed from a direction parallel to the axis is shown.

[0326] The energy required for cleavage on each crystal plane of an InGaZnO4 crystal was calculated using first-principles calculations. The calculation is performed using pseudopotentials and density functionals using a plane wave basis. The pseudopotential used is the ultrasoft type pseudopotential. The potential is used. The functional is GGA PBE. The cutoff is The energy is set to 400 eV.

[0327] The energy of the initial structure was derived after structural optimization including the cell size. In addition, the energy of the structure after cleavage on each plane is expressed as the atomic ratio with the cell size fixed. It is derived after performing structural optimization of the arrangement.

[0328] Based on the crystal structure of InGaZnO4 shown in Figure 51, the first plane, the second plane, and the third plane A structure cleaved at either the first or fourth plane was created, and the cell size was fixed and structural optimization calculations were performed. Here, the first plane is a crystal plane between the Ga-Zn-O layer and the In-O layer, ( The second plane is a crystal plane parallel to the (001) plane (or ab plane) (see Figure 51(A)). , the crystal plane between the Ga-Zn-O layer and the Ga-Zn-O layer, and the (001) plane (or a The third plane is parallel to the (110) plane (see Figure 51(A)). (See Figure 51(B)). The fourth plane is the (100) plane (or bc plane). The crystal planes are parallel (see Figure 51(B)).

[0329] Under the above conditions, the energy of the structure after cleavage on each plane is calculated. The difference between the energy of the structure and the energy of the initial structure is divided by the area of ​​the cleavage plane. The cleavage energy, which is a measure of the ease of cleavage on each plane, is calculated. Energy is the kinetic energy of the electrons and the interatomic and atomic energies of the atoms and electrons contained in the structure. This energy takes into account interactions between electrons and between electrons.

[0330] The calculation results show that the cleavage energy of the first face is 2.60 J / m 2 , the cleavage energy of the second face -0.68J / m 2 , the cleavage energy of the third face is 2.18 J / m 2 , cleavage of the fourth plane Energy is 2.12J / m 2 It was found that (see table below).

[0331] [Table 3]

[0332] From this calculation, in the structure of the InGaZnO4 crystal shown in Figure 51, The cleavage energy is the lowest at the Ga-Zn-O layer and the Ga-Zn-O layer. It can be seen that the plane (cleavage plane) between the two is the easiest to cleave. When referred to as a cleavage plane, it refers to the second plane, which is the plane that is most likely to cleave.

[0333] Since the cleavage plane is on the second plane between the Ga-Zn-O layers, The InGaZnO4 crystal shown in 51(A) is separated by a plane equivalent to the two second planes. Therefore, when ions or the like are bombarded with a target, the highest cleavage energy is obtained. The wafer-like units (which we call pellets) cleaved from the lower surface of the ghee are the best. It is thought that the InGaZnO4 pellets will fly out in small units. The result is three layers: a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer.

[0334] The first plane (a crystal plane between the Ga-Zn-O layer and the In-O layer, which is a (001) plane) (or ab-plane)), the third plane (a crystal plane parallel to the (110) plane), The cleavage energy of the fourth plane (a crystal plane parallel to the (100) plane (or bc plane)) is low. This suggests that the planar shape of the pellets is often triangular or hexagonal.

[0335] Next, classical molecular dynamics calculations were performed to determine the homologous structure of the target InGa Assuming a ZnO4 crystal, the target is sintered with argon (Ar) or oxygen (O). The cleavage plane of the InGaZnO4 crystal (26 The cross-sectional structure of the 88-atom GaN crystal is shown in FIG. 52(A), and the top view structure is shown in FIG. 52(B). The fixed layer shown in (A) is a layer in which the arrangement of atoms is fixed so that the positions do not fluctuate. The temperature control layer shown at 52(A) is a layer that is always kept at a constant temperature (300K).

[0336] For classical molecular dynamics calculations, Fujitsu Ltd.'s Materials Explorer 5 was used. The initial temperature is 300K, the cell size is constant, and the time step size is 0.01f. The time is set to femtoseconds and the number of steps is set to 10 million. In the calculation, under these conditions, 300 eV of energy is applied, and atoms are injected into the cell from a direction perpendicular to the ab plane of the InGaZnO4 crystal. is incident.

[0337] FIG. 53(A) shows the state where argon is introduced into the cell having the InGaZnO4 crystal shown in FIG. Fig. 53(B) shows the atomic arrangement 99.9 picoseconds (psec) after irradiation. The atomic arrangement shown in Figure 53 is 99.9 picoseconds after oxygen is injected into the hole. A part of the fixing layer shown in (A) is omitted.

[0338] From Figure 53(A), within 99.9 picoseconds after argon enters the cell, the ) the cracks occur from the cleavage plane corresponding to the second plane shown in Fig. 1. Therefore, InGaZnO4 When argon collides with a crystal of the above, if the top surface is the second surface (0th), the second surface ( It can be seen that a large crack occurs in the second part.

[0339] On the other hand, from FIG. 53(B), within 99.9 picoseconds after oxygen enters the cell, the It can be seen that the cracks originate from the cleavage plane corresponding to the second plane shown in A). In the event of a collision, a large crack will occur on the second (first) surface of the InGaZnO4 crystal. You can see that this is happening.

[0340] Therefore, the top surface of the target containing InGaZnO4 crystals having a homologous structure When atoms (ions) collide with the InGaZnO4 crystal, it cleaves along the second plane, It can be seen that flat particles (pellets) peel off. At this time, the size of the pellets It was found that the collision with oxygen was smaller than that with argon. Light.

[0341] The above calculations suggest that the detached pellet contains a damaged area. Damaged areas in the matrix can be repaired by reacting oxygen with the defects caused by the damage. There are cases.

[0342] Therefore, we investigated whether the pellet size differs depending on the type of atoms collided. do.

[0343] In FIG. 54(A), argon is introduced into the cell having the InGaZnO4 crystal shown in FIG. The trajectory of each atom from 0 picoseconds to 0.3 picoseconds after irradiation is shown in Fig. 54(A) corresponds to the period between FIG. 52 and FIG. 53(A).

[0344] As shown in Figure 54(A), argon collides with gallium (Ga) in the first layer (Ga-Zn-O layer). Then, after the gallium collides with the zinc (Zn) in the third layer (Ga-Zn-O layer), It can be seen that zinc reaches the vicinity of the sixth layer (Ga-Zn-O layer). The colliding argon is repelled out. Therefore, the crystals of InGaZnO4 are When argon is bombarded against the target, a turtle is formed on the second surface (second) in Figure 52(A). It is thought that cracks will occur.

[0345] In addition, in FIG. 54(B), oxygen is added to the cell having the InGaZnO4 crystal shown in FIG. The trajectory of each atom from 0 picoseconds to 0.3 picoseconds after injection is shown. Therefore, FIG. 54(B) corresponds to the period between FIG. 52 and FIG. 53(A).

[0346] On the other hand, as shown in FIG. 54(B), oxygen collides with gallium (Ga) in the first layer (Ga-Zn-O layer). When the gallium collides with the zinc (Zn) in the third layer (Ga-Zn-O layer), It can be seen that the zinc does not reach the fifth layer (In-O layer). Oxygen is expelled out. Therefore, the target containing InGaZnO4 crystals When oxygen is bombarded, it is believed that a crack will appear on the second surface (first surface) in FIG. 52(A). can be.

[0347] This calculation also shows that when atoms (ions) collide with InGaZnO4 crystals, the cleavage plane It is suggested that the material peels off from the surface.

[0348] In addition, we consider the difference in crack depth from the viewpoint of conservation laws. The conservation laws can be expressed as Equations 4 and 5. Here, E is the Argo The energy of neutrons or oxygen (300 eV), m A is the mass of argon or oxygen, v A is the velocity of argon or oxygen before the collision, v' A is the velocity of argon or oxygen after the collision, m Ga is the mass of gallium, v Ga is the velocity of gallium before the collision, v' Ga is the gallium after the collision is the speed.

[0349]

number

[0350]

number

[0351] Assuming that the collisions of argon or oxygen are elastic, v A , v' A , v Ga Oh Bi'v' Ga The relationship can be expressed as in Equation 6.

[0352]

number

[0353] From Equation 4, Equation 5 and Equation 6, v Ga If you set it to 0, argon or oxygen will collide. The velocity of gallium after the Ga can be expressed as in Equation 7.

[0354]

number

[0355] In Formula 7, m A Substitute the mass of argon or the mass of oxygen into and find Compare the velocity of gallium after the collision. The energies of argon and oxygen before the collision When the collision rate is the same, the collision rate of argon is 1.24 times higher than that of oxygen. Therefore, the energy of gallium is also higher than that of Argon. When an atom collides with another atom, the velocity is squared higher than when an oxygen atom collides with another atom.

[0356] When argon was bombarded, the amount of gallium after the bombardment was greater than when oxygen was bombarded. Therefore, when argon is collided, It is believed that cracks occurred at deeper positions in the case of bombardment with oxygen than in the case of bombardment with oxygen.

[0357] From the above calculations, it was found that the target containing InGaZnO4 crystals with a homologous structure When sputtering, it peels off from the cleavage plane and forms a pellet. Sputtering areas of other structures on the target that do not have a surface will not form pellets. The sputtered particles are formed in a size on the atomic level, which is smaller than the size of the sputtered particles. Because it is smaller than a pellet, it can be vacuum pumped through the sputtering device. Therefore, the crystal of InGaZnO4 with homologous structure When a target containing Zn is sputtered, particles of various sizes and shapes fly to the substrate and accumulate. It is difficult to imagine a model in which a film is formed by deposition of sputtered pellets. The model for forming a C-OS film shown in Figure 46(A) is reasonable.

[0358] The density of the CAAC-OS film thus formed is comparable to that of single-crystal OS. For example, the density of a single crystal OS with a homologous structure of InGaZnO4 is 6.36g. / cm 3 The density of CAAC-OS, which has a similar atomic ratio, is 6.3 g / c m 3 It will be about that amount.

[0359] Figure 55 shows the In-Ga-Zn oxide, a CAAC-OS film formed by sputtering. (See FIG. 55(A)) and the cross section of the target (See FIG. 55(B)). The atomic arrangement is shown. The atomic arrangement was observed using high-angle annular dark-field scanning transmission electron microscopy (HA ADF-STEM:High-Angle Annular Dark Field S canning Transmission Electron Microscopy In HAADF-STEM, the image intensity of each atom is proportional to the square of the atomic number. Therefore, Zn (atomic number 30) and Ga (atomic number 31), which have similar atomic numbers, The HAADF-STEM uses a Hitachi HD-27 scanning transmission electron microscope. Use 00.

[0360] Comparing Figure 55(A) and Figure 55(B), the CAAC-OS and the target are Both have homologous structures, and it can be seen that the arrangement of their atoms corresponds to each other. Therefore, as shown in the deposition model in Figure 46(A), the crystal structure of the target is transformed. The image shows that a CAAC-OS film is formed.

[0361] (Embodiment 4) In this embodiment, one embodiment of a light-emitting device using a semiconductor device according to one embodiment of the present invention will be described. In this embodiment, the structure of a pixel portion of a light-emitting device will be described with reference to FIG. B) will be used to explain.

[0362] In FIG. 25A, a plurality of FETs 500 are formed on a first substrate 502. The ET 500 is electrically connected to each light emitting element (504R, 504G, 504B, 504W). Specifically, the first conductive film 506 of each FET 500 and the light emitting element are electrically connected to each other. Each of the light emitting elements (504R, 504G, 504B, 504W) is , the first conductive film 506, the second conductive film 507, the EL layer 510, and the third conductive film 512. It is thus constituted.

[0363] In addition, at positions facing each of the light emitting elements (504R, 504G, 504B, 504W), Each of the color layers (514R, 514G, 514B, 514W) is provided. The color layers (514R, 514G, 514B, 514W) are in contact with the second substrate 516. A sealing film 518 is provided between the first substrate 502 and the second substrate 516. The sealing film 518 is formed of, for example, a glass material such as glass frit, Two-part resins that cure at room temperature, photocurable resins, thermosetting resins, etc. The above resin materials can be used.

[0364] In addition, the partition wall 5 is formed so as to cover the ends of the first conductive film 506 and the second conductive film 507 adjacent to each other. A structure 509 is provided on the partition wall 508. The first conductive film 506 functions as a reflective electrode and as an anode of the light-emitting element. In addition, the second conductive film 507 has a function of adjusting the optical path length of each light-emitting element. An EL layer 510 is formed on the second conductive film 507, and a third The third conductive film 512 is formed as a semi-transmissive and semi-reflective electrode. The structure 509 functions as a light-emitting element and as a cathode of the light-emitting element. It is provided between the colored layers and functions as a spacer.

[0365] In addition, the EL layer 510 is formed by applying the same to each of the light-emitting elements (504R, 504G, 504B, 504 The light emitting elements (504R, 504G, 504B) can be used in common. , 504W) are formed by the first conductive film 506 and the third conductive film 512 from the EL layer 510. It has a micro-optical resonator (also called a microcavity) structure that resonates light emission. Even if the EL layer 510 is included, it is possible to narrow the spectrum of light of different wavelengths and extract it. Specifically, each light-emitting element (504R, 504G, 504B, 504W) has an EL layer By adjusting the thickness of the second conductive film 507 provided below 510, The spectrum obtained from the EL layer 510 is a desired emission spectrum, and light emission with good color purity is obtained. Therefore, by using the structure shown in FIG. 25(A), the coating of the EL layer This eliminates the need for a separation process, making it easier to achieve high resolution.

[0366] The light-emitting device shown in FIG. 25(A) has a colored layer (color filter). By combining the microcavity structure with a color filter, the color purity can be further improved. Specifically, the light emitting element 504R emits red light. The optical path length of the light emitting element is adjusted so that red light passes through the colored layer 514R in the direction of the arrow. The light emitting element 504G emits light of a green color. The path length is adjusted, and green light is emitted in the direction of the arrow through the colored layer 514G. In addition, the light path length of the light-emitting element 504B is adjusted so that blue light can be emitted. The blue light is emitted in the direction of the arrow through the colored layer 514B. The optical path length of the light emitting element is adjusted so that white light is emitted. White light is emitted in the direction of the arrow.

[0367] The method of adjusting the optical path length of each light-emitting element is not limited to the above. In the optical element, the thickness of the EL layer 510 may be adjusted to adjust the optical path length.

[0368] The colored layers (514R, 514G, 514B) transmit light of a specific wavelength band. For example, a red (R) color filter that transmits light in the red wavelength range is sufficient. -Filter, green (G) color filter that transmits light in the green wavelength band, blue wave A blue (B) color filter that transmits long-band light can be used. The colored layer 514W may be made of, for example, an acrylic resin material that does not contain a pigment. The colored layers (514R, 514G, 514B, 514W) can be made of various materials. Printing, inkjet printing, photolithography etching, etc. It can be formed.

[0369] The first conductive film 506 is, for example, a conductive film having a high reflectance (a reflectance of visible light of 40% or more). A metal film having a thickness of 100% or less, preferably 70% or more and 100% or less, can be used. The conductive film 506 is made of aluminum, silver, or an alloy containing these metal materials (e.g., For example, an alloy of silver, palladium, and copper) can be formed as a single layer or a multilayer.

[0370] The second conductive film 507 is formed using, for example, a conductive metal oxide. Conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium oxide. Indium Tin Oxide (also known as ITO), Indium Zinc Lead oxide (Indium Zinc Oxide) or these metal oxide materials with acid The second conductive film 50 may contain silicon oxide or tungsten oxide. 7 is provided between the EL layer 510 to be formed later and the first conductive film 506. This is advantageous because it can suppress the generation of an insulating film formed on the first conductive film 50. A conductive metal oxide used as the second conductive film 507 may be formed under the layer 6 .

[0371] The third conductive film 512 is made of a conductive material having a reflectivity and a conductive material having a light-transmitting property. The reflectance of visible light is 20% or more and 80% or less, preferably 40% or more. The third conductive film 512 is preferably made of, for example, silver, magnesium, or the like. A thin layer (e.g., 10 nm or less) of a metal or an alloy containing these metal materials is formed, and After that, a conductive metal oxide that can be used for the second conductive film 507 may be formed.

[0372] In the above-described configuration, the structure for extracting light emission on the second substrate 516 side (top end) is used. The light emitting device has a structure of a light emitting diode (mission structure). The first substrate 501 on which the FET 500 is formed is A structure in which light is extracted from the first substrate 501 side (bottom emission structure), or a structure in which light is extracted from the first substrate 501 side and the second substrate 502 side The light emitting device has a structure (dual emission structure) in which light is extracted from both sides of the substrate 516. In the case of a bottom emission structure, for example, the colored layers (514R, 514G, 51 4B, 514W) may be formed below the first conductive film 506. A light-transmitting substrate may be used for the substrate on the light-emitting side, and a transparent substrate may be used for the substrate on the non-light-emitting side. Both light-transmitting and light-shielding substrates can be used.

[0373] In FIG. 25(A), the light emitting elements are four colors (red (R), green (G), blue (B), and white However, the present invention is not limited to this. For example, the light emitting element may have three colors (red, (R), green (G), and blue (B).

[0374] Here, the connection relationship between each light emitting element and each FET will be described in detail with reference to FIG. FIG. 25B shows one example of the configuration of the area 520 surrounded by the dashed line shown in FIG. Here is an example.

[0375] In FIG. 25B, an insulating film 522 that functions as a planarizing film is formed on the FET 500. The insulating film 522 is provided with a source electrode or a drain electrode of the FET 500. An opening 524 is formed on the insulating film 522, which reaches the conductive film. A first conductive film is connected to the conductive film that functions as the source electrode or drain electrode of the ET500. A first conductive film 506 is formed on the first conductive film 506. A second conductive film 507 is formed on the first conductive film 506. has been formed.

[0376] The FET 500 has the same configuration as the transistor 150 shown in the previous embodiment. Therefore, the description here is omitted.

[0377] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. There can be.

[0378] (Embodiment 5) In this embodiment, the transistor and the capacitor described in the previous embodiment are used. An example of such a display device will be described below with reference to FIGS.

[0379] 26 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver is provided on the first substrate 701. A pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, A sealant 712 is disposed so as to surround the path portion 704 and the gate driver circuit portion 706. and a second substrate 705 disposed so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 26, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0380] The display device 700 is surrounded by a sealant 712 on the first substrate 701. A pixel section 702, a source driver circuit section 704, and a gate driver circuit section 705 are arranged in a region different from the region. The flexible printed circuit (FPC) terminal section 708 is electrically connected to the flexible printed circuit (FPC) circuit section 706. In addition, the FPC terminal portion 708 is provided with an FP The pixel section 702 and the source driver circuit section 704 are connected by the FPC 716. Various signals are supplied to the pixel portion 702, the switch portion 703, and the gate driver circuit portion 706. The base driver circuit section 704, the gate driver circuit section 706, and the FPC terminal section 708 are Various signals supplied by the FPC 716 are A pixel section 702, a source driver circuit section 704, a gate driver circuit section 705, and a portion 706, and an FPC terminal portion 708.

[0381] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0382] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit portion 706 includes a plurality of transistors. In addition, in the pixel portion 702, a transistor according to the present invention can be used. A transistor and a capacitor which are the semiconductor device of one embodiment of the present invention can be used.

[0383] The display device 700 can also include various elements. The elements can include, for example, liquid crystal Elements, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) etc.), transistors (transistors that emit light according to current), electron emitters, electron insulators , electrophoretic element, grating light valve (GLV), plasma display (P Display elements using DP, MEMS (Micro-Electro-Mechanical Systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter ), MIRASOL (registered trademark), IMOD (Interference Modulation ) element, shutter type MEMS display element, optical interference type MEMS display element, elect Rougheting element, piezoelectric ceramic display, carbon nanotube display In addition to these, the device has at least one of an electric or magnetic function. The display medium may have a contrast, brightness, reflectance, transmittance, etc. that change depending on the display device. An example of a display device using an EL element is an EL display. An example of a display device using electrons is a field emission display (FED). or SED type flat panel display (SED: Surface-conduction Display using liquid crystal elements. An example of a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Spray, reflective LCD, direct-view LCD, projection LCD An example of a display device using electronic ink or electrophoretic elements is the electronic pen. In addition, there are also other LCDs that can realize semi-transmissive LCDs and reflective LCDs. In this case, a part or the whole of the pixel electrode is made to function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0384] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel of white (W). As in the column, two colors of RGB compose one color element, and two different colors are created by the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be selected for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used with monochrome displays. The present invention can also be applied to display devices such as those shown in FIG.

[0385] In this embodiment, a liquid crystal element and an EL element are used as display elements. 27 and 28. Note that FIG. 27 shows the area indicated by the dashed line QR in FIG. FIG. 28 is a cross-sectional view of the liquid crystal display device shown in FIG. 26, which is a cross-sectional view taken along the dashed line QR, and shows a configuration in which an EL element is used as a display element. It is.

[0386] First, the common parts shown in FIG. 27 and FIG. 28 will be explained, and then the different parts will be explained. This will be explained below.

[0387] <Explanation of common parts of display device> The display device 700 shown in FIG. 27 and FIG. 28 includes a wiring portion 711 and a pixel portion 702. The display panel 700 includes a source driver circuit section 704 and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Yes.

[0388] Transistor 750 and transistor 752 are similar to transistor 150 shown above. The structures of the transistors 750 and 752 are the same as those described above. Any other transistors than those shown in the embodiment modes may be used.

[0389] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. Therefore, the retention time of electric signals such as image signals can be extended, and the power supply When the write interval is on, it is possible to set it longer. This reduces the frequency of refresh operations. This has the effect of reducing power consumption.

[0390] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section In other words, the driver transistor can be formed on the same substrate as the driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, a high quality image can be provided.

[0391] The capacitance element 790 has a similar configuration to the capacitance element 160 shown above.

[0392] 27 and 28, a transistor 750, a transistor 752, and a capacitor An insulating film 766 and a planarizing insulating film 770 are provided on the capacitor 790 .

[0393] The insulating film 766 can be formed using a material and a method similar to those of the insulating film 128 in the above embodiment. The planarization insulating film 770 can be formed by a method. Acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, epoxy Heat-resistant organic materials such as epoxy resins can be used. The planarization insulating film 770 may be formed by stacking a plurality of insulating films. The planarizing insulating film 770 does not necessarily have to be provided.

[0394] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 75. 0, 752 source electrode and drain electrode, a conductive film formed in a different process, for example, A conductive film functioning as the first gate electrode or a conductive film functioning as the second gate electrode is used. For example, when a material containing copper is used for the signal line 710, the wiring resistance There is little signal delay caused by this, making it possible to display on a large screen.

[0395] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the drain electrode. The terminal of the PC 716 is electrically connected via an anisotropic conductive film 780 .

[0396] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0397] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778.

[0398] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738, and a film that contacts the colored film 736 An insulating film 734 is provided.

[0399] <Example of the configuration of a display device using a liquid crystal element as a display element> The display device 700 shown in FIG. 27 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is a second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. By controlling the light transmission or non-transmission, an image can be displayed.

[0400] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. and displays the reflected light through the colored film 736, that is, the so-called reflective color liquid crystal display device.

[0401] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0402] In the display device 700 shown in FIG. 27, the planarization insulating film 770 of the pixel section 702 The unevenness is formed in a part of the insulating film 770 by, for example, forming an organic resin film. The reflecting current can be formed by forming a reflecting current on the surface of the organic resin film. The conductive film 772, which functions as an electrode, is formed along the above-mentioned unevenness. When light enters the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772. This makes it possible to improve visibility.

[0403] The display device 700 shown in FIG. 27 is a reflective color liquid crystal display device. However, the present invention is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. A transmissive color liquid crystal display device may be formed by using the above-mentioned. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0404] Although not shown in FIG. 27, the conductive films 772 and 774 on the side in contact with the liquid crystal layer 776 In addition, although not shown in FIG. Optical members (optical substrates) such as optical members, phase difference members, and anti-reflection members may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Crites, sidelights, etc. may also be used.

[0405] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0406] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in the liquid crystal layer. It has a short response time, is optically isotropic so no alignment treatment is required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. It is possible to prevent electrostatic damage caused by electrostatic discharge, and thus to prevent defects in liquid crystal display devices during the manufacturing process. Damage can be reduced.

[0407] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0408] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The liquid crystal display device may be a transmission type liquid crystal display device. There are several types of vertical alignment modes, including: For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV mode, etc. can be used.

[0409] <Display device using light-emitting elements as display elements> The display device 700 shown in FIG. 28 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. do.

[0410] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one of the electrodes of the display element. In the above, a conductive film that transmits light or a conductive film that reflects visible light can be used. Examples of conductive films that are transparent to visible light include indium (In), zinc (Zn), and ZnO. It is recommended to use a material containing one of the following elements: Zn (Zn) or tin (Sn). The reflective conductive film may be made of a material containing aluminum or silver. stomach.

[0411] In addition, in the display device 700 shown in FIG. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0412] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0413] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0414] (Embodiment 6) In this embodiment, a structure example of a display device according to one embodiment of the present invention will be described.

[0415] [Configuration example] FIG. 36A is a top view of a display device including a semiconductor device according to one embodiment of the present invention. FIG. 36B shows a pixel of a display device using a semiconductor device according to one embodiment of the present invention. FIG. 36(C) shows a pixel circuit in which a liquid crystal element is used. The pixel circuit when an organic EL element is used for the pixel of a display device using the semiconductor device according to the present invention Show the way.

[0416] The transistor used in the pixel can be any of the above-described transistors. In this example, an n-channel transistor is used. A transistor manufactured through the same process may be used as a driver circuit. The transistors used as the driving circuits may be separately manufactured. For example, The transistors used in the driver circuits are the transistors described above, and the transistors used in the pixels are The above-mentioned transistor is a single-gate transistor that does not have a gate electrode 104a. The above-mentioned capacitor element may be used for the pixel. In this way, by using the above-described transistors and capacitors in the pixel and the driver circuit, This results in a display device with high display quality and / or high reliability.

[0417] An example of a top view of an active matrix display device is shown in FIG. On the plate 5000, a pixel section 5001, a first scanning line driving circuit 5002, a second scanning line driving circuit 5003, and a A signal line driver circuit 5004 is disposed in the pixel portion 5001. 5004, and the first scanning line is electrically connected to the signal line driver circuit 5004 by a plurality of scanning lines. The first scanning line driver circuit 5002 and the second scanning line driver circuit 5003 are electrically connected to each other. In the regions partitioned by the scanning lines and the signal lines, pixels each having a display element are arranged. The display device substrate 5000 is made of a flexible printed circuit board (FPC). A timing control circuit (controller, control I d Circuit) is connected to the C).

[0418] A first scanning line driver circuit 5002, a second scanning line driver circuit 5003, and a signal line driver circuit 5 004 is formed on the same substrate 5000 as the pixel portion 5001. In comparison with the case where the display device is manufactured by using a drive circuit, the manufacturing cost of the display device can be reduced. If a separate operating circuit is created, the number of connections between the wiring will increase. By providing a driver circuit, the number of connections between wiring can be reduced, improving reliability, or and / or improve yield.

[0419] [Liquid crystal display device] An example of the circuit configuration of a pixel is shown in FIG. 1 shows a pixel circuit that can be applied to a pixel or the like.

[0420] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. The pixel electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel voltages of the multi-domain designed pixels to be The signals applied to the poles can be controlled independently.

[0421] A gate wiring 5012 of a transistor 5016 and a gate wiring 5017 of a transistor 5017 013 are separated so that different gate signals can be applied. A source electrode or drain electrode 5014 functioning as a data line is connected to a transistor 5016. It is shared by transistor 5016 and transistor 5017. The above-described transistors can be appropriately used for the capacitor 5023 and the The above-described capacitors can be appropriately used for the capacitor 5029. It is possible to provide a liquid crystal display device with high level and / or reliability.

[0422] A first pixel electrode electrically connected to the transistor 5016, a transistor 5017, and The shape of the second pixel electrode that is electrically connected to the first pixel electrode and the second pixel electrode is described below. The electrodes are separated by slits. The first pixel electrode is V-shaped. The second pixel electrode is formed so as to surround the outside of the first pixel electrode.

[0423] The gate electrode of the transistor 5016 is electrically connected to the gate wiring 5012. The gate electrode of the transistor 5017 is electrically connected to the gate wiring 5013. By applying different gate signals to the line 5012 and the gate wiring 5013, the transistor 5016 and the transistor The alignment of the liquid crystal can be controlled by varying the operation timing of the transistor 5017.

[0424] In addition, a capacitance wiring 5010, a gate insulator functioning as a dielectric, and a first pixel electrode Alternatively, a capacitive element may be formed by a capacitive electrode electrically connected to the second pixel electrode.

[0425] The multi-domain structure has a first liquid crystal element 5018 and a second liquid crystal element 5019 in one pixel. The first liquid crystal element 5018 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 5019 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween. can be.

[0426] Note that the display device according to one embodiment of the present invention is not limited to the pixel circuit illustrated in FIG. For example, a switch, a resistor, a capacitor, a transistor, etc. may be newly added to the pixel shown in FIG. Additional components such as sensors, logic circuits, etc. may be added.

[0427] [Light emitting device] Another example of the circuit configuration of a pixel is shown in FIG. 36(C). 1 shows a pixel structure of a display device (also called a light-emitting device) using a light-emitting element.

[0428] In the organic EL element, a pair of light emitting diodes that the organic EL element has is turned on by applying a voltage to the light emitting element. Electrons are injected from one electrode and holes are injected from the other electrode into a layer containing a light-emitting organic compound. When the electrons and holes recombine, a light-emitting organic compound is produced. An excited state is formed, and light is emitted when the excited state returns to the ground state. Therefore, such a light-emitting element is called a current-excitation type light-emitting element.

[0429] FIG. 36C is a diagram showing an example of a pixel circuit. Here, one pixel has an n-channel This example uses two n-channel transistors and one capacitor. The transistor described above can be used for the transistor. In addition, the pixel circuit is suitable for digital time gray scale driving. It can be used.

[0430] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, I will explain it below.

[0431] The pixel 5020 includes a switching transistor 5021 and a driving transistor 5022. The switching transistor 502 includes a light emitting element 5024 and a capacitor element 5023. 1, the gate electrode is connected to the scanning line 5026, and the first electrode (the source electrode, the drain electrode) The first electrode (the other of the source electrode and drain electrode) is connected to a signal line 5025, and the second electrode (the other of the source electrode and drain electrode) is connected to a drive The gate electrode of the driving transistor 5022 is connected to the gate electrode of the driving transistor 5022. The gate electrode is connected to a power supply line 5027 via a capacitor element 5023, and the first electrode is connected to a power supply line 5024. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 5024. The second electrode of the light-emitting element 5024 corresponds to a common electrode 5028. is electrically connected to a common potential line formed on the same substrate.

[0432] The switching transistor 5021 and the driving transistor 5022 are the transistors described above. In addition, the above-mentioned capacitor can be used for the capacitor 5023. This makes it possible to provide an organic EL display device with high display quality and / or high reliability. It becomes.

[0433] The potential of the second electrode (common electrode 5028) of the light emitting element 5024 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 5027. For example, GND, 0V, or the like can be set as the low power supply potential. The high and low power supply potentials are set so that the potential difference is equal to or greater than the threshold voltage in the positive direction. By applying a voltage to the element 5024, a current flows through the light emitting element 5024, causing it to emit light. The forward voltage of the light emitting element 5024 refers to a voltage required for achieving a desired luminance. At least the forward threshold voltage.

[0434] The gate capacitance of the driving transistor 5022 is used as the capacitor 5023. The gate capacitance of the driving transistor 5022 can be reduced by A capacitance may be formed between the panel formation region and the gate electrode.

[0435] Next, a signal to be input to the driving transistor 5022 will be described. In the case of the driving method, the driving transistor 5022 is in two states, on and off. A video signal is input to the driving transistor 5022. In order to operate the transistor 22 in a linear region, a voltage higher than the voltage of the power supply line 5027 is applied to the driving transistor 22. A gate electrode of the transistor 5022 is applied to the signal line 5025. A voltage equal to or greater than the threshold voltage Vth of the input transistor 5022 is applied.

[0436] When analog gradation driving is performed, the gate electrode of the driving transistor 5022 is connected to the light emitting element 5 024 plus the threshold voltage Vth of the driving transistor 5022 or more In addition, the voltage of the video is applied so that the driving transistor 5022 operates in the saturation region. A signal is input to pass a current through the light emitting element 5024. In addition, the driving transistor 5022 is saturated. In order to operate the driving transistor 5022 in the sum region, the potential of the power supply line 5027 is set to the gate By converting the video signal into an analog signal, the light emitting element 5024 receives the video signal. A current corresponding to a signal is passed through the liquid crystal display, enabling analog gray scale driving.

[0437] Note that a display device using a semiconductor device according to one embodiment of the present invention has a pixel structure shown in FIG. For example, a switch, a resistor, a capacitor, and a capacitor element may be added to the pixel circuit shown in FIG. Additional elements, sensors, transistors, or logic circuits may be added.

[0438] For example, FIG. 37(A) is a diagram showing an example of a pixel circuit. Here, one pixel has n transistors. An example using three channel transistors and one capacitor will be shown.

[0439] FIG. 37A shows an example of a circuit diagram of a pixel 5111. The pixel 5111 includes a transistor 5155, a transistor 5156, a transistor 5157, and a capacitor 5158, and a light-emitting element 5154.

[0440] The pixel electrode of the light emitting element 5154 is turned on in accordance with the image signal Sig input to the pixel 5111. The luminance of the light emitting element 5154 is controlled by the potential between the pixel electrode and the common electrode. It is determined by the difference.

[0441] The transistor 5156 is connected to the wiring SL and the gate of the transistor 5155. The transistor 5155 has a function of controlling the state of the transistor. The other of the source and drain is electrically connected to the wiring VL. The transistor 5157 is connected to the wiring ML and the The capacitor element 5158 has a function of controlling the conduction state between the source and the drain. One of the pair of electrodes is electrically connected to the gate of the transistor 5155, and the other is It is electrically connected to the anode of element 5154 .

[0442] In addition, the switching of the transistor 5156 causes an electrical The potential of the wiring GL connected to the transistor 5157 is controlled by the potential of the wiring GL. The switching is performed according to the potential of the wiring GL electrically connected to the gate of the transistor 5157. This is carried out.

[0443] In addition, the transistors 5155, 5156, and 5157 are At least one of the above-described transistors can be used for the capacitor 515. The above-mentioned capacitance element can be used for 8.

[0444] Next, an example of the operation of the pixel 5111 shown in FIG.

[0445] FIG. 37B shows the voltage of the wiring GL electrically connected to the pixel 5111 shown in FIG. 13 is a timing chart showing an example of a potential of an image signal Sig supplied to the wiring SL. The timing chart shown in FIG. 37B is included in the pixel 5111 shown in FIG. This is an example in which all the transistors are n-channel types.

[0446] First, in a period t1, a high-level potential is applied to the wiring GL. The image signal S is supplied to the wiring SL. The potential Vdata of ig is given, and the potential Vdata is and applied to the gate of transistor 5155.

[0447] Moreover, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is a potential Vcat, which is a threshold voltage Vthe of the light emitting element 5154 and a transistor. It is preferable to set the potential higher than the potential obtained by adding the threshold voltage Vth of the transistor 5155. By providing the above potential difference between VL and the wiring CL, The drain current of the transistor 5155 is determined by the drain current. is supplied to the light emitting element 5154, thereby determining the luminance of the light emitting element 5154.

[0448] In addition, when the transistor 5155 is an n-channel type, the voltage of the wiring ML is The potential is higher than the potential of the wiring CL plus the threshold voltage Vthe of the light emitting element 5154. The potential of the wiring VL is lower than the potential of the wiring ML by the threshold voltage Vth It is preferable that the potential is higher than the sum of the potentials of the transistors 5157 and 5158. Even if the transistor 5155 is connected to the light emitting element 5154, the drain current of the transistor 5155 is connected to the wiring instead of the light emitting element 5154. Priority can be given to ML.

[0449] Next, in a period t2, a low-level potential is applied to the wiring GL. Transistor 5156 and transistor 5157 are turned off. Transistor 5156 is turned off. As a result, the potential Vdata is held at the gate of the transistor 5155. A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The light emitting element 5154 emits light according to the luminance determined in the period t1.

[0450] Next, in a period t3, a high-level potential is applied to the wiring GL. The transistor 5156 and the transistor 5157 are turned on. A potential is applied such that the gate voltage of 5155 becomes greater than the threshold voltage Vth. A potential Vcat is applied to the line CL. The potential of the line ML is The potential of the wiring V The potential of L is a potential obtained by adding the threshold voltage Vth of the transistor 5155 to the potential of the wiring ML. With the above configuration, the drain current of the transistor 5155 is It is possible to give priority to wiring ML rather than 5154.

[0451] The drain current of the transistor 5155 is supplied to the monitor circuit via the wiring ML. The monitor circuit uses the drain current flowing through the line ML to A signal including a value of the signal as information is generated using the semiconductor device according to one embodiment of the present invention. In the light emitting device, the potential V of the image signal Sig supplied to the pixel 5111 is adjusted by using the above signal. The data value can be corrected.

[0452] In the light-emitting device having the pixel 5111 shown in FIG. 37A, after the operation of the period t2, The operation in the period t3 may not be performed. For example, in the pixel 5111, The operation of the period t2 may be repeated several times, and then the operation of the period t3 may be performed. After the operation for the period t3 is performed in the pixel 5111 in the row, the image signal corresponding to the minimum gray scale value 0 is A signal is written to the pixels 5111 in one row where the operation is performed, thereby making the light emitting element 5154 non-emitting. After the pixel 5111 in the next row is switched to the light state, the operation for the period t3 is performed. good.

[0453] For example, FIG. 38A is a diagram showing an example of a pixel circuit. 1 shows an example in which four n-channel transistors and one capacitor are used.

[0454] FIG. 38A shows an example of a circuit diagram of a pixel 5211. The pixel 5211 includes a transistor 5215, a transistor 5216, a transistor 5217, and a capacitor 5218, The pixel includes a light-emitting element 5214 and a transistor 5219 .

[0455] The pixel electrode of the light emitting element 5214 is turned on in accordance with the image signal Sig input to the pixel 5211. The luminance of the light emitting element 5214 is controlled by the potential between the pixel electrode and the common electrode. It is determined by the difference.

[0456] The transistor 5219 is connected to the wiring SL and the gate of the transistor 5215. The transistor 5215 has a function of controlling the state of the transistor. The transistor 5216 is electrically connected to the anode of the optical element 5214. , the function of controlling the conduction state between the other of the source and drain of the transistor 5215 The transistor 5217 is connected to the wiring ML and the source and drain of the transistor 5215. The capacitor 5218 has a function of controlling the electrical continuity between the pair of electrodes. One of them is electrically connected to the gate of the transistor 5215, and the other is electrically connected to the gate of the light-emitting element 521 The positive electrode of the cathode of the cathode 4 is electrically connected to the anode of the anode 4.

[0457] In addition, the switching of the transistor 5219 causes an electric current to flow to the gate of the transistor 5219. The switching of the transistor 5216 is performed according to the potential of the wiring GLa which is connected to the The potential of the wiring GLb electrically connected to the gate of the transistor 5216 is set to The switching of the transistor 5217 is performed by the gate of the transistor 5217. This is done according to the potential of the wiring GLc electrically connected to the

[0458] Note that the transistors 5215, 5216, 5217, and At least one of the transistors 5219 can be the above-described transistor. In addition, the capacitor 5218 can be any of the above-described capacitors.

[0459] Next, an example of the operation of external correction of the pixel 5211 shown in FIG.

[0460] FIG. 38B illustrates a wiring GLa electrically connected to the pixel 5211 illustrated in FIG. The timing of the potentials of the wirings GLb and GLc and the potential of the image signal Sig supplied to the wiring SL The timing chart shown in FIG. 38(B) is the same as that shown in FIG. ) is an example in which all transistors included in the pixel 5211 are n-channel type. It is something.

[0461] First, in a period t1, a high-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the bell is applied to the line GLc, and a potential of the low level is applied to the line GLc. The transistor 5219 and the transistor 5216 are turned on, and the transistor 5217 is turned off. The line SL is supplied with a potential Vdata of the image signal Sig, and the potential V Data is provided to the gate of transistor 5215 via transistor 5219. .

[0462] Moreover, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is obtained by adding the threshold voltage Vthe of the light emitting element 5214 to the potential Vcat. The potential Vano of the wiring VL is preferably higher than the potential of the transistor 5216. The other of the source and drain of the transistor 5215 is applied via the The value of the drain current of the transistor 5215 is determined according to the potential Vdata. Then, the drain current is supplied to the light emitting element 5214, so that the light emitting element 5214 emits light. The degree is determined.

[0463] Next, in a period t2, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the bell is applied to the line GLc, and a potential of the low level is applied to the line GLc. The transistor 5216 is turned on, and the transistor 5219 and the transistor 5217 are turned off. When the transistor 5219 is turned off, the gate of the transistor 5215 is The potential Vdata is maintained. The potential Vano is applied to the wiring VL, and the potential Vdata is maintained at the wiring C. A potential Vcat is applied to L. Therefore, in the light emitting element 5214, a constant The set brightness is maintained.

[0464] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A potential of the bell is applied to the line GLc, and a high-level potential is applied to the line GLc. The transistor 5217 is turned on, and the transistor 5219 and the transistor 5216 are turned off. A potential Vcat is applied to the wiring CL. A potential Vano is applied to the wiring ML. is provided and is connected to a monitor circuit.

[0465] By the above operation, the drain voltage of the transistor 5215 is increased through the transistor 5217. The drain current is supplied to the light emitting element 5214. In addition, the drain current is supplied to the light emitting element 5214 via the wiring ML. The monitor circuit uses the drain current flowing through the line ML to A signal including the value of the drain current as information is generated. In a light emitting device using such a semiconductor device, the image signal supplied to the pixel 5211 is The value of the potential Vdata of the image signal Sig can be corrected.

[0466] In the light-emitting device having the pixel 5211 shown in FIG. 38A, after the operation of the period t2, For example, in a light emitting device, the operation during the period t1 to the period t2 may not be performed. After repeating the above operation several times, the operation in the period t3 may be performed. After the operation of the pixel 5211 during the period t3, an image signal corresponding to the minimum gradation value 0 is By writing to the pixels 5211 in one row where the operation has been performed, the light emitting element 5214 is turned into a non-light emitting state. After this state, the operation for the period t3 may be performed for the pixels 5211 in the next row. .

[0467] For example, FIG. 39(A) is a diagram showing an example of a pixel circuit. Illustrated is an example in which five n-channel transistors and one capacitor are used.

[0468] FIG. 39A shows an example of a circuit diagram of a pixel 5311. 1 includes a transistor 5315, a transistor 5316, a transistor 5317, and a capacitor A capacitor 5318, a light-emitting element 5314, a transistor 5319, and a transistor 532. 0 and.

[0469] The transistor 5320 controls the electrical continuity between the wiring RL and the anode of the light-emitting element 5314. The transistor 5319 is connected to the wiring SL and the gate of the transistor 5315. The transistor 5315 has a function of controlling the conduction state between the source and the drain. One of the drains is electrically connected to the anode of the light-emitting element 5314. 16 indicates a conductive state between the wiring VL and the other of the source and drain of the transistor 5315. The transistor 5317 has a function of controlling the state of the transistor 531. The capacitance element 53 has a function of controlling the conduction state between the other of the source and drain of the capacitance element 53. One of the pair of electrodes of the transistor 5315 is electrically connected to the gate of the transistor 5315, and the other One side is electrically connected to the anode of the light emitting element 5314 .

[0470] In addition, the switching of the transistor 5319 causes an electric current to flow to the gate of the transistor 5319. The switching of the transistor 5316 is performed according to the potential of the wiring GLa which is connected to the The potential of the wiring GLb electrically connected to the gate of the transistor 5316 is set to The switching of the transistor 5317 is performed by the gate of the transistor 5317. The potential of the wiring GLc electrically connected to the transistor 5320 is used. The switching is performed by changing the voltage of the wiring GLd electrically connected to the gate of the transistor 5320. This is done according to rank.

[0471] In addition, transistors 5315, 5316, 5317, At least one of the transistor 5319 and the transistor 5320 is The above-described capacitor can be used as the capacitor 5318. can.

[0472] Next, an example of the operation of external correction of the pixel 5311 shown in FIG.

[0473] FIG. 39B illustrates a wiring GLa electrically connected to the pixel 5311 illustrated in FIG. The potentials of the wirings GLb, GLc, and GLd and the potential of the image signal Sig supplied to the wiring SL The timing chart shown in FIG. In the case where all the transistors included in the pixel 5311 shown in FIG. 39A are n-channel type, This illustrates the case.

[0474] First, in a period t1, a high-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A low-level potential is applied to the wiring GLc, a high-level potential is applied to the wiring GLd. Therefore, the transistors 5319, 5316, and The transistor 5320 is turned on and the transistor 5317 is turned off. The potential Vdata of the image signal Sig is applied to the L. The potential Vd is applied to the gate of the transistor 5315 through the resistor 5319. The value of the drain current of the transistor 5315 is determined according to ata. A potential Vano is applied to the wiring VL, and a potential V1 is applied to the wiring RL. The drain current is connected to the wiring VL via the transistor 5316 and the transistor 5320. It flows between the lines RL.

[0475] The potential Vano is obtained by adding the threshold voltage Vthe of the light emitting element 5314 to the potential Vcat. The potential Vano of the wiring VL is preferably higher than the potential of the transistor 5316. The other of the source and drain of the transistor 5315 is supplied through the wiring The potential V1 applied to RL is applied to the transistor 5315 through the transistor 5320. A potential Vcat is applied to the line CL.

[0476] The potential V1 is obtained by subtracting the threshold voltage Vth of the transistor 5315 from the potential V0. In the period t1, the potential V1 is set to be sufficiently lower than the potential Vcat. The potential can be made sufficiently lower than the potential obtained by subtracting the threshold voltage Vthe of the light emitting element 5314 from the potential. Therefore, the light emitting element 5314 does not emit light.

[0477] Next, in a period t2, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A high-level potential is applied to the wiring GLc, a low-level potential is applied to the wiring GLd, Therefore, the transistor 5316 is turned on, and the transistor 5317 is turned on. 319, transistor 5317, and transistor 5320 are turned off. When the transistor 5319 is turned off, the potential Vdata is applied to the gate of the transistor 5315. Retained.

[0478] Moreover, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. Therefore, the drain current of the transistor 5315, the value of which is determined during the period t1, is When the transistor 5320 is turned off, the light is supplied to the light emitting element 5314. The drain current is supplied to the light emitting element 5314, and the luminance of the light emitting element 5314 is determined. This luminance is then maintained for a period t2.

[0479] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A low level potential is applied to the wiring GLc, a high level potential is applied to the wiring GLd, Therefore, the transistor 5317 is turned on, and the transistor 5 319, the transistor 5316, and the transistor 5320 are turned off. A potential Vcat is applied to the wiring ML. A potential Vano is applied to the wiring ML. and connected to a monitor circuit.

[0480] By the above operation, the drain voltage of the transistor 5315 is increased through the transistor 5317. The drain current is supplied to the light emitting element 5314. In addition, the drain current is supplied to the light emitting element 5314 through the wiring ML. The monitor circuit uses the drain current flowing through the line ML to A signal including the value of the drain current as information is generated. In a light emitting device using such a semiconductor device, the image signal supplied to the pixel 5311 is The value of the potential Vdata of the image signal Sig can be corrected.

[0481] In the light-emitting device having the pixel 5311 shown in FIG. 39A, after the operation of the period t2, For example, in a light emitting device, the operation during the period t1 to the period t2 may not be performed. After repeating the above operation several times, the operation in the period t3 may be performed. After the operation of the pixel 5311 during the period t3, an image signal corresponding to the minimum gradation value 0 is By writing to the pixels 5311 in one row where the operation has been performed, the light emitting element 5314 is turned into a non-light emitting element. After this state, the operation for the period t3 may be performed for the pixels 5311 in the next row. .

[0482] In addition, in the pixel 5311 shown in FIG. 39A, the light emitting element 5314 is degraded, and the light emitting element 5314 is no longer emitting light. Even if the resistance value between the anode and cathode of the optical element 5314 varies between pixels, the potential Vdata can be tracked. When a voltage is applied to the gate of the transistor 5315, the potential of the source of the transistor 5315 is set to a predetermined value. Therefore, the luminance of the light emitting element 5314 can be set to the potential V1. This can prevent the occurrence of fluctuations.

[0483] FIG. 40A is a diagram showing an example of a pixel circuit. 1 shows an example in which six n-channel transistors and one capacitor are used.

[0484] FIG. 40A shows an example of a circuit diagram of a pixel 5411. The pixel 5411 includes a transistor 5415, a transistor 5416, a transistor 5417, and a capacitor 5418, A light emitting element 5414, a transistor 5440, a transistor 5441, and a transistor 5442.

[0485] The pixel electrode of the light emitting element 5414 is turned on in accordance with the image signal Sig input to the pixel 5411. The luminance of the light emitting element 5414 is controlled by the potential between the pixel electrode and the common electrode. It is determined by the difference.

[0486] The transistor 5440 is connected to a wiring SL and one of a pair of electrodes of a capacitor 5418. The other of the pair of electrodes of the capacitor 5418 is , electrically connected to one of the source and drain of the transistor 5415. A transistor 5416 controls the conduction state between the wiring VL1 and the gate of the transistor 5415. The transistor 5441 is one of a pair of electrodes of the capacitor 5418. The transistor 5415 has a function of controlling the conduction state between the gate of the transistor 5415 and the gate of the transistor The transistor 5415 and the light-emitting element 541 are connected to each other. The transistor 5417 has a function of controlling the conduction state between the anode of the transistor 5417 and the anode of the transistor 4. A function of controlling the conduction state between one of the source and drain of the sta 5415 and the wiring ML. has.

[0487] In addition, in FIG. 40A, the other of the source and drain of the transistor 5415 is a wiring. Electrically connected to VL.

[0488] In addition, the selection of whether the transistor 5440 is on or off is performed by the transistor 5440. The potential of the wiring GLa electrically connected to the gate of the transistor 5 The on or off selection in 416 is electrically connected to the gate of transistor 5416. The on / off state of the transistor 5441 is controlled according to the potential of the wiring GLa. The selection of the off state is performed by changing the potential of the wiring GLb electrically connected to the gate of the transistor 5441. The selection of whether the transistor 5442 is on or off is performed according to the transistor This is performed according to the potential of the wiring GLb electrically connected to the gate of the transistor 5442. The on / off selection of the transistor 5417 is performed by the gate of the transistor 5417. This is performed according to the potential of the wiring GLc electrically connected to

[0489] FIG. 40B illustrates a wiring GLa electrically connected to the pixel 5411 illustrated in FIG. The timing of the potentials of the wirings GLb and GLc and the potential of the image signal Sig supplied to the wiring SL The timing chart shown in FIG. 40(B) is the same as that shown in FIG. ) is an example in which all transistors included in a pixel 5411 are n-channel type. It is something.

[0490] First, in a period t1, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the bell is applied to the line GLc, and a high-level potential is applied to the line GLc. The transistor 5441, the transistor 5442, and the transistor 5417 are turned on, and the transistor Transistor 5440 and transistor 5416 are turned off. Transistor 5442 and transistor When the transistor 5417 is turned on, one of the source and drain of the transistor 5415 is connected to the The other of the pair of electrodes of the capacitor 5418 (illustrated as node A) is connected to a wiring The potential V0 of ML is given.

[0491] Moreover, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is a potential obtained by adding the threshold voltage Vthe of the light emitting element 5414 to the potential V0. It is preferable that the potential V0 is set to be higher than the potential Vcat of the light emitting element 5414. It is preferable that the potential V0 is set to the above value, which is lower than the potential obtained by adding the threshold voltage Vthe. By setting the threshold voltage, it is possible to prevent a current from flowing through the light-emitting element 5414 during the period t1. .

[0492] Next, a low-level potential is applied to the wiring GLb, so that the transistors 5441 and Transistor 5442 is turned off and node A is held at potential V0.

[0493] Next, in a period t2, a high-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A potential of the bell is applied to the line GLc, and a potential of the low level is applied to the line GLc. The transistor 5440 and the transistor 5416 are turned on, and the transistor 5441 and the transistor Then, the transistor 5442 and the transistor 5417 are turned off.

[0494] When the period t1 is changed to the period t2, the potential applied to the wiring GLa is changed from a low level to a high level. After switching to high level, the potential applied to the wiring GLc is switched from high level to low level. By performing such an operation, the current given to the wiring GLa is Fluctuations in the potential of node A due to potential switching can be prevented.

[0495] Moreover, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. A potential Vdata of the image signal Sig is applied to the wiring SL, and a potential VL1 is applied to the wiring VL2. The potential V1 is given by multiplying the potential Vcat by the threshold voltage of the transistor 5415. Vth is added to the potential Vano, and the threshold voltage of the transistor 5415 is added to the potential Vano. It is preferable that the potential is lower than the potential obtained by adding Vth.

[0496] In the pixel configuration shown in FIG. 40A, the potential V1 is set to the threshold voltage of the light emitting element 5414. Even if the voltage Vthe is increased to a value greater than the sum of the potential Vcat, the transistor 5442 is not turned off. As long as the potential V0 is low, the light emitting element 5414 does not emit light. It is possible to widen the range of values ​​that can be taken as V1-V0. Therefore, the freedom to set the values ​​of V1-V0 increases, so the transistor 5415 When the time required to obtain the threshold voltage Vth is shortened, or when Even if the period is limited, the threshold voltage Vth of the transistor 5415 is accurately Acquisition can be made.

[0497] By the above operation, a node B is applied to the gate of the transistor 5415. A potential V1 higher than the potential obtained by adding the threshold voltage Vth to the potential of node A is input, and The transistor 5415 is turned on. As a result, the capacitance element 54 The charge of 18 is released, and the potential of node A, which was at potential V0, starts to rise. And finally, At this time, the potential of the node A converges to V1-Vth, and the gate voltage of the transistor 5415 reaches a threshold. When the voltage Vth converges to a lower value, transistor 5415 turns off.

[0498] In addition, one of the pair of electrodes of the capacitor 5418 (illustrated as node C) The potential Vdata of the image signal Sig applied to the wiring SL is input to the transistor 5440. It is given to you.

[0499] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the bell is applied to the line GLc, and a potential of the low level is applied to the line GLc. The transistor 5441 and the transistor 5442 are turned on, and the transistor 5440 and the transistor Then, transistor 5416 and transistor 5417 are turned off.

[0500] When the period t2 transitions to the period t3, the potential applied to the wiring GLa changes from a high level to a low level. After the potential is changed to low level, the potential applied to the wiring GLb is changed from low level to high level. With the above configuration, it is preferable to switch the potential applied to the wiring GLa to Therefore, it is possible to prevent the potential at node A from fluctuating.

[0501] Moreover, a potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. .

[0502] By the above operation, the potential Vdata is applied to the node B, so that the transistor 5415 The gate voltage of the transistor 5415 is Vdata-V1+Vth. The threshold voltage can be set to a value that takes into account the threshold voltage Vth. This makes it possible to suppress the variation in the threshold voltage Vth of the transistor 5415. Therefore, the variation in the current value supplied to the light emitting element 5414 can be suppressed, and the luminance of the light emitting device can be improved. It is possible to reduce unevenness.

[0503] Note that by increasing the fluctuation of the potential applied to the wiring GLb, the transistor 5442 In order to prevent the variation in the threshold voltage of the light emitting element 5414 from affecting the current value supplied to the light emitting element 5414, That is, the high-level potential applied to the wiring GLb can be The low-level potential applied to the line GLb is sufficiently higher than the threshold voltage of the transistor. By making the threshold voltage of the transistor 5442 sufficiently smaller, 5442 threshold voltage variation. It is possible to prevent the influence of the current value of the light emitting element 5414.

[0504] Next, in a period t4, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A potential of the bell is applied to the line GLc, and a high-level potential is applied to the line GLc. The transistor 5417 is turned on, and the transistors 5416, 5440, and The transistor 5441 and the transistor 5442 are turned off.

[0505] A potential Vano is applied to the wiring VL, and the wiring ML is connected to the monitor circuit. .

[0506] By the above operation, the drain current Id of the transistor 5415 becomes The monitor circuit does not flow to the wiring ML but flows to the wiring ML through the transistor 5417. Using the drain current Id, a signal including the value of the drain current Id as information is generated. This drain current Id is determined by the mobility of the transistor 5415 and the The size of the channel depends on the size of the channel (channel length, channel width, etc.). In a light-emitting device using the semiconductor device according to one embodiment of the present invention, the pixel 5411 is driven using the above signal. The value of the potential Vdata of the supplied image signal Sig can be corrected. The effect of variations in the mobility of the transistor 5415 can be reduced.

[0507] In the light-emitting device having the pixel 5411 shown in FIG. 40A, after the operation of the period t3, For example, in a light emitting device, the operation in the period t1 to the period t3 may not be performed. After repeating the above operation several times, the operation in the period t4 may be performed. After the operation of the pixel 5411 during the period t4, an image signal corresponding to the minimum gradation value 0 is By writing to the pixels 5411 in one row where the operation has been performed, the light emitting element 5414 is turned into a non-light emitting state. After this state, the operation for the period t4 may be performed for the pixels 5411 in the next row. .

[0508] In the light-emitting device having the pixel 5411 shown in FIG. The other of the source and drain is electrically isolated from the gate of the transistor 5415. Therefore, in the period t2, the potentials of the transistors can be controlled individually. The other potential of the source and drain of the transistor 5415 is connected to the gate of the transistor 5415. The potential can be set to a value higher than the potential obtained by adding the threshold voltage Vth to the potential. Therefore, when the transistor 5415 is normally on, i.e., when the threshold voltage Vt When h has a negative value, the source potential of the transistor 5415 is Charge can be stored in the capacitor 5418 until the potential becomes higher than the gate potential V1. Therefore, in a light-emitting device using a semiconductor device according to one embodiment of the present invention, the transistor 541 Even if the transistor 5 is normally on, the threshold voltage Vth can be obtained during the period t2. During the period t3, the transistor 5 The gate voltage of 415 can be set.

[0509] Therefore, in a light-emitting device using the semiconductor device according to one embodiment of the present invention, transistor 5 Even if the 415 is normally on, it is possible to reduce display unevenness and provide high-quality display. can.

[0510] In addition to the characteristics of the transistor 5415, the characteristics of the light-emitting element 5414 were also monitored. At this time, the potential Vdata of the image signal Sig may be controlled to It is preferable to prevent current from flowing through the transistor 5415. The current of the light element 5414 can be extracted. As a result, the current characteristic of the light emitting element 5414 It is possible to obtain the deterioration and variation state of the

[0511] For example, in this specification, a display element, a display device having a display element, a light-emitting device, A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element, or the light-emitting device may include, for example, For example, EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent transistors that emit light when exposed to light, electron emitters, liquid crystal elements, electronic ink, electrophoretic elements, graphene rating light valve (GLV), plasma display (PDP), MEMS Display element using microelectromechanical system, digital micromirror DMD (Digital Micro Shutter), DMS (Digital Micro Shutter), IMOD (Interface Modulation Device) Optical interference, optical shutter-type MEMS display element MEMS display element, electrowetting element, piezoelectric ceramic display , a display element using carbon nanotubes, etc. In addition, contrast, brightness, reflectance, transmittance, etc. change due to electrical or magnetic effects. An example of a display device using an EL element is an EL display. An example of a display device using electron emission elements is the field emitter. Flat-panel display (FED) or SED (Surface Emitting Diode) type flat panel display (SED) ace-conduction Electron-emitter Display) An example of a display device using liquid crystal elements is a liquid crystal display (transmissive liquid crystal Displays, semi-transmissive LCD displays, reflective LCD displays, direct-view LCD displays Play, projection type liquid crystal display), etc. Electronic ink, electronic liquid powder (registered trademark), An example of a display device using an electrophoretic element is electronic paper. When realizing a semi-transmissive or reflective liquid crystal display, one of the pixel electrodes For example, a part or the whole of the pixel electrode may function as a reflective electrode. A part or the whole of the material may contain aluminum, silver, etc. It is also possible to provide a memory circuit such as an SRAM under the reflective electrode. Power consumption can be further reduced.

[0512] In addition, if the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light ( In order to display full color on a display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B), or red (C). ), yellow (Y), etc. can be used in appropriate combination. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a color layer and a region not having a color layer, The white light in the region may be directly used for display. By placing the colored layer over the entire display, the decrease in brightness caused by the colored layer can be reduced during bright display, and power consumption can be reduced by 2. However, in some cases, the emission of light from organic EL elements and inorganic EL elements can be reduced by about 10 to 30%. When using optical elements to display full color, R, G, B, Y, and W are each emitted in different colors. By using a self-luminous element, it is possible to obtain a light emission from a colored layer. In some cases, power consumption can be reduced even further.

[0513] <module> A display module to which a semiconductor device according to one embodiment of the present invention is applied will be described below with reference to FIG. The explanation will be given using 1.

[0514] The display module 8000 shown in FIG. 41 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003, The cell 8006, the backlight unit 8007, the frame 8009, the printed circuit board 80 10, and a battery 8011. In some cases, the display device may not have the touch panel 8004 or the like.

[0515] The semiconductor device according to one embodiment of the present invention can be used for the cell 8006, for example.

[0516] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the cell 800 The shape and dimensions can be changed appropriately to suit the size of 6.

[0517] The touch panel 8004 is a resistive or capacitive touch panel. 6. Also, a touch panel can be attached to the opposing substrate (sealing substrate) of the cell 8006. Alternatively, each pixel of the cell 8006 may have a touch panel function. It is also possible to provide an optical sensor in the cell 80 to make it an optical touch panel. 06. A touch sensor electrode is provided in each pixel to create a capacitive touch panel. is also possible.

[0518] The backlight unit 8007 includes a light source 8008. Alternatively, the light diffusing plate may be provided at the end of the light receiving unit 8007.

[0519] The frame 8009 has a function of protecting the cell 8006 and also a function of detecting the operation of the printed circuit board 8010. The frame may also have a function as an electromagnetic shield to block electromagnetic waves generated by the frame. The frame 8009 may also function as a heat sink.

[0520] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. In some cases, the battery 8011 may not be required.

[0521] The display module 8000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. Additional ones may be provided.

[0522] (Embodiment 7) In this embodiment, an electronic device in which the semiconductor device of one embodiment of the present invention can be used will be described. This will be explained with reference to FIG.

[0523] 44(A) to 44(H) are diagrams showing electronic devices. These electronic devices are Body 6000, display unit 6001, speaker 6003, LED lamp 6004, operation keys 6 005 (including a power switch or an operation switch), a connection terminal 6006, a sensor 60 07 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , including a function for measuring odor or infrared rays), a microphone 6008, etc. It is possible.

[0524] FIG. 44(A) shows a mobile computer, which includes, in addition to the above, a switch 6009 , an infrared port 6010, etc. FIG. 44(B) shows a mobile phone equipped with a recording medium. A portable image playback device (e.g., a DVD playback device) that, in addition to the above, has a display unit 6002, a recording medium reading unit 6011, etc. In addition to the above, the display unit 6002, the support unit 6012, and the earphones are FIG. 44(D) shows a portable game machine, which has the above-mentioned In addition to the above, it can have a recording medium reading unit 6011, etc. In addition to the above, the digital camera includes an antenna 6014, a shutter, It may have buttons 6015, an image receiving unit 6016, etc. In addition to the above, the device includes a display unit 6002, a recording medium reading unit 6011, etc. FIG. 44(G) shows a television receiver, which, in addition to the above, includes a tuner, a picture FIG. 44(H) shows a portable television receiver. In addition to those mentioned above, it may have a charger 6017 capable of transmitting and receiving signals, etc.

[0525] The electronic devices shown in Figures 44(A) to 44(H) can have various functions. For example, the function to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software ( A function to control processing by a program, wireless communication function, and various functions using wireless communication function Functions for connecting to computer networks, transmitting various data using wireless communication functions, or receiving the program or data recorded on the recording medium, and displaying the program or data. The electronic device may have a function of displaying information on a display unit. In this case, one display unit is used mainly for displaying image information, and another display unit is used mainly for displaying text. A function that displays text information, or a function that displays images that take parallax into account on multiple displays Furthermore, electronic equipment having an image receiving unit can have a function of displaying a physical image. The camera has the functions of taking still images, taking videos, and storing the images automatically or manually. function to automatically correct the image, and to store the captured image on a recording medium (external or built-in to the camera) The camera can have a function to display the captured image on the display unit. The functions that the electronic devices shown in FIG. 44(H) can have are not limited to those described above, and various It can have such functions.

[0526] The electronic device described in this embodiment has a display unit for displaying some information. Note that the semiconductor device of one embodiment of the present invention is not limited to an electronic device having a display portion. can also be applied to

[0527] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done. [Explanation of symbols]

[0528] 100 Substrates 101 Insulating film 102 Insulating film 102a Insulating film 102b Insulating film 104a Gate electrode 104a1 Conductive film 104a2 Conductive film 104b Lower electrode 104b1 Conductive film 104b2 Conductive film 106 First Area 106a Channel formation region 106b Channel formation region 106c Channel formation region 107a Second Area 107a1 Low resistance area 107a2 Low resistance area 107b Second Area 107b1 Low resistance region 107b2 Low resistance area 108 Insulating film 112a Gate insulating film 112b Insulating film 113 Detachment prevention membrane 114a Gate electrode 114a1 Conductive film 114a2 Conductive film 114b Upper electrode 114b1 Conductive film 114b2 Conductive film 116a Source electrode 116a1 Conductive film 116a2 Conductive film 116b Drain electrode 116b1 Conductive film 116b2 Conductive film 118 Insulating film 126 Oxide Semiconductor Film 126a Oxide semiconductor film 126b Oxide semiconductor film 128 Insulating film 132 Insulating film 138 Insulating Film 140 Oxygen 142 Impurity elements 148 Insulating Film 150 Transistors 160 Capacitive element 204 Wiring 204a Conductive film 204b Conductive film 212 Insulating film 214 Wiring 214a Conductive film 214b Conductive film 216 Wiring 216a Conductive film 216b Conductive film 400 Substrates 453 Insulating film 453a Insulating film 453b Insulating film 455 Oxide Semiconductor Film 455a Channel Region 455b Low resistance region 455c low resistance area 455d area 455e area 455f Low resistance area 455g low resistance area 455h Low resistance region 455i low resistance area 457 Insulating Film 457a Insulating film 457b Insulating film 459 Conductive Film 459a Conductive film 459b Conductive film 465 Nitride insulating film 467 Insulating Film 468 Conductive Film 469 Conductive Film 475 Insulating Film 500 FET 501 Substrate 502 Substrate 504R Light emitting element 504G Light emitting element 504B Light emitting element 504W light emitting element 506 Conductive Film 507 Conductive Film 508 Bulkhead 509 Structure 510 EL layer 512 Conductive film 514R colored layer 514G colored layer 514B Colored layer 514W colored layer 516 Substrate 518 Sealing film 520 areas 522 Insulating film 524 Opening 600 pellets 600a Pellets 600b Pellets 601 ION 620 Substrate 630 Target 700 Display device 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light-shielding film 750 Transistors 752 Transistor 760 Connection electrode 766 Insulating Film 770 Planarizing Insulating Film 772 Conductive Film 774 Conductive Film 775 Liquid crystal elements 776 Liquid crystal layer 778 Structure 780 Anisotropic Conductive Film 782 Light emitting element 784 Conductive Film 786 EL layer 788 Conductive Film 790 Capacitive element 5000 boards 5001 Pixel unit 5002 Scanning line driver circuit 5003 Scanning line driver circuit 5004 Signal line driver circuit 5010 Capacitor wiring 5012 Gate wiring 5013 Gate wiring 5014 Drain electrode 5016 Transistor 5017 Transistor 5018 Liquid crystal element 5019 Liquid crystal element 5020 pixels 5021 Switching transistor 5022 Driving transistor 5023 Capacitive element 5024 Light emitting element 5025 Signal Line 5026 Scan Lines 5027 Power line 5028 Common electrode 5029 Capacitive element 5111 pixels 5154 Light emitting element 5155 Transistor 5156 Transistor 5157 Transistor 5158 Capacitive element 5211 pixels 5214 Light emitting element 5215 Transistor 5216 Transistor 5217 Transistor 5218 Capacitor 5219 Transistor 5311 pixels 5314 Light emitting element 5315 Transistor 5316 Transistor 5317 Transistor 5318 Capacitive element 5319 Transistor 5320 Transistor 5411 pixels 5414 Light emitting element 5415 Transistor 5416 Transistor 5417 Transistor 5418 Capacitor 5440 Transistor 5441 Transistor 5442 Transistor 6000 Chassis 6001 Display section 6002 Display section 6003 Speaker 6004 LED Lamp 6005 Operation key 6006 Connection terminal 6007 Sensor 6008 Microphone 6009 Switch 6010 Infrared port 6011 Recording medium reading unit 6012 Support part 6013 Earphones 6014 Antenna 6015 Shutter button 6016 Image receiving unit 6017 charger 6100 pellets 6120 Substrate 6161 area 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Cell 8007 Backlight unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

1. A first conductive film; a first insulating film having a region above the first conductive film; a second insulating film having a region above the first insulating film; an oxide semiconductor film having a region above the first insulating film; a third insulating film having a region above the oxide semiconductor film; a second conductive film having a region above the second insulating film; a third conductive film having an area above the second conductive film; a fourth insulating film having a region above the second conductive film; a fourth conductive film having a region above the third insulating film; the first insulating film contains nitrogen; the second insulating film contains oxygen; the oxide semiconductor film has a region overlapping with the first conductive film, the fourth conductive film has a region in contact with the oxide semiconductor film, both ends of the third insulating film are located outside both ends of the second conductive film in a channel length direction; both ends of the third insulating film are located inside both ends of the first conductive film in a channel length direction; the oxide semiconductor film has a first region and a second region adjacent to the first region, the second region has a thickness smaller than the thickness of the first region; the first region overlaps with the first conductive film; the second region has a region overlapping with the first conductive film and a region not overlapping with the first conductive film, a shape of an end of the third insulating film in a cross-sectional view includes a region where an angle between a tangent to a side surface of the third insulating film and a surface of the oxide semiconductor film changes.

2. A first conductive film; a first insulating film having a region above the first conductive film; a second insulating film having a region above the first insulating film; an oxide semiconductor film having a region above the first insulating film; a third insulating film having a region above the oxide semiconductor film; a second conductive film having a region above the second insulating film; a third conductive film having an area above the second conductive film; a fourth insulating film having a region above the second conductive film; a fourth conductive film having a region above the third insulating film; the first insulating film contains nitrogen; the second insulating film contains oxygen; the oxide semiconductor film has a region overlapping with the first conductive film, the fourth conductive film has a region in contact with the oxide semiconductor film, both ends of the third insulating film are located outside both ends of the second conductive film in a channel length direction; both ends of the third insulating film are located inside both ends of the first conductive film in a channel length direction; the oxide semiconductor film has a first region and a second region adjacent to the first region, the second region has a thickness smaller than the thickness of the first region; the first region overlaps with the first conductive film; the second region has a region overlapping with the first conductive film and a region not overlapping with the first conductive film, the first region overlaps the third insulating film; the second region does not overlap the third insulating film, a shape of an end of the third insulating film in a cross-sectional view includes a region where an angle between a tangent to a side surface of the third insulating film and a surface of the oxide semiconductor film changes.

3. In claim 1 or 2, The fourth conductive film has a region overlapping with the first conductive film.

4. In any one of claims 1 to 3, A transistor having a thickness of the second region that is smaller than a thickness of the first region by 0.1 nm or more and 5 nm or less.

5. In any one of claims 1 to 4, The oxide semiconductor film of the transistor contains In, Ga, and Zn.

Images