Semiconductor device and display device

Abstract

To provide a display device capable of partial driving while simplifying a structure of a circuit including a wire.SOLUTION: Signal processing circuits are provided at a plurality of stages in accordance with gate signal lines in a pixel region. To a first transistor that controls the potential of the gate signal line in the signal processing circuit, a signal that controls an active state of the gate signal line (state in which a selection signal is output) and a non-active state (state in which the selection signal is not output or a non-selection signal is continuously output) is input. To a second transistor that outputs a start signal to the next stage and a reset signal to the previous stage, a clock signal is input. Thus, the number of wires necessary for the operation of a device is reduced.SELECTED DRAWING: Figure 19

Description

[Technical field]

[0001] One aspect of the present invention relates to a display device. For example, a liquid crystal display device is exemplified. A pixel is selected by a signal line and a source signal line or a video signal line to display an image. Such display devices are included as one of the technical fields. [Background technology]

[0002] A display device that can reduce power consumption by partially rewriting images has been developed. Such displays have some games that can be used to partially rewrite the image. The device is equipped with a gate driver circuit that can drive only the gate signal lines (also called partial drive). It is being done.

[0003] Patent Document 1 discloses a gate driver circuit capable of implementing partial driving. In Patent Document 1, the gate driver circuit is divided into multiple groups. A different start pulse is input to each group. By controlling the gate driver circuit of Patent Document 1, partial driving is realized. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-004176 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional technology, it is not possible to know in advance which part of the gate signal line is to be selected. It is determined by the groups into which the gates are divided and the start pulse input to each group. It was not possible to select only an arbitrary portion of the port signal line. Since it is necessary to input different start pulses to each gate driver circuit, The number of signals required to operate the display increased. When the pixel portion is formed on a substrate, the number of connection points between the substrate on which the pixel portion is formed and an external circuit increases. .

[0006] One embodiment of the present invention is a display device capable of partial driving while simplifying a circuit configuration including wiring. The objective is to provide the following. [Means for solving the problem]

[0007] According to one embodiment of the present invention, a plurality of signal processing circuits are provided in correspondence with gate signal lines in a pixel region, A first transistor for controlling the potential of the gate signal line in the signal processing circuit is connected to the gate signal line active state (selection signal is output), inactive state (selection signal is not output) A signal that controls the state where the non-selection signal is not output or the non-selection signal continues to be output is input, and the next stage A clock signal is input to the second transistor, which outputs a start signal to the first stage and a reset signal to the previous stage. By configuring the device so that a signal is input, the number of wires required for device operation can be reduced.

[0008] Corresponding to each of a plurality of gate signal lines extending in an area in which pixels are arranged in a matrix In the case of a display device in which a plurality of signal processing circuit sections are provided in a plurality of stages, Circuitry is provided for selecting a particular gate signal line within a pixel area. A signal processing circuit for selecting a specific gate signal line supplies an active state signal to a first terminal. A signal for controlling the active and inactive states is input, and the second terminal is connected to the gate signal line. The first transistor has a clock signal input to its first terminal, and its second terminal outputs a start signal to the next-stage signal processing circuit section and a reset signal to the previous-stage signal processing circuit section. It includes a configuration composed of a second transistor. Furthermore, a circuit section for controlling the gate potential of the first transistor and the second transistor is included. A plurality of stages of signal processing circuit sections are provided. By sequentially selecting the signal processing circuit sections according to the above configuration and making it possible to select the signal or potential output to the gate signal line, it can be operated to supply a signal for driving a pixel to a specific gate signal line.

[0009] For a display device provided with m stages of signal processing circuit sections corresponding to each of a plurality of gate signal lines extending in a region where pixels are arranged in a matrix, a first wiring to which a clock signal is input, a second wiring to which a signal for selecting an active state in which a clock signal is input and an inactive state in which a constant potential is input is input, a third wiring to which a clock signal having an opposite phase to the first wiring is input, a fourth wiring to which a signal for selecting an active state in which a clock signal having an opposite phase to the signal of the second wiring is input and an inactive state in which a constant potential is input is input, and a circuit configuration for selecting a specific gate signal line in the pixel region are provided. The signal processing circuit section of the nth stage (1 < n < m) has a first transistor whose first terminal is connected to the second wiring and whose second terminal is connected to the nth gate signal line, and a first transistor whose first terminal is connected to the first wiring and whose second terminal is connected to the reset signal input terminal of the signal processing circuit section of the (n - 1)th stage and the start signal input A circuit section for controlling the gate potentials of the first transistor and the second transistor is provided. The signal processing circuit section of the (n + 1)-th stage (1 < n < m) has a third transistor whose first terminal is connected to the fourth wiring and whose second terminal is connected to the (n + 1)-th gate signal line, and a fourth transistor whose first terminal is connected to the third wiring and whose second terminal is connected to the reset signal input terminal of the signal processing circuit section of the n-th stage and the start signal input terminal to the signal processing circuit section of the (n + 2)-th stage. A circuit section for controlling the gate potentials of the third transistor and the fourth transistor is provided. When m stages of signal processing circuit sections are provided, the signals transmitted by the first to fourth wirings select the signal processing circuit sections sequentially, and by making it possible to select the signal or potential output to the gate signal line, it can be operated to supply a signal for driving a pixel to a specific gate signal line. The first to fourth transistors provided in the signal processing circuit section for selecting the gate signal line have the following configuration, in other words.

[0010] The first transistor of the signal processing circuit section of the n-th stage (1 < n < m) has a first terminal to which a signal for selecting an active state in which a clock signal is input and a non-active state in which a constant potential is input is input, and a second terminal for outputting a signal to the n-th gate signal line. The second transistor has a first terminal to which a clock signal is input and a second terminal for outputting a reset signal of the signal processing circuit section of the (n - 1)-th stage and a start signal to the signal processing circuit section of the (n + 1)-th stage. The third transistor of the signal processing circuit section of the (n + 1)-th stage (1 < n < m) has an active state in which an inverted-phase clock signal is input in synchronization with the clock signal and a non-a ctive state in which a constant potential is input. It has a first terminal and a second terminal for outputting a signal to the (n + 1)-th gate signal line. The fourth transistor has a first terminal to which a clock signal is input and a second terminal for outputting a reset signal of the signal processing circuit section of the n-th stage and a start signal to the signal processing circuit section of the (n + 2)-th stage. The fourth transistor has a first terminal to which a clock signal is input and a second terminal for outputting a reset signal of the signal processing circuit section of the n-th stage and a start signal to the signal processing circuit section of the (n + 2)-th stage. It has a first terminal to which a clock signal is input and a second terminal for outputting a reset signal of the signal processing circuit section of the n-th stage and a start signal to the signal processing circuit section of the (n + 2)-th stage. The third transistor of the signal processing circuit section of the (n + 1)-th stage (1 < n < m) has an active state in which an inverted-phase clock signal is input in synchronization with the clock signal and a non-active state in which a constant potential is input. It has a first terminal and a second terminal for outputting a signal to the (n + 1)-th gate signal line. a first terminal to which a signal for selecting an active state or an inactive state is input, and a n+1-th gate signal line and a second terminal for outputting a signal to the fourth transistor. a first terminal to which a clock signal of a first phase is input, and a reset signal and and a second terminal for outputting a start signal to the (n+2)th stage signal processing circuit section. The first transistor and the third transistor are connected to the active state (selection signal active (selection signal is not output or non-selection signal is not output) or inactive (selection signal is not output or non-selection signal is The second transistor and the fourth transistor operate to control the state in which the second transistor and the fourth transistor are continuously output. The master controls the operation of the front and rear signal processing circuits to control the signal It can be operated to provide a signal to drive the pixel.

[0011] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, and a first signal processing circuit having a first circuit portion, a fourth transistor, a fifth transistor a second signal processing circuit having a seventh transistor, a sixth transistor and a second circuit portion; and a third signal processing circuit having a second circuit portion. The first output terminal of the circuit portion is connected to the gate of the first transistor and the gate of the second transistor. The second output terminal of the first circuit portion is electrically connected to the gate of the third transistor. The first input terminal of the first circuit portion is electrically connected to the first output of the fourth transistor. The first output terminal of the second circuit portion is electrically connected to the terminal of the fourth transistor. The second transistor of the second circuit portion is electrically connected to the gate of the first transistor and the gate of the fifth transistor. The output terminal is electrically connected to the gate of the sixth transistor. The input terminal is electrically connected to the first terminal of the first transistor. The input terminal of the second circuit portion is electrically connected to the first terminal of the seventh transistor. The first output terminal of the third circuit section is electrically connected to the gate of the seventh transistor. The first input terminal of the first transistor is electrically connected to the first terminal of the fourth transistor. The second terminal of the transistor is electrically connected to the second terminal of the seventh transistor. The first terminal of the third transistor is electrically connected to the first terminal of the sixth transistor. The first terminal of the second transistor and the second terminal of the third transistor are connected to the first gate. The first terminal of the fifth transistor and the sixth transistor are electrically connected to the first terminal of the sixth transistor. The second terminal of the gate electrode is electrically connected to the second gate signal line.

[0012] In one aspect of the invention, the second terminal of the first transistor is connected to the first clock. The second terminal of the second transistor is electrically connected to a first wiring to which a clock signal is input. The second clock signal or the first voltage is selectively input to the second wiring. The second terminal of the fourth transistor is connected to a third wiring to which a third clock signal is input. The second terminal of the fifth transistor is electrically connected to the fourth clock signal or the second It may be electrically connected to a fourth wiring to which a voltage is selectively input.

[0013] In the above embodiment of the present invention, the channel width of the second transistor is The channel width of the fifth transistor is larger than the channel width of the fourth transistor. It may be larger than the channel width of the star.

[0014] In one embodiment of the present invention, the first to seventh transistors have the same conductivity type. A display device comprising:

[0015] In one embodiment of the present invention, the first to seventh transistors each have a channel formation region The insulating layer may include an oxide semiconductor.

[0016] In one embodiment of the present invention, the second circuit portion includes an eighth transistor and a ninth transistor. The second transistor may include a third transistor, a fourth transistor, and an inverter circuit. The first output terminal of the circuit part is connected to the input terminal of the inverter circuit, the first a terminal, a first terminal of the ninth transistor, and a first terminal of the tenth transistor; The second output terminal of the second circuit portion is connected to the output terminal of the inverter circuit, The first input terminal of the second circuit portion is electrically connected to the gate of the transistor of the first a second terminal of the first transistor and a gate of the second transistor; The second input terminal of the second circuit portion is electrically connected to the gate of the ninth transistor. can be.

[0017] In this specification, anything explicitly stated as singular is singular. However, it is not limited to this, and it is also possible to have a plurality of the above. Where something is explicitly stated as plural, it is preferable that it be plural. However, It is not limited to this and may be singular.

[0018] In this specification, the terms "first," "second," "third," and the like refer to various elements, members, regions, layers, Used to describe an area in a way that distinguishes it from others. Thus, first, second, third, etc. The term does not limit the number of elements, members, regions, layers, areas, etc. , "first" can be replaced with "second" or "third", etc.

[0019] In this specification, the terms "above" and "below" mean that the positional relationship of the components is "directly above" or "below" For example, the term "gate electrode on a gate insulating layer" is not limited to "directly under the gate electrode." If expressed, it does not exclude the inclusion of other components between the gate insulating layer and the gate electrode. Additionally, the terms "upper" and "lower" are merely used for convenience of explanation.

[0020] In this specification, the terms "electrode," "wiring," and "terminal" refer to these components. For example, an "electrode" may be used as a part of a "wiring". In addition, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes". This also includes cases where a "terminal" is formed integrally with a "wire." For example, when referring to a "first terminal," it is not limited to referring to a part. If the source or drain electrode of the transistor is included, may also include a conductor electrically connected to the region that essentially functions as the drain region. . Effect of the Invention

[0021] According to one embodiment of the present invention, in a configuration of a driver circuit of a display device, a circuit configuration including wiring In other words, the active state (the state in which the selection signal is output) active state (selection signal is not output or non-selection signal is continuously output) and inactive state (selection signal is not output or non-selection signal is continuously output) By providing wiring (such as a clock signal line) through which a signal that controls the A drivable display device can be provided. [Brief description of the drawings]

[0022] [Figure 1] FIG. 2 is a diagram illustrating a configuration of a circuit according to an embodiment. [Diagram 2] 1A shows an example of a truth table for explaining the operation of the circuit shown in FIG. 1A, and an example of a logic circuit for explaining the operation. [Diagram 3] FIG. 2 is an example of a schematic diagram for explaining the operation of the circuit illustrated in FIG. [Figure 4] FIG. 2 is a diagram illustrating a configuration of a circuit according to an embodiment. [Diagram 5] FIG. 2 is a diagram illustrating a configuration of a circuit according to an embodiment. [Figure 6] FIG. 2 is a diagram for explaining the configuration of a signal processing circuit according to an embodiment. [Figure 7] 7 is an example of a timing chart for explaining the operation of the signal processing circuit shown in FIG. 6. [Figure 8] FIG. 7 is a schematic diagram illustrating an example of the operation of the signal processing circuit shown in FIG. 6. [Figure 9] FIG. 7 is a schematic diagram illustrating an example of the operation of the signal processing circuit shown in FIG. 6. [Figure 10] FIG. 7 is a schematic diagram illustrating an example of the operation of the signal processing circuit shown in FIG. 6. [Figure 11] 7 is an example of a timing chart for explaining the operation of the signal processing circuit shown in FIG. 6. [Figure 12] 7 is an example of a timing chart for explaining the operation of the signal processing circuit shown in FIG. 6. [Figure 13] FIG. 2 is a diagram for explaining the configuration of a signal processing circuit according to an embodiment. [Figure 14] FIG. 2 is a diagram for explaining the configuration of a signal processing circuit according to an embodiment. [Figure 15]FIG. 2 is a diagram for explaining the configuration of a signal processing circuit according to an embodiment. [Figure 16] FIG. 2 is a diagram for explaining the configuration of a signal processing circuit according to an embodiment. [Figure 17] 4 is an example for explaining the configuration of a part of a circuit included in a signal processing circuit. [Figure 18] 4 is an example for explaining the configuration of a part of a circuit included in a signal processing circuit. [Figure 19] 3 is an example for explaining a configuration of a shift register circuit according to an embodiment. [Figure 20] 20 is an example of a timing chart for explaining the operation of the shift register circuit shown in FIG. 19. [Figure 21] 1 is an example illustrating a configuration of a display device according to an embodiment. [Figure 22] 2 is an example for explaining a configuration of a pixel of a display device according to an embodiment. [Figure 23] 1A and 1B are an example for explaining a circuit diagram of a pixel of a display device according to an embodiment and a configuration of the pixel; [Figure 24] 2 is an example for explaining a configuration of a pixel of a display device according to an embodiment. [Diagram 25] 4 is an example of a timing chart for explaining an operation of a pixel of the display device according to the embodiment. [Figure 26] 2 is an example for explaining a configuration of a pixel of a display device according to an embodiment. [Figure 27] 1 is a diagram illustrating an example of an apparatus embodying the technical concept of the present invention; [Figure 28] 1 is a diagram illustrating an example of an apparatus embodying the technical concept of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the present invention in various forms without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that various modifications may be made to the details of the present invention. In addition, in the configuration described below, A part or a part having a similar function is indicated by a common reference numeral in different drawings, and the same part is indicated by a common reference numeral in different drawings. Detailed description of the parts having the same functions will be omitted. Layer thicknesses or areas may be exaggerated for clarity. is not limited to this scale.

[0024] (Circuit configuration according to one embodiment) In FIG. 1A, the output for an input signal is determined by transistors 101 and 102. 1 shows an example of the configuration of a circuit in which a signal is controlled.

[0025] The transistors 101 and 102 constituting the circuit shown in FIG. The n-channel transistor has a gate and a source. When the potential difference (Vgs) between the gate and transistor becomes larger than the threshold voltage, the transistor turns on. Note that the circuit in FIG. 1A can be replaced with a p-channel transistor.

[0026] The connections of the circuit shown in FIG. The transistor (for example, one of the source electrode and the drain electrode) is connected to the wiring 111. A second terminal of the transistor 101 (for example, the other of the source electrode and the drain electrode) is connected to the wiring 112. The first terminal of the transistor 102 is connected to the wiring 113. The second terminal of the transistor 102 is connected to the wiring 114. The gate of the transistor 101 is connected to the gate of the transistor 102. The connection point with the gate of sta 102 is indicated as node N1.

[0027] The wirings 111 to 114 will be described below.

[0028] A digital signal such as a clock signal is input to the wiring 111 and the wiring 113. That is, the wiring 111 and the wiring 113 are connected to elements constituting a circuit such as the transistor 101. The wiring 111 and the wiring 113 are wirings for transmitting signals such as clock signals. has a function as a signal line or a clock signal line.

[0029] Note that the potential of the H level of the signal input to the wiring 111 and the wiring 113 is set to the potential V1 The potential of the L level signal input to the wiring 111 and the wiring 113 is set as a potential V2 for convenience. do.

[0030] Note that one of the signal input to the wiring 111 and the signal input to the wiring 113 is an active The signal input to the wiring 111 is either in an active state or in an inactive state. The other of the signal input to the wiring 113 is in an active state. In the above, "a signal becomes inactive" means that the signal becomes inactive when the signal becomes inactive and reaches a certain value (e.g., a potential (e.g., a value equal to potential V1, a value equal to potential V2, or a value equal to ground potential) In this specification, the term "a signal becomes active" does not mean "a signal becomes inactive" This refers to something other than "becoming active."

[0031] The wiring 112 is connected to the output terminal (second terminal) of the transistor 101. Thus, a signal controlled by the transistor 101 is output from the wiring 112. That is, the wiring 112 is connected to the output terminal of the transistor 101. The wiring 112 is a wiring for transmitting a signal to a connected load, etc. It functions as a signal line.

[0032] When a digital signal is input to the wiring 111, the signal output from the wiring 112 is The H-level potential of the signal output from the wiring 112 is also a digital signal. This potential is approximately equal to the H level potential of the signal input to the line 111 (for example, potential V1). The L-level potential of the signal output from the wiring 112 is the same as the L-level potential of the signal input to the wiring 111. The potential is approximately equal to the L level potential of the signal (for example, potential V2).

[0033] The wiring 114 is connected to the output terminal (second terminal) of the transistor 102. As a result, a signal controlled by the transistor 102 is output from the wiring 114. That is, the wiring 114 is connected to the output signal controlled by the transistor 102. The wiring 114 is a wiring for transmitting a signal to a connected load, etc. It functions as a signal line.

[0034] When a digital signal is input to the wiring 113, the signal output from the wiring 114 The H-level potential of the signal output from the wiring 114 is also a digital signal. This potential is approximately equal to the H level potential of the signal input to the line 113 (for example, potential V1). The L level potential of the signal output from the wiring 114 is the same as the L level potential of the signal input to the wiring 113. The potential is approximately equal to the potential of the level (for example, potential V2).

[0035] The circuit shown in FIG. 1A is used as a part of a driver circuit for a gate signal line of a display device. In that case, one of the wirings 112 and 114 may extend to the pixel portion. The gate of a transistor (for example, a selection transistor) provided in each pixel is It functions as a gate signal line (also called a gate line, a scanning line, or a selection line) that is connected to the The other of the wiring 112 and the wiring 114 is a transfer signal (start The wiring can be used to transmit a signal (a signal or a reset signal).

[0036] Examples of functions of the transistor 101 and the transistor 102 will be described.

[0037] The transistor 101 is a switch that controls the conduction state between the wiring 111 and the wiring 112. Alternatively, the transistor 101 functions as a transistor for increasing or decreasing the potential of the wiring 112. Alternatively, the transistor 101 has a function of controlling the timing at which the node N The function of this transistor is to control the timing at which the potential of transistor 1 is increased.

[0038] The transistor 102 is a switch that controls the conduction state between the wiring 113 and the wiring 114. Alternatively, the transistor 102 functions as a transistor for increasing or decreasing the potential of the wiring 114. Alternatively, the transistor 102 has a function of controlling the timing at which the node N The function of this transistor is to control the timing at which the potential of transistor 1 is increased.

[0039] FIG. 2 shows the potential of the wiring 111, the potential of the wiring 114, the potential of the transistor At least eight operations are performed by combining the conductive states of transistors 101 and 102. FIG. 2A shows the operations (shown as operations DR1 to DR8). An example of a truth table to explain the eight operations is shown in Figure 2(B). An example of a logic circuit for realizing this is shown below.

[0040] In the operation DR1, the potential of the wiring 111 becomes equal to the potential V1, and the potential of the wiring 113 becomes equal to the potential The transistor 101 is turned on, and the wiring 111 and the wiring 112 are connected to each other. The transistor 102 is turned on, and the wiring 113 and the wiring 114 are electrically connected. Therefore, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is The potential of the wiring 113 is supplied to the wiring 114, and the potential of the wiring 114 is This potential becomes equal to the potential V1 (see FIG. 3(A)).

[0041] In the operation DR2, the potential of the wiring 111 becomes equal to the potential V1, and the potential of the wiring 113 becomes equal to the potential The transistor 101 is turned on, and the wiring 111 and the wiring 112 are connected to each other. The transistor 102 is turned on, and the wiring 113 and the wiring 114 are electrically connected. Therefore, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is The potential of the wiring 113 is supplied to the wiring 114, and the potential of the wiring 114 is This potential becomes equal to the potential V2 (see FIG. 3(B)).

[0042] In the operation DR3, the potential of the wiring 111 becomes equal to the potential V2, and the potential of the wiring 113 becomes equal to the potential The transistor 101 is turned on, and the wiring 111 and the wiring 112 are connected to each other. The transistor 102 is turned on, and the wiring 113 and the wiring 114 are electrically connected. Therefore, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is The potential of the wiring 113 is supplied to the wiring 114, and the potential of the wiring 114 is This potential becomes equal to V1 (see FIG. 3(C)).

[0043] In the operation DR4, the potential of the wiring 111 becomes equal to the potential V2, and the potential of the wiring 113 becomes equal to the potential V1. The transistor 101 is turned on, and the wiring 111 and the wiring 112 are connected to each other. The transistor 102 is turned on, and the wiring 113 and the wiring 114 are electrically connected. Therefore, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 is The potential of the wiring 113 is supplied to the wiring 114, and the potential of the wiring 114 is This potential becomes equal to the potential V2 (see FIG. 3(D)).

[0044] In the operations DR5 to DR8, the transistor 101 is turned off, and the wiring 111 and the wiring The transistor 102 is turned off, and the wiring 113 and the wiring 112 are not electrically connected to each other. Therefore, the wiring 112 is in a high impedance state (denoted as Z). The potential of the wiring 112 remains at the value before the operations DR5 to DR8 are performed. 114 is in a high impedance state (denoted as Z), and the potential of the wiring 114 is in the operating DR5 3. The value remains the same as before DR8 was performed (see FIGS. 3(E), (F), (G), and (H)).

[0045] For example, after the circuit shown in FIG. 1A performs the operation DR1, any one of the operations DR5 to DR8 is performed. When one of the operations is performed, the potential of the wiring 112 is equal to the potential V1. The potential of 14 is equal to the potential V1. Also, the circuit shown in FIG. 1(A) operates DR2. When any one of the operations DR5 to DR8 is performed after the above, the potential of the wiring 112 The potential of the wiring 114 is equal to the potential V2. After the circuit shown in FIG. 1A performs the operation DR3, any one of the operations DR5 to DR8 is performed. When one operation is performed, the potential of the wiring 112 is equal to the potential V2, and the potential of the wiring 114 is equal to the potential V3. The potential is equal to the potential V1. After the circuit shown in FIG. 1(A) performs the operation DR4, When any one of the operations DR5 to DR8 is performed, the potential of the wiring 112 is V 2, and the potential of the wiring 114 becomes equal to the potential V2.

[0046] In addition, the transistors 101 and 102 may be connected in series, such as in the case of operation DR1, operation DR2, or operation DR3. When the transistor 102 is turned on, the potential of the wiring 112 and the potential of the wiring 114 become smaller. When at least one of the potentials is equal to the potential V1, the potential of the node N1 is V1+Vth101( Vth101 is higher than the threshold voltage of the transistor 101, and V1+Vth102 ( Vth102 is higher than the threshold voltage of the transistor 102. In this way, the transistor 101 and the transistor 102 are turned on, and the wiring When the potential of the wiring 112 and the potential of the wiring 114 are both equal to the potential V2, the potential of the node N1 The value is higher than V2+Vth101 and higher than V2+Vth102. In addition, transistor 1, such as operation DR5, operation DR6, operation DR7, or operation DR8, When the transistor 101 and the transistor 102 are turned off, the potential of the node N1 is V2+Vth Lower than V2+Vth101 and lower than V2+Vth102 (preferably equal to V2) become.

[0047] As described above, the circuit in FIG. 1A controls the potential of the wiring 111 and the potential of the wiring 113. By controlling the potential of the wiring 112, the potential of the wiring 114 can be made equal. , can also be different.

[0048] The wiring 111 and the wiring 113 are not limited to the above signals, and various other signals or An example of such a voltage can be described below.

[0049] The potential of the H level of the signal input to the wiring 111 and the potential of the H level of the signal input to the wiring 113 The potential of the bell can be different from that of the transistor. When the line 114 is connected to the load, the amplitude voltage of the signal output from the line 114 drives a load such as a transistor. In such a case, it may be preferable to increase the input voltage to the wiring 113. The H-level potential of the signal input to the wiring 111 is higher than the H-level potential of the signal input to the wiring 111. Such measures can reduce power consumption while driving a large load. It becomes possible.

[0050] A predetermined voltage (for example, voltage V1 or voltage V 2) can be supplied. Therefore, the wiring 111 or the wiring 113 can be used as a power supply line. It is possible for the voltage V1 to have a function as a reference potential (for example, a ground potential). The voltage V2 is equal to the difference between the reference potential (e.g., ground potential) and the potential V1. potential V1) and the potential V2.

[0051] The circuit shown in FIG. 1A operates in accordance with the truth table shown in FIG. 2A (for example, operations DR1 to DR2). R8) and can perform various other actions. Some examples are explained below. Reveal.

[0052] In the operations DR1 to DR8, one of the transistors 101 and 102 In this case, transistor 10 can be in an on state and the other can be in an off state. The gate of transistor 101 and the gate of transistor 102 are connected to different wirings or different nodes. It is expected that this will happen.

[0053] In addition, one or both of the wiring 111 and the wiring 113 can be in a floating state. That is, the supply of a signal, voltage, or the like to one or both of the wiring 111 and the wiring 113 is stopped. For example, in the operations DR5 to DR8, the wiring 111 and the wiring 113 In operations DR5 to DR8, either or both of the transistors DR1 and DR2 can be floating. Since the transistor 101 and the transistor 102 are turned off, the wiring 111 and the wiring 11 The potential of the wiring 111 and 3 does not affect the operation. It is preferable that one or both of the wirings 113 are in a floating state.

[0054] As another example, the wiring 111 or the wiring 112 may be connected to one or both of the wiring 114. It is possible to supply the potential V2 from a wiring different from that of the operation DR3. In one or more of DR4, action DR5, action DR6, action DR7, and action DR8, It is preferable to supply a potential V2 to the wiring 112. In order to realize such an operation, the potential V2 When the supply line and the line 112 are connected via a switch (e.g., a transistor), Also, the operation DR2, operation DR4, operation DR5, operation DR6, operation DR7 and operation D It is preferable to supply a potential V2 to the wiring 114 in one or more of R8. In order to realize this, a switch (for example, a transistor) is connected between the wiring to which the potential V2 is supplied and the wiring 114. In the operations DR5 to DR8, the wiring 112 and the wiring 1 Since the wiring 114 is in a floating state, the potentials of the wiring 112 and the wiring 114 depend on the previous operation. Therefore, a potential V2 is supplied to the wiring 112 and the wiring 114, and the current flow is changed in accordance with the previous operation. The wiring 112 and the wiring 114 can be set to a potential V2 without the need for a Since the wiring 112 and the wiring 114 are in a floating state, noise is likely to occur in the wiring 112 and the wiring 114. Therefore, by supplying a potential V2 to the wiring 112 and the wiring 114, the noise It is possible to reduce this.

[0055] Although an example of a circuit having two transistors is shown in FIG. The present invention is not limited to the above circuit, and various circuit configurations can be used as circuits that realize similar functions. An example is shown in Figure 4.

[0056] FIG. 4A shows N (N is a natural number) transistors 31 (transistors 31_1 to 31_3). 1_N) in which the first terminals of the N transistors 31 are , N wirings 32 (shown as wirings 32_1 to 32_N). The second terminals of the capacitors 31 are connected to N wirings 33 (represented as wirings 33_1 to 33_N). The gates of the N transistors 31 are connected to each other. A first terminal of the transformer 31_i (i is any one of 1 to N) is connected to the wiring 32_i. A second terminal of the transistor 31_i is connected to the wiring 33_i. The transistor 1 has a function similar to that of the transistor 101 or the transistor 102. The wiring 33 has a function similar to that of the wiring 111 or the wiring 113. 4. However, if the number of transistors 31 is too large, the circuit size becomes large. Therefore, N is preferably 2 or more and 5 or less. More preferably, , 2 or 3. FIG. 4(B) shows an example of a circuit having three transistors. Shows.

[0057] In addition, in one or both of the transistors 101 and 102, A capacitor can be connected between the first terminal and the second terminal. A capacitance element 121 is connected between the gate and the second terminal of the transistor 101. In the circuit shown in FIG. 4C, a capacitor 122 is connected between the first terminal and the second terminal. In the above, a parasitic capacitance between the gate and the second terminal of the transistor 101 or The potential of the node N1 is increased by using the parasitic capacitance between the gate of 102 and the second terminal. In this case, the transistor 101 and the transistor A capacitance element is connected between the gate and the second terminal of one or both of the transistors 102 and 103. This makes it possible to increase the amount of rise in the potential of the node N1.

[0058] An example of the size of each transistor and the width of each wiring in FIG. 1(A) and FIG. 4(A) to (C) An example will be described below.

[0059] The larger the load on a wiring or node, the longer it takes to charge and discharge that load. The greater the load on the line or node, the greater the signal distortion and delay. The larger the load connected to a transistor, the greater the W / L (W: channel width, L It is preferable to increase the ratio of the signal width to the channel length. This reduces signal distortion and delay. Therefore, when a load such as a pixel is connected to the wiring 114, The load of the line 4 is larger than the load of the line 112. Therefore, the channel of the transistor 102 The width of the transistor 101 is preferably larger than the channel width of the transistor 101. The channel width of the transistor 102 is at least twice as large as that of the transistor 101, and is preferably at least 30 times as large. More preferably, it is 5 times or more and 20 times or less. Even more preferably, it is 8 times or more and 1 It is less than five times.

[0060] In addition, when a load such as a pixel is connected to the wiring 114, the load of the wiring 114 becomes Therefore, when the wiring 113 and the wiring 114 are in a conductive state, The current value of the line 113 is the current of the line 111 when the line 111 and the line 112 are in a conductive state. As a result, the decrease in the potential of the wiring 113 due to the voltage drop is The decrease in potential of the wiring 113 is larger than the decrease in potential of the wiring 111 due to the The width of the wiring 113 is preferably larger than the width of a portion of the wiring 111. Since the resistance value of the wiring 113 can be reduced, the decrease in potential of the wiring 113 due to the voltage drop can be reduced. It can be reduced.

[0061] In addition, when a load such as a pixel is connected to the wiring 114, the load of the wiring 114 becomes Therefore, the signal on the wire 114 is more likely to be distorted and delayed than the signal on the wire 112. Therefore, the width of a part of the wiring 114 is set to be smaller than the width of a part of the wiring 112. This makes it possible to reduce the resistance of the wiring 114. This makes it possible to reduce distortion and delay of the signal on line 114.

[0062] The wiring 112 or the wiring 114 is connected to a load such as a transistor provided in a pixel of a display device. FIG. 1B shows a case where a pixel including a liquid crystal element is connected to the wiring 114. The pixel 10 includes a transistor 11, a liquid crystal element 12, and a capacitor 13 (for example, The first terminal of the transistor 11 is connected to a wiring 21 (for example, a source signal The second terminal of the transistor 11 is connected to the liquid crystal element 12. The gate of the transistor 11 is connected to a first electrode (for example, a pixel electrode). A first electrode of the capacitance element 13 is connected to a wiring 23 (for example, a capacitance line). A second electrode of the capacitor element 13 is connected to a first electrode of the liquid crystal element 12. The second electrode (eg, a common electrode) is connected to the wiring 22.

[0063] However, the wiring 114 is not limited to the pixel 10 shown in FIG. 1B, and various other loads may be used. For example, a light emitting element (for example, an EL element) can be connected to the wiring 114. A display element having a memory property (for example, an electrophoretic display element), a display element in which the gray scale is changed by electrophoresis, display element that changes gradation by electrodeposition, A display element that changes the gradation by the ROMIC method, and a display element that changes the gradation by the twist ball method display elements that display colored particles, display elements that include electronic ink, and display elements that include colored particles. As another example, the wiring 114 may be connected to a pixel having either one of the As another example, a protection diode can be connected to the wiring 114. Circuits such as multiplexers can be connected.

[0064] When a load such as a transistor is connected to the wiring 114, the wiring 114 is Alternatively, the area of ​​the wiring 114 may be larger than the area of ​​the wiring 112. Therefore, when a load is connected to the wiring 114 as shown in FIG. It is preferable to provide a protection circuit 130 for the wiring 114. This can prevent elements and the like connected to the power supply from being destroyed by electrostatic discharge.

[0065] FIG. 5B shows an example of the protection circuit 130. The protection circuit 130 shown in FIG. N is a natural number) of transistors 131 (referred to as transistors 131_1 to 131_N) A first terminal of a transistor 131_i (i is any one of 2 to N-1) is The second terminal of the transistor 131_i is connected to the second terminal of the transistor 131_i-1. The terminal of the transistor 131_i+1 is connected to the first terminal of the transistor 131_i+1. The gate of the transistor 131_i is connected to the second terminal of the transistor 131_i. The first terminal of the transistor 131_1 is connected to the wiring 114. The transistor 131_N has a second terminal connected to the wiring 141. The wiring 141 is connected to a predetermined voltage (for example, a voltage V2). Supplied.

[0066] In the protection circuit 130 shown in FIG. 5B, as shown in FIG. 5C, The gates of the gates 131_1 to 131_N can be connected to a wiring 141.

[0067] When the voltage V1 is supplied to the wiring 141, in the protective circuit illustrated in FIG. The gate of the transistor 131_i is connected to the first terminal of the transistor 131_i. The gate of the transistor 131_1 is connected to the wiring 114. The gate may be connected to a first terminal of the transistor 131_N.

[0068] When the voltage V1 is supplied to the wiring 141, in the protective circuit illustrated in FIG. The gates of the transistors 131_1 to 131_N can be connected to the wiring 114. It is.

[0069] The circuit configuration described in FIG. 1 to FIG. 5 is implemented on a semiconductor substrate such as a silicon wafer, SOI ( All integrated circuits manufactured using silicon-on-insulator (Silicon-on-Insulator) substrates As another embodiment, it can be used as a part or a part of an insulating substrate such as glass. A channel region is formed in a semiconductor film such as polycrystalline silicon or amorphous silicon provided on the The above circuit configuration can be realized by using a transistor having the above structure. Alternatively, an oxide semiconductor can be used.

[0070] (Signal Processing Circuit According to an Embodiment) FIG. 6 shows an example of another circuit including the circuit configuration shown in FIG. It can be used for gate signal line driving circuits, source signal line (video signal line) driving circuits, etc. This is an example of a signal processing circuit that can

[0071] The signal processing circuit shown in FIG. A transistor 201, a transistor 202, a transistor 203, and a transistor 204 , a transistor 205 , and a circuit 300 .

[0072] The polarity of the transistors 201 to 205 is the same as that of the transistors 101 and 102. It is preferable that the polarity of the semiconductor layer is the same as that of the semiconductor layer (for example, n-channel type). This is because transistors can be manufactured using

[0073] The circuit 300 is composed of one or more transistors. The polarity of the upper transistor is the same as that of the transistor 101 and the transistor 102 (e.g. As in the above, a silicon semiconductor, an oxide semiconductor, etc. This is because transistors can be manufactured using

[0074] The connection relationship of the signal processing circuit shown in FIG. The first terminal of the transistor 201 is connected to the wiring 115. The second terminal of the transistor 201 is connected to the wiring 112. The first terminal of the transistor 202 is connected to the wiring 115. The second terminal of the transistor 202 is connected to the wiring 114. The gate of the transistor 202 is The first terminal of the transistor 203 is connected to the gate of the transistor 201. The second terminal of the transistor 203 is connected to the node N1. The gate of the transistor 203 is connected to the gate of the transistor 201. A first terminal of the transistor 204 is connected to the wiring 116. The gate of the transistor 204 is connected to the wiring 116. A first terminal of the transistor 205 is connected to the wiring 115. The terminal of the transistor 205 is connected to the node N1. The gate of the transistor 205 is connected to the wiring 117. Depending on the configuration, the circuit 300 may be connected to various wirings (e.g., wirings 111 to 117). In the example of FIG. 6, the circuit 300 includes a node N1 and a transistor It is connected to the gate of the transistor 201 .

[0075] The gate of the transistor 201, the gate of the transistor 202, and the gate of the transistor The connection point between the gate of 203 and the circuit 300 is referred to as node N2.

[0076] The wiring 115, the wiring 116, and the wiring 117 will be described below.

[0077] A predetermined voltage (for example, voltage V2) is supplied to the wiring 115. transmits a voltage (for example, voltage V2) from an external circuit such as a power supply circuit to the signal processing circuit shown in FIG. Therefore, the wiring 115 is a power supply line, a negative power supply line, a ground line, or the like. It has the function of

[0078] A signal (for example, a start signal) is input to the wiring 116. That is, the wiring 116 is 6. The signal processing circuit shown in FIG. 6 is connected to an external circuit such as a timing controller or another circuit. The wiring 116 is a signal line for transmitting a signal (for example, a start signal). Also, the H-level input to the wiring 116 functions as a start signal line. The potential of the signal becomes substantially equal to the potential V1, and the L level of the signal input to the wiring 116 The potential at this point is approximately equal to the potential V2.

[0079] A signal (for example, a reset signal) is input to the wiring 117. 6. The signal processing circuit shown in FIG. 6 is connected to an external circuit such as a timing controller or another circuit. The wiring 117 is a signal line for transmitting a signal (for example, a reset signal). In addition, the H-level input to the wiring 117 functions as a reset signal line. The potential of the signal becomes substantially equal to the potential V1, and the L level of the signal input to the wiring 117 The potential at this point is approximately equal to the potential V2.

[0080] Note that the wiring 115 can be supplied with a voltage from an external circuit such as a power supply circuit. In addition, the wiring 116 and the wiring 117 are connected to an external circuit such as a timing controller or a signal It is possible for a signal to be input from another circuit formed on the same substrate as the signal processing circuit.

[0081] Examples of functions of the transistors 201 to 205 will be described below.

[0082] The transistor 201 serves as a switch that controls the electrical continuity between the wiring 115 and the wiring 112. Alternatively, the transistor 201 may be configured to set the potential of the wiring 112 to a constant potential (e.g., For example, the potential of the wiring 115).

[0083] The transistor 202 is a switch that controls the conduction state between the wiring 115 and the wiring 114. Alternatively, the transistor 202 may function as a constant potential. (for example, the potential of the wiring 115).

[0084] The transistor 203 is a switch that controls the electrical continuity between the wiring 115 and the node N1. Alternatively, the transistor 203 may function as a constant potential. (for example, the potential of the wiring 115).

[0085] The transistor 204 serves as a switch that controls the electrical continuity between the wiring 116 and the node N1. Alternatively, the transistor 204 has the following functions: The output terminal of the transistor is connected to the node N1. The transistor 204 has a function of controlling the timing at which the potential of the node N1 is increased. The transistor 204 has a function of controlling the timing of putting the node N1 into a floating state. Alternatively, the transistor 204 controls the timing of the set operation of the signal processing circuit. It has the function of

[0086] The transistor 205 is a switch that controls the conduction state between the wiring 115 and the node N1. The transistor 205 operates at a timing when the potential of the node N1 is decreased. Alternatively, the transistor 205 functions as a switch for controlling the signal processing. It has the function of controlling the timing of the reset operation of the circuit.

[0087] An example of the functions of the circuit 300 will be described below.

[0088] The circuit 300 functions as a control circuit that controls the potential of the node N2. The circuit 300 has a function of controlling the conduction state of the transistors 201 to 203. The circuit 300 is an inverter circuit that inverts the potential of the node N1 and outputs the inverted potential to the node N2. It has the function of

[0089] Regarding an example of the operation of the signal processing circuit shown in FIG. 13 are both in an active state, and The signal is in an active state and the signal input to the wiring 113 is in an inactive state. The following will explain the case where a clock signal is input to the wiring 111. In the case of the active state, the clock signal input to the wiring 111 is transmitted to the wiring 112. When a clock signal that is in phase with the VCLK signal is input and in the inactive state, the voltage V Assume that an L-level signal is input.

[0090] First, a signal input to the wiring 111 and a signal input to the wiring 113 are both active. For an example of the operation in the blocked state, refer to the timing chart shown in FIG. The timing chart shown in FIG. 7A is divided into periods A1 to E1 (each period is one gate). The period is also called the selection period.

[0091] In the period A1, the potential of the wiring 111 (denoted as V111) is equal to the potential V2. The potential of the wiring 116 (denoted as V116) is equal to the potential V2. The potential of the wiring 117 (denoted as V117) is equal to the potential V2. As a result, the transistor 204 is turned on, and the wiring 116 and the node N1 The transistor 205 is turned off, and the wiring 115 and the node N1 are Therefore, the potential of the wiring 116 is supplied to the node N1, and The potential (denoted VN1) begins to rise.

[0092] After that, the potential of the node N1 becomes V2+Vth101 (Vth101 is the potential of the transistor 10 1) and V2+Vth102 (Vth102 is the threshold voltage of transistor 10 At this time, the circuit 300 is at a potential (for example, a potential V2) is supplied to the node N2, and the potential of the node N2 (denoted as VN2) becomes V2. The potential of the node N2 is V2+Vth201 (Vth201 is the threshold voltage of the transistor 201). V2+Vth202 (Vth202 is the threshold voltage of transistor 202) and less than V2+Vth203 (Vth203 is the threshold voltage of the transistor 203). As a result, the transistor 101 is turned on, and the wiring 111 and the wiring 112 The transistor 102 is turned on, and the wiring 113 and the wiring 114 are connected to each other. The transistor 201 is turned off, and the wiring 115 and the wiring 112 are The transistor 202 is turned off, and the wiring 115 and the wiring 114 are The transistor 203 is turned off, and the wiring 115 and the node N1 are Therefore, the potential of the wiring 111 is supplied to the wiring 112, and The potential (indicated as V112) is equal to the potential V2. The potential of the wiring 114 (denoted as V114) becomes equal to the potential V2.

[0093] Thereafter, the potential of the node N1 becomes V1-Vth204 (Vth204 is the potential of the transistor 20 As a result, the transistor 204 is turned off and the line 1 16 and node N1 are in a non-conductive state. Therefore, node N1 is in a floating state, and The potential of N1 is maintained at V1-Vth204 (see FIG. 8A). The circuit formed by the transistors 101 and 102 is shown in FIG. ) performs operation DR4 shown in FIG.

[0094] In the period B1, the potential of the wiring 111 is equal to the potential V1. The potential of the wiring 116 is equal to the potential V2. The potential of the wiring 117 is equal to the potential V 2. Node N1 is left floating and the potential at node N1 is V1- The potential of the node N2 remains at Vth204.

[0095] As a result, the transistor 201 remains off, and the wiring 115 and the wiring 112 The transistor 202 remains off, and the wiring 115 and The transistor 203 remains off. The wiring 115 and the node N1 remain in a non-conductive state. The transistor 204 is in an off state. Therefore, the wiring 116 and the node N1 remain in a non-conductive state. The transistor remains in an off state, and the wiring 115 and the node N1 remain in a non-conducting state. The resistor 101 remains on, and the wiring 111 and the wiring 112 remain in a conductive state. The transistor 102 remains on, and the wiring 113 and the wiring 114 are in electrical continuity. It will remain as it is.

[0096] Therefore, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 112 starts to rise. The potential of the wiring 113 is supplied to the wiring 114, and the potential of the wiring 114 starts to rise. Therefore, the potential of the node N1 is The parasitic capacitance between the gate and the second terminal of the transistor 101 and the gate It increases due to the parasitic capacitance between the first terminal and the second terminal.

[0097] Finally, the potential of the node N1 becomes higher than V1+Vth101 and V1+Vth Therefore, the potential of the wiring 112 is equal to the potential V1. The potential of the wiring 114 can rise to a value equal to the potential V1. That is, in the period B1, the transistors 101 and The circuit formed by the transistor 102 performs the operation DR1 shown in FIG.

[0098] In the period C1, the potential of the wiring 111 is equal to the potential V2. The potential of the wiring 116 remains equal to the potential V2. The potential of the wiring 117 This makes the transistor 204 remain in the off state, and the potential V 116 and node N1 remain non-conductive. Transistor 205 turns on. Therefore, the potential of the wiring 115 is equal to the potential of the node N1. , and the potential of the node N1 becomes equal to the potential V2.

[0099] As a result, the transistor 101 is turned off, and the wiring 111 and the wiring 112 are non-conductive. The transistor 102 is turned off, and the wiring 113 and the wiring 114 are non-conductive. At this time, the circuit 300 supplies a potential (for example, a potential V1) to the node N2, The potential of the node N2 is higher than V2+Vth201 and higher than V2+Vth202. And it is higher than V2+Vth203.

[0100] As a result, the transistor 201 is turned on, and the wiring 115 and the wiring 112 are electrically connected. The transistor 202 is turned on, and the wiring 115 and the wiring 114 are brought into electrical continuity. The transistor 203 is turned on, and electrical continuity is established between the wiring 115 and the node N1. Therefore, the potential of the wiring 115 is supplied to the wiring 112, and the potential of the wiring 112 becomes The potential of the wiring 115 is supplied to the wiring 114, and the potential of the wiring 114 is In other words, in the period C1, the transistor 101 The circuit formed by the transistor 102 performs the operation DR8 shown in FIG. cormorant.

[0101] In the periods D1 and E1, the potential of the wiring 111 is either the potential V1 or the potential V2 (in the period D The potential of the wiring 113 is equal to the potential V1 in the period E1 and the potential V2 in the period E2. The potential V1 is equal to the potential V2 in the period D1, and the potential V2 is equal to the potential V1 in the period E1. The potential of the wiring 116 remains equal to the potential V2. The potential of the wiring 117 becomes equal to the potential V2. At this time, the circuit 300 continues to supply a potential (for example, potential V1) to the node N2. The potential of the node N2 is higher than V2+Vth201 and higher than V2+Vth202. And it remains higher than V2+Vth203.

[0102] As a result, the transistor 204 remains off, and the wiring 116 and the node N1 remains non-conductive. Transistor 205 is turned off. Transistor 203 remains in the on state, and electrical continuity between the wiring 115 and the node N1 remains. The potential of the wiring 115 remains supplied to the node N1, and the potential of the node N1 is V2 As a result, the transistor 101 remains off, and the wiring 1 The transistor 102 remains in an off state. Therefore, the wiring 113 and the wiring 114 remain in a non-conducting state. The transistor 201 is turned on. The transistor 2 remains in the ON state, and the wiring 115 and the wiring 112 remain in an electrically connected state. 02 remains in the on state, and the wiring 115 and the wiring 114 remain in the conductive state. Therefore, the potential of the wiring 115 remains supplied to the wiring 112, and the potential of the wiring 112 is The potential of the wiring 115 remains supplied to the wiring 114, and the potential of the wiring 115 remains supplied to the wiring 114. The potential of the line 114 remains equal to the potential V2 (see FIG. 9B). The circuit formed by the transistors 101 and 102 is shown in FIG. In addition, in the period E1, the transistor 101 and the transistor The circuit formed by the converter 102 performs the operation DR8 shown in FIG.

[0103] Next, a signal input to the wiring 111 is in an active state, and a signal input to the wiring 113 is in an active state. An example of the operation when the signal to be transmitted is inactive is shown in the timing diagram of FIG. The timing chart shown in FIG. E2 (each period is also called one gate selection period).

[0104] In the period A2, the signal processing circuit shown in FIG. 6 performs the same operation as in the period A1. The description of the operation in the period A2 is omitted. The circuit formed by the transistor 102 performs the operation DR4 shown in FIG. cormorant.

[0105] In the period B2, the potential of the wiring 113 remains equal to the potential V2. Therefore, in the period B2, the potential of the wiring 114 remains equal to the potential V2 (see FIG. In other words, in the period B2, the transistors 101 and 10 The circuit formed by 2 performs the operation DR2 shown in FIG.

[0106] In the period C2, the signal processing circuit shown in FIG. 6 performs the same operation as in the period C1. The description of the operation during the period C2 will be omitted. The circuit formed by the transistor 102 performs the operation DR8 shown in FIG. cormorant.

[0107] In the periods D2 and E2, the potential of the wiring 113 remains equal to the potential V2. In other words, in the period D2, the transistor The circuit formed by the transistor 101 and the transistor 102 is the same as that shown in FIG. In the period E2, the transistors 101 and 102 are The circuit thus configured performs the operation DR8 shown in FIG.

[0108] As described above, the signal processing circuit illustrated in FIG. 6 outputs a signal to be input to the wiring 113 in an active state. By controlling whether the potential of the wiring 112 is in an active state or an inactive state, The potentials of the wiring 112 and the wiring 114 are both set to the potential V1, or the potentials of the wiring 112 and the wiring 114 are both set to the potential V2. 4 is made equal to potential V1 and the other is made equal to potential V2. This can be done.

[0109] The wirings 115 to 117 are not limited to the signals or voltages described above, but may be used for various other signals or voltages. It is possible to input various voltages. An example will be described below.

[0110] A signal (for example, an inverted signal of the signal input to the wiring 111) is input to the wiring 115. That is, the wiring 115 can receive an inverted signal of a signal input to the wiring 111 or the like. It is possible for the wiring to transmit a signal to the signal processing circuit shown in FIG. 15 can function as a signal line, a clock signal line, or an inverted clock signal line. When a signal is input to the wiring 115, the transistor connected to the wiring 115 (e.g., transistor 201, transistor 202, or transistor 203, etc.) Since a reverse bias can be applied, degradation of the transistor can be suppressed.

[0111] When a signal is input to the wiring 115, the wiring 115 is connected to a timing controller or the like. A signal is input from an external circuit or from another circuit formed on the same substrate as the signal processing circuit. is possible.

[0112] The signal processing circuit shown in FIG. 6 is not limited to the timing charts shown in FIGS. Various other timing charts can be used. This is explained below.

[0113] In the timing chart shown in FIG. 7A, a signal input to the wiring 111 and a signal input to the wiring 1 13 can be unbalanced. In the timing chart, the signal input to the wiring 111 can be unbalanced. A balanced signal is one in which the time it is high and the time it is low are roughly equal. The signal is not a balanced signal. In the timing chart, a signal input to the wiring 111 and a signal input to the wiring 113 The timing chart for the case where both the 1st and 2nd signals are unbalanced is shown in FIG. The time during which the signal input to the wiring 111 and the signal input to the wiring 113 are at the H level is shorter than the L level time.

[0114] In the timing chart shown in FIG. 7A, the signal input to the wiring 111 is unbalanced. Similarly, in the timing chart shown in FIG. The signal input to the 1 can be unbalanced. In the timing chart, the timing when the signal input to the wiring 111 is unbalanced A chart is shown below.

[0115] In the timing charts shown in FIGS. 7(A), (B), 11(A), and (B), The signal input to 111 and / or the signal input to wiring 113 is converted into a multiphase clock signal. Note that a signal input to the wiring 111 and a signal input to the wiring 113 The clock signal may be a 3-phase, 4-phase, 6-phase or 8-phase clock signal. This reduces power consumption. FIG. 12(A) shows the configuration of the embodiment shown in FIG. 7(A) while suppressing an increase in the number of signals. In the timing chart, a signal input to the wiring 111 and a signal input to the wiring 113 This shows an example in which the 1st and 2nd phase signals are converted into a 3-phase clock signal.

[0116] Timing charts shown in Figs. 7(A), (B), 11(A), (B), and 12(A) In the period E1, the potential of the node N2 is less than V2+Vth201, V2+V It can be less than Vth202 and less than V2+Vth203. The potential of node N2 can be V2. Since the time that the transistors 201 to 203 are in the ON state can be shortened, The degradation of 3 (e.g., threshold voltage shift or mobility reduction) can be reduced. 12(B) is a node in the period E1 in the timing chart shown in FIG. 13 shows a timing chart when the potential of N2 becomes V2.

[0117] The signal processing circuit capable of performing the above-mentioned operation is not limited to that shown in FIG. Various configurations can be used for the above. An example will be described.

[0118] In the signal processing circuit illustrated in FIG. 6, a first terminal of the transistor 204 is connected to the wiring 118. Alternatively, the first terminal may be connected to the signal processing circuit shown in FIG. a transistor having a first terminal connected to the node N1 and a gate connected to the wiring 116; A predetermined voltage (for example, voltage V1) is applied to the wiring 118. The wiring 118 is a wiring that is supplied with power and functions as a power supply line or a positive power supply line. In the case of the signal (for example, the signal line 111) that is at the H level at least during the period A1 and the period A2, It is also possible to input an inverted signal of the signal input to the In the signal processing circuit illustrated in FIG. 6, a first terminal of the transistor 204 is connected to the wiring 118. The resulting circuit is shown.

[0119] In the signal processing circuit shown in FIG. 6 and FIG. 13A, a transistor 201 and a transistor 202 or 203 can be omitted. This reduces the number of transistors. This allows for improved yield and reliability. 6, the transistor 201 is omitted. When a load such as a pixel is connected to the wiring 114, the transistor 201 is preferably omitted. When the signal input to the wiring 113 is inactive, the transistor It is preferable to omit the controller 201.

[0120] In the signal processing circuits shown in FIGS. 6, 13A, and 13B, the transistor 221 and the transistor A first terminal of the transistor 221 may be connected to the wiring 115. A second terminal of the transistor 221 is connected to the wiring 112. The gate of the transistor 221 is connected to the wiring 117. The first terminal of the transistor 222 is connected to the wiring 117. A second terminal of the transistor 222 is connected to the wiring 114. The gate of the transistor 222 is connected to the wiring 117. The transistor 221 is turned on, and the wiring 115 and the wiring 112 are brought into a conductive state. Therefore, in the periods C1 and C2, the fall time of the potential of the wiring 112 is shortened. In the periods C1 and C2, the transistor 222 is turned on, and Therefore, in the periods C1 and C2, the wiring 115 and the wiring 114 are electrically connected to each other. The fall time of the potential of the line 114 can be shortened. In the signal processing circuit shown in FIG. The circuit is shown below.

[0121] In the signal processing circuits shown in FIGS. 6, 13A, and 13B, the transistor 221 In particular, only one of the transistors 222 and 223 may be provided in the wiring 114. In the case where a load such as the above is connected, it is preferable to provide only the transistor 222. When the signal applied to line 113 is inactive, only transistor 222 is set. It is preferable to do so.

[0122] In the signal processing circuits shown in FIG. 6, FIG. 13(A), (B), and FIG. 14(A), A first terminal of the transistor 223 is connected to the wiring 115. The second terminal of the transistor 223 is connected to the node N2. The gate of the transistor 22 is connected to the wiring 116. 3 is turned on, and electrical continuity is established between the wiring 115 and the node N2. In addition, in the period A2, the fall time of the potential of the node N2 can be shortened. FIG. 14B shows a case where a transistor 223 is provided in the signal processing circuit shown in FIG. The circuit for this case is shown.

[0123] In the signal processing circuits shown in Figs. 6, 13(A), (B), 14(A), and (B), A first terminal of the transistor 224 may be connected to the wiring 118. The second terminal of the transistor 224 is connected to the node N2. The gate of the transistor 224 is connected to the wiring 117. The stator 224 is turned on, and the wiring 118 and the node N2 are brought into a conductive state. In the periods C1 and C2, the rise time of the potential of the node N2 can be shortened. 15A shows a configuration in which the transistor 224 is not added to the signal processing circuit shown in FIG. The circuit when the above is provided is shown.

[0124] The signal processing circuits shown in Figs. 6, 13(A), (B), 14(A), (B), and 15(A) In the circuit, a transistor 225 and a transistor 226 may be provided. A first terminal of the transistor 225 is connected to the wiring 112. The gate of the transistor 225 is connected to the wiring 111. A first terminal of the transistor 226 is connected to the wiring 114. The gate of the transistor 226 is connected to the wiring 111. In the periods D1 and D2, the transistor 225 is turned on, and the wiring 112 and node N1 are in a conductive state. is turned on, and electrical continuity is established between the wiring 114 and the node N1. In the signal processing circuit shown in FIG. 6, a transistor 225 and a transistor 226 are provided. The circuit for this case is shown below.

[0125] Note that the signals shown in Figs. 6, 13(A), (B), 14(A), (B), and 15(A) In the processing circuit, only one of the transistor 225 and the transistor 226 is provided. In particular, when a load such as a pixel is connected to the wiring 114, the transistor 226 In particular, when the signal input to the wiring 113 is inactive, In this case, it is preferable to provide only transistor 226.

[0126] Note that the gate of the transistor 225 can be connected to the wiring 113. In addition, the gate of the transistor 226 can be connected to the wiring 113.

[0127] When the transistor 225 or the transistor 226 is provided, the transistor 203 It is possible to omit the above.

[0128] The signals shown in Figs. 6, 13(A), (B), 14(A), (B), and 15(A), (B) The signal processing circuit may include a transistor 227. A first terminal of the transistor 227 is connected to the wiring 116. A second terminal of the transistor 227 is connected to the node N1. The gate of the transistor 227 is connected to the wiring 119. The wiring 119 is a signal A signal (for example, an inverted signal of a signal input to the wiring 111, or a signal input to the wiring 111) A signal line, clock signal line, or inverted clock signal line is input. The signal input to the wiring 119 is a digital signal. The H-level potential of the signal input to the wiring 119 is the same as the H-level potential of the signal input to the wiring 111. The potential of the signal input to the wiring 119 is approximately equal to the H level potential (for example, potential V1). The L-level potential of the signal input to the wiring 111 (for example, For example, the potential is approximately equal to the potential V2 during the periods A1, C1, E1, and A2. In the periods C2 and D2, the transistor 227 is turned on and the wiring 116 The node N1 is in a conductive state. 2 shows a circuit in which a transistor 227 is provided.

[0129] Figure 6, Figure 13(A), (B), Figure 14(A), (B), Figure 15(A), (B), Figure 16 In the signal processing circuit shown in (A), a transistor 228 and a transistor 229 are provided. A first terminal of the transistor 228 is connected to the wiring 115. The second terminal of the transistor 228 is connected to the wiring 112. The gate of the transistor 228 is connected to the wiring A first terminal of the transistor 229 is connected to the wiring 115. The second terminal of the transistor 229 is connected to the wiring 114. The gate of the transistor 229 is It is connected to the wiring 119. For example, in the period A1, the period C1, the period E1, the period A2, and the period C2 In the period E2, the transistor 228 is turned on, and the wiring 115 and the wiring 112 are in a conductive state. In this state, the transistor 229 is turned on, and the wiring 115 and the wiring 114 are brought into electrical continuity. 16B. Note that in the signal processing circuit shown in FIG. 2 shows a circuit in which a transistor 229 is provided.

[0130] In addition, Figs. 6, 13(A), (B), 14(A), (B), 15(A), (B), In the signal processing circuit shown in FIG. In particular, when a load such as a pixel is connected to the wiring 114, In this case, it is preferable to provide only the transistor 229. When the signal goes to an inactive state, it is preferable to only provide transistor 229.

[0131] The circuit 300 can have various configurations, one example of which is described below. .

[0132] FIG. 17A illustrates an example in which an inverter circuit 301 is used as the circuit 300. The input terminal of the inverter circuit 301 is connected to the node N1. The input terminal of the inverter circuit 301 is connected to the node N2. 1, and may be connected to wiring 112, wiring 114, wiring 111, etc. do.

[0133] FIG. 17B shows an example of a circuit 300 including a transistor 302 and a transistor 303. The circuit 300 shown in FIG. 17B functions as an inverter circuit. The first terminal of the transistor 302 is connected to the wiring 118. The gate of the transistor 302 is connected to the wiring 118. A first terminal of the transistor 303 is connected to the wiring 115. The gate of transistor 303 is connected to node N1. As shown in FIG. 17C, in the circuit 300 shown in FIG. 17B, The gate of the transistor 302 can be connected to the node N2. As shown in FIG. 17B, in the circuit 300 shown in FIG. 17B, the transistor 302 is replaced with a resistor element The resistor element 304 can be replaced with a resistor 304 between the wiring 118 and the node N2. It should be noted that the circuit 300 shown in FIG. 17(B), FIG. 17(C) and FIG. 17(D) In the above, the gate of the transistor 303 is connected to the wiring 112 or the wiring 114. is possible.

[0134] FIG. 17E shows a transistor 305, a transistor 306, a transistor 307, and a transistor 17(E) shows an example of a circuit 300 having a transistor 308. The circuit 300 shown in FIG. The first terminal of the transistor 305 is connected to the wiring 118. The second terminal of the transistor 305 is connected to the node N2. A first terminal of the transistor 306 is connected to the wiring 115. A second terminal of the transistor 306 is connected to the The gate of transistor 306 is connected to node N1. A first terminal of the transistor 307 is connected to the wiring 118. A second terminal of the transistor 307 is The gate of the transistor 307 is connected to the wiring 118. A first terminal of the transistor 308 is connected to the wiring 115. The second terminal of the transistor 308 is connected to the gate of the transistor 305. The gate is connected to a node N1. The gate of the transistor 306 can be connected to the line 112 or the line 114 . In the circuit 300 illustrated in FIG. 17E, the gate of the transistor 308 is connected to the wiring 1. 12 or wiring 114.

[0135] FIG. 18A shows a transistor 311, a transistor 312, a transistor 313, and a transistor An example of a circuit 300 having a transistor 314 is shown in FIG. By using this configuration, the timing chart shown in FIG. 12(B) can be realized. A first terminal of the transistor 311 is connected to the wiring 111. A first terminal of the transistor 312 is connected to the wiring 115. The second terminal of the transistor 312 is connected to a node N2. The gate of the transistor 312 is connected to the node N1. The first terminal of the transistor 313 is connected to the wiring 1. The second terminal of the transistor 313 is connected to the gate of the transistor 311. The gate of the transistor 313 is connected to the wiring 111. A first terminal of the transistor 314 is connected to the wiring 115. A second terminal of the transistor 314 is connected to the wiring 115. The gate of transistor 314 is connected to node N2. As shown in FIG. 18B, in the circuit 300 shown in FIG. A first terminal of the transistor 315 is connected to the wiring 115. The second terminal of the transistor 315 is connected to the gate of the transistor 311. The gate of the transistor 315 is connected to the wiring 119. As shown in FIG. 18A, the transistor 315 and the transistor 3 A first terminal of the transistor 316 is connected to the wiring 115. The second terminal of the transistor 316 is connected to the node N2. The gate of the transistor is connected to a wiring 119. In the circuit 300 shown in FIG. 1, the gate of the transistor 312 is connected to the wiring 112 or the wiring 11. 4. In addition, FIG. 18(A), FIG. 18(B) and FIG. 18(C) In the circuit 300 shown in FIG. 1, the gate of the transistor 314 is connected to the wiring 112 or the wiring 114. It is possible to connect with.

[0136] An example of the ratio of the sizes of the transistors will be described below.

[0137] When a load such as a pixel is connected to the wiring 114, the load of the wiring 114 is Therefore, the W / L ratio of transistor 202 is greater than the W / L ratio of transistor 201. / L ratio. This allows the fall time of the signal on the wiring 114 to be It is possible to reduce the layout area while shortening the length. More preferably, it is 1.2 times or more and 7 times or less. Even more preferably, it is 2 More than twice as much and less than five times as much.

[0138] When a load such as a pixel is connected to the wiring 114, the load of the wiring 114 is On the other hand, when the channel widths of the transistors 101 and 102 are Therefore, the load of the node N1 is smaller than the load of the wiring 114 and is smaller than the load of the wiring 112. Therefore, the W / L ratio of transistor 203 is larger than that of transistor 201. The W / L ratio of transistor 203 is preferably greater than the W / L ratio of transistor 20 A W / L ratio of less than 2 is preferred.

[0139] When a load such as a pixel is connected to the wiring 114, the load of the wiring 114 is On the other hand, the load of the node N1 is smaller than the load of the wiring 114. The W / L ratio of transistor 204 is therefore The W / L ratio of transistor 204 is preferably greater than that of transistor 101. It is preferable that the W / L ratio is smaller than that of the transistor 102 .

[0140] When a load such as a pixel is connected to the wiring 114, the load of the wiring 114 is Therefore, the W / L ratio of transistor 222 is greater than the W / L ratio. This allows the fall time of the signal on the wiring 114 to be It is possible to shorten the length and reduce the layout area.

[0141] When a load such as a pixel is connected to the wiring 114, the load of the wiring 114 is On the other hand, the load of the node N2 is smaller than the load of the wiring 114. The load of transistor 223 is larger than that of transistor 112. The W / L ratio of transistor 223 is preferably greater than that of transistor 201. It is preferable that the W / L ratio is smaller than that of the transistor 202 .

[0142] In the period C1 or C2, the timing at which the potential of the node N2 rises is advanced. As a result, the timing at which the transistors 201 and 202 are turned on is accelerated. Therefore, it is preferable that the W / L ratio of the transistor 224 is large. On the other hand, in the period C1 or C2, the timing at which the potential of the node N1 decreases is delayed. By shortening the time when the transistors 101 and 102 are turned off, As a result, the potential V2 of the wiring 111 and the potential V3 of the wiring 113 are 12 and the wiring 114, respectively. The fall time of the signal at transistor 14 can be shortened. The W / L ratio of 24 is preferably greater than the W / L ratio of transistor 205 .

[0143] When a load such as a pixel is connected to the wiring 114, the load of the wiring 114 is Therefore, the W / L ratio of transistor 226 is greater than the W / L ratio of transistor 225. It is preferable that the ratio is greater than the / L ratio.

[0144] The transistor 225 and the transistor 201 are connected to the potential of the wiring 112 or the potential of the node N1. However, the W / L ratio of transistor 225 is too large. In this case, the potential of the node N1 decreases during the periods B1 and B2, which may cause a malfunction. Therefore, the W / L ratio of transistor 225 is greater than the W / L ratio of transistor 201. It is preferable that the distance between the slits is smaller than the distance between the slits.

[0145] The transistor 226 and the transistor 202 are connected to the potential of the wiring 114 or the potential of the node N1. However, the W / L ratio of transistor 226 is too large. In this case, the potential of the node N1 decreases during the periods B1 and B2, which may cause a malfunction. Therefore, the W / L ratio of transistor 226 is greater than the W / L ratio of transistor 202. It is preferable that the distance between the slits is smaller than the distance between the slits.

[0146] When a load such as a pixel is connected to the wiring 114, the load of the wiring 114 is Therefore, the W / L ratio of transistor 229 is greater than the W / L ratio of transistor 228. It is preferable that the ratio is greater than the / L ratio.

[0147] As a display device having the above-described transistor, the following structure is one embodiment of the present invention. Includes.

[0148] The pixel includes a driving circuit and a pixel, the driving circuit including a first transistor and a second transistor. the pixel includes a third transistor and a liquid crystal element, and the first transistor The terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the third wiring. The second terminal of the second transistor is electrically connected to the fourth wiring. The gate of the transistor is electrically connected to the gate of the first transistor, and the gate of the third transistor is electrically connected to the gate of the second transistor. The first terminal of the third transistor is electrically connected to the fifth wiring, and the second terminal of the third transistor is electrically connected to the fifth wiring. The gate of the third transistor is electrically connected to one electrode of the liquid crystal element. The channel width of the first transistor is electrically connected to the wiring of the second transistor. A display device that is smaller than the channel width.

[0149] The pixel includes a driving circuit, a pixel, and a protection circuit. The driving circuit includes a first transistor and a second transistor. The pixel has a third transistor and a liquid crystal element, and the first transistor The first terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is The first terminal of the second transistor is electrically connected to the second wiring, and the first terminal of the second transistor is electrically connected to the third wiring. The second terminal of the second transistor is electrically connected to the fourth wiring. The gate of the second transistor is electrically connected to the gate of the first transistor. The first terminal of the third transistor is electrically connected to the fifth wiring. The second terminal of the transistor is electrically connected to one electrode of the liquid crystal element, and the gate of the third transistor is The protection circuit is electrically connected to the fourth wiring. A display device.

[0150] The pixel includes a driving circuit and a pixel, the driving circuit including a first transistor and a second transistor. a third transistor and an inverter circuit, and a pixel includes a fourth transistor and a liquid crystal display. a first terminal of the first transistor electrically connected to a first wiring; The second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the third wiring, and the second terminal of the second transistor is , the gate of the second transistor is electrically connected to the fourth wiring, The first terminal of the third transistor is electrically connected to the gate of the and a second terminal of the third transistor is electrically connected to the gate of the first transistor. and an input terminal of the inverter circuit is electrically connected to the gate of the first transistor. an output terminal of the inverter circuit is electrically connected to a gate of the third transistor; The first terminal of the fourth transistor is electrically connected to the sixth wiring. The second terminal of the transistor is electrically connected to one electrode of the liquid crystal element, and the gate of the fourth transistor is The port is a display device that is electrically connected to the fourth wiring.

[0151] (Configuration of a shift register according to an embodiment) FIG. 19 shows an example of a shift register circuit. This shift register circuit has the signal shown in FIG. It should be noted that, instead of the signal processing circuit shown in FIG. A signal processing circuit shown at 16 can also be applied.

[0152] The shift register circuit shown in FIG. 19 includes m (m is a natural number) circuits 401 (circuits 401_ 19 includes a circuit 401 shown in FIG. An example in which the signal processing circuit shown in FIG.

[0153] The circuit 402 functions as a dummy circuit. It is possible to have the same configuration as circuit 401, or a different configuration from circuit 401. For example, in the circuit 402, the transistor 101, the transistor 201, and the transistor It is possible to omit one or more of the transistors 205. Alternatively, the circuit 402 may be omitted. It is possible to do so.

[0154] The shift register circuit shown in FIG. m), m wirings 412 (represented as wirings 412_1 to 412_m), and wiring 41 3, wiring 414, wiring 415, wiring 416, wiring 417, wiring 418, and wiring 419 and the wiring 420. However, if the dummy circuit is omitted, the wiring 419 It is possible to omit the wiring 420.

[0155] The connection relationship of the circuit 401 will be described below. Here, the circuit 401_i (i is 2 or more) The connection relationship of the circuit 401_i is explained as an example. -1, the wiring 411_i, the wiring 411_i+1, the wiring 412_i, the wiring 413, and the wiring One of the wires 415 is connected to one of the wiring 414 and the wiring 416, and the wiring 417. Specifically, in the circuit 401_i, the wiring 111 is connected to one of the wiring 413 and the wiring 415. The wiring 112 is connected to the wiring 411_i. The wiring 113 is connected to the wiring 414. The wiring 114 is connected to one of the wirings 412_i and 416. The wiring 114 is connected to the wiring 412_i. The wiring 15 is connected to the wiring 417. The wiring 116 is connected to the wiring 411_i-1. The line 117 is connected to the wiring 411_i+1. The circuit 401_m differs from the circuit 401_i in that the wiring 418 is connected to the wiring 418. The circuit 401 differs from the circuit 401_i in that the line 117 is connected to a wiring 420.

[0156] The connection relationship of the circuit 402 will be described below. The circuit 402 includes a wiring 419 and a wiring 20, the wiring 411_m, one of the wiring 413 and the wiring 415, the wiring 414 and the wiring 41 6 is connected to the wiring 417. The wiring 112 is connected to one of the wiring 413 and the wiring 415. The wiring 112 is connected to the wiring 419. The wiring 113 is connected to one of the wiring 414 and the wiring 416. The wiring 114 is The wiring 115 is connected to the wiring 417. The wiring 116 is connected to the wiring 4 11_m. The wiring 117 is connected to the wiring 417.

[0157] An example of the wirings 411 to 418 will be described below.

[0158] An output signal of the circuit 401 is output from the wiring 411. The wiring 411 is a wiring for transmitting the output signal of the circuit 401 to the circuit to which it is connected. For example, the wiring 411_i transmits an output signal of the circuit 401_i to the circuit 4 01_i−1 and the circuit 401_i+1. The output signal output from the output terminal 111 is input to the wiring 116 of the circuit 401 in the next stage. The output signal output from 11 is input to the wiring 117 of the circuit 401 in the previous stage. The output signal output from the wiring 411 is a start signal and / or a reset signal. It has the following functions.

[0159] An output signal of the circuit 401 is output from the wiring 412. A signal line is a line for transmitting an output signal of the line 401 to a load connected to the line 412. In particular, when a pixel is connected to the wiring 412, the wiring 412 The output signal of the circuit 401 is transmitted as a signal for controlling the timing of selecting pixels. The wiring 412 functions as a gate signal line or a scanning signal line. It functions as a scanning line.

[0160] A signal such as a clock signal is input to the wiring 413. A signal line or a clock signal is a wiring that transmits a signal such as a clock signal to a shift register circuit. It has the function of a line.

[0161] A signal that is in either an active state or an inactive state is input to the wiring 414. When the signal input to the wiring 414 is in an active state, A signal having the same phase as the signal input to the wiring 413 is input to the wiring 414. When the signal to be transmitted is inactive, the wiring 414 carries an L-level signal or potential. That is, the wiring 414 is in an active state or an inactive state. A signal line or a clock line is a line that transmits a signal to the shift register circuit. It functions as a signal line.

[0162] The wiring 415 is connected to an inverted signal of the signal input to the wiring 413 (for example, an inverted clock signal). Alternatively, a signal having a phase shift from the signal input to the wiring 413 is input. The wiring 415 receives an inverted signal (for example, an inverted clock signal) of the signal input to the wiring 413 or The signal input to the wiring 413 is a signal that is out of phase with the signal input to the wiring 413. It functions as a signal line, a clock signal line, or an inverted clock signal line. do.

[0163] A signal that is in either an active state or an inactive state is input to the wiring 416. When the signal input to the wiring 416 is in an active state, A signal having the same phase as the signal input to the wiring 415 is input to the wiring 416. When the signal to be transmitted is inactive, the line 416 carries an L-level signal or potential. That is, the wiring 416 is in an active state or an inactive state. A signal line or a clock line is a line that transmits a signal to the shift register circuit. It functions as a signal line.

[0164] A predetermined voltage such as voltage V2 is supplied to the wiring 417. This is the wiring for supplying a certain voltage such as V1 to the shift register circuit. It functions as a power line or ground line.

[0165] A signal such as a start signal is input to the wiring 418. The wiring is for transmitting signals such as a clock signal to the shift register circuit (particularly the circuit 401_1). It functions as a signal line.

[0166] The wiring 413, the wiring 414, the wiring 415, the wiring 416, and the wiring 418 are each provided with a tie wire. A signal can be input from an external circuit such as a timing controller. A signal generated based on a signal input to the wiring 413 may be input to the wiring 414 . A signal generated based on the signal input to the wiring 415 is input to the wiring 416. This is also fine.

[0167] Note that the wiring 417 can be supplied with a voltage from an external circuit such as a power supply circuit. .

[0168] An example of the operation of the shift register circuit shown in FIG. An example of a timing chart for explaining the operation of the register circuit is shown in FIG. The timing chart shows the wirings 412_i to 412_m among the wirings 412_1 to 412_m. 20 shows an example in which only the potential of the wiring 413 (V413 and 414), the potential of the wiring 414 (denoted as V414), and the potential of the wiring 415 (denoted as V415). ), the potential of the wiring 416 (denoted as V416), the potential of the wiring 417 (denoted as V417), The potentials of the wirings 411_1 to 411_m (denoted as V411_1 to V411_m) and The potentials of lines 412_1 to 412_m (denoted as V412_1 to V412_m) are shown.

[0169] The wirings 411_1 to 411_m are connected by shifting a signal input to the wiring 417. Thus, the wiring 411_1 goes to H level in order.

[0170] For example, when the potential of the wiring 411_i-1 is at an H level, the circuit 401_i in FIG. The operation in the period A1 or A2 described above is performed. Therefore, the potential of the wiring 411_i is L It becomes a level.

[0171] After that, the signal input to the wiring 413 and the signal input to the wiring 415 are inverted. Then, the circuit 401_i performs the operation in the period B1 or B2 described in FIG. As a result, the potential of the wiring 411_i becomes H level.

[0172] After that, the signal input to the wiring 413 and the signal input to the wiring 415 are inverted, The potential of 411_i+1 becomes H level. Then, the circuit 401_i performs the periodic operation described with reference to FIG. Therefore, the potential of the wiring 411_i becomes the L level. do.

[0173] After that, every time the signal input to the wiring 413 and the signal input to the wiring 415 are inverted, In addition, the circuit 401_i performs the operation in the period D1 or D2 described in FIG. The operation in the period E1 and the operation in the period E2 described above are performed alternately. The rank will remain at L level.

[0174] Here, among the wirings 412_1 to 412_m, the wirings 412_i to 412_i+3 In order to partially select only the first and second pixels, the wirings 411_1 to 411_i-1 are sequentially set to H level. During the period, the signal input to the wiring 414 and the signal input to the wiring 416 are inactive. The potential is set to a constant potential (potential V2), for example.

[0175] After that, during a period in which the wirings 411_i to 411_i+3 are sequentially set to the H level, The signal input to the wiring 414 and the signal input to the wiring 416 are set to an active state.

[0176] After that, during a period in which the wirings 411_i+3 to 411_m are sequentially set to the H level, The signal input to 414 and the signal input to wiring 416 are in an inactive state (e.g., The potential is set to a constant potential (potential V2).

[0177] As described above, the active state of the signal input to the wiring 414 and the signal input to the wiring 416 is By controlling the active and inactive states, the wirings 412_1 to 412_i-1 , and the wirings 412_i+4 to 412_m can be left at the L level, and the wirings 412_i Up to 412_i+3 can be set to H level in order.

[0178] As described above, the signal input to the wiring 414 and the signal input to the wiring 416 are activated. By selecting whether to set the wiring 412_1 to the active or inactive state, 412_m can be partially selected. In other words, partial driving can be realized. Cut.

[0179] In the conventional technology, multiple start signals are required to achieve partial driving. In other words, the number of signals was increasing. Therefore, the gate driver circuit was placed on the same substrate as the pixel section. In this case, the number of connection points between the substrate on which the pixel portion is formed and the external circuit increases. This resulted in lower yields, lower reliability, and increased costs. In contrast, the semiconductor device of the present embodiment is capable of suppressing an increase in the number of signals. Alternatively, it is possible to suppress an increase in the number of connections between the substrate on which the pixel unit is formed and an external circuit. It is possible to improve the yield. It is possible to improve the reliability. It is possible to reduce costs.

[0180] In addition, with conventional technology, it was necessary to control multiple start signals at different timings. This resulted in an increase in the circuit scale of the timing controller. The power consumption of the controller has increased. Or the cost of the timing controller has increased. In contrast, a semiconductor device or a display device using the above-mentioned shift register circuit The above can suppress an increase in the circuit scale of the timing controller. It is possible to suppress an increase in the power consumption of the timing controller. This will help curb the increase in trolling costs.

[0181] In addition, in the conventional technology, the gate driver circuits are divided into multiple groups, and each group is By controlling the input start signal, partial drive was achieved. The pixels or rows that can be selectively selected are limited, and it is not possible to select only arbitrary pixels or rows. As a result, in some images, pixels or rows that do not need to be selected may be selected. As a result, it was not possible to reduce power consumption sufficiently. In the display device using the above-mentioned shift register circuit, a signal (e.g., a clock signal or an inverted The clock signal) can be selected depending on whether it is in the active or inactive state. Therefore, it is possible to select only a given pixel or row. Or, you can select only the pixels or rows that you need to select. Power consumption can be significantly reduced.

[0182] In addition, in the conventional technology, when switching groups due to delays in multiple start signals, There was a misalignment in the output signal, which resulted in an incorrect video signal being input to the pixels. In response to this problem, the display quality is degraded by using the above-mentioned shift register circuit. The device does not cause any output signal deviation or prevent incorrect video signals from entering the pixels. Alternatively, it is possible to prevent the display quality from being deteriorated.

[0183] (Configuration of a display device according to an embodiment) FIG. 21A shows an example of a display device in which the above-described shift register circuit is used. The display device shown in (A) includes a circuit 5501 (for example, a timing controller) and a circuit 55 The circuit 5502 includes a circuit 5504 (for example, a driver circuit) and a pixel portion 5503. (e.g., a source driver circuit) and a circuit 5505 (e.g., a gate driver circuit). The pixel portion 5503 is connected to a circuit 5504 through a plurality of wirings 5507 (for example, signal lines, source lines, etc.). signal line, video signal line) are arranged extending from the circuit 5505. For example, signal lines, gate signal lines, or scanning lines are arranged in an extended manner. In each of the intersection regions with the multiple wirings 5508, pixels 5506 are arranged in a matrix. The pixel 5506 is connected to a wiring 5507 and a wiring 5508. 01 is connected to circuit 5504 and circuit 5505.

[0184] In the pixel portion 5503, various wirings may be provided according to the structure of the pixel 5506. For example, the pixel 5506 may be a liquid crystal element or a display element having a memory function. In this case, a capacitance line may be provided in the pixel portion 5503. When the pixel portion 5503 has a light emitting element such as an EL element, a power supply line such as an anode line is connected to the pixel portion 5503. As another example, the pixel 5506 may have a plurality of switches or transistors. In this case, the pixel portion 5503 is provided with a wiring having the same function as the wiring 5508 (for example, a signal line, In this case, the same as the circuit 5505 It is preferable to newly provide a circuit (for example, a gate driver circuit) having the above function.

[0185] All or part of the circuit 5501, the circuit 5504, and the circuit 5505 are the same as the pixel portion 5503. Alternatively, the circuits 5501, 5504, and 5505 may be formed on the same substrate. In this case, it is preferable that the pixel portion 5503 is formed on a different substrate. This will be described with reference to Figures 21(B), 21(C), 21(D) and 21(E).

[0186] FIG. 21B shows a circuit 5504 on the same substrate as the pixel portion 5503 (denoted as a substrate 5509). and a circuit 5505 are formed on a substrate (e.g., a silicon substrate, S This shows an example in which a circuit 5501 is formed on a substrate (such as an OI substrate). This reduces the number of connections between the substrate and external circuits, improving reliability. This can improve yields and reduce manufacturing costs.

[0187] The substrate on which the pixel portion 5503 is formed and the external circuit are connected via an FPC pad or the like. And the external circuit is TAB (Tape Automated Bondi ng) method to FPC (Flexible Printed Circuit) Alternatively, the external circuitry can be implemented using the COG (Chip on Glass) method. Therefore, it is recommended to mount it on a substrate 5509 .

[0188] In FIG. 21C, a circuit 5505 is formed on the same substrate as the pixel portion 5503. Circuit 5501 and circuit 5503 are mounted on a substrate (e.g., silicon substrate, SOI substrate, etc.) different from that of circuit 5501 and circuit 5503. 5504 is formed on the same substrate as the pixel portion 5503. The driving frequency of the circuit 5505 can be set higher than the driving frequency of the circuit 5504. Therefore, amorphous silicon, microcrystalline silicon, oxide semiconductor, or The pixel portion 5503 and the circuit 5505 are formed by using transistors using organic semiconductors. This allows for a reduction in the number of manufacturing steps, a reduction in manufacturing costs, an improvement in reliability, and an improvement in yield. Furthermore, the pixel portion 5503 can be enlarged, and the display device The display area can be enlarged.

[0189] FIG. 21D shows that a part of the circuit 5504 (circuit 5504a) is provided on the same substrate as the pixel portion 5503. 5503) and a circuit 5505 are formed on a substrate different from the pixel portion 5503. An example is shown in which another part of the circuit 5504 (designated as circuit 5504b) is formed. The driving frequency of the circuit 5504a is lower than the driving frequency of the circuit 5504b. As in the display device shown in (B), the display device may be made of amorphous silicon, microcrystalline silicon, an oxide semiconductor, or a The pixel portion 5503, the circuit 5504a, and the circuit 550 5. The circuit 5504a can be configured by using a switch, an inverter circuit, a selector, CIRCUIT, DEMULTIPLEXER CIRCUIT, SHIFT REGISTER CIRCUIT, DECODER CIRCUIT AND BUFFER CIRCUIT The circuit 5504b may be configured with one or more of the following: a shift register circuit; Decoder circuits, latch circuits, D / A conversion circuits, level shifter circuits, buffer circuits, etc. It is preferable that the method is composed of one or more of the following:

[0190] FIG. 21E shows a circuit 5501 and a circuit 5504 on a substrate different from the pixel portion 5503. An example in which a path 5505 is formed is shown.

[0191] As a gate driver circuit for such a display device, the shift register circuit shown in FIG. By using the path, it is possible to partially scan the display. This reduces the amount of image that needs to be rewritten, which reduces power consumption. Cut.

[0192] (Circuit configuration of pixel according to one embodiment) FIG. 22(A) shows a circuit configuration of a pixel having a liquid crystal element. The pixel shown in FIG. The transistor 801, the capacitor 802, and the liquid crystal element 803 are included. A first terminal of the transistor 801 is connected to a wiring 811. One electrode of the element 802 and one electrode of the liquid crystal element 803 (for example, a pixel electrode) are connected. The gate of the transistor 801 is connected to a wiring 812. The electrode is connected to a wiring 813. The other electrode of the liquid crystal element 803 is a common electrode 814 ( However, the pixel in this embodiment is connected to the The present invention is not limited to the configuration shown in FIG. 22(A), and various other configurations are possible.

[0193] The wiring 811 is connected to a signal (e.g., For example, a video signal is input to the wiring 811. A signal (for example, a gate) for controlling the conductive state of the transistor 801 is connected to the wiring 812. Therefore, the wiring 812 functions as a gate signal line. A predetermined voltage is supplied to the wiring 813. Therefore, the wiring 813 is a power supply line or a capacitor. A predetermined voltage (for example, a common voltage) is supplied to the common electrode 814. However, the wiring 811, the wiring 812, the wiring 813 and the common electrode 814 are the same as those described above. It is possible to input various other signals or voltages. For example, the voltage supplied to the wiring 813 can be changed. As another example, the voltage applied to the common electrode 814 can be controlled. This allows the voltage to be changed, which makes it possible to realize common inversion driving. Cut.

[0194] The transistor 801 controls the electrical continuity between the wiring 811 and one electrode of the liquid crystal element 803. The transistor 801 has a function as a switch that controls the potential of the wiring 811. The timing at which the voltage Vcc is input to the pixel can be controlled. The capacitor 813 functions as a storage capacitor that holds a potential difference between one electrode of the capacitor 813 and the wiring 813. The element 802 keeps the liquid crystal element 80 in the off state even during the period when the transistor 801 is in the off state. The potential of one electrode of the liquid crystal element 803 can be kept constant. However, the transistor 801 and the capacitor 802 are The functions are not limited to those described above, and various other functions may be included.

[0195] The operation of the pixel shown in Fig. 22(A) will be briefly described. Gray scale control of the liquid crystal element 803 This is achieved by applying a voltage to the liquid crystal element 803 to generate an electric field in the liquid crystal element 803. The voltage applied to the liquid crystal element 803 is controlled by changing the potential of one electrode of the liquid crystal element 803. Specifically, the potential of one electrode of the liquid crystal element 803 is controlled by This is performed by controlling a signal input to the wiring 811. The signal to be sent to the liquid crystal element 803 is turned on by turning on the transistor 801. Even when the transistor 801 is turned off, the capacitance element 802 Thus, a voltage continues to be applied to the liquid crystal element 803 .

[0196] Next, a pixel having a light-emitting element such as an electroluminescence element (EL element) will be described. FIG. 22B shows the circuit configuration of a pixel having a light-emitting element. The pixel includes a transistor 901, a transistor 902, a capacitor element 903, and a light-emitting element 904. A first terminal of the transistor 901 is connected to a wiring 911. The second terminal of the transistor 901 is connected to the gate of the transistor 902. The gate of the transistor 902 is connected to a wiring 912. The first terminal of the transistor 902 is connected to a wiring 913. The second terminal of the transistor 902 is connected to one electrode of the light-emitting element 904. One electrode of the capacitor 903 is connected to the gate of the transistor 902. The other electrode of the capacitor 903 is connected to a wiring 913. The other electrode of the light-emitting element 904 is 22(B) and is connected to a common electrode 914. The present invention is not limited to this configuration, and various other configurations are possible.

[0197] The wiring 911 is connected to a light emitting element 904 for controlling the gradation of the light emitting element 904 or a current supplied to the light emitting element 904. A signal (for example, a video signal) for displaying the image is input to the wiring 911. The wiring 912 has a function as a line. For this reason, the wiring 912 is used as a gate signal line. A predetermined voltage (for example, an anode voltage) is supplied to the wiring 913. Therefore, the wiring 913 functions as a power supply line or an anode line. A predetermined voltage (for example, a cathode voltage) is supplied to the wiring 911 and the wiring 94. 12, the wiring 913 and the common electrode 914 are not limited to those described above, and various other signals may be used. It is possible to input a signal, voltage, etc.

[0198] The transistor 901 controls the conduction state between the wiring 911 and the gate of the transistor 902. The transistor 901 has a function as a switch that controls the potential of the wiring 911. The transistor 902 is a light-emitting element. The capacitor 904 functions as a driving transistor for controlling the current supplied to the capacitor 904. 3 is a storage capacitor that holds a potential difference between the gate of the transistor 902 and the wiring 913. The capacitor 903 functions as a In this case, the potential of the gate of the transistor 902 can be kept constant. This allows the potential difference between the gate and source of the transistor 902 to be maintained at a constant value. Therefore, a current can be continuously supplied to the light emitting element 904. However, the transistor 9 The functions of the transistor 902 and the capacitor 903 are not limited to those described above. It is possible for the casing to have a variety of functions.

[0199] The operation of the pixel shown in Fig. 22B will be briefly described. Grayscale control of the light-emitting element 904 is supplied to the light emitting element 904 by controlling the potential of the gate of the transistor 902. The potential of the gate of the transistor 902 is controlled by controlling the current flowing through the This is done by controlling the signal input to the wiring 911. The signal is applied to the gate of the transistor 902 by the transistor 901 being turned on. Even when the transistor 901 is turned off, the power is supplied to the Therefore, the potential of the gate of the transistor 902 is maintained at a constant value. Even if 901 is turned off, current continues to be supplied to the light emitting element 904 .

[0200] Note that at least one of a transistor and a capacitor is provided in the pixel shown in FIG. By correcting the threshold voltage of the transistor 902 or correcting the mobility of the transistor 902, It is possible.

[0201] The pixel configurations shown in FIG. 22(A) and FIG. 22(B) can be used in the display device shown in FIG. These pixels are connected to the circuitry described in FIG. 1(A) or FIG. 6. It can be used as a load.

[0202] (Pixel configuration according to one embodiment) FIG. 23A shows an example of a circuit diagram of a pixel that can be used in the display device. The display device includes a transistor 5451, a capacitor 5452, and a display element 5453. A first terminal of the transistor 5451 is connected to a wiring 5461. The terminals are connected to one electrode of the capacitor element 5452 and one electrode of the display element 5453 (pixel electrode The gate of the transistor 5451 is connected to a wiring 5462. The other electrode of the capacitor 5452 is connected to a wiring 5463. The other electrode is the electrode 5454 (also called the common electrode, counter electrode, or cathode electrode). One electrode of the display element 5453 is shown as an electrode 5455.

[0203] The display element 5453 preferably has a memory property. The driving method of the element 5453 is a microcapsule type electrophoresis method, a microcup type electrophoresis method, etc. Gas electrophoresis, horizontal electrophoresis, vertical electrophoresis, twist ball, Powder movement method, Electronic Liquid Powder (registered trademark) method, Cholesteric liquid crystal element, Chiral nematic Liquid crystal, antiferroelectric liquid crystal, polymer dispersed liquid crystal, charged toner, electrowetting There are various types of methods, such as electrochromism, electrodeposition, etc.

[0204] FIG. 23(B) shows a cross-sectional view of a pixel using a microcapsule type electrophoretic method. A plurality of microcapsules 5480 are disposed between the electrode 5454 and the electrode 5455. A number of microcapsules 5480 are fixed by a resin 5481. The resin 5481 has a function as an indium ion. The resin 5481 may have a light-transmitting property. The space formed by the electrode 5454, the electrode 5455, and the microcapsule 5480 is filled with air. Alternatively, the electrode 545 may be filled with a gas such as an inert gas. A layer containing an adhesive or a bonding agent is formed on one or both of the microphone 4 and the electrode 5455. The microcapsule 5480 may be fixed in place. The two types of particles are different colors. For example, it is preferable to use a particle composed of a black pigment and a particle composed of a white pigment. The particles to be dispersed are contained in microcapsules 5480.

[0205] FIG. 24A shows a display device using a twist ball method. The cross-sectional view of a pixel is shown. The twist ball method changes the reflectance by rotating the display element. The difference from FIG. 23B is that the electrodes 5454 and 5455 Instead of the microcapsule 5480, a twist ball 5486 is placed between the The twist ball 5486 is a particle 5487 and a ball is formed around the particle 5487. The particles 5487 each have a hemispherical surface. The particle 5487 is a spherical particle painted in a certain color and a different color. The hemispheres are painted white and black, respectively. A charge density difference is provided. Therefore, a potential difference is applied between the electrodes 5454 and 5455. By generating the electric field, the particle 5487 can be rotated according to the electric field direction. The cavity 5488 is filled with a liquid. The liquid is the same as the liquid 5483. However, the twist ball 5486 is not limited to the structure shown in FIG. For example, the structure of the twist ball 5486 can be cylindrical or elliptical, etc. It is.

[0206] FIG. 24B shows a microcup type electrophoretic display device as a display element 5453. The cross-sectional view of a pixel when using a microcup array is shown. A microcup 5491 having a number of recesses is filled with a charged dye dispersed in a dielectric solvent 5492. The sealing layer 5494 is then filled with particles 5493. An adhesive layer 5495 may be formed between the dielectric solvent 5492 and the electrode 5455. For this purpose, it is possible to use a non-colored solvent, or a colored solvent such as red or blue. Here, the case where there is one type of charged pigment particles is illustrated, but the charged pigment particles may be used in combination. Two or more types may be used. Since the microcups have a wall structure that separates the cells, The contents of the microcups are sealed, so they can withstand high temperatures and pressure. , the influence of environmental changes can be reduced.

[0207] FIG. 24C shows a case where an electronic liquid powder (registered trademark) method is used as a display element 5453. The cross-sectional view of a pixel is shown in Fig. 1. The powder used here exhibits fluidity and has both the properties of a fluid and a particle. In this method, the cells are separated by partitions 5456, and powder 5457 is placed in the cells. and liquid powder 5458 are placed. White particles and However, the types of liquid powder 5457 and liquid powder 5458 are as follows: For example, the liquid powder 5457 and the liquid powder 5458 may be any other than white and black. It is possible to use two colors of colored particles. Another example is liquid powder 5457 and liquid powder 54 It is possible to omit either 58 or 59.

[0208] As shown in FIG. 23A, a signal is input to the wiring 5461. A signal (for example, a video signal) for controlling the gray scale of the display element 5453 is input to the input terminal 1. In this way, the wiring 5461 is a signal line or a source signal line (a video signal line or a source line A signal is input to the wiring 5462. A signal (e.g., a gate signal) for controlling the conductive state of the transistor 5451 is input to the input terminal 462. In this way, the wiring 5462 is a signal line or a gate line. The wiring 5463 functions as a gate signal line (also called a scanning signal line or a gate line). A predetermined voltage is supplied to the wiring 5463. The wiring 5463 is connected to the capacitor 5452. Therefore, the wiring 5463 functions as a power supply line or a capacitance line. A predetermined voltage is supplied to the electrodes 5454 between a plurality of pixels or all pixels. Therefore, the electrode 5454 is a common electrode (common electrode, counter electrode or cathode) It functions as a metal electrode.

[0209] Note that signals input to the wiring 5461, the wiring 5462, the wiring 5463, and the electrode 5454 The voltages or signals are not limited to those described above, and various other signals or voltages may be input. For example, a signal can be input to the wiring 5463. Since the potential of the electrode 5455 can be controlled by the Therefore, the wiring 5463 can function as a signal line. As another example, the voltage supplied to the electrode 5454 may be changed. This allows the voltage applied to the display element 5453 to be adjusted. The amplitude voltage of a signal input to the wiring 5461 can be reduced.

[0210] The transistor 5451 has a function of controlling the conduction state between the wiring 5461 and the electrode 5455. Alternatively, the transistor 5451 may transfer the potential of the wiring 5461 to the electrode 5455. The transistor 5451 has a function of controlling the timing of supplying the signal to the pixel 5. In this way, the transistor 545 has a function of controlling the timing of selecting the transistor 545. The transistor 54 functions as a switch or a selection transistor. The transistor 5451 is an N-channel type. When an L signal is input to wiring 5461, the switch is turned on, and when an L signal is input to wiring 5462, the switch is turned off. However, the polarity of the transistor 5451 is not limited to an N-channel type. 451 can be a P-channel type. In this case, the transistor 5451 When an L signal is input to the wiring 5462, it is turned on, and when an H signal is input to the wiring 5462, it is turned on. The capacitor 5452 is turned off when the potential between the electrode 5455 and the wiring 5463 is changed. Alternatively, the capacitor 5452 has a function of holding the potential of the electrode 5455 at a predetermined value. This function maintains the value even when the transistor 5451 is turned off. A voltage can be continuously applied to the display element 5453. In this manner, the capacitor 5452 , and functions as a storage capacitor. The functions of the are not limited to those described above, and may have various other functions. do.

[0211] Next, an outline of the operation of the pixel shown in FIG. The adjustment is controlled by applying a voltage to the display element 5453 to generate an electric field in the display element 5453. The voltage applied to the display element 5453 is controlled by the potential of the electrode 5454 and This is done by controlling the potential of the electrode 5454 and the electrode 5455. The control of the electrode 5455 is performed by controlling the voltage supplied to the electrode 5454. The potential is controlled by controlling a signal input to the wiring 5461. The signal input to the line 5461 is turned on by the transistor 5451. Supplied to pole 5455.

[0212] The strength of the electric field applied to the display element 5453, the direction of the electric field applied to the display element 5453, By controlling one or more of the following, the display element 5453 can be displayed. The gradation of the display element 5453 can be controlled. By not generating a potential difference between the display element 5453 and the pixel electrode 5454, the gray level of the display element 5453 can be maintained. do.

[0213] Next, an example of the operation of this pixel will be described. The example shows a period T having a selected period and a non-selected period. The period T starts from the start of the selected period. This refers to the period between the current time and the start time of the next selection period.

[0214] During the selection period, an H signal is input to the wiring 5462, so that the potential of the wiring 5462 (potential V 5462) becomes H level. Therefore, the transistor 5451 is turned on. Therefore, the wiring 5461 and the electrode 5455 are in a conductive state. The input signal is supplied to the electrode 5455 via the transistor 5451. The potential of the electrode 5455 (shown as potential V5455) is equal to the signal input to the wiring 5461. At this time, the capacitance of the capacitor 5452 is In the non-selection period, an L signal is input to the wiring 5462, so that the potential difference is maintained. The potential of 62 becomes L level. Therefore, the transistor 5451 is turned off. Then, the wiring 5461 and the electrode 5455 are not electrically connected to each other. Then, the electrode 5455 is in a floating state. At this time, the capacitor 5452 is connected to the electrode 5455 and the wiring 546 during the selection period. 3. Therefore, the potential of the electrode 5455 is The value remains equal to the value of the signal input to the wiring 5461. Even if the transistor 5451 is turned off, a voltage is continuously applied to the display element 5453. As described above, the signal input to the wiring 5461 during the selection period can be controlled. By this, it is possible to control the voltage applied to the display element 5453. The gray scale of the display element 5453 is controlled by controlling a signal input to the wiring 5461 during a selection period. This can be done by

[0215] The potential of the electrode 5455 in the non-selection period is the off-current of the transistor 5451, Feedthrough of resistor 5451 and charge injection of transistor 5451 Due to one or more of the above influences, the signal input to the wiring 5461 during the selection period may differ from the signal This can happen.

[0216] As shown in FIG. 25B, during a part of the selection period, the potential of the electrode 5455 is set to the potential of the electrode 5 454. This allows the pixel 5450 to be selected every time Even if the same signal continues to be input to the pixel 5450, the electrode 5455 By changing the potential, the electric field strength of the display element 5453 can be changed. Therefore, it is possible to reduce afterimages or to increase the response speed. In addition, it is possible to reduce the variation in response speed between pixels, thereby preventing unevenness or afterimages. In order to realize such a driving method, the selection period is divided into a period T1 and a period T2. In the period T1, a signal input to the wiring 5461 is divided into In the period T2, the input to the wiring 5461 is The signal to be output may have various values ​​to control the gray scale of the display element 5453. If the time T1 is too long, the signal for controlling the grayscale of the display element 5453 is Therefore, the time to write to 50 is shorter than the time period T1. In particular, it is preferable that the period T1 is 1% or more and 20% or less of the selection period. More preferably, it is 3% or more and 15% or less, and further preferably, it is 5% or more and 10% or less. It is.

[0217] Next, the gray scale of the display element 5453 is controlled by the time for which a voltage is applied to the display element 5453. An example of the operation of the pixel of this embodiment will be described. The timing chart has a period Ta and a period Tb. The period Ta is N (N is a natural number). Each of the N periods T has the same structure as the periods T shown in FIG. The period Ta is a period for changing the gray scale of the display element 5453 (for example, The period Tb is the display period during the period Ta. This is a period during which the gray level of the element 5453 is maintained (a retention period).

[0218] A voltage V0 is supplied to the electrode 5454. Therefore, the electrode 5454 is at a potential V0. A signal having at least three values ​​is input to the wiring 5461. The potentials of the values ​​are potential VH (VH>V0), potential V0, and potential VL (VL <V0)と Therefore, the electrode 5455 is selectively applied with a potential VH, a potential V0, and a potential VL. can be.

[0219] In each of the N periods T included in the period Ta, the potential applied to the electrode 5455 is controlled. By this, it is possible to control the voltage applied to the display element 5453. When a potential VH is applied to 5455, the potential difference between the electrodes 5454 and 5455 is , VH-V0. This allows a positive voltage to be applied to the display element 5453. When a potential V0 is applied to the electrode 5455, the electrodes 5454 and 5455 The potential difference becomes zero. This allows a voltage of zero to be applied to the display element 5453. When a potential VL is applied to the electrode 5455, the electrodes 5454 and 5455 The potential difference between the two electrodes is VL-V0. This causes a negative voltage to be applied to the display element 5453. As described above, in the period Ta, a positive voltage (VH-V 0), negative voltage (VL-V0), and zero can be applied in various orders. This allows fine control of the gray scale of the display element 5453. Alternatively, afterimages can be reduced. Alternatively, the response speed can be increased.

[0220] When a positive voltage is applied to the display element 5453, the gradation of the display element 5453 becomes black ( When a negative voltage is applied to the display element 5453, Therefore, the gray level of the display element 5453 approaches white (also called the second gray level). When zero voltage is applied to 5453, the grayscale of the display element 5453 is maintained.

[0221] In the period Tb, the signal input to the wiring 5461 is not written to the pixel 5450. Therefore, in the period Tb, the voltage applied to the electrode 5455 in the N-th period T of the period Ta is In particular, in the period Tb, an electric field is applied to the display element 5453. It is preferable to maintain the gray level of the display element 5453 by not causing the pixel shift. In the N-th period T of the period Ta, a potential V0 is preferably applied to the electrode 5455. This is preferable. Since the potential V0 is applied to the electrode 5455 even during the period Tb, Therefore, zero voltage is applied to the display element 5453. It can be held.

[0222] The closer the gradation level that the display element 5453 next displays to the first gradation level, the greater the amount of current that is applied during the period Ta. It is preferable to lengthen the time during which the potential VH is applied to the electrode 5455. In this case, it is preferable to increase the number of times that the potential VH is applied to the electrode 5455. , the time when potential VH is applied to electrode 5455 to the time when potential VL is applied to electrode 5455 Alternatively, during the N periods T, the potential VH is at the electrode 545 The number of times that potential VL is applied to electrode 5455 minus the number of times that potential VL is applied to electrode 5455 is the most It is recommended to do so.

[0223] The closer the gradation level that the display element 5453 next displays is to the second gradation level, the greater the amount of current that is applied during the period Ta. It is advisable to lengthen the time during which the potential VL is applied to the electrode 5455. In this case, it is preferable to increase the number of times that the potential VL is applied to the electrode 5455. , from the time when potential VL is applied to electrode 5455 to the time when potential VH is applied to electrode 5455 Alternatively, during the N periods T, the potential VL is at the electrode 545 The number of times that potential VH is applied to electrode 5455 minus the number of times that potential VH is applied to electrode 5455 is the most It is recommended to do so.

[0224] During the period Ta, the potentials (potential VH, potential V0, potential VL) applied to the electrode 5455 The combination of not only depends on the gray scale that the display element 5453 will next display, but also depends on the display element It is possible to rely on the gray level already displayed by the display element 5453. Even if the gradation displayed by the display element 5453 is the same, the gradation already displayed by the display element 5453 may be different. In this case, the combination of potentials applied to the electrodes 5455 may be different.

[0225] For example, during the period Ta for displaying the gradation already displayed by the display element 5453, The longer the time that the potential VH is applied to the electrode 5455, the greater the potential VH applied to the electrode 5455. The longer the time that the potential VL is applied to the electrode 5455 from the time that the potential VL is applied to the electrode 5455, the The more times the potential VH is applied to the electrode 5455 among the N periods T, or the more times the potential VH is applied to the electrode 5455 among the N periods T, the greater the During the period T, the number of times that the potential VH is applied to the electrode 5455 is determined by the number of times that the potential VL is applied to the electrode 5455. The greater the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 during the period Ta, the greater the Alternatively, the potential VL may be applied to the electrode 5455 during the N periods T. Alternatively, during the period Ta, the potential VL is applied to the electrode 5455. The time during which the potential VH is applied to the electrode 5455 is increased by subtracting the time during which the potential VH is applied to the electrode 5455 from the time during which the potential VH is applied to the electrode 5455. Alternatively, the number of times that the potential VL is applied to the electrode 5455 during the N periods T may be determined as the potential V It is advisable to increase the number of times H is applied to the electrode 5455. can be reduced.

[0226] As another example, the gradation already displayed by the display element 5453 may be displayed during a period Ta In this case, the longer the time that the potential VL is applied to the electrode 5455, the The longer the time that potential VH is applied to electrode 5455 minus the time that potential VH is applied to electrode 5455, the For example, the more times the potential VL is applied to the electrode 5455 among the N periods T, or The number of times that the potential VL is applied to the electrode 5455 during the period T is determined as the number of times that the potential VH is applied to the electrode 5455. The greater the value obtained by subtracting the number of times given to the electrode 5455 during the period Ta, the greater the potential VH applied to the electrode 5455. Alternatively, the potential VH may be applied to the electrode 545 during the N periods T. Alternatively, during the period Ta, the potential VH may be applied to the electrode 545 5 minus the time that potential VL is applied to electrode 5455. Alternatively, the number of times the potential VH is applied to the electrode 5455 during the N periods T may be determined as follows: It is preferable to increase the number of times the potential VL is applied to the electrode 5455. , the afterimage can be reduced.

[0227] Each of the N periods T is of equal length. However, the length of the N periods T is not limited to this. For example, at least two of the N periods T are different in length. In particular, it is advisable to weight the length of N periods T. For example, when N=4, In some cases, if the length of the first period T is time h, then the length of the second period T is time h x 2 Let the length of the third period T be time h × 4. Let the length of the fourth period T be It is recommended to set the time to h × 8. In this way, by weighting the length of the N periods T, This reduces the number of times the pixel 5450 is selected, and the voltage is applied to the display element 5453. This allows for precise control of the time the power is applied, thereby reducing power consumption. .

[0228] A potential VH or a potential VL can be selectively applied to the electrode 5454. It is also preferable to selectively apply a potential VH or a potential VL to the electrode 5455. For example, When a potential VH is applied to the electrode 5454, when a potential VH is applied to the electrode 5455, A voltage of zero is applied to the display element 5453. When a potential VL is applied to the electrode 5455, A negative voltage is applied to the display element 5453. On the other hand, a potential VL is applied to the electrode 5454. In this case, when a potential VH is applied to the electrode 5455, a positive voltage is applied to the display element 5453. When a potential VL is applied to the electrode 5455, a voltage of zero is applied to the display element 5453. In this way, the signal input to the wiring 5461 is converted into a binary (digital) signal. Therefore, the circuit for outputting a signal to the wiring 5461 can be simplified. .

[0229] During the period Tb or a part of the period Tb, a signal is input to the wiring 5461 and the wiring 5462. In other words, the wiring 5461 and the wiring 5462 can be in a floating state. Note that during the period Tb or part of the period Tb, the signal In other words, the wiring 5463 can be in a floating state. In addition, during the period Tb or a part of the period Tb, no voltage is supplied to the electrode 5454. That is, the electrode 5454 can be in a floating state.

[0230] The pixel illustrated in FIG. 23A can be used in the display device illustrated in FIG. The pixel shown in FIG. 23(A) is a load connected to the circuits described in FIG. 1(A) and FIG. 6. The pixel shown in FIG. 23A is a display element having a memory function. Therefore, the pixel shown in FIG. 23A and the shift register shown in FIG. It is preferable to combine the pixel shown in FIG. By driving the shift register circuit described above, the image is displayed only when the gray scale is changed. On the other hand, if the gray scale is not changed, the video signal can be input to the pixel. Even if no signal is input to the pixel, the display element has a memory function, so the gray scale can be maintained for a long time. This can be done.

[0231] (Pixel configuration according to one embodiment) FIG. 26A shows an example of a top-gate transistor as a configuration of the pixel. FIG. 26(A) shows an example of a display element formed on a display device. The transistor shown in FIG. 26A includes a substrate 5260 and an insulating layer 52. 61 (for example, an undercoat film), a semiconductor layer 5262, and an insulating layer 5263 (for example, a gate insulating film) a conductive layer 5264 (for example, a gate electrode or a wiring) and an insulating layer 526 having an opening. 5 (for example, an interlayer film or a planarization film, etc.), and a conductive layer 5266 (for example, a source layer of a transistor An electrode of a transistor, an electrode of a capacitor, or a wiring, etc. A layer 5261 is formed on a substrate 5260. A semiconductor layer 5262 is formed on the insulating layer 5261. An insulating layer 5263 is formed to cover the semiconductor layer 5262. The insulating layer 5264 is formed on the semiconductor layer 5262 and on the insulating layer 5263. 5 is formed on the insulating layer 5263 and on the conductive layer 5264. The conductive layer 5266 is It is formed on the border layer 5265 and in the opening in the insulating layer 5265 .

[0232] The semiconductor layer 5262 includes a region 5262a, a region 5262b, and a region 5262c. The region 5262a is a region to which impurities are added, and serves as a source region or a drain region. The region 5262b is doped with impurities at a lower concentration than the region 5262a. The region is used as a lightly doped drain (LDD) region. The region 5262c is a region to which no impurities are added, and serves as a channel region. Note that impurities can be added to the region 5262c. This makes it possible to improve the characteristics of the transistor and control the threshold voltage. The concentration of the impurity added to the region 5262c is equal to the concentration of the impurity added to the region 5262a and the region 5262b. This can reduce the off-state current. It is possible to omit 5262b.

[0233] FIG. 26B shows an example of a bottom-gate transistor and a display element formed thereon. The structure of the transistor shown in FIG. 26B is described below. The transistor shown in FIG. 26(B) includes a substrate 5280 and a conductive layer 5281 (e.g., a gate electrode). or wiring, an insulating layer 5282 (for example, a gate insulating film), a semiconductor layer 5283, A conductor layer 5284 and a conductive layer 5285 (e.g., a source electrode of a transistor, The conductive layer 5281 is a layer including a drain electrode, an electrode of a capacitor, or a wiring. 280. An insulating layer 5282 is formed over the conductive layer 5281. The semiconductor layer 5283 is formed on the conductive layer 5281 and on the insulating layer 5282. Layer 5284 is formed on semiconductor layer 5283. Conductive layer 5285 is formed on semiconductor layer 528. 4 and on insulating layer 5282.

[0234] The semiconductor layer 5284 is doped with impurities (such as phosphorus). The semiconductor layer 5284 has an N-type conductivity. The semiconductor layer 5283 is preferably intrinsic or close to intrinsic. Alternatively, the semiconductor layer 5283 preferably has a lower impurity concentration than the semiconductor layer 5284. I wish.

[0235] When an oxide semiconductor or a compound semiconductor is used as the semiconductor layer 5283, the semiconductor layer It is advisable to omit 5284 (see Figure 26(C)).

[0236] Here, on the transistors shown in FIG. 26(A), FIG. 26(B), and FIG. 26(C), Various layers can be provided, an example of which is described below.

[0237] For example, an opening is formed on the transistor shown in FIG. 26(A), FIG. 26(B), and FIG. 26(C). An insulating layer 5267 (for example, an interlayer film or a partition wall) having an opening and a conductive layer 5268 (for example a pixel electrode, a reflective electrode, or a wiring, and an insulating layer 5269 having an opening (for example, a partition wall). A light emitting layer 5270 and a conductive layer 5271 (for example, a common electrode or a counter electrode) are provided. The insulating layer 5267 can be formed on the conductive layer 5266 and the insulating layer 5267. 265. A conductive layer 5268 is formed on the insulating layer 5267 and between the insulating layer 5267. An insulating layer 5269 is formed in the opening on the insulating layer 5267 and on the conductive layer 5268. The light-emitting layer 5270 is formed on the insulating layer 5269 and in the opening of the insulating layer 5269. A conductive layer 5271 is formed on the insulating layer 5269 and on the light emitting layer 5270.

[0238] As another example, the upper part of the transistor shown in FIG. 26(A), FIG. 26(B) and FIG. 26(C) An insulating layer 5286 (for example, an interlayer film or a planarization film) having an opening and a conductive layer 528 7 (for example, a pixel electrode, a reflective electrode, or a wiring), a liquid crystal layer 5288, and a conductive layer 5289 ( For example, a common electrode or a counter electrode can be provided. 5282 and on the conductive layer 5285. The conductive layer 5287 is formed on the insulating layer 5286. A liquid crystal layer 5288 is formed on the insulating layer 5286 and in the opening of the insulating layer 5286. and a conductive layer 5287. A conductive layer 5289 is formed on a liquid crystal layer 5288. In addition, on the insulating layer 5286 and the conductive layer 5287, an alignment film and a protrusion It is possible to provide one or more. It is possible to provide one or more of a conductive layer, a filter, and a black matrix. An alignment film can be provided under 5289.

[0239] The semiconductor layer may be a non-single crystal semiconductor (e.g., amorphous silicon, polycrystalline (e.g., monocrystalline silicon, microcrystalline silicon, etc.), single crystal semiconductors (e.g., monocrystalline silicon, etc.), compounds Semiconductors (e.g., SiGe, GaAs, etc.), oxide semiconductors (e.g., ZnO, InG aZnO, IZO (indium zinc oxide), ITO (indium tin oxide), SnO, TiO, AlZnSnO(AZTO), etc.), organic semiconductors, or carbon nanotubes There are some.

[0240] The oxide semiconductor material will be described in detail. The In-Sn-Ga-Zn-O system, which is a material with a ternary metal oxide, and the In-Ga-Zn- O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series, A In-Ga-Zn-O, Sn-Al-Zn-O, and binary metal oxides such as In-Zn -O series, Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, There are In-Mg-O, In-O, Sn-O, and Zn-O systems. In particular, In-G The a-Zn-O oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and a sufficiently small off-current. It is possible to reduce the size of the semiconductor and its field effect mobility is high, making it suitable for use in transistors. It is suitable as a conductive material.

[0241] A representative example of an In-Ga-Zn-O oxide semiconductor material is InGaO3( ZnO) m(m>0 and m is not a natural number). In addition, M was used, and InMO3(ZnO) m (m>0 and m is not a natural number) There are oxide semiconductor materials that are used in the present invention. Here, M is gallium (Ga), aluminum (Al ), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. For example, M may be Ga, Ga, and Applying Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. The above composition is derived from the crystal structure and is not intended to be construed as a general guide. Note that this is merely an example. 19 (a toms / cm 3 ) or less.

[0242] The above-mentioned oxide semiconductor transistor has a field-effect mobility of 1 cm 2 / V sec or more, preferably 10 cm 2 / Vsec or more can be obtained, enabling high-definition display screens In addition, the pixel circuit can be operated even when the transistor is used. The signal processing circuit according to the embodiment can be configured using the above.

[0243] (Various devices according to an embodiment) 27(A) to 27(H) and 28(A) to 28(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, and a LE. D lamp 5004, operation key 5005 (including power switch or operation switch), connection Terminal 5006, sensor 5007 (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance , light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation (including functions to measure flow rate, humidity, gradient, vibration, odor, or infrared rays), 5008, etc.

[0244] FIG. 27(A) shows a mobile computer, which includes, in addition to the above, a switch 5009 , an infrared port 5010, etc. FIG. 27(B) shows a mobile phone equipped with a recording medium. A portable image reproducing device (e.g., a DVD reproducing device) and, in addition to the above, the following devices are also included: The display unit 5002, the recording medium reading unit 5011, etc. In addition to the above, the display includes a second display unit 5002 and a support unit 5012. , earphones 5013, etc. FIG. 27(D) shows a portable game machine. In addition to the above, the recording medium reading unit 5011 and the like can be included. FIG. 27(E) shows It is a projector, and in addition to the above, has a light source 5033, a projection lens 5034, etc. FIG. 27(F) shows a portable gaming machine, which, in addition to the above, has a second display. 27G shows a television. It is a receiver, and in addition to the above, may have a tuner, an image processor, and the like. FIG. 27(H) shows a portable television receiver, which, in addition to the above, is capable of transmitting and receiving signals. 28(A) is a display, In addition to the above, a support stand 5018, etc. can be provided. In addition to the above, there is an external connection port 5019, a shutter button 5015, an image receiving FIG. 28(C) shows a computer, which may include the above-mentioned In addition to the above, there is a pointing device 5020, an external connection port 5019, and a reader / writer. 5021, etc. FIG. 28(D) shows a mobile phone, In addition, antenna 5014, one-segment partial reception service channel for mobile phones and mobile terminals It may have a tuner, etc.

[0245] The electronic devices shown in FIGS. 27(A) to 27(H) and 28(A) to 28(D) are For example, various information (still images, videos, text images, etc.) can be stored. ) on the display, touch panel function, calendar, date or time display, etc. Functions for controlling processing by various software (programs), wireless communication functions , a function for connecting to various computer networks using wireless communication functions, wireless communication functions A function for transmitting or receiving various data using the Or, the data can be read and displayed on a display unit. In electronic devices having such a display unit, one display unit is used mainly to display image information, and another A function that mainly displays text information on one display unit, or a function that takes parallax into consideration on multiple displays By displaying the image, it is possible to provide a function of displaying a stereoscopic image. In electronic devices having an image receiving unit, the functions of taking still images, taking videos, The function of automatically or manually correcting the captured image, and the function of storing the captured image on a recording medium (external or camera) It can have functions such as storing the captured image on the camera (built into the camera), displaying the captured image on the display, etc. In addition, the electronic devices shown in Figs. 27(A) to 27(H) and Figs. 28(A) to 28(D) The functions that the device can have are not limited to these, and the device can have a variety of functions.

[0246] The electronic device described above has a display unit for displaying some information. By using the configuration according to one embodiment as a circuit for rewriting an image, This makes it possible to reduce power consumption.

[0247] FIG. 28(E) shows an example in which a display device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. The display device is a wall-mounted type that is integrated with the building and requires a certain amount of space to install. It can be installed without requiring a large space.

[0248] FIG. 28(F) shows another example in which a display device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 and is The display panel 5026 becomes viewable.

[0249] Although a wall and a unit bath are used as examples of structures, the present embodiment is not limited to these. Display devices can be installed in a variety of buildings.

[0250] Next, an example in which the display device is integrated with a moving object will be shown. The figure shows an example in which the device is installed in an automobile. The vehicle body 5029 is attached to the vehicle body 5029, and the vehicle body operation or information input from inside and outside the vehicle is input on demand. The information can be displayed on the screen of the terminal. The information can have a navigation function.

[0251] FIG. 28(H) is a diagram showing an example in which a display device is integrated into a passenger airplane. FIG. 28(H) shows a passenger plane with a display panel 5031 mounted on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge portion 5032. This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0252] In addition, although automobile bodies and airplane bodies are exemplified as moving bodies, the present invention is not limited to these. Motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (including monorails, railways, etc.) It can be installed on a variety of things, such as boats. [Explanation of symbols]

[0253] 10 pixels 11 Transistor 12 Liquid crystal element 13 Capacitive element 21 Wiring 22 Wiring 23 Wiring 31 Transistor 32 Wiring 33 Wiring 101 Transistor 102 Transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 119 Wiring 121 Capacitive element 122 Capacitive element 130 Protection circuit 131 Transistor 141 Wiring 201 Transistor 202 Transistor 203 Transistor 204 Transistor 205 Transistor 221 Transistor 222 Transistor 223 Transistor 224 Transistor 225 Transistor 226 Transistor 227 Transistor 228 Transistor 229 Transistor 300 circuits 301 Inverter circuit 302 Transistor 303 Transistor 304 Resistance element 305 Transistor 306 Transistor 307 Transistor 308 Transistor 311 Transistor 312 Transistor 313 Transistor 314 Transistor 315 Transistor 316 Transistor 401 Circuit 402 Circuit 411 Wiring 412 Wiring 413 Wiring 414 Wiring 415 Wiring 416 Wiring 417 Wiring 418 Wiring 419 Wiring 420 Wiring 801 Transistors 802 Capacitive element 803 Liquid crystal element 811 Wiring 812 Wiring 813 Wiring 814 Common electrode 901 Transistor 902 Transistor 903 Capacitive element 904 Light emitting element 911 Wiring 912 Wiring 913 Wiring 914 Common electrode 5000 cabinet 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Reader / Writer 5022 Case 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bath 5028 Display Panel 5029 Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection Lens 5260 PCB 5261 Insulation layer 5262 Semiconductor layer 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulating layer 5268 Conductive layer 5269 Insulation layer 5270 Light-emitting layer 5271 Conductive layer 5280 Board 5281 Conductive layer 5282 Insulation layer 5283 Semiconductor layer 5284 Semiconductor layer 5285 Conductive layer 5286 Insulation layer 5287 Conductive layer 5288 Liquid crystal layer 5289 Conductive layer 5450 pixels 5451 Transistor 5452 Capacitor 5453 Display element 5454 Electrode 5455 Electrode 5456 Bulkhead 5457 Powder fluid 5458 Powder fluid 5461 Wiring 5462 Wiring 5463 Wiring 5480 Microcapsules 5481 Resin 5483 liquid 5486 Twist Ball 5487 particles 5488 Cavity 5491 Microcup 5492 Dielectric Solvent 5493 Charged pigment particles 5494 Sealing layer 5495 Adhesive layer 5501 Circuit 5502 Circuit 5503 Pixel unit 5504 Circuit 5505 Circuit 5506 pixels 5507 Wiring 5508 Wiring 5509 Circuit Board 5262a area 5262b area 5262c area 5504a Circuit 5504b circuit

Claims

1. A gate driver is provided. the gate driver includes a first signal processing circuit and a second signal processing circuit; the first signal processing circuit includes first to eleventh transistors; one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a gate signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a first power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second power supply line; a gate of the fourth transistor is always electrically connected to a wiring to which an output signal of the second signal processing circuit is input; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a first signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the first power supply line; the gate of the sixth transistor is always electrically connected to the second signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the first power supply line; a gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the first signal line; a gate of the eighth transistor is always electrically connected to the first signal line; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the first power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the first power supply line; the gate of the tenth transistor is always electrically connected to a third signal line; one of the source and the drain of the eleventh transistor is always electrically connected to the gate signal line; When the potential of the fourth signal line is input to the gate of the eleventh transistor, the potential of the gate of the eleventh transistor is controlled in accordance with the potential of the fourth signal line; when the other of the source or the drain of the second transistor is in a conductive state with the gate signal line via at least a channel formation region of the second transistor, a potential having a value that causes the gate signal line to be at an L level is input to the gate signal line via at least a channel formation region of the second transistor, a gate signal line connected to the first transistor through a channel formation region of the first transistor, the gate signal line being electrically connected to the first transistor through a channel formation region of the first transistor;

2. A gate driver is provided. the gate driver includes a first signal processing circuit and a second signal processing circuit; the first signal processing circuit includes first to eleventh transistors; one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a gate signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a first power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second power supply line; a gate of the fourth transistor is always electrically connected to a wiring to which an output signal of the second signal processing circuit is input; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a first signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the first power supply line; the gate of the sixth transistor is always electrically connected to the second signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the first power supply line; a gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the first signal line; a gate of the eighth transistor is always electrically connected to the first signal line; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the first power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the first power supply line; the gate of the tenth transistor is always electrically connected to a third signal line; one of the source and the drain of the eleventh transistor is always electrically connected to the gate signal line; When the potential of the fourth signal line is input to the gate of the eleventh transistor, the potential of the gate of the eleventh transistor is controlled in accordance with the potential of the fourth signal line; when the other of the source or the drain of the second transistor is in a conductive state with the gate signal line via at least a channel formation region of the second transistor, a potential having a value that causes the gate signal line to be at an L level is input to the gate signal line via at least a channel formation region of the second transistor, when the other of the source or the drain of the eleventh transistor is in a conductive state with the gate signal line at least via a channel formation region of the eleventh transistor, a potential having a value that causes the gate signal line to be at an L level is input to the gate signal line at least via the channel formation region of the eleventh transistor, the W / L (W is a channel width, L is a channel length) of the third transistor is smaller than the W / L of the second transistor; A semiconductor device in which the W / L of the fourth transistor is smaller than the W / L of the first transistor.

3. A gate driver and a pixel, the gate driver includes a first signal processing circuit and a second signal processing circuit; the first signal processing circuit includes first to eleventh transistors; one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a gate signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a first power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second power supply line; a gate of the fourth transistor is always electrically connected to a wiring to which an output signal of the second signal processing circuit is input; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a first signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the first power supply line; the gate of the sixth transistor is always electrically connected to the second signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the first power supply line; a gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the first signal line; a gate of the eighth transistor is always electrically connected to the first signal line; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the first power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the first power supply line; the gate of the tenth transistor is always electrically connected to a third signal line; the pixel includes a twelfth transistor and a liquid crystal element; One of the source and the drain of the twelfth transistor is always electrically connected to the liquid crystal element; the other of the source and the drain of the twelfth transistor is always electrically connected to a source line; the gate of the twelfth transistor is always electrically connected to the gate signal line; when the other of the second transistor is in a conductive state with a gate of the twelfth transistor at least through a channel formation region of the second transistor, a potential at which the twelfth transistor is turned off is input to the gate of the eleventh transistor at least through the channel formation region of the second transistor, A display device in which, when the other of the 11th transistor is in a conductive state with a gate of the 12th transistor at least through a channel formation region of the 11th transistor, a potential at which the 12th transistor is turned off is input to the gate of the 11th transistor at least through the channel formation region of the 11th transistor.

4. A gate driver and a pixel, the gate driver includes a first signal processing circuit and a second signal processing circuit; the first signal processing circuit includes first to eleventh transistors; one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a gate signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a first power supply line; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a second power supply line; a gate of the fourth transistor is always electrically connected to a wiring to which an output signal of the second signal processing circuit is input; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a first signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the first power supply line; the gate of the sixth transistor is always electrically connected to the second signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the first power supply line; a gate of the seventh transistor is always electrically connected to the second signal line; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the first signal line; a gate of the eighth transistor is always electrically connected to the first signal line; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the first power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the first power supply line; the gate of the tenth transistor is always electrically connected to a third signal line; the pixel includes a twelfth transistor and a liquid crystal element; One of the source and the drain of the twelfth transistor is always electrically connected to the liquid crystal element; the other of the source and the drain of the twelfth transistor is always electrically connected to a source line; the gate of the twelfth transistor is always electrically connected to the gate signal line; when the other of the second transistor is in a conductive state with a gate of the twelfth transistor at least through a channel formation region of the second transistor, a potential at which the twelfth transistor is turned off is input to the gate of the eleventh transistor at least through the channel formation region of the second transistor, when the other of the eleventh transistor is in a conductive state with a gate of the twelfth transistor at least via a channel forming region of the eleventh transistor, a potential at which the twelfth transistor is turned off is input to the gate of the eleventh transistor at least via the channel forming region of the eleventh transistor, the W / L (W is a channel width, L is a channel length) of the third transistor is smaller than the W / L of the second transistor; A display device, wherein the W / L of the fourth transistor is smaller than the W / L of the first transistor.

Images