Display device

Abstract

To improve the reliability of a display device that includes a thin-film transistor using an oxide semiconductor.SOLUTION: In a display device with a thin-film transistor in each pixel, the thin-film transistor has: an oxide semiconductor layer; a gate insulating layer; a gate electrode superposed on the oxide semiconductor layer via the gate insulating layer; a source electrode contacted with the oxide semiconductor layer; a drain electrode contacted with the oxide semiconductor layer; and a first metal layer contacted with the oxide semiconductor layer and arranged between the source electrode and the drain electrode so as to be separated from the source and drain electrodes.SELECTED DRAWING: Figure 4B

Description

[Technical field]

[0001] An embodiment of the present invention relates to a display device including a thin film transistor in each pixel, and more particularly to a display device including a thin film transistor using an oxide semiconductor. [Background technology]

[0002] In recent years, oxide semiconductors have been attracting attention as semiconductors that form the channel layers of thin-film transistors used in organic light-emitting diode displays (OLED displays). Thin-film transistors using oxide semiconductors have low leakage current in the off state and can be driven at low frequencies. Therefore, thin-film transistors using oxide semiconductors can realize displays with low power consumption.

[0003] Generally, thin film transistors have a problem that their electrical characteristics are deteriorated by hot carriers generated near the boundary between the channel region and the drain region. Specifically, it is known that the threshold of the Vg-Id characteristic is shifted by hot carriers. This problem is not an exception even in thin film transistors using oxide semiconductors, and it is desirable to take measures against hot carriers in order to improve reliability. For example, Patent Document 1 discloses a technology for arranging a buffer region between the channel region and the drain region to relieve electric field concentration as a hot carrier countermeasure. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-114426 A Summary of the Invention [Problem to be solved by the invention]

[0005] The technology described in Patent Document 1 determines the length (L) of the buffer region by controlling the amount of setback when isotropically etching the drain electrode. Therefore, when forming multiple thin film transistors on a substrate, the distribution of the amount of etching may vary within the substrate surface. In this case, it is not possible to form a buffer region of uniform length for multiple thin film transistors, which may reduce the reliability of the display device.

[0006] An object of the present invention is to improve the reliability of a display device including a thin film transistor using an oxide semiconductor. [Means for solving the problem]

[0007] A display device according to an embodiment of the present invention has a thin film transistor in each pixel, the thin film transistor including an oxide semiconductor layer, a gate insulating layer, a gate electrode overlapping the oxide semiconductor layer via the gate insulating layer, a source electrode in contact with the oxide semiconductor layer, a drain electrode in contact with the oxide semiconductor layer, and a first metal layer in contact with the oxide semiconductor layer and disposed between the source electrode and the drain electrode at a distance from the source electrode and the drain electrode. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a configuration of a display device according to a first embodiment of the present invention. [Diagram 2] 1 is a circuit diagram showing a circuit configuration of a pixel in a display device according to a first embodiment of the present invention. [Diagram 3] 1 is a cross-sectional view showing a configuration of a display unit in a display device according to a first embodiment of the present invention. [Figure 4A] 1 is a cross-sectional view illustrating a configuration of a thin-film transistor used in a display device according to a first embodiment of the present invention. [Figure 4B] 1 is a plan view illustrating a configuration of a thin-film transistor used in a display device according to a first embodiment of the present invention. [Figure 5A]2A to 2C are cross-sectional views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 5B] 2A to 2C are plan views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 6A] 2A to 2C are cross-sectional views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 6B] 2A to 2C are plan views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 7A] 2A to 2C are cross-sectional views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 7B] 2A to 2C are plan views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 8A] 2A to 2C are cross-sectional views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 8B] 2A to 2C are plan views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 9A] 2A to 2C are cross-sectional views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 9B] 2A to 2C are plan views illustrating a method for manufacturing a thin-film transistor used in the display device according to the first embodiment of the present invention. [Figure 10A] FIG. 5 is a cross-sectional view showing the configuration of a thin-film transistor used in a display device according to a second embodiment of the present invention. [Figure 10B] FIG. 11 is a plan view illustrating a configuration of a thin-film transistor used in a display device according to a second embodiment of the present invention. [Figure 11A] FIG. 11 is a cross-sectional view showing the configuration of a thin-film transistor used in a display device according to a third embodiment of the present invention. [Figure 11B] FIG. 11 is a plan view illustrating a configuration of a thin-film transistor used in a display device according to a third embodiment of the present invention. [Figure 12A] FIG. 11 is a cross-sectional view showing the configuration of a thin-film transistor used in a display device according to a fourth embodiment of the present invention. [Figure 12B] FIG. 11 is a plan view illustrating a configuration of a thin-film transistor used in a display device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the present invention can be implemented in various forms without departing from the gist of the present invention. The present invention is not to be interpreted as being limited to the description of the embodiments exemplified below. In order to clarify the explanation, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual form. However, the drawings are merely examples and do not limit the interpretation of the present invention.

[0010] In the description of the embodiments of the present invention, the direction from the substrate toward the light-emitting element is defined as "upper", and the opposite direction is defined as "lower". However, the expressions "upper" and "lower" merely describe the upper-level relationship of each element. For example, the expression that the light-emitting element is disposed on the substrate includes the case where another member is interposed between the substrate and the light-emitting element. Furthermore, the expressions "upper" and "lower" include not only the case where the elements overlap in a planar view, but also the case where they do not overlap.

[0011] In describing the embodiments of the present invention, elements having similar functions to elements already described may be designated by the same reference numerals or the same reference numerals plus an alphabet or other symbols, and description thereof may be omitted.

[0012] In the description of the embodiments of the present invention, a plurality of elements formed by processing a certain film such as etching may be described as elements having different functions or roles. These elements are composed of the same layer structure and the same material. Therefore, the elements formed from a certain film may be called elements provided in the "same layer."

[0013] In the description of the embodiments of the present invention, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] In the description of the embodiments of the present invention, the term "display device" refers to a device that displays an image. That is, the term "display device" includes not only a display panel or a display module, but also a device in which other optical members (e.g., a polarizing member, a touch panel, etc.) are attached to the display panel or the display module.

[0015] First Embodiment [Configuration of display device 100] 1 is a plan view showing a configuration of a display device 100 according to a first embodiment of the present invention. The display device 100 includes a display unit 120, a drive circuit unit 130, and a terminal unit 140. The display unit 120, the drive circuit unit 130, and the terminal unit 140 are provided on a substrate 110.

[0016] The display unit 120 has a plurality of pixels 200R, 200G, and 200B. The pixel 200R corresponds to a pixel that emits red light. The pixel 200G corresponds to a pixel that emits green light. The pixel 200B corresponds to a pixel that emits blue light. The display unit 120 displays an image by controlling the emission and non-emission of the plurality of pixels 200R, 200G, and 200B. In this embodiment, when there is no particular need to distinguish between the colors RGB, the pixels may simply be referred to as pixels 200. The configuration of each pixel 200 will be described later.

[0017] The drive circuit unit 130 controls each pixel 200 of the display unit 120. The drive circuit unit 130 includes, for example, a gate line drive circuit, etc. Although not shown in FIG. 1, the drive circuit unit 130 may include a data line drive circuit.

[0018] The terminal unit 140 functions as a terminal that receives signals from the outside to be supplied to the display unit 120 and the drive circuit unit 130. The terminal unit 140 includes a plurality of terminals 141. A flexible printed circuit board 150 is connected to the terminal unit 140, and the plurality of terminals 141 are each connected to a corresponding terminal on the flexible printed circuit board 150. In this embodiment, a driver IC chip 160 is provided on the flexible printed circuit board 150. However, this is not limiting, and the driver IC chip 160 may be omitted.

[0019] 1 shows the entire configuration of the display device 100 in a plan view, the substrate 110 may be bent between the display unit 120 and the terminal unit 140. In this case, a flexible substrate such as a resin substrate may be used as the substrate 110. In such a configuration, the terminal unit 140 and the flexible printed circuit board 150 can be folded onto the back side of the display device 100, and the display device 100 can be made smaller in size.

[0020] [Configuration of pixel circuit 300] 2 is a circuit diagram showing a circuit configuration of a pixel 200 in the display device 100 of the first embodiment of the present invention. The pixel circuit 300 includes a selection transistor 310, a drive transistor 320, a capacitor 330, and a light emitting element 340.

[0021] The selection transistor 310 is connected to a gate line 312 and a data line 314. Specifically, the gate line 312 is connected to the gate of the selection transistor 310. The data line 314 is connected to the source of the selection transistor 310. The selection transistor 310 functions as a switch for selecting whether or not to input a data signal (video signal Vs) to the pixel circuit 300. The drain of the selection transistor 310 is connected to the gate of the drive transistor 320 and the capacitor 330.

[0022] The driving transistor 320 is connected to an anode power line 322, a light emitting element 340, and a capacitor 330. Specifically, the anode power line 322 is connected to the drain of the driving transistor 320. The light emitting element 340 is connected to the source of the driving transistor 320. The capacitor 330 is connected between the gate and source of the driving transistor 320. The driving transistor 320 functions as a valve for controlling the amount of current flowing to the light emitting element 340. A high potential power supply voltage (PVDD) is applied to the anode power line 322.

[0023] The capacitor 330 serves to hold the data signal input via the selection transistor 310. A voltage corresponding to the data signal held in the capacitor 330 is applied to the gate of the drive transistor 320. As a result, the amount of current flowing via the drive transistor 320 is controlled in accordance with the data signal.

[0024] The light emitting element 340 is connected between the drive transistor 320 and the cathode power line 324. Specifically, the anode of the light emitting element 340 is connected to the source of the drive transistor 320. That is, the anode of the light emitting element 340 is connected to the anode power line 322 via the drive transistor 320. The cathode of the light emitting element 340 is connected to the cathode power line 324. A low potential power supply voltage (PVSS) is applied to the cathode power line 324.

[0025] In the pixel circuit 300, when the selection transistor 310 is turned on, a data signal is input from the data line 314. A voltage corresponding to the input data signal is held by the capacitor 330. Thereafter, during a light emission period, the gate of the drive transistor 320 is controlled by the voltage held in the capacitor 330, and a current corresponding to the data signal flows through the drive transistor 320. When a current flows through the light emitting element 340, the light emitting element 340 emits light with a luminance corresponding to the amount of current.

[0026] [Configuration of pixel 200] Fig. 3 is a cross-sectional view showing the configuration of the display unit 120 in the display device 100 according to the first embodiment of the present invention. Specifically, the cross-sectional structure shown in Fig. 3 corresponds to a cross-sectional view of the display unit 120 shown in Fig. 1 taken along dashed line AA. Since the basic structures of the pixels 200R, 200G, and 200B are the same, the description in Fig. 3 focuses on pixel 200G that emits green light.

[0027] As shown in Fig. 3, a driving transistor 320 is provided on the substrate 110. Although not shown in Fig. 3, each element constituting a pixel circuit 300, such as a selection transistor 310 and a capacitor 330, is also provided on the substrate 110.

[0028] The driving transistor 320 is covered with an insulating layer 121 including a resin layer. The resin layer included in the insulating layer 121 plays a role in flattening undulations caused by the driving transistor 320 and the like. The insulating layer 121 may have a laminated structure of an inorganic insulating layer and a resin layer. The material of the inorganic insulating layer may be, for example, a silicon-based inorganic material such as silicon oxide or silicon nitride. The material of the resin layer may be, for example, a photosensitive organic material such as acrylic or polyimide.

[0029] An anode electrode 122 is provided on the insulating layer 121. The anode electrode 122 is an anode of the light-emitting element 340 and also functions as a pixel electrode of the pixel 200. The anode electrode 122 is electrically connected to the source electrode of the driving transistor 320 through a contact hole provided in the insulating layer 121. In this embodiment, the anode electrode 122 is made of a transparent conductive layer. However, the present invention is not limited to this example, and the anode electrode 122 may be made of a metal layer or may have a laminated structure of a transparent conductive layer and a metal layer. For example, a transparent conductive layer containing a metal oxide can be used as the anode electrode 122. In this embodiment, a conductive layer in which a metal layer containing silver and a transparent conductive layer made of ITO (Indium Tin Oxide) are laminated is used as the anode electrode 122. In this case, the conductive layer on the side in contact with the organic layer 124 described later is made a transparent conductive layer.

[0030] A partition layer 123 is provided on the anode electrode 122. The partition layer 123 has an opening so that a part of the surface of the anode electrode 122 is exposed. In other words, the partition layer 123 is provided so as to cover the end of the anode electrode 122. It is preferable that the inner wall of the opening of the partition layer 123 has a gentle tapered shape. By making the inner wall of the opening of the partition layer 123 have a tapered shape, it is possible to reduce poor coverage of the organic layer 124 or the cathode electrode 125 formed on the anode electrode 122. The partition layer 123 may also be called a bank or a rib.

[0031] On the anode electrode 122, an organic layer 124 including at least a hole transport layer, a light emitting layer, and an electron transport layer is provided. In the case of the pixel 200G, the light emitting layer of the organic layer 124 is made of an organic material that emits green light. Similarly, in the case of the pixel 200R and the pixel 200B, the light emitting layer of the organic layer 124 is made of an organic material that emits red light and an organic material that emits blue light, respectively. The hole transport layer and the electron transport layer included in the organic layer 124 may be provided so as to straddle each pixel 200. In addition, the organic layer 124 may further include a functional layer such as an electron injection layer, an electron blocking layer, a hole injection layer, or a hole blocking layer.

[0032] A cathode electrode 125 is provided on the organic layer 124. The cathode electrode 125 may be provided so as to straddle each pixel 200. In this embodiment, the cathode electrode 125 is made of a metal layer. However, this is not limited to the example, and the cathode electrode 125 may be made of a transparent conductive layer, or may have a laminated structure of a transparent conductive layer and a metal layer. For example, a metal layer containing an alkali metal or an alkaline earth metal can be used as the cathode electrode 125. In this embodiment, a metal layer made of an MgAg alloy (an alloy containing magnesium and silver) is used as the cathode electrode 125. In this case, the thickness of the cathode electrode 125 is set to a level that allows visible light to pass through.

[0033] A sealing layer 126 is provided on the cathode electrode 125. The sealing layer 126 has a structure in which, for example, an inorganic insulating layer 126a, an organic insulating layer 126b, and an inorganic insulating layer 126c are laminated. For example, silicon-based inorganic materials such as silicon oxide and silicon nitride can be used as the material of the inorganic insulating layer 126a and the inorganic insulating layer 126c. The inorganic insulating layer 126a and the inorganic insulating layer 126c have a role of preventing the intrusion of moisture from the outside. Therefore, it is preferable to use an insulating layer having a dense film quality as the inorganic insulating layer 126a and the inorganic insulating layer 126c. For example, a resin material such as an acrylic resin, an epoxy resin, a polyimide resin, a silicon resin, a fluorine resin, or a siloxane resin can be used as the material of the organic insulating layer 126b.

[0034] In this embodiment, a cover glass 128 is provided on the sealing layer 126 via an adhesive layer 127. Although not shown in FIG. 3, an optical member such as a polarizing plate or a touch sensor may be further provided above or below the cover glass 128.

[0035] [Configuration of thin film transistor 10] FIG. 4A is a cross-sectional view showing the configuration of a thin-film transistor 10 used in the display device 100 of the first embodiment of the present invention. FIG. 4B is a plan view showing the configuration of a thin-film transistor 10 used in the display device 100 of the first embodiment of the present invention. For convenience of explanation, the insulating layers 18 and 19 shown in FIG. 4A are omitted in FIG. 4B. The thin-film transistor 10 can be used for at least one of the selection transistor 310 and the drive transistor 320 shown in FIG. 2. The thin-film transistor 10 shown in FIGS. 4A and 4B is an example of a bottom-gate transistor.

[0036] A gate electrode 11 is provided on a substrate 110 having an insulating surface. For example, a light-transmitting substrate made of glass, quartz, sapphire, or the like can be used as the substrate 110. However, a non-light-transmitting substrate made of silicon, ceramics, or the like may also be used as the substrate 110. Furthermore, a flexible substrate made of a resin material such as polyimide resin, acrylic resin, siloxane resin, or fluororesin may also be used as the substrate 110.

[0037] The gate electrode 11 is made of, for example, a metal material such as titanium, tantalum, tungsten, molybdenum, vanadium, aluminum, copper, or niobium, or an alloy material containing these metals. The gate electrode 11 may have a single layer structure or a multilayer structure.

[0038] The gate electrode 11 is covered with insulating layers 12 and 13. In this embodiment, the insulating layer 12 is a silicon nitride layer. The insulating layer 13 is a silicon oxide layer. In this embodiment, the insulating layers 12 and 13 are stacked to function as a gate insulating layer. However, this is not limiting, and the insulating layer 13 may be used as a single layer as the gate insulating layer.

[0039] An oxide semiconductor layer 30 is provided on the insulating layer 13. For example, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium aluminum zinc oxide (IAZO), zinc oxide (ZnO), or the like can be used as the material of the oxide semiconductor layer 30. The oxide semiconductor layer 30 may be a single layer or a multilayer. In this embodiment, indium gallium zinc oxide (IGZO) is used as the oxide semiconductor layer 30. Therefore, the thin film transistor 10 of this embodiment operates as an N-channel transistor in which electrons are the majority carriers. The structure of the oxide semiconductor layer 30 will be described in detail later.

[0040] On the oxide semiconductor layer 30, a source electrode 14 and a drain electrode 15 are provided so as to contact the end of the oxide semiconductor layer 30. Specifically, in a cross-sectional view, the source electrode 14 is provided so as to contact a first end of the oxide semiconductor layer 30, and the drain electrode 15 is provided so as to contact a second end opposite to the first end. In this embodiment, the source electrode 14 and the drain electrode 15 are provided so as to cover three sides at the end of the oxide semiconductor layer 30, but this is not limited to the example. For example, the source electrode 14 and the drain electrode 15 may be provided so as to cross the oxide semiconductor layer 30 (i.e., to cover two sides).

[0041] The source electrode 14 and the drain electrode 15 are made of a metal material such as titanium, aluminum, tantalum, tungsten, molybdenum, vanadium, aluminum, copper, or niobium, or an alloy material containing these metals. The source electrode 14 and the drain electrode 15 may have a single-layer structure or a multilayer structure. In this embodiment, a metal layer having a three-layer structure of titanium / aluminum / titanium is used as the source electrode 14 and the drain electrode 15.

[0042] In this embodiment, the metal layers 16 and 17 are formed at the same time as the source electrode 14 and the drain electrode 15. That is, the metal layers 16 and 17 are provided in the same layer as the source electrode 14 and the drain electrode 15. Therefore, the metal layers 16 and 17 have a three-layer structure of titanium / aluminum / titanium, similar to the source electrode 14 and the drain electrode 15. However, the present invention is not limited to this example, and the metal layers 16 and 17 may be formed of a metal material different from that of the source electrode 14 and the drain electrode 15.

[0043] Both the metal layers 16 and 17 are provided so as to be in contact with the oxide semiconductor layer 30. At this time, the metal layers 16 and 17 are disposed so as to be spaced apart from the source electrode 14 and the drain electrode 15, respectively. Specifically, in this embodiment, the distance between the source electrode 14 and the metal layer 16 is 1.0 μm or more and 3.0 μm or less (preferably, 1.5 μm or more and 2.0 μm or less). The distance between the drain electrode 15 and the metal layer 17 is also 1.0 μm or more and 3.0 μm or less (preferably, 1.5 μm or more and 2.0 μm or less).

[0044] In this embodiment, the metal layers 16 and 17 are electrically floating. However, this is not the only example, and the metal layers 16 and 17 may be fixed at a constant potential. There is no particular limit to the width of the metal layers 16 and 17. In this embodiment, the width of the metal layers 16 and 17 is 1.0 μm or more and 3.0 μm or less. However, the lower limit of the width of the metal layers 16 and 17 may be the minimum width that can be exposed.

[0045] Insulating layers 18 and 19 are provided on the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17. The insulating layers 18 and 19 function as passivation layers, respectively. In this embodiment, a silicon oxide layer is used as the insulating layer 18. Also, a silicon nitride layer is used as the insulating layer 19. In addition to serving as a passivation layer, the insulating layer 18 has a role of supplying oxygen to the oxide semiconductor layer 30. Therefore, it is preferable to use a material having a relatively high oxygen content, such as silicon oxide or silicon oxynitride, as the material of the insulating layer 18. In contrast, the insulating layer 19 mainly serves as a passivation layer. Therefore, it is preferable to use a silicon nitride layer having a dense film quality as the insulating layer 19.

[0046] [Configuration of oxide semiconductor layer 30] In the thin film transistor 10 of this embodiment, the oxide semiconductor layer 30 has a plurality of regions having different electrical resistances (in other words, a plurality of regions having different electrical conductivities). Specifically, the oxide semiconductor layer 30 has a source region 31, a drain region 32, first low-resistance regions 33 to 36, second low-resistance regions 37 and 38, and a channel region 39.

[0047] The first low-resistance regions 33 to 36 and the second low-resistance regions 37 and 38 all have a lower electrical resistance than the channel region 39. The second low-resistance regions 37 and 38 have an even lower electrical resistance than the first low-resistance regions 33 to 36. The electrical resistance of the second low-resistance regions 37 and 38 is substantially equal to the electrical resistance of the source region 31 and the drain region 32. In this embodiment, the first low-resistance regions 33 to 36 function as buffer regions that relieve electric field concentration in the vicinity of the source region 31 or the drain region 32. Such a buffer region is effective as a measure against hot carriers.

[0048] The oxide semiconductor layer 30 of the present embodiment is made of indium gallium zinc oxide (IGZO), and therefore has a physical property that when oxygen is desorbed from the inside of the layer to the outside, the electrical resistance of the portion from which the oxygen is desorbed decreases. Therefore, when another metal layer is in contact with the oxide semiconductor layer 30, a phenomenon occurs in which oxygen is desorbed from the inside of the oxide semiconductor layer 30 as the other metal layer is oxidized. That is, the oxide semiconductor layer 30 of the present embodiment has a physical property that the electrical resistance of the portion in contact with the other metal layer and the vicinity thereof decreases. Therefore, in the oxide semiconductor layer 30 of the present embodiment, a region having a lower electrical resistance than the channel region 39 is formed due to the influence of the source electrode 14, the drain electrode 15, the metal layer 16, the metal layer 17, and the like.

[0049] 4A, the source region 31 and the drain region 32 are formed in regions of the oxide semiconductor layer 30 that are in contact with the source electrode 14 and the drain electrode 15, respectively. The second low-resistance regions 37 and 38 are formed in regions of the oxide semiconductor layer 30 that are in contact with the metal layers 16 and 17.

[0050] The first low-resistance region 33 is formed between the source region 31 and the second low-resistance region 37. At this time, the first low-resistance region 33 is formed over the entire region between the source region 31 and the second low-resistance region 37. Similarly, the first low-resistance region 34 is formed between the drain region 32 and the second low-resistance region 38. In this case, the first low-resistance region 34 is formed over the entire region between the drain region 32 and the second low-resistance region 38. The first low-resistance region 35 is formed between the second low-resistance region 37 and the channel region 39. Similarly, the first low-resistance region 36 is formed between the second low-resistance region 38 and the channel region 39.

[0051] As described above, the source region 31, the drain region 32, the first low-resistance regions 33 to 36, and the second low-resistance regions 37 and 38 are formed by oxygen desorption from inside the oxide semiconductor layer 30. Therefore, the oxygen concentrations in these regions are lower than the oxygen concentration in the channel region 39. In addition, the first low-resistance regions 33 to 36 are not in direct contact with the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17. Therefore, the oxygen concentrations in the first low-resistance regions 33 to 36 are higher than the source region 31, the drain region 32, and the second low-resistance regions 37 and 38, and lower than the channel region 39.

[0052] In addition, the length of the first low-resistance regions 33 to 36 (length along the direction in which carriers move) varies depending on the conditions of the manufacturing process after the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17 are formed. For example, the length of the first low-resistance regions 33 to 36 can be controlled by the process temperature when forming the insulating layer 18, or the bake temperature after forming the insulating layer 18. In this embodiment, for example, the process temperature when forming the insulating layer 18 is controlled so that the first low-resistance regions 35 and 36 are each 0.5 μm or more and 1.5 μm or less. However, this is not the only example, and any control method is possible as long as the lengths of the first low-resistance regions 35 and 36 can be set to the desired lengths.

[0053] In the first low-resistance region 34, oxygen is desorbed due to the influence of both the drain electrode 15 and the metal layer 17. Therefore, the formation of the first low-resistance region 34 proceeds from both the region close to the drain electrode 15 and the region close to the metal layer 17. Therefore, for example, when the above-mentioned process temperature is used, the length of the first low-resistance region 34 is about twice as long as the first low-resistance region 36. That is, the length of the first low-resistance region 34 is 1.0 μm or more and 3.0 μm or less. As a result, the length of the buffer region in the vicinity of the drain region 32 is substantially the sum of the lengths of the first low-resistance regions 34 and 36. That is, according to this embodiment, a low-resistance region having a length of 1.5 μm or more and 4.5 μm or less (preferably 2.0 μm or more and 3.0 μm or less) can be formed as the buffer region in the vicinity of the drain region 32. Here, the description has been given with attention to the vicinity of the drain region 32, but the same applies to the vicinity of the source region 31.

[0054] According to the findings of the present applicant, in a thin film transistor using an oxide semiconductor, the longer the low resistance region disposed near the drain region, the higher the hot carrier resistance. Specifically, the present applicant has found that if the length of the low resistance region is at least 1.5 μm or more (preferably 2.0 μm or more), the deterioration of characteristics due to hot carriers can be effectively suppressed. However, when oxygen is desorbed from the oxide semiconductor layer 30 using only the source electrode 14 and the drain electrode 15, it is difficult to form a low resistance region of sufficient length.

[0055] In contrast, in this embodiment, the total length over which the low resistance regions are formed can be increased simply by forming the metal layers 16 and 17 simultaneously with the formation of the source electrode 14 and the drain electrode 15. Thus, according to this embodiment, the first low resistance regions 33 to 36 of sufficient length can be formed without increasing the manufacturing process.

[0056] In addition, since the lengths of the first low-resistance regions 33-36 are determined by the thermal history and the like after forming the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17, there is little variation in the lengths of the first low-resistance regions 33-36 within the surface of the substrate 110. Therefore, buffer regions of uniform length can be formed for a plurality of thin film transistors 10.

[0057] Furthermore, according to this embodiment, it is possible to form buffer regions of sufficient length near both the source region 31 and the drain region 32. Therefore, for example, in a thin film transistor in which the source and drain are interchanged, such as the selection transistor 310 shown in Fig. 2, it is possible to suppress characteristic degradation due to hot carriers regardless of the direction of carrier movement. Even when the source and drain are interchanged due to AC driving or the like, it is possible to suppress characteristic degradation regardless of the direction of carrier movement.

[0058] As described above, according to the present embodiment, it is possible to improve the reliability of the display device 100 including the thin film transistor 10 using an oxide semiconductor.

[0059] [Method of manufacturing thin film transistor 10] 5A, 6A, 7A, 8A, and 9A are cross-sectional views showing a method for manufacturing the thin-film transistor 10 used in the display device 100 of the first embodiment of the present invention. Figures 5B, 6B, 7B, 8B, and 9B are plan views showing a method for manufacturing the thin-film transistor 10 used in the display device 100 of the first embodiment of the present invention.

[0060] 5A and 5B, a gate electrode 11 is formed on a substrate 110. Specifically, a metal layer is formed containing a metal material (in this embodiment, aluminum and titanium are used as the metal material) that constitutes the gate electrode 11. Thereafter, the metal layer in which aluminum and titanium are laminated is etched to form the gate electrode 11.

[0061] Next, as shown in FIGS. 6A and 6B, insulating layers 12 and 13 are formed so as to cover the gate electrode 11. In this embodiment, first, a silicon nitride layer is formed as the insulating layer 12. Then, a silicon oxide layer is formed as the insulating layer 13 on the insulating layer 12. After forming the insulating layer 13, an oxide semiconductor layer 30 is formed on the insulating layer 13. In this embodiment, first, an oxide semiconductor layer made of indium gallium zinc oxide (IGZO) is formed to a thickness of 40 nm or more and 100 nm or less. Then, the oxide semiconductor layer is etched to form the oxide semiconductor layer 30.

[0062] 7A and 7B, the metal layer 20 is formed so as to cover the oxide semiconductor layer 30. The metal layer 20 is formed by stacking a titanium layer, an aluminum layer, and a titanium layer in this order from the bottom up. In this embodiment, the titanium layer is provided as the bottommost layer to prevent the oxide semiconductor layer 30 and the aluminum layer from coming into direct contact with each other. This makes it possible to prevent excessive oxygen from being released from the oxide semiconductor layer 30 due to oxidation of the aluminum layer.

[0063] 8A and 8B, the metal layer 20 is etched to form the source electrode 14, the drain electrode 15, the metal layer 16, and the metal layer 17. At this time, as shown in Fig. 8B, the metal layers 16 and 17 are formed so as to cross the oxide semiconductor layer 30. In this embodiment, the source electrode 14 and the metal layer 16, or the drain electrode 15 and the metal layer 17 are spaced apart by a distance of 1.0 µm to 3.0 µm (preferably, 1.5 µm to 2.0 µm).

[0064] Next, as shown in FIG. 9A and FIG. 9B, an insulating layer 18 is formed so as to cover the source electrode 14, the drain electrode 15, the metal layer 16, the metal layer 17, and the oxide semiconductor layer 30. In this embodiment, a silicon oxide layer is formed as the insulating layer 18 to a thickness of 100 nm to 300 nm. In this embodiment, during the process of forming the insulating layer 18, the source region 31, the drain region 32, the first low-resistance regions 33 to 36, the second low-resistance regions 37 and 38, and the channel region 39 are formed in the oxide semiconductor layer 30. After the insulating layer 18 is formed, a bake process may be performed on the insulating layer 18. The length of the first low-resistance regions 33 to 36 may be adjusted by the temperature of the bake process on the insulating layer 18.

[0065] In the above-mentioned process of forming the insulating layer 18 and the process of baking the insulating layer 18, oxygen is supplied to the channel region 39 from the silicon oxide layer that is the insulating layer 18. This makes it possible to adjust the electrical resistance of the channel region 39 so that the channel region 39 functions normally as a channel. The oxygen released from the insulating layer 18 is also supplied to the first low-resistance regions 33-36. However, oxygen is desorbed from the first low-resistance regions 33-36 due to the influence of the metal layers 16 and 17. Therefore, the electrical resistance of the first low-resistance regions 33-36 becomes lower than the electrical resistance of the channel region 39.

[0066] 9A and 9B, an insulating layer 19 is formed on the insulating layer 18. In this embodiment, a silicon nitride layer is formed to a thickness of 100 nm or more and 200 nm or less as the insulating layer 19. This completes the thin film transistor 10 having the structure described with reference to FIGS. 4A and 4B.

[0067] <Second embodiment> In this embodiment, a display device including a thin film transistor 10a having a structure different from that of the first embodiment will be described. In this embodiment, the differences from the first embodiment will be mainly described. In the drawings used to describe this embodiment, the same components as those in the first embodiment will be denoted by the same reference numerals and detailed descriptions thereof will be omitted.

[0068] Fig. 10A is a cross-sectional view showing the configuration of a thin film transistor 10a used in a display device according to a second embodiment of the present invention. Fig. 10B is a plan view showing the configuration of a thin film transistor 10a used in a display device according to a second embodiment of the present invention. As shown in Figs. 10A and 10B, in this embodiment, a metal layer (metal layer 16 shown in Figs. 4A and 4B) is not provided near the source electrode 14.

[0069] In the case of a thin film transistor in which the positional relationship between the source and drain does not change and carriers always move in a fixed direction, it is sufficient to provide a buffer region of sufficient length only in the vicinity of the drain region. In response to such a case, in this embodiment, the first low-resistance regions 34 and 36 are provided only in the vicinity of the drain region 32. In this case, only the first low-resistance region 41 formed by the oxidation of the source electrode 14 is formed in the vicinity of the source region 31. Therefore, in this embodiment, the region between the first low-resistance region 41 and the first low-resistance region 36 functions as a channel region 42.

[0070] In this embodiment as well, the first low-resistance regions 34 and 36 can be formed with sufficient length near the drain region 32 without increasing the manufacturing process. Moreover, similar to the first embodiment, the lengths of the first low-resistance regions 34 and 36 can be made uniform among the multiple thin film transistors 10a. Thus, according to this embodiment, the reliability of the display device including the thin film transistors 10a using an oxide semiconductor can be improved.

[0071] <Third embodiment> In this embodiment, a display device including a thin film transistor 10b having a structure different from that of the first embodiment will be described. The thin film transistor 10b of this embodiment corresponds to a top gate type thin film transistor instead of the bottom gate type thin film transistor 10 described in the first embodiment.

[0072] FIG. 11A is a cross-sectional view showing the configuration of a thin-film transistor 10b used in a display device according to a third embodiment of the present invention. FIG. 11B is a plan view showing the configuration of a thin-film transistor 10b used in a display device according to a third embodiment of the present invention. For convenience of explanation, the gate insulating layer 52, the insulating layer 54, and the insulating layer 55 shown in FIG. 11A are omitted in FIG. 11B. The thin-film transistor 10b can be used for at least one of the selection transistor 310 and the drive transistor 320 shown in FIG. 2. The thin-film transistor 10b shown in FIGS. 11A and 11B is an example of a top-gate transistor.

[0073] An oxide semiconductor layer 60 is provided on the substrate 110 via an underlayer 51. The underlayer 51 may be a silicon oxide layer or an insulating layer having a two-layer structure of a silicon nitride layer and a silicon oxide layer. When the underlayer 51 has a two-layer structure, it is preferable that the insulating layer in contact with the oxide semiconductor layer 60 is a silicon oxide layer. The material of the substrate 110 is the same as that of the first embodiment, and therefore a description thereof will be omitted here.

[0074] The oxide semiconductor layer 60 may be made of, for example, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium aluminum zinc oxide (IAZO), or zinc oxide (ZnO). The oxide semiconductor layer 60 may be a single layer or a multilayer. In this embodiment, indium gallium zinc oxide (IGZO) is used as the oxide semiconductor layer 60. Therefore, the thin film transistor 10b of this embodiment operates as an N-channel transistor in which the majority carriers are electrons.

[0075] The oxide semiconductor layer 60 is covered with a gate insulating layer 52. In this embodiment, a silicon oxide layer is used as the gate insulating layer 52. However, the present invention is not limited to this example, and an insulating layer having a two-layer structure of a silicon nitride layer and a silicon oxide layer may be used as the gate insulating layer 52. In this case, however, it is preferable that the insulating layer in contact with the oxide semiconductor layer 60 is a silicon oxide layer.

[0076] A gate electrode 53 is provided on the gate insulating layer 52. The material of the gate electrode 53 is the same as that of the first embodiment, and therefore the description thereof will be omitted here. The gate electrode 53 is covered with insulating layers 54 and 55. In this embodiment, the insulating layer 54 is a silicon oxide layer. The insulating layer 54 is provided mainly to insulate and separate the gate electrode 53 from the source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59. The insulating layer 55 is a silicon nitride layer. The insulating layer 55 functions as a passivation film. However, this is not limited to this example, and the insulating layer 55 can be omitted.

[0077] On the insulating layer 55, a source electrode 56, a drain electrode 57, a metal layer 58, and a metal layer 59 are provided. In this embodiment, as the source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59, a metal layer having a three-layer structure of titanium / aluminum / titanium is used as the source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59, as in the first embodiment. In this embodiment, the metal layers 58 and 59 may be electrically floating or may be fixed at a constant potential. In this embodiment, the source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59 are simultaneously formed in the same process. However, this is not limited to this example, and the metal layers 58 and 59 may be formed of a metal material different from that of the source electrode 56 and the drain electrode 57.

[0078] The source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59 are in contact with the oxide semiconductor layer 60 through contact holes provided in the gate insulating layer 52, and the insulating layers 54 and 55. Therefore, as in the first embodiment, oxygen is released from the oxide semiconductor layer 60 as the source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59 are oxidized. As a result, the source region 61, the drain region 62, the first low-resistance regions 63 to 66, and the second low-resistance regions 67 and 68 are formed in the oxide semiconductor layer 60. Details of the source region 61, the drain region 62, the first low-resistance regions 63 to 66, and the second low-resistance regions 67 and 68 are similar to those of the source region 31, the drain region 32, the first low-resistance regions 33 to 36, and the second low-resistance regions 37 and 38 described in the first embodiment, and therefore will not be described here.

[0079] The metal layers 58 and 59 are disposed apart from the source electrode 56 and the drain electrode 57, respectively. Specifically, in this embodiment, the length of the first low-resistance region 63 or the length of the first low-resistance region 64 is designed to be 1.0 μm or more and 3.0 μm or less (preferably, 1.5 μm or more and 2.0 μm or less). Therefore, the length of the buffer region near the source region 61 or the drain region 62 (the total length of the first low-resistance regions 63 and 65 or the total length of the first low-resistance regions 64 and 66) is 1.5 μm or more and 4.5 μm or less (preferably, 2.0 μm or more and 3.0 μm or less).

[0080] As described above, according to this embodiment, the first low-resistance regions 63-66 can be formed with sufficient length without increasing the number of manufacturing processes. Furthermore, since the length of the first low-resistance regions 63-66 is determined by the thermal history after the source electrode 56, the drain electrode 57, the metal layer 58, and the metal layer 59 are formed, there is little variation in length within the surface of the substrate 110, and buffer regions with uniform length can be formed for the plurality of thin film transistors 10b. Thus, according to this embodiment, the reliability of a display device including thin film transistors 10b using an oxide semiconductor can be improved.

[0081] <Fourth embodiment> In this embodiment, a display device including a thin film transistor 10c having a structure different from that of the third embodiment will be described. In this embodiment, differences from the first embodiment will be mainly described. In the drawings used to describe this embodiment, the same components as those in the first embodiment will be denoted by the same reference numerals and detailed descriptions thereof will be omitted.

[0082] Fig. 12A is a cross-sectional view showing the structure of a thin film transistor 10c used in a display device according to a fourth embodiment of the present invention. Fig. 12B is a plan view showing the structure of a thin film transistor 10c used in a display device according to a second embodiment of the present invention. As shown in Figs. 12A and 12B, in this embodiment, the metal layers 71 and 72 are the same metal layer as the gate electrode 53.

[0083] In this embodiment, after the gate insulating layer 52 is formed, contact holes are formed in the gate insulating layer 52 so as to expose the regions that will later become the second low-resistance regions 67 and 68. Thereafter, a metal layer in which aluminum and titanium are laminated is formed, and etching is performed to form the gate electrode 53, the metal layer 71, and the metal layer 72. That is, in this embodiment, the gate electrode 53, the metal layer 71, and the metal layer 72 are simultaneously formed in the same process. However, this is not limiting, and the metal layers 71 and 72 may be formed of a metal material different from that of the gate electrode 53.

[0084] Both the metal layer 71 and the metal layer 72 are in contact with the oxide semiconductor layer 60 via contact holes provided in the gate insulating layer 52. Therefore, due to the source electrode 56, the drain electrode 57, the metal layer 71, and the metal layer 72, first low-resistance regions 63 to 66 and second low-resistance regions 67 and 68 are formed in the oxide semiconductor layer 60. The configuration of the oxide semiconductor layer 60 is similar to that of the third embodiment, and therefore a description thereof will be omitted here.

[0085] In this embodiment as well, the first low-resistance regions 64 and 66 can be formed with sufficient length near the drain region 62 without increasing the manufacturing process. Moreover, similar to the third embodiment, the lengths of the first low-resistance regions 64 and 66 can be made uniform for the plurality of thin film transistors 10c. Thus, according to this embodiment, the reliability of the display device including the thin film transistors 10c using an oxide semiconductor can be improved.

[0086] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0087] Furthermore, even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0088] 10, 10a to 10c... thin film transistor, 11... gate electrode, 12, 13... insulating layer, 14... source electrode, 15... drain electrode, 16, 17... metal layer, 18, 19... insulating layer, 20... metal layer, 30... oxide semiconductor layer, 31... source region, 32... drain region, 33 to 36... first low resistance region, 37, 38... second low resistance region, 39... channel region, 41... first low resistance region, 42... channel region, 51... underlayer, 52... gate insulating layer, 53... gate electrode, 54, 55... insulating layer, 56... source electrode, 57... drain electrode, 58, 59... metal layer, 60... oxide semiconductor layer, 61... source region, 62... drain region, 63 to 66... ​​first low resistance region, 67, 68... second low resistance region, 71, 72... gold metal layer, 100...display device, 110...substrate, 120...display section, 121...insulating layer, 122...anode electrode, 123...partition layer, 124...organic layer, 125...cathode electrode, 126...sealing layer, 126a, 126c...inorganic insulating layer, 126b...organic insulating layer, 127...adhesive layer, 128...cover glass, 130...driving circuit section, 140...terminal section, 141...terminal, 150...flexible printed circuit board, 160...driver IC chip, 200...pixel, 200R, 200G, 200B...pixel, 300...pixel circuit, 310...selection transistor, 312...gate line, 314...data line, 320...driving transistor, 322...anode power line, 324...cathode power line, 330...capacitor, 340...light-emitting element

Claims

1. A display device having a thin film transistor in each pixel, The thin film transistor is an oxide semiconductor layer; A gate insulating layer; a gate electrode overlapping the oxide semiconductor layer with the gate insulating layer interposed therebetween; a source electrode in contact with the oxide semiconductor layer; a drain electrode in contact with the oxide semiconductor layer; a first metal layer in contact with the oxide semiconductor layer and disposed between the source electrode and the drain electrode at a distance from the source electrode and the drain electrode; having the oxide semiconductor layer has a channel region and a region in contact with the first metal layer; A display device, wherein an oxygen concentration in a region in contact with the first metal layer is lower than an oxygen concentration in the channel region.

2. The display device according to claim 1 , wherein the distance between the first metal layer and the drain electrode is not less than 1.0 μm and not more than 3.0 μm.

3. The display device according to claim 1 , wherein the first metal layer and the drain electrode are provided in the same layer.

4. The display device according to claim 1 , wherein the first metal layer and the drain electrode are made of the same metal material.

5. The display device according to claim 1 , wherein the first metal layer is electrically floating.

6. The display device according to claim 1 , wherein the oxide semiconductor layer has a channel region, a drain region, and a low resistance region between the channel region and the drain region.

7. the low resistance region includes a first region, The display device according to claim 6 , wherein the first region is disposed between the region in contact with the first metal layer and the drain region.

8. The low resistance region further includes a second region, The display device according to claim 7 , wherein the second region is disposed between the region in contact with the first metal layer and the channel region.

9. The display device according to claim 8 , wherein the first region and the second region are separated from each other by a region in contact with the first metal layer.

10. The display device according to claim 1 , wherein the first metal layer penetrates the gate insulating layer and contacts the oxide semiconductor layer.

11. 2. The display device according to claim 1, further comprising a second metal layer in contact with the oxide semiconductor layer, between the source electrode and the first metal layer, and spaced apart from the source electrode and the first metal layer.

12. The display device according to claim 11 , wherein the distance between the second metal layer and the source electrode is not less than 1.0 μm and not more than 3.0 μm.

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