Method for improving read current stability in analog non-volatile memories by post-program conditioning for memory cells exhibiting random telegraph noise

Abstract

A memory device and method for a non-volatile memory cell having a gate, comprising programming the memory cell to an initial program state corresponding to a target read current and threshold voltage, comprising applying a program voltage having a first value to the gate, storing the first value in memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and in response to determining that the first read current is greater than the target read current, subjecting the memory cell to additional programming, the additional programming comprising retrieving the first value from the memory, determining a second value that is greater than the first value, and programming the selected non-volatile memory cell, comprising applying a program voltage having the second value to the gate.

Description

[Technical field]

[0001] (Priority Claim) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 196,130, filed June 2, 2021, and U.S. Patent Application No. 17 / 481,225, filed September 21, 2021.

[0002] FIELD OF THEINVENTION The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during read operations. [Background technology]

[0003] Non-volatile memory devices are well known in the art. For example, U.S. Patent No. 7,868,375 discloses a four-gate memory cell structure and is incorporated herein by reference for all purposes. Specifically, FIG. 1 of the present application illustrates a split-gate memory cell 10 having spaced apart source and drain regions 14 and 16 formed in a silicon semiconductor substrate 12. The source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other memory cells in the same row or column), and the drain region 16 is typically connected to a bit line by a bit line contact 28. A channel region 18 of the substrate is defined between the source region 14 and the drain region 16. A floating gate 20 is disposed vertically above and insulated from a first portion of the channel region 18 (and is partially vertically above and insulated from the source region 14) (as well as controlling the conductivity of the first portion of the channel region 18). A control gate 22 is disposed vertically above and insulated from the floating gate 20. A select gate 24 is disposed vertically above and insulated from (and controls the conductivity of) a second portion of the channel region 18. An erase gate 26 is disposed vertically above and insulated from the source region 14 and is laterally adjacent to the floating gate 20. A plurality of such memory cells can be arranged in rows and columns to form an array of memory cells.

[0004] Various combinations of voltages are applied to the control gate 22, select gate 24, erase gate 26, and / or source and drain regions 14 / 16 to program the split gate memory cell 10 (i.e., to inject electrons into the floating gate), erase the split gate memory cell 10 (i.e., to remove electrons from the floating gate), and read the split gate memory cell 10 (i.e., to measure or detect the conductivity of the channel region 18 to determine the programming state of the floating gate 20).

[0005] The split gate memory cell 10 can be operated in a digital manner, where the split gate memory cell 10 is set to one of only two possible states: a programmed state and an erased state. The split gate memory cell 10 is erased by applying a high positive voltage to the erase gate 26 and optionally a negative voltage to the control gate 22, inducing tunneling of electrons from the floating gate 20 to the erase gate 26 (leaving the floating gate 20 in a more positively charged state - the erased state). The split gate memory cell 10 can be programmed by applying positive voltages to the control gate 22, the erase gate 26, the select gate 24 and the source region 14, and applying a current to the drain region 16. Electrons then flow from the drain region 16 towards the source region 14 along the channel region 18, accelerating and heating some of the electrons, whereby some of the electrons are injected into the floating gate 20 by hot electron injection (leaving the floating gate 20 in a more negatively charged state - the programmed state). The split gate memory cell 10 can be read by applying a positive voltage to the select gate 24 (turning on the portion of the channel region 18 under the select gate 24) and on the drain region 16 (and optionally on the erase gate 26 and / or control gate 22) and sensing the flow of current through the channel region 18. If the floating gate 20 is positively charged (i.e., the split gate memory cell 10 is erased), the split gate memory cell 10 is on and current flows from the drain region 16 to the source region 14 (i.e., the split gate memory cell 10 is sensed to be in its erased "1" state based on the sensed current). If the floating gate 20 is negatively charged (i.e., the split gate memory cell 10 is programmed), the portion of the channel region 18 under the floating gate is off, thereby preventing significant current flow (i.e., the split gate memory cell 10 is sensed to be in its programmed "0" state based on no or minimal current flow).

[0006] Table 1 provides non-limiting examples of erase, program, and read voltages, where Vcc is the power supply voltage or another positive voltage, such as 2.5V. Table 1 [Table 1]

[0007] The split gate memory cell 10 can be manipulated in an analog fashion, alternating between changing the memory state (i.e., the amount of charge, such as the number of electrons on the floating gate 20) of the split gate memory cell 10 continuously anywhere from a fully erased state (minimum number of electrons on the floating gate 20) to a fully programmed state (maximum number of electrons on the floating gate 20), or only a portion of this range. This means that the split gate memory cell 10 storage is analog, allowing for very precise and individual adjustment of each split gate memory cell 10 in an array of split gate memory cells 10. Alternatively, the split gate memory cell 10 can be operated as a MLC (multi-level cell), configured to be programmed to one of many discrete values ​​(e.g., 16 or 64 different values). In the case of analog or MLC programming, the programming voltage is applied for a finite time, or as a series of pulses, until the desired programming state is achieved. In the case of multiple programming pulses, intervening read operations between the programming pulses can be used to determine whether the desired programming state has been achieved (in which case programming stops) or not (in which case programming continues).

[0008] Split gate memory cells 10 operated in an analog fashion or as MLC may be more susceptible to noise and read current instability that may adversely affect the accuracy of the split gate memory cell 10. One cause of read current instability in analog non-volatile memory devices is the capture and release of electrons by oxide traps located at and near the interface between the gate oxide and the memory cell channel region. The gate oxide is an insulating layer that separates the floating gate 20 from the region 18 of the channel substrate 12. When electrons are captured in the interface traps, they reduce the channel conductivity during a read operation, thus increasing the threshold voltage Vt of the split gate memory cell 10 (i.e., the minimum voltage of the control gate 22 required to turn on the channel region 18 of the split gate memory cell 10 to produce a predetermined target current, e.g., 1 μA). When the control gate voltage is equal to or greater than the threshold voltage Vt, a conductive path is created between the source region 14 and the drain region 16, allowing current of at least the predetermined target current to flow. When the control gate voltage is below the threshold voltage Vt, no conduction path is created and any current between the source region 14 and the drain region 16 is considered a sub-threshold or leakage current. Electrons trapped in the interface traps can be released from the interface traps, lowering the threshold current Vt of the memory cell and thus increasing the channel conductivity during a read operation. These single-electron events of electron capture and release by the interface traps appear as read current noise and are referred to as random telegraph noise (RTN). In general, the RTN caused by a single interface trap is characterized by two states: a lower Vt state (and higher read current state) when the electron is released from the interface and a higher Vt state (and lower read current state) when the electron is captured by the interface trap. As explained above, the instability of the split gate memory cell 10 during read can be characterized by the threshold voltage Vt, i.e., the control gate voltage corresponding to a given target current, or by the memory cell current under a given read voltage condition.Although the present embodiment is specifically described with reference to memory cell read instability as a threshold voltage, Vt, the use of memory cell current under a given read voltage is specifically contemplated.

[0009] RTN that occurs during programming can be addressed as part of the program operation. However, one problem with RTN is that after programming of the memory cell is complete, electron emission can occur that undesirably lowers the threshold voltage Vt of the memory cell (and thus undesirably increases the channel conductivity during a read operation). Thus, RTN must be addressed in analog and MLC non-volatile memory devices, such as, but not limited to, the split gate memory cell 10, to compensate for RTN after programming. Summary of the Invention

[0010] The aforementioned problems and needs are addressed by a memory device comprising a plurality of non-volatile memory cells, each of the memory cells comprising a first gate, and a control circuit. The control circuit comprises: programming a selected non-volatile memory cell of the plurality of non-volatile memory cells to an initial program state corresponding to a threshold voltage for a first gate of the selected non-volatile memory cell that meets or exceeds a target threshold voltage for a first gate of the selected non-volatile memory cell, the target threshold voltage for the first gate corresponding to a target read current, programming the selected non-volatile memory cell includes applying a program voltage having a first value to the first gate; storing the first value in a memory; reading the selected non-volatile memory cell in a first read operation using a read voltage applied to a first gate of the selected non-volatile memory cell to generate a first read current, the read voltage being less than a target threshold voltage for the first gate; and in response to determining that the first read current is greater than the target read current, subjecting the selected non-volatile memory cell to additional programming, the additional programming being configured to: Retrieving a first value from memory; determining a second value greater than the first value; and programming the selected non-volatile memory cell including applying a program voltage having a second value to the first gate.

[0011] 1. A method of programming selected non-volatile memory cells of a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells including a first gate, the method comprising: programming a selected non-volatile memory cell to an initial program state corresponding to meeting or exceeding a target threshold voltage for a first gate of the selected non-volatile memory cell, the target threshold voltage corresponding to a target read current, the programming including applying a program voltage having a first value to the first gate; storing the first value in a memory; reading the selected non-volatile memory cell in a first read operation using a read voltage less than a target threshold voltage applied to a first gate of the selected non-volatile memory cell to generate a first read current; and in response to determining that the first read current is greater than the target read current, subjecting the selected non-volatile memory cell to additional programming, the additional programming comprising: Retrieving a first value from a memory; determining a second value greater than the first value; and programming the selected non-volatile memory cell including applying a program voltage having a second value to the first gate.

[0012] Other objects and features will become apparent from a study of the specification, claims, and accompanying drawings.

[0013]

[0014]

[0015]

[0016] [Brief description of the drawings]

[0017] [Figure 1] 1 is a side cross-sectional view of a conventional memory cell. [Diagram 2] FIG. 1 illustrates components of a memory device. [Diagram 3] FIG. 2 is a flow diagram showing steps for programming a memory cell. [Figure 4] FIG. 1 is a flow diagram showing steps for post-program conditioning of memory cells. [Diagram 5] FIG. 13 is a flow diagram illustrating steps of a first alternative embodiment for post-program conditioning of memory cells. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] This embodiment illustrates a technique for compensating for RTN by performing a post-program adjustment to improve read operation accuracy after programming of a non-volatile memory cell, such as the split-gate memory cell 10 of FIG. 1, is completed.

[0019] The memory cell programming and post-program conditioning techniques are implemented as part of an arrangement of control circuitry 66 that controls various device elements for the memory array, which can be better understood from the exemplary memory device architecture illustrated in Figure 2. The memory device includes an array 50 of split-gate memory cells 10, which can be isolated into two separate planes (Plane A 52a and Plane B 52b). The split-gate memory cells 10 can be of the type shown in Figure 1 and arranged in multiple rows and columns in a semiconductor substrate 12, and thus formed on a single chip. Adjacent to the array 50 of split gate memory cells 10 are address decoders (e.g., XDEC 54), source line drivers (e.g., SLDRV 56), column decoders (e.g., YMUX 58), high voltage row decoders (e.g., HVDEC 60), and bit line controllers (e.g., BLINHCTL 62), which are used to decode addresses and provide various voltages to various gates and regions of the split gate memory cells 10 during read, program, and erase operations on selected split gate memory cells 10 of the array 50. The column decoders 58 include sense amplifiers that include circuitry for measuring current on the bit lines during read operations. The control circuitry 66 is configured to control the various device elements to perform each operation (program, erase, read) on selected split gate memory cells 10 of the array 50, as described herein. The charge pump CHRGPMP 64, under the control of the control circuitry 66, provides the various voltages used to read, program, and erase selected split gate memory cells 10 of the array 50. The control circuitry 66 is configured to operate the memory device to program, erase, and read selected split-gate memory cells 10 of the array 50. As part of these operations, the control circuitry 66 may be provided with access to input data, which is the data to be programmed into selected split-gate memory cells 10 of the array 50, along with program, erase, and read commands provided on the same or different lines.Data read from the array 50, i.e., from selected split-gate memory cells 10 of the array 50, is provided as outgoing data. The control circuit 66 includes, or is provided with access to, a separate memory, such as a random access memory (RAM) 70 for storing voltage values, as will be explained further below.

[0020] The post-program conditioning technique involves the control circuitry 66 performing an initial programming of memory cells, followed by performing post-program conditioning on memory cells that exhibit unacceptable levels of read current instability after the initial programming. Memory cell programming is described first, followed by post-program conditioning. Thus, the control circuitry 66 may be loaded with and configured by software, i.e., non-transitory electronically readable instructions, or firmware, to perform the methods described below in connection with Figures 4 and 5. The control circuitry 66 may be implemented by a microcontroller, a dedicated circuit, a processor, or a combination thereof.

[0021] Memory cell programming involves programming a selected memory cell to an initial programming state using a programming voltage pulse to determine the threshold voltage parameter of the memory cell (i.e., a target current I target The threshold voltage parameter is a control gate threshold voltage Vtcg, which is the threshold voltage of the memory cell as seen by the control gate 22 (also referred to herein as the first gate). Specifically, the control gate threshold voltage Vtcg determines the target current (I) required for the channel region 18 to become a conductive path and therefore for the memory cell to be considered turned on when the read potential of the read operation is applied to the select gate 24 and drain region 16. targetVtcg is the voltage applied to the control gate 22 that results in a read current through the channel of a predetermined level of source / drain current, also known as current drain (Vtcg) (e.g., 1 μA). The control gate threshold voltage Vtcg varies as a function of the programming state of the split gate memory cell 10, but it is desirable for the control gate threshold voltage Vtcg to vary over time by less than a predetermined amount once the split gate memory cell 10 is programmed to a particular programming state.

[0022] Initial memory cell programming is illustrated as steps 1-4 in FIG. 3 and involves programming a selected split-gate memory cell 10 to a target control gate threshold voltage Vtcg associated with that particular desired initial programming state. target The technique begins in step 1 with the control circuit 66 programming a selected split-gate memory cell 10 of the array 50. As explained above, this programming step involves applying a programming voltage to the selected split-gate memory cell 10 for a limited time (i.e., at least one pulse) resulting in the injection of electrons into the floating gate 20. In step 1 programming, the voltage Vcg applied to the control gate 22 is the control gate program voltage Vcg program In step 2, a read operation is performed that includes applying a read voltage, e.g., from the SLDRV 56, to the selected split gate memory cell 10 and measuring the current Iread through the channel region 18 of the selected split gate memory cell 10 using the column decoder 58 and bit line controller 62. In this read operation, the voltage Vcg applied to the control gate 22 has a value equal to the target control gate threshold voltage Vtcg. target In step 3, the control gate threshold voltage Vtcg of the memory cell is set to the target control gate threshold voltage Vtcg from the read operation in step 2. target (i.e., the read current I measured by the column decoder 58 and the bit line controller 62)read is the target current I target where the target current I target Equal to I read is the target control gate threshold voltage Vtcg target The read current I read is also referred to herein as the second read current. If the determination is no (i.e., the control gate threshold voltage Vtcg is less than the target control gate threshold voltage Vtcg target (not less than or equal to) and in step 4, the control gate program voltage Vcg used for programming program is increased relative to that used in the previous step 1 programming of the memory cell, and then the increased control gate program voltage Vcg program Step 1 is repeated using the target control gate threshold voltage Vtcg of the memory cell. target has been reached or exceeded (i.e., the read current I read is the target current I target Steps 1-4 are repeated in sequence by control circuit 66 until it is determined that the threshold voltage Vtcg is equal to or lower than the desired initial programming state. At that point, the memory cell is programmed to its desired initial programming state (i.e., equal to or lower than its target control gate threshold voltage Vtcg). target It is at this point that traditional programming usually ends.

[0023] However, if a programmed memory cell exhibits RTN after programming is complete, the electrons trapped in the interface traps contribute to the measured control gate threshold voltage Vtcg of the memory cell as part of the programming. If / when electrons are released from the interface traps after programming is completed, the control gate threshold voltage Vtcg is equal to or greater than the target control gate threshold voltage Vtcg. target ΔVtcg max where ΔVtcg maxis the maximum allowable read error with respect to the control gate threshold voltage Vtcg fluctuation. max A control gate threshold voltage drop exceeding Vcg is considered an unacceptable error in a subsequent read operation. Thus, post-program conditioning begins at step 5 of FIG. 4 and involves removing the maximum control gate program voltage Vcg used in programming the memory cell. program The value (also referred to herein as the first value) is stored in memory (i.e., the last control gate program voltage Vcg used in programming the particular split-gate memory cell). program value, in the last iteration of step 4, the initial control gate program voltage Vcg from step 1 program The control gate threshold voltage Vtcg of the memory cell is set to the target control gate threshold voltage Vtcg target (i.e., the read current I read is the target current I target In this case, the initial control gate program voltage Veg program is the maximum control gate program voltage Vcg program In one embodiment, if post-programming adjustment is performed immediately after analog programming, the maximum Vcg program The memory used to store the value is RAM 70. However, if the user intends to perform a post-program adjustment sometime after analog programming, the maximum control gate program voltage Vcg may instead be program The value can be stored in a file (e.g., in non-volatile storage accessible by control circuit 66) to preserve the data for a longer period. Maximum Control Gate Program Voltage Vcg program Storing the value is performed by control circuitry 66 after the split-gate memory cell 10 is found to be programmed to its desired initial program state, as described above in connection with step 3.

[0024] In step 6, the split gate memory cell 10 is programmed to have the target control gate threshold voltage Vtcg used in step 2.target The memory cell is read using a smaller control gate voltage Vcg (also referred to herein as a first read operation). Specifically, the control gate voltage Vcg used for this read operation is Vtcg target -ΔV tcg where ΔV tcg is the maximum allowable deviation of the control gate threshold voltage (ΔVtcg max ), but need not be. As a non-limiting example, AVtcg can be, for example, 20 mV. In step 7, the read current I read is the target read current I target It is determined whether the read current I read is also referred to herein as the first read current. If the memory cell does not exhibit unacceptable RTN after programming, ΔV tcg A small decrease in I target , or even lower, and the determination in step 7 should be no. In that case, the memory cell can be considered properly programmed and no post-program conditioning is required. However, as shown in optional step 8, steps 6 and 7 can be repeated one or more times (wherein the repeated read operation is also referred to herein as a second read operation), so that a positive determination in step 7 subjects the memory cell to another programming round, as described below, regardless of how many previous negative determinations there were. Repeating steps 6 and 7 even if the result of step 7 is initially negative is advantageous because electrons are not necessarily released from the traps before the first read, but may be released from the traps after the first read, and a yes, or positive determination in step 7 may occur in a subsequent read operation if there is electron release after the first read operation.

[0025] If a memory cell exhibits unacceptable RTN and there is interface trapped electron emission before or during this read operation, the control gate threshold voltage Vtcg of the memory cell drops, resulting in a read current I read The current rises to I target If so, the determination in step 7 is yes, i.e., affirmative, and the selected split-gate memory cell 10 is subjected to another programming round beginning in step 9, where the maximum control gate program voltage Vcg stored in step 5, i.e., in the RAM 70 (or other memory) is exceeded. program The value is retrieved. The retrieved control gate program voltage Vcg program The value is increased (see step 10) in preparation for use in programming (e.g., the increased value of the control gate program voltage Vcg, also referred to herein as the second value). program ) by determining the increased control gate program voltage Vcg program The value is stored in RAM 70 (or other memory) (see step 11). The memory cell is then programmed with an increased control gate program voltage Vcg in step 12 (similar to step 1 described above). programThe memory cell is then programmed with the value. The process then returns to step 6, where the memory cell is once again read as described above with respect to step 6, followed by the determination of step 7 as described above. If the subsequent determination at step 7 is yes, steps 9-12 are performed again, followed by another read at step 6 and the determination at step 7. If the subsequent determination at step 7 is no, the post-program conditioning can end, or steps 6 and 7 can be repeated one or more times, as shown in optional step 8, even if steps 9-12 have been performed one or more times. There is no limit to the number of read and determine operations (steps 6 and 7), and the number of programming rounds (steps 9-12). The number of times steps 6 and 7 and 9-12 are repeated can be user-defined by considering the desired programming time. The post-program conditioning process can also be repeated at a time after the previous instance of post-program conditioning, where an increased control gate program voltage Vcg program The values ​​may be stored in a more permanent memory, such as a hard drive or other non-volatile storage accessible by control circuitry 66 for longer term storage.

[0026] An advantage of the technique described above is that if a memory cell exhibits unacceptable RTN after programming is initially completed, the memory cell will be programmed deeper (i.e., will exhibit a higher control gate threshold voltage Vtcg) than it would otherwise be, and the control gate threshold voltage Vtcg will be lower than the target control gate threshold voltage Vtcg. target By utilizing the techniques described above, even if electron emission occurs, the control gate threshold voltage Vtcg of the split gate memory cell 10 does not vary an undesired amount from the target control gate threshold voltage Vtcg. target , and is less likely to drop by an amount that exceeds the allowable level ΔVtcg. This is because the split gate memory cell 10 is targetThe higher and deeper it is programmed, the more accurately future read operations will reflect the desired programming state of the memory cell within acceptable levels of ΔVtcg variation.

[0027] 5 illustrates a first alternative embodiment, which is the same way as described above and depicted in FIGS. 3 and 4, except that step 6A is added before step 6, and after step 12, the process returns to step 6A instead of step 6, and will not be described again. Specifically, before the memory cell is read in step 6, a negative voltage, provided by, for example, the SLDRV 56, under the control of the control circuit 66 is applied to the memory cell (e.g., to any non-floating gates of the memory cell, such as the control gate 22, the erase gate 26, and / or the select gate 24), the negative voltage being defined with respect to the potential of the substrate 12. This negative voltage applied to the split gate memory cell 10 induces a field stress in the gate oxide of the split gate memory cell 10, stimulating the detrapping (ejection) of electrons from oxide traps at and near the interface. In one embodiment, the negative voltage is applied to the control gate 22, but may additionally or alternatively be applied to any gate or terminal capacitively coupled to the floating gate 20. Thus, for split-gate memory cells 10 having oxide traps that give rise to RTN, the negative voltage helps stimulate detrapping of electrons, setting the control gate threshold voltage Vtcg to a lower threshold voltage Vt state, and increasing the likelihood that the determination of step 7 will be positive (and thus the memory cell will be subjected to additional programming). Because RTN has erratic behavior, defective memory cells may remain in one control gate threshold voltage Vtcg state even during the read operation of step 6, and thus not be properly identified for additional programming in steps 9-12. Thus, application of a negative voltage (e.g., −1V to −7V) prior to the read operation of step 6 may stimulate memory cells with RTN to assume a lower control gate threshold voltage Vtcg state, thereby being identified in step 7 for additional programming, enhancing programming efficiency and accuracy. There is a characteristic time during which memory cells maintain their control gate threshold voltage Vtcg state acquired under the applied voltage stress after its removal.Therefore, the delay between the application of the negative voltage in step 6A and the read operation in step 6 is, in one embodiment, not longer than a typical electron capture and release time (e.g., 100 ms at room temperature), otherwise applying the negative voltage in step 6A before the read operation in step 6 may not be very efficient.

[0028] It will be understood that the above is not limited to the embodiments described and illustrated herein above, but encompasses any variations falling within the scope of any claim. For example, any reference to an embodiment or the present invention herein is not intended to limit the scope of the claims or the terms of the claims, but instead merely relates to one or more features that may be covered by one or more of the claims. The material, process, and numerical example described above are merely examples and should not be considered as limiting the scope of the claims. Furthermore, as will be apparent from the claims and the specification, unless otherwise specified, not all method steps need to be performed in the exact order illustrated or claimed. An example of the threshold voltage Vtcg used in the techniques described above is the threshold voltage of the memory cell as seen from the control gate 22. However, the techniques described above can be implemented with respect to the threshold voltage Vt as seen from any one or more gates in the non-floating split gate memory cell 10. Additionally, the above description can be implemented in an array of memory cells having fewer gates than those of FIG. 1 (e.g., no control gates combined with erase gates and / or select gates).

Claims

1. 1. A memory device comprising: a plurality of non-volatile memory cells, each having a first gate; A control circuit, the control circuit comprising: programming a selected non-volatile memory cell of the plurality of non-volatile memory cells to an initial program state corresponding to a threshold voltage for the first gate of the selected non-volatile memory cell that meets or exceeds a target threshold voltage for the first gate of the selected non-volatile memory cell, the target threshold voltage for the first gate corresponding to a target read current, and the programming of the selected non-volatile memory cell includes applying a program voltage having a first value to the first gate; storing the first value in a memory; reading the selected non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the selected non-volatile memory cell to generate a first read current, the read voltage being less than a target threshold voltage for the first gate; and in response to determining that the first read current is greater than the target read current, subjecting the selected non-volatile memory cell to additional programming, the additional programming comprising: Retrieving the first value from the memory; and determining a second value greater than the first value; and programming the selected non-volatile memory cell including applying a program voltage having the second value to the first gate.

2. The memory device of claim 1 , wherein the control circuitry is configured to store the second value in the memory.

3. 1. A memory device, comprising: spaced apart source and drain regions formed in a semiconductor substrate, the source and drain regions having a channel region of the substrate extending therebetween; a floating gate disposed vertically above and insulated from a first portion of the channel region; a select gate disposed vertically above and insulated from a second portion of the channel region; 2. The memory device of claim 1, wherein for each of said plurality of non-volatile memory cells, said first gate is disposed vertically above and insulated from said floating gate.

4. Each of the plurality of non-volatile memory cells 4. The memory device of claim 3, further comprising an erase gate disposed above and insulated from said source region.

5. A memory device, the control circuit comprising: applying at least one first pulse of a programming voltage to the selected non-volatile memory cell; reading the selected non-volatile memory cell using a read voltage applied to the first gate of the selected non-volatile memory cell to generate a second read current, the read voltage being equal to the target threshold voltage for the first gate; 2. The memory device of claim 1, further configured to program the selected non-volatile memory cells to the initial programmed state by: applying at least one second pulse of a programming voltage to the selected non-volatile memory cells in response to determining that the second read current is not less than or equal to the target read current.

6. 6. The memory device of claim 5, wherein the at least one first pulse of programming voltage comprises a first program voltage applied to the first gate, and the at least one second pulse of programming voltage comprises a second program voltage applied to the first gate that is greater than the first program voltage.

7. A memory device, the control circuit comprising: reading the selected non-volatile memory cell in a second read operation performed in response to determining in the first read operation that the first read current is not greater than the target read current using a read voltage less than the target threshold voltage applied to the first gate of the selected non-volatile memory cell to generate a second read current; in response to determining that the second read current is greater than the target read current, subjecting the selected non-volatile memory cell to the additional programming; 2. The memory device of claim 1, configured to: not subject the selected non-volatile memory cell to the additional programming in response to determining that the second read current is not greater than the target read current.

8. 2. The memory device of claim 1, wherein the control circuitry is configured to apply a negative voltage to a non-floating gate of the selected non-volatile memory cell after the programming of the selected non-volatile memory cell to an initial programmed state and before the first read operation.

9. 2. The memory device of claim 1, wherein the control circuitry is configured to apply a negative voltage to the first gate of the selected non-volatile memory cell after the programming of the selected non-volatile memory cell to the initial programmed state and before the first read operation.

10. A memory device, the control circuit comprising: applying a negative voltage to the first gate of the selected non-volatile memory cell after the programming of the selected non-volatile memory cell to the initial programmed state and before the first read operation; 8. The memory device of claim 7, configured to: apply a negative voltage to the first gate of the selected non-volatile memory cell during the first read operation after determining that the first read current is not greater than the target read current and before the second read operation.

11. 1. A method of programming selected non-volatile memory cells of a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells including a first gate, the method comprising: programming the selected non-volatile memory cell to an initial program state corresponding to meeting or exceeding a target threshold voltage for the first gate of the selected non-volatile memory cell, the target threshold voltage corresponding to a target read current, the programming comprising applying a program voltage having a first value to the first gate; storing the first value in a memory; reading the selected non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the selected non-volatile memory cell, the read voltage being less than the target threshold voltage to generate a first read current; and in response to determining that the first read current is greater than the target read current, subjecting the selected non-volatile memory cell to additional programming, the additional programming comprising: retrieving the first value from the memory; determining a second value greater than the first value; and programming the selected non-volatile memory cell including applying a program voltage having the second value to the first gate.

12. The method of claim 11 , further comprising storing the second value in the memory.

13. Each of the plurality of non-volatile memory cells spaced apart source and drain regions formed in a semiconductor substrate, the source and drain regions having a channel region of the substrate extending therebetween; a floating gate disposed vertically above and insulated from a first portion of the channel region; a select gate disposed vertically above and insulated from a second portion of the channel region; 12. The method of claim 11, wherein for each of the plurality of non-volatile memory cells, the first gate is disposed vertically above and insulated from the floating gate.

14. Each of the plurality of non-volatile memory cells The method of claim 13 , further comprising an erase gate disposed above and insulated from the source region.

15. 11. A method, comprising: programming the selected non-volatile memory cells to the initial programmed state; applying at least one first pulse of a programming voltage to the selected non-volatile memory cell; reading the selected non-volatile memory cell using a read voltage applied to the first gate of the selected non-volatile memory cell to generate a second read current, the read voltage being equal to the target threshold voltage; 12. The method of claim 11, further comprising: in response to determining that the second read current is greater than the target read current, applying at least one second pulse of a programming voltage to the selected non-volatile memory cell.

16. 16. The method of claim 15, wherein the at least one first pulse of programming voltage comprises a first program voltage applied to the first gate, and the at least one second pulse of programming voltage comprises a second program voltage applied to the first gate that is greater than the first program voltage.

17. 11. The method, comprising: reading the selected non-volatile memory cell in a second read operation performed in response to determining in the first read operation that the first read current is not greater than the target read current, the second read operation using a read voltage applied to the first gate of the selected non-volatile memory cell that is less than the target threshold voltage to generate a second read current; in response to determining that the second read current is greater than the target read current, subjecting the selected non-volatile memory cell to the additional programming; 12. The method of claim 11, further comprising: in response to determining that the second read current is not greater than the target read current, not subjecting the selected non-volatile memory cell to the additional programming.

18. 12. The method of claim 11, further comprising applying a negative voltage to a non-floating gate of the selected non-volatile memory cell after the programming of the selected non-volatile memory cell to the initial programmed state and before the first read operation.

19. 12. The method of claim 11, further comprising applying a negative voltage to the first gate of the selected non-volatile memory cell after the programming of the selected non-volatile memory cell to the initial programmed state and before the first read operation.

20. applying a negative voltage to the first gate of the selected non-volatile memory cell after the programming of the selected non-volatile memory cell to the initial programmed state and before the first read operation; 18. The method of claim 17, further comprising: applying a negative voltage to the first gate of the selected non-volatile memory cell after determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

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