Semiconductor Device

Abstract

To suppress a temperature improvement of a center part of a semiconductor substrate having anisotropy in thermal conductivity.SOLUTION: A semiconductor device includes a semiconductor substrate having a rectangular form with a side extended along a first direction and a side extended along a second direction in view along a thickness direction. A thermal conductivity K1 in the first direction of the semiconductor substrate is different from a thermal conductivity K2 in the second direction of the semiconductor substrate. A relationship between a length L1 in the first direction of the semiconductor substrate and a length L2 in the second direction of the semiconductor substrate of L1 / L2=(K1 / K2)0.5 is satisfied within a range of an error of -5% to +5%.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] During use of a semiconductor device, the semiconductor substrate generates heat. The center of the semiconductor substrate is more likely to become hotter than the outer periphery of the semiconductor substrate. Patent Document 1 discloses a technology for making the density of cells through which current flows lower in the center of the semiconductor substrate than in the outer periphery of the semiconductor substrate. This technology makes it possible to suppress the temperature rise in the center of the semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-027440 A Summary of the Invention [Problem to be solved by the invention]

[0004] The thermal conductivity of a semiconductor substrate may be anisotropic. In such a semiconductor substrate, if the shape of the semiconductor substrate does not match the anisotropy of the thermal conductivity, a temperature rise may easily occur in the center of the semiconductor substrate. In this specification, a technology is proposed for suppressing a temperature rise in the center of a semiconductor substrate having anisotropic thermal conductivity. [Means for solving the problem]

[0005] The semiconductor device disclosed in this specification has a semiconductor substrate having a rectangular shape with sides extending in a first direction and sides extending in a second direction when viewed along the thickness direction. A thermal conductivity K1 of the semiconductor substrate in the first direction is different from a thermal conductivity K2 of the semiconductor substrate in the second direction. A length L1 of the semiconductor substrate in the first direction and a length L2 of the semiconductor substrate in the second direction are

number

[0006] In this semiconductor device, the thermal resistance of a path from the center of the semiconductor substrate to an end of the semiconductor substrate along the first direction is substantially equal to the thermal resistance of a path from the center of the semiconductor substrate to the end of the semiconductor substrate along the second direction. Therefore, heat can be efficiently dissipated from the center of the semiconductor substrate in both the first and second directions, and a temperature rise in the center of the semiconductor substrate can be suppressed. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a plan view of a semiconductor chip included in the semiconductor device of the first embodiment. [Diagram 2] 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment taken along the

[0010] direction. [Diagram 3] Graph showing the relationship between the thermal conductivity of β-type gallium oxide and temperature T. [Figure 4] FIG. 11 is a plan view of a semiconductor chip included in a semiconductor device according to a second embodiment. [Diagram 5] FIG. 11 is a longitudinal sectional view of a semiconductor device according to a second embodiment taken along the

[0010] direction. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In one example of the semiconductor device disclosed in the present specification, the semiconductor substrate may be made of an oxide semiconductor. The semiconductor substrate may be made of gallium oxide. The semiconductor substrate may be made of β-type gallium oxide. In this case, the first direction may be a

[0010] direction.

[0009] The semiconductor device disclosed in this specification as an example may further include an upper electrode provided on an upper surface of the semiconductor substrate, and a lower electrode provided on a lower surface of the semiconductor substrate. Also, a current may flow between the upper electrode and the lower electrode via the semiconductor substrate. In this case, a heat sink may be joined to the lower electrode. Also, the heat sink may have isotropic thermal conduction characteristics. Also, a metal block may be joined to the upper electrode. Also, the metal block may have isotropic thermal conduction characteristics.

[0010] The semiconductor device according to the present invention may further include a temperature detection element for detecting a temperature of the semiconductor substrate, the temperature detection element being provided at a central portion of an upper surface of the semiconductor substrate. EXAMPLES

[0011] 1 and 2, a semiconductor device 10 of the first embodiment includes a semiconductor chip 12, a metal block 30, and a heat sink 40. The metal block 30 is fixed to the upper surface of the semiconductor chip 12. The heat sink 40 is fixed to the lower surface of the semiconductor chip 12. In the first embodiment, the semiconductor chip 12 is a Schottky barrier diode.

[0012] The semiconductor chip 12 has a semiconductor substrate 22, an upper electrode 26, and a lower electrode 28. The semiconductor substrate 22 is made of β-type gallium oxide. The upper surface 22a of the semiconductor substrate 22 is made of the (001) plane of β-type gallium oxide. That is, the thickness direction of the semiconductor substrate 22 is parallel to the

[0001] direction of β-type gallium oxide. Hereinafter, the thickness of the semiconductor substrate 22 is referred to as thickness D. When the semiconductor substrate 22 is viewed along the thickness direction as shown in FIG. 1, the semiconductor substrate 22 has a rectangular shape that is long in the horizontal direction. When the semiconductor substrate 22 is viewed from above, the long side 23 is parallel to the

[0010] direction of β-type gallium oxide, and the short side 24 is parallel to the

[0100] direction of β-type gallium oxide. Hereinafter, the length of the long side 23 (i.e., the length in the

[0010] direction of the semiconductor substrate 22) will be referred to as length L1, and the length of the short side 24 (i.e., the length in the

[0100] direction of the semiconductor substrate 22) will be referred to as length L2.

[0013] The upper electrode 26 covers the upper surface 22a of the semiconductor substrate 22. The upper electrode 26 is in Schottky contact with the semiconductor substrate 22. The lower electrode 28 covers the lower surface 22b of the semiconductor substrate 22. The lower electrode 28 is in ohmic contact with the semiconductor substrate 22. Thus, a Schottky barrier diode is formed by the semiconductor substrate 22, the upper electrode 26, and the lower electrode 28. When the potential of the upper electrode 26 is higher than the potential of the lower electrode 28, a current flows from the upper electrode 26 to the lower electrode 28 through the inside of the semiconductor substrate 22. When the potential of the upper electrode 26 is lower than the potential of the lower electrode 28, the current flowing through the semiconductor substrate 22 stops.

[0014] A metal block 30 is joined to the upper electrode 26 via solder or the like. Although not shown, a heat sink is joined to the upper surface of the metal block 30 via an insulating layer or the like. The metal block 30 functions as a wiring member that passes current to the semiconductor chip 12, and also functions as a heat sink that dissipates heat from the semiconductor chip 12. The metal block 30 is made of a metal such as copper. The metal block 30 has isotropic heat conduction characteristics. In other words, the thermal conductivity of the metal block 30 is the same in all directions.

[0015] A heat sink 40 is joined to the lower electrode 28 via solder or the like. The heat sink 40 functions as a wiring member that passes current to the semiconductor chip 12, and also functions as a heat sink member that dissipates heat from the semiconductor chip 12. The heat sink 40 is made of a metal such as aluminum. The heat sink 40 has isotropic heat conduction characteristics. In other words, the thermal conductivity of the heat sink 40 is the same in all directions.

[0016] The semiconductor substrate 22 made of β-type gallium oxide has anisotropy in thermal conductivity. That is, the thermal conductivity of β-type gallium oxide varies depending on the crystal direction. FIG. 3 shows the relationship between the thermal conductivity of β-type gallium oxide and the temperature T for each crystal direction. As shown in FIG. 3, in β-type gallium oxide, the thermal conductivity in the

[0010] direction is higher than the thermal conductivity in other directions. As described above, when the semiconductor substrate 22 is viewed along the thickness direction, the long side 23 is parallel to the

[0010] direction, and the short side 24 is parallel to the

[0100] direction. Therefore, the thermal conductivity K1 of the semiconductor substrate 22 in the direction along the long side 23 is higher than the thermal conductivity K2 of the semiconductor substrate 22 in the direction along the short side 24. For example, the thermal conductivity K1 in the

[0010] direction at T = 150°C is 14.4 W / mK, and the thermal conductivity K2 in the

[0100] direction at 150°C is 7.2 W / mK.

[0017] The lengths L1 and L2 of the semiconductor substrate 22 satisfy the following formula 1 with an error ranging from −5% to +5%.

number

[0018] Satisfying formula 1 within the error range of -5% to +5% is equivalent to satisfying formula 2 below.

number

[0019] When the Schottky barrier diode is turned on and a current flows through the semiconductor substrate 22, the semiconductor substrate 22 generates heat. Since the semiconductor substrate 22 is joined to the metal block 30 and the heat sink 40 over a wide range of the upper surface 22a and the lower surface 22b, a current flows relatively evenly throughout the semiconductor substrate 22. Also, since the semiconductor substrate 22 is joined to the metal block 30 and the heat sink 40 over a wide range of the upper surface 22a and the lower surface 22b, heat is dissipated approximately evenly throughout the semiconductor substrate 22 by the metal block 30 and the heat sink 40. When a current flows evenly through the semiconductor substrate 22 and heat is dissipated evenly in the semiconductor substrate 22, the center 22c of the semiconductor substrate 22 becomes the hottest part of the semiconductor substrate 22. That is, the heat generated in the semiconductor substrate 22 also moves laterally (i.e., in a direction perpendicular to the thickness direction) inside the semiconductor substrate 22. The center 22c of the semiconductor substrate 22 is easily heated because it is far from the outer peripheral end face of the semiconductor substrate 22. The Schottky barrier diode is controlled so that the temperature of the central portion 22c of the semiconductor substrate 22 does not exceed a reference value (i.e., the maximum operating temperature set for the Schottky barrier diode (e.g., 150° C.)). For example, the temperature of the central portion 22c is predicted based on the operating conditions of the Schottky barrier diode, and the current value and current flow time of the Schottky barrier diode are limited so that the temperature of the central portion 22c does not exceed the reference value. In the semiconductor device 10 of the first embodiment, the shape of the semiconductor substrate 22 satisfies the above formula 1, and therefore a temperature rise in the central portion 22c is suppressed. Suppression of the temperature rise in the central portion 22c will be described in detail below.

[0020] The heat dissipation path 101 in FIG. 1 indicates a heat dissipation path that extends from the center 22c along the

[0010] direction to the short side 24 (i.e., the outer peripheral end surface of the semiconductor substrate 22). The heat dissipation path 102 in FIG. 1 indicates a heat dissipation path that extends from the center 22c along the

[0100] direction to the long side 23 (i.e., the outer peripheral end surface of the semiconductor substrate 22). Generally, the thermal resistance R of a heat dissipation path is determined by the formula R=Lr / (S·K). In this formula, the variable Lr is the length of the heat dissipation path, the variable S is the cross-sectional area of ​​the heat dissipation path, and the variable K is the thermal conductivity of the heat dissipation path. The cross-sectional area S1 of the heat dissipation path 101 is the product of the length L2 and the thickness D. The length Lr1 of the heat dissipation path 101 is half the length L1. Therefore, the thermal resistance R1 of the heat dissipation path 101 satisfies the relationship R1=Lr1 / (S1·K1)=L1 / (2·L2·D·K1). The cross-sectional area S2 of the heat dissipation path 102 is the product of the length L1 and the thickness D. Furthermore, the length Lr2 of the heat dissipation path 102 is half the length L2. Therefore, the thermal resistance R2 of the heat dissipation path 102 satisfies the relationship R2=Lr2 / (S2·K2)=L2 / (2·L1·D·K2). When the thermal resistance R1 of the heat dissipation path 101 and the thermal resistance R2 of the heat dissipation path 102 are equal, the relationship L1 / (2·L2·D·K1)=L2 / (2·L1·D·K2) is satisfied. This formula is equal to the above formula 1. Therefore, satisfying the above formula 1 means that the thermal resistance R1 of the heat dissipation path 101 and the thermal resistance R2 of the heat dissipation path 102 are equal to each other.

[0021] As described above, the lengths L1 and L2 of the semiconductor substrate 22 satisfy the above formula 1 with an error within the range of −5% to +5%. Therefore, in the semiconductor substrate 22, the thermal resistance R1 of the heat dissipation path 101 and the thermal resistance R2 of the heat dissipation path 102 are approximately equal. Therefore, when the Schottky barrier diode operates, heat is dissipated approximately evenly from the center portion 22c by the heat dissipation paths 101 and 102. Therefore, the center portion 22c efficiently dissipates heat, and a temperature rise in the center portion 22c is suppressed. Therefore, the semiconductor device 10 of the first embodiment can continue to operate even under relatively severe temperature conditions.

[0022] As shown in Fig. 3, the thermal conductivity varies depending on the temperature of the semiconductor substrate. Thermal conductivities K1 and K2 in the above formula 1 can be those within the operating temperature range of the semiconductor device. For example, the thermal conductivity at the maximum operating temperature of the semiconductor device (e.g., 150°C) can be used as the thermal conductivities K1 and K2. EXAMPLES

[0023] 4 and 5 show a semiconductor device 110 of Example 2. In addition, in FIG. 4 and 5, the same reference numerals as those in Example 1 are given to the parts corresponding to the parts of the semiconductor device 10 of Example 1. In the semiconductor device 110 of Example 2, the semiconductor chip 12 is a MOSFET (metal oxide semiconductor field effect transistor). That is, a MOSFET structure having a gate electrode, a gate insulating film, a source layer, a body layer, a drain layer, and the like is formed inside the semiconductor substrate 22. In Example 2, the upper electrode 26 is the source electrode of the MOSFET, and the lower electrode 28 is the drain electrode of the MOSFET. The upper electrode 26 is connected to the metal block 30, and the lower electrode 28 is connected to the heat sink 40. In addition, in Example 2, the metal block 30 is arranged so as to cover the temperature detection element 90 described later.

[0024] In the second embodiment, a temperature detection element 90 is provided on the upper surface 22a of the semiconductor substrate 22. The temperature detection element 90 is a pn diode configured of a polysilicon film provided on the upper surface 22a of the semiconductor substrate 22. The temperature detection element 90 is insulated from the semiconductor substrate 22 by an interlayer insulating film (not shown). The upper surface electrode 26 is provided on the upper surface 22a so as to avoid the temperature detection element 90 and its wirings 91, 92. In addition, signal electrodes 27a to 27c are provided on the upper surface 22a of the semiconductor substrate 22. The signal electrodes 27a to 27c are disposed next to the upper surface electrode 26. Each of the signal electrodes 27a to 27c is connected to a terminal (not shown) by a wire 94.

[0025] The signal electrode 27c is connected to the gate electrode (not shown) of the MOSFET. The MOSFET is used in a state where a higher potential is applied to the bottom electrode 28 (i.e., drain electrode) than to the top electrode 26 (i.e., source electrode). When a predetermined potential is applied to the signal electrode 27c (i.e., gate electrode), the MOSFET turns on and a current flows inside the semiconductor substrate 22 from the bottom electrode 28 to the top electrode 26. When the potential of the signal electrode 27c drops, the MOSFET turns off and the current stops.

[0026] The signal electrode 27a is connected to the temperature detection element 90 by a wiring 91. The signal electrode 27b is connected to the temperature detection element 90 by a wiring 92. A constant current can be passed through the temperature detection element 90 (i.e., a pn diode) via the signal electrodes 27a and 27b. When the temperature of the temperature detection element 90 changes, the forward voltage drop generated in the temperature detection element 90 changes. Therefore, the temperature of the temperature detection element 90 can be detected by measuring the voltage between the signal electrodes 27a and 27b. Since the temperature detection element 90 is provided at the center of the upper surface 22a of the semiconductor substrate 22, the temperature detection element 90 can detect the temperature of the central portion 22c of the semiconductor substrate 22.

[0027] In Example 2, the semiconductor substrate 22 is also made of β-type gallium oxide. In Example 2, similar to Example 1, the long side 23 is parallel to the

[0010] direction and the short side 24 is parallel to the

[0100] direction. In Example 2, the lengths L1 and L2 of the semiconductor substrate 22 also satisfy the above formula 1 with an error within the range of −5% to +5%.

[0028] In the second embodiment, the semiconductor substrate 22 generates heat during operation of the MOSFET. Also, during operation of the MOSFET, the temperature of the central portion 22c of the semiconductor substrate 22 is detected by the temperature detection element 90. The MOSFET 90 is controlled so that the temperature of the central portion 22c detected by the temperature detection element 90 does not exceed a reference value (for example, a maximum operating temperature set for the MOSFET). For example, when the temperature detected by the temperature detection element 90 exceeds the reference value, the current flowing through the MOSFET may be suppressed. Also, for example, when the temperature detected by the temperature detection element 90 exceeds the reference value, the operating time of the MOSFET may be limited. In the second embodiment, as in the first embodiment, the lengths L1 and L2 of the semiconductor substrate 22 satisfy the formula 1 within an error range of −5% to +5%, so that heat is efficiently released from the central portion 22c of the semiconductor substrate 22. Therefore, the temperature rise of the central portion 22c of the semiconductor substrate 22 is suppressed, and the temperature rise detected by the temperature detection element 90 is suppressed. Therefore, the MOSFET can continue to operate even under severe temperature conditions.

[0029] In the second embodiment, the location of the highest temperature in the semiconductor substrate 22 may be shifted from the central portion 22c depending on the layout of the MOSFETs in the semiconductor substrate 22. In this case, the position of the temperature detection element 90 may be shifted from the central portion 22c.

[0030] In the above-mentioned Examples 1 and 2, the direction in which the long sides 23 extend is the

[0010] direction, and the direction in which the short sides 24 extend is the

[0100] direction. However, as long as the thermal conductivity in the direction in which the long sides 23 extend is higher than the thermal conductivity in the direction in which the short sides 24 extend, the directions in which the long sides 23 extend and the short sides 24 extend may be any direction.

[0031] In the above-mentioned first and second embodiments, the semiconductor substrate 22 is made of β-type gallium oxide, but the semiconductor substrate 22 may be made of other gallium oxide, the semiconductor substrate 22 may be made of an oxide semiconductor other than gallium oxide, or the semiconductor substrate 22 may be made of a semiconductor other than an oxide semiconductor. As the material of the semiconductor substrate 22, various materials having anisotropy in thermal conductivity can be used.

[0032] The

[0010] direction in the embodiment is an example of a first direction. The

[0100] direction in the embodiment is an example of a second direction. The long side 23 in the embodiment is an example of a side extending along the first direction. The short side 24 in the embodiment is an example of a side extending along the second direction.

[0033] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0034] 10: semiconductor device, 12: semiconductor chip, 22: semiconductor substrate, 23: long side, 24: short side

Claims

1. A semiconductor device comprising: The semiconductor substrate (22) has a rectangular shape with a side (23) extending along a first direction and a side (24) extending along a second direction when viewed along the thickness direction, a thermal conductivity K1 in the first direction of the semiconductor substrate is different from a thermal conductivity K2 in the second direction of the semiconductor substrate; a length L1 of the semiconductor substrate in the first direction and a length L2 of the semiconductor substrate in the second direction, [0010] The semiconductor device satisfies the above relationship with an error within a range of -5% to +5%.

2. The semiconductor device according to claim 1 , wherein the semiconductor substrate is made of an oxide semiconductor.

3. 3. The semiconductor device according to claim 1, wherein said semiconductor substrate is made of gallium oxide.

4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor substrate is made of β-type gallium oxide.

5. The semiconductor device according to claim 4 , wherein the first direction is a [010] direction.

6. An upper electrode (26) provided on an upper surface of the semiconductor substrate; A lower electrode (28) provided on the lower surface of the semiconductor substrate; and 6. The semiconductor device according to claim 1, wherein a current flows between said upper electrode and said lower electrode via said semiconductor substrate.

7. 7. The semiconductor device according to claim 6, wherein a heat sink (40) is joined to said lower electrode.

8. The semiconductor device according to claim 7 , wherein said heat sink has isotropic thermal conduction characteristics.

9. 9. The semiconductor device according to claim 6, wherein a metal block (30) is joined to the upper electrode.

10. The semiconductor device according to claim 9 , wherein the metal block has isotropic thermal conduction properties.

11. The semiconductor device according to any one of claims 1 to 10, further comprising a temperature detection element (90) for detecting a temperature of the semiconductor substrate.

12. The semiconductor device according to claim 11 , wherein the temperature detection element is provided at a central portion of an upper surface of the semiconductor substrate.

Images