Image sensor and image sensor pixel having a JFET source follower

Abstract

To provide an image sensor having a JFET source follower, and an image sensor pixel.SOLUTION: In some embodiments, an image sensor pixel includes a junction field effect transistor (JFET), and a floating diffusion region configured to function as a gate for the JFET. An image sensor can contain a plurality of pixels. At least one pixel includes the floating diffusion region formed in the semiconductor substrate, a transfer gate configured to selectively cause a transfer of light charge stored in the pixel to the floating diffusion region, and a JFET having (i) a source and a drain connected by a channel region, and (ii) a gate including the floating diffusion region.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to an image sensor and an image sensor pixel having a JFET source follower.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 62 / 141,222, filed March 31, 2015, which is incorporated by reference in its entirety for each PCT member state and territory where incorporation by reference is permitted or not prohibited. [Background technology]

[0003] Quantum image sensors (QIS) have been proposed as a potential next-generation image sensor. In single-bit QIS, a special sub-diffraction-limited size binary output photoelement that senses a single photoelectron is called a "jot". At the core of single-bit and multi-bit QIS implementations is single-electron sensitivity (~0.15er.ms) that can be obtained from high in-pixel conversion gain, e.g., >1000μV / e-. The required high conversion gain requires that the floating diffusion (FD) node capacitance be minimized. Our previous QIS research has shown that the FD node capacitance has been significantly reduced, but further reduction of the FD node capacitance and / or additional or alternative methods of reducing the FD node capacitance may still be advantageous and / or desirable. Summary of the Invention [Problem to be solved by the invention]

[0004] As an example, our previous QIS research shows that some QIS pixel designs incorporating pump gate charge transfer with distal FD and gateless reset have a significantly lower total FD capacitance, with the remaining FD capacitance coming primarily from the MOSFET source follower (SF). Calculations for such an example QIS design indicate that to achieve a conversion gain of 1000 μV / e-, the total FD capacitance needs to be less than 0.16 fF. In a 65 nm CMOS process, the MOSFET SF contributes about 0.3 fF to the FD capacitance, thus making it substantially more difficult to achieve a conversion gain of 1000 μV / e- with such designs at this technology node. [Means for solving the problem]

[0005] Some embodiments provide an image sensor pixel including a junction field effect transistor (JFET) and a floating diffusion region configured to function as a gate for the JFET. In some embodiments, the image sensor can include a plurality of pixels, where at least one pixel includes a floating diffusion region formed in a semiconductor substrate, a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion region, and a JFET having (i) a source and a drain coupled by a channel region, and (ii) a gate including the floating diffusion region.

[0006] In some embodiments, the channel region includes a first doped region of a first conductivity type configured to provide conduction between the source and drain along a lateral direction substantially parallel to a surface of the substrate, the floating diffusion region includes a second doped region of a second conductivity type opposite the first conductivity type, and the second doped region of the floating diffusion region is disposed adjacent to and below the first doped region along the lateral direction between the source and drain.

[0007] In some embodiments, the floating diffusion region and the channel region can be configured such that charge selectively transferred to the floating diffusion region by operation of the transfer gate changes the current between the source and drain through the channel region.

[0008] Also, in some embodiments, the floating diffusion region and the channel region can be configured such that charge selectively transferred to the floating diffusion region by operation of the transfer gate causes a change in potential at the gate and subsequently causes a change in potential at the source of the JFET.

[0009] In some embodiments, the capacitance of the floating diffusion region is small enough to provide a conversion gain of at least 500 μV / e− and the image sensor is configured as a QIS.

[0010] In some embodiments, the channel may be configured as a buried channel.

[0011] Although pixels according to some embodiments of the present invention are suitable for use in image sensors requiring ultra-high conversion gain (e.g., QIS, qDIS, or other single-bit or multi-bit photoelectron counting sensors), it will be understood in light of the following disclosure that some embodiments of the present invention are also applicable to conventional CMOS image sensors (e.g., CMOS image sensors currently commercially available for consumer, manufacturing and / or scientific applications).

[0012] Throughout this specification and claims, the following terms at least take the meaning expressly associated therewith, unless the context dictates otherwise. The meanings specified below are not necessarily limiting, but merely illustrative of the terms. As used herein, the phrase "an embodiment" may refer to the same embodiment, but not necessarily. Also, the meanings of "a," "an," and "the" include plural referents, so that, for example, "an embodiment" is not limited to a single embodiment, but refers to one or more embodiments. Similarly, the phrase "one embodiment" is not necessarily limited to the same embodiment, but refers to a single embodiment. As used herein, the term "or" is an inclusive "or" operator, and is equivalent to the term "and / or" unless the context clearly dictates otherwise. The term "based on" is not exclusive, and may be based on additional factors not listed, unless the context clearly dictates otherwise.

[0013] Also, the designations "n" and "p" (e.g., "n-type", "p-type", "n-type well", etc.) are used herein in the normal and customary manner to designate donor-type and acceptor-type impurities that promote electron and hole carriers as majority carriers, respectively. The term "substrate" is to be understood as semiconductor-based materials such as silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technologies, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when referring to a "substrate" in the following description, previous process steps may have been used to form regions or junctions in the base semiconductor structure or foundation. Also, the semiconductor need not be silicon-based, but may be based on, for example, silicon-germanium, germanium, or gallium arsenide.

[0014] Additionally, the term "coupled" as used herein means directly connected or indirectly connected through one or more intermediate elements, unless the context clearly indicates otherwise, and may also mean or include electrically coupled, such as conductively coupled, capacitively coupled, and / or inductively coupled, depending on the context. Additionally, "conductively coupled" means coupled through one or more intermediate elements that allow energy transfer through a conductive current, which may include direct current and alternating current, and "capacitively coupled" means electrostatically coupled (e.g., through a series of capacitive components) through one or more dielectric media that allow energy transfer through a displacement current rather than a direct current, and possibly through one or more intervening conductors. Additionally, those skilled in the art will appreciate that elements may be capacitively coupled intentionally or unintentionally (e.g., parasitically) and that elements referred to as capacitively coupled may refer to intentional capacitive coupling, depending on the context. Those skilled in the art will also appreciate that the term "coupled" may also refer to operative coupling through direct and / or indirect connections, depending on the context. For example, when a conductor (e.g., a control line) is said to be coupled to the gate of a transistor, it can mean that the conductor can control the gate potential to control the operation of the transistor (e.g., switching the transistor between "on" and "off" states), regardless of whether the conductor is indirectly connected to the gate (e.g., via another transistor) and / or directly.

[0015] Terms such as "upper," "top," "lower," "bottom," "overlying," "underlying," "above," and "below" in relation to layers, junctions, doped regions, or other structures will be understood to denote relative spatial location with respect to the perspective of the figure, merely for ease of reference and clarity of explanation in relation to describing cross-sectional views of pixels shown in the figures, and will not indicate a preferred or required orientation. In this regard, it will also be understood that such terms have no relation to terms such as "frontside" or "backside," in relation to the surface of the wafer / substrate of the image sensor that is configured to be illuminated. For example, depending on the viewing perspective, a first doped region can be said to be above or on top of a second doped region, even if it is located near the "backside" of the wafer / substrate (and the image sensor can be configured for backside illumination). Thus, as noted above, the terms "top," "upper," "bottom," "lower," and the like, used herein are merely a convenient convention for referring to different layers, ease of reference, and do not otherwise impose limitations on the overall design and / or orientation of an image sensor or pixel according to the present disclosure.

[0016] In this regard, for ease of reference, two layers, regions, or other structures / elements may be said to be "adjacent" herein if they do not include one or more intervening layers, regions (e.g., doped regions), or other structures / elements. In other words, while two layers, regions, or other structures / elements that are spatially referenced to one another (e.g., "on," "above," "on," "below," "under," etc.) may have one or more intervening layers, regions, or other structures / elements, use of the term "adjacent" (or similarly "directly," such as "directly on," "directly overlying," etc.) means that there are no intervening layers, regions, or other structures / elements.

[0017] Those skilled in the art will appreciate that the above brief description and the following description of the drawings are intended to illustrate and explain certain embodiments of the present invention, but are not intended to be representative or exhaustive of all subject matter and embodiments falling within the scope of the present invention, nor are they intended to limit or characterize the present invention or to limit the advantages that may be achieved by embodiments of the present invention, nor are they intended to require that the present invention necessarily provide one or more of the advantages set forth herein for certain embodiments. Thus, the accompanying drawings, which are referenced herein and which form a part hereof, illustrate certain embodiments of the present invention and, together with the detailed description, serve to explain the principles of certain embodiments of the present invention.

[0018] The aspects, features and advantages of several embodiments of the present invention, both in terms of structure and operation, will be understood and become readily apparent when considered in conjunction with the following description of non-limiting and non-exclusive embodiments in conjunction with the accompanying drawings in which the same reference numerals indicate the same or similar parts throughout the various views. [Brief description of the drawings]

[0019] [Figure 1A]1 is a schematic plan view of an example pixel of an image sensor according to some embodiments of the present disclosure. [Figure 1B] 1B is a schematic orthogonal cross-sectional view of an exemplary pixel according to the embodiment of FIG. 1A, according to some embodiments of the present disclosure. [Figure 1C] 1B is a schematic orthogonal cross-sectional view of an exemplary pixel according to the embodiment of FIG. 1A, according to some embodiments of the present disclosure. [Figure 2A] 4 is a schematic orthogonal cross-sectional view of an exemplary pixel according to another embodiment of a pixel according to some embodiments of the present disclosure. [Figure 2B] 4 is a schematic orthogonal cross-sectional view of an exemplary pixel according to another embodiment of a pixel according to some embodiments of the present disclosure. [Diagram 3] 1A-1C show results obtained by performing a TCAD simulation of a pixel structure according to an exemplary embodiment of the present disclosure. [Figure 4] 1A-1C show results obtained by performing a TCAD simulation of a pixel structure according to an exemplary embodiment of the present disclosure. [Diagram 5] 1A-1C show results obtained by performing a TCAD simulation of a pixel structure according to an exemplary embodiment of the present disclosure. [Figure 6] 1A-1C show results obtained by performing a TCAD simulation of a pixel structure according to an exemplary embodiment of the present disclosure. [Figure 7] 1A-1C show results obtained by performing a TCAD simulation of a pixel structure according to an exemplary embodiment of the present disclosure. [Figure 8] 1A-1C show results obtained by performing a TCAD simulation of a pixel structure according to an exemplary embodiment of the present disclosure. [Figure 9] 1A-1C show results obtained by performing a TCAD simulation of a pixel structure according to an exemplary embodiment of the present disclosure. [Figure 10]FIG. 2 illustrates an exemplary layout design according to some embodiments of the present disclosure using an industrial 65 nm CMOS CIS process. [Figure 11] FIG. 2 illustrates an exemplary layout design according to some embodiments of the present disclosure using an industrial 65 nm CMOS CIS process. [Figure 12] FIG. 1 is a block diagram of an example image sensor architecture that can be used to implement some embodiments according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Exemplary embodiments of an image sensor pixel having a JFET source follower are disclosed. As will be appreciated by one of ordinary skill in the art in light of this disclosure, embodiments according to the present disclosure may include a QIS (e.g., n It is particularly suitable for implementing single-bit or multi-bit QISs having a full well capacity (FWC) of 1 (usually n being an integer less than or equal to 6 or 7) optical carriers, and other JOT-based image sensor implementations.

[0021] Briefly, in some embodiments, a pixel includes a floating diffusion region (FD) configured as the gate of a JFET source follower. In such embodiments, the FD includes a first semiconductor region of a first conductivity type (e.g., n-type) configured to control the conductance of a second semiconductor region having a second conductivity type opposite the first conductivity type (e.g., p-type) configured as a channel region of the JFET based on an amount of photocharge transferred from a photodiode of the pixel to the FD.

[0022] Such embodiments are suitable for reducing FD capacitance, e.g. by reducing SF capacitance (e.g. compared to a pixel / jot including a MOSFET SF) and can be advantageously implemented with a pumped-gate charge transfer gate with distal FD and / or gateless reset to provide a pixel with very small FD capacitance and concomitantly very high conversion gain suitable for QIS implementation.

[0023] Additionally, JFET SFs according to some embodiments generally have better noise performance than MOSFET SFs, thus reducing the minimum high conversion gain required or desired for a given implementation (e.g., of a QIS pixel). Also, the gate-source capacitance in a JFET SF is a junction capacitance, which is typically much smaller than the oxide capacitance of a MOSFET, such that the total FD capacitance of a pixel using a JFET SF is significantly reduced compared to a pixel using a MOSFET SF. In TCAD simulations using designs according to exemplary embodiments described below, a conversion gain of 2 mV / e- was found without including metal lines, and a conversion efficiency of 1.7 mV / e- was found with including metal lines.

[0024] Further aspects, features and advantages of certain embodiments of the present invention will be further appreciated in light of the following description of various exemplary embodiments.

[0025] FIG 1A is a schematic plan view of a portion of an exemplary pixel 100 of an image sensor according to some embodiments of the present disclosure. FIG 1B and FIG 1C show exemplary cross-sectional doping schematics of the pixel along respective orthogonal directions indicated by cross-sectional reference lines XX' and YY' in FIG 1A, and also show the pixel's readout MOSFET Mrs (e.g., a row select transistor within the pixel) and column bus 32. (As will be appreciated, Mrs selectively couples the source of the JFET to the column bus 32, which is biased by a current source Is and coupled to further off-pixel readout circuitry, in response to a readout signal RS.) As will be appreciated by those skilled in the art, FIG 1A, FIG 1B, and FIG 1C (as well as FIG 2A and FIG 2B) show features in exemplary idealized / simplified forms for clarity of explanation and do not show all features or elements that may be present or included within a pixel, such as metallization, interlayer dielectrics, and vias / contacts. Also, in light of the present disclosure, it will be understood that while this exemplary embodiment is configured for backside illumination (BSI), embodiments according to the present disclosure are not limited to a BSI configuration, and frontside illumination embodiments can also be implemented with the FD also functioning as the gate of the JFET SF.

[0026] As shown in FIGS. 1A-1C, an exemplary embodiment of a JFET pixel configured to include a floating diffusion region formed in a p-type substrate 17 and functioning as the gate of a JFET SF includes: (i) a pump-gated transfer gate substantially or completely covering a photodiode region including an n-type storage well (SW) region that accumulates / stores photocarriers (photoelectrons) generated in the pixel region during an integration period; (ii) a floating diffusion region FD including an n-type doped region 16 disposed within a lightly doped n-type region (e.g., n-) 18 that is laterally distal (e.g., spaced apart and not overlapping) from the TG; (iii) a reset drain (RD) including an n+ doped region 11 laterally displaced from the FD and configured for gateless reset of the FD; and (iv) p+ doped regions 12 and 14 in contact with an interposed p-type region 20 that covers the n-type region 16 of the FD and is laterally bounded by the n- doped region of the FD.

[0027] Also shown diagrammatically are (i) a dielectric layer 19 that forms part of the TG gate stack (e.g., a gate dielectric) and extends over the pixel (e.g., provides surface passivation), and (ii) a lightly doped (n-) n-type region 27 (e.g., lightly doped compared to the n-type doping of SW region 25 so that generated photocarriers drift towards storage well (SW) region 25) disposed below the storage well (SW) region. Drain and source contacts 24 and 26 may also be formed through dielectric 19 as shown, with electrical isolation provided by shallow trench isolation (STI).

[0028] Thus, as one of ordinary skill in the art will appreciate in view of this disclosure, the p+ regions 12 and 14, p-type region 20, and FD are configured as the drain, source, channel, and gate regions, respectively, of the JFET SF. And, in configuration, the JFET channel region overlays the FD / gate regions that operate to tune / control the JFET channel, thus providing a compact, small footprint design suitable for QIS implementation. In this configuration, according to some embodiments, such as the embodiment of Figures 1A-1C, the conduction direction of the JFET channel between the source and drain becomes approximately perpendicular to the direction of charge transfer from the charge storage well of the photodiode to the FD.

[0029] According to the exemplary embodiment of Figures 1A-1C, the structure and operation of the pump gate can be implemented in accordance with (i) U.S. Provisional Patent Application No. 61 / 973,825, filed April 1, 2014, entitled "CMOS Image Sensor with Pump Gate and Extremely High Conversion Gain," and (ii) a low full well capacity vertical pump gate pixel as disclosed in "A Pump-gate Jot Device with High Conversion Gain for a Quanta Image Sensor," IEEE Journal of the Electron Devices Society, 3(2), February 2015, each of which is incorporated herein by reference in its entirety. For example, although not explicitly shown in Figure 1C, such a vertical pump gate pixel can include a buried n-type charge storage region and a laterally adjacent p+ doped pinning region, as disclosed, for example, in the above-referenced U.S. Provisional Patent Application and IEEE Journal article. However, it will be understood that various embodiments according to the present disclosure are not limited to using a pump transfer gate positioned substantially below the transfer gate, nor to using a photodiode, but may be implemented with any photodiode and transfer gate configuration suitable to meet the design requirements of a given implementation (including, for example, a configuration having an embedded photodiode positioned laterally relative to the transfer gate).

[0030] Gateless reset can be implemented according to the embodiments described in U.S. Provisional Patent Application No. 62 / 128,893, filed March 5, 2015, entitled "Gateless Reset for Image Sensor Pixels," which is incorporated herein by reference in its entirety. As will be appreciated by those skilled in the art, the exemplary gateless reset embodiment shown in FIGS. 1A-1C does not include a reset transistor gate formed between the FD and reset drain (RD) regions (e.g., no gate electrode stack is disposed on the surfaces above and between the FD and RD as shown). In operation, the potential of the FD is reset by selectively applying a voltage pulse to the RD via conductive line 18 (e.g., interconnect metallization) to control charge transfer from the FD to the RD region, without the use of a transistor gate-controlled (e.g., inversion layer charge-containing) conductive channel between the FD and RD. In some embodiments, the RD can also include a less highly doped n-type region (e.g., compared to the n+ doping of region 11) disposed adjacent to region 11 and laterally toward the FD. However, it will be understood that various embodiments according to the present disclosure are not limited to using a gateless reset of the FD, and for example, various embodiments may use a reset gate transistor that is optionally implemented as a pump gate (e.g., that does not overlap the FD region).

[0031] 1A-1C, in a JFET source follower, the source and drain are formed on p+ doped wells 12 and 14 and are connected by a p-type channel 20 surrounded by an n-doped well. Specifically, as shown in FIG. 1B, there is an n-doped region 16 below the p-type channel 20, which serves as the charge storage node for the floating diffusion (FD) and the gate of the JFET.

[0032] Briefly, in operation of this exemplary embodiment, photon-generated electrons are collected / stored in the SW potential well of region 25 and selectively transferred to the FD during a charge transfer operation by selective operation of transfer gate TG. The transferred electrons in the FD accumulate in n-type region 16, thus changing the potential of region 16 and n-well 18. The potential of region 16 changes the depletion region in the overlying p-type channel, and thus the resistivity, which therefore changes according to the charge transferred to region 16 of the FD. Also, during readout, the source of the JFET source follower is selectively connected to a current source (e.g., Is), so that the voltage of the JFET source changes to follow the potential of the n-well. Thus, photon-generated electrons can be detected by measuring the voltage change of the source node (with off-pixel readout circuitry (not shown) connected to column bus 32). As will be appreciated by one skilled in the art, operation of the exemplary pixel of Figures 1A-1C can employ correlated double sampling by providing appropriate readout control signal timing and off-pixel array readout circuitry.

[0033] As will be appreciated by those skilled in the art in view of the present disclosure and in accordance with the embodiment of Figures 1A-1C, to improve the performance of the JFET source follower, the JFET source region should be surrounded by an n-doped well so that the current from source to drain is restricted to flow through the p-type channel 20. Any current leakage path between the source and drain reduces the gain of the source follower. The n-doped well 16, which serves as the FD charge storage region and the gate of the JFET, should be more heavily doped than the nearby n-doped well 18 so that transferred electrons accumulate only in the n-region 16. Any electrons that accumulate elsewhere in the n-well are not effective in changing the resistivity of the p-channel (20). In a backside illuminated (BSI) image sensor, the drain of the JFET can also serve as a substrate contact. Thus, a deep p-well 22 can be formed below the drain region 12 to ensure a good connection to the bulk. In some embodiments, substrate 17 may include a p+ region formed on the backside to provide for a backside contact (not shown in the exemplary BSI embodiment of FIGS. 1A-1C).

[0034] The JFET source follower is a Si-SiO 2 Although it has better noise performance than MOSFET source followers with interface traps, the surface interface traps may still cause unwanted read noise due to the extreme sensitivity of the p-channel to potential changes. Thus, some embodiments can be implemented with a buried channel source follower to further improve noise performance. For example, Figures 2A and 2B are schematic orthogonal cross-sectional views of an exemplary embodiment similar to that of Figures 1A-1C, but with a buried p-channel 30 formed and surrounded by an n-doped well 18. As shown, the n-type region 16 of the FD, which serves as the charge storage region of the FD and the gate of the JFET, is located below the channel 30.

[0035] As a non-limiting example merely to further illustrate aspects of some embodiments, a jot device similar to the exemplary embodiment of Figures 1A-1C including a pump gate TG, a gateless reset, and a JFET source follower was simulated in Synopsys TCAD. In this example, the photodiode SW has a full well capacity of 350e-, and the JFET was biased by a 2μA current source. The results of this exemplary simulation are further described with reference to Figures 3-8.

[0036] Figure 3 shows the potential profile of the device during the reset stage. In this example, the bias voltage of the reset drain varies between 5 V and 2.3 V. When the bias voltage is high, electrons in the FD move to the RD due to the fringing effect, and the potential of the FD rises to 2.8 V. After reset, the bias voltage of the RD is kept at 2.3 V to maintain the potential barrier between the FD and RD and prevent charge leakage.

[0037] The potential profile of the charge transfer step (SW to FD) is shown in Figure 4. In this example, the TG is biased at 2.5V during the charge transfer, and there is a monotonic potential rise from SW to the p-type well region PW, as described in more detail in U.S. Provisional Patent Application No. 61 / 973,825, and this charge is temporarily transferred to the PW region. When the TG bias voltage is returned to a low voltage of -0.5V and the potential of PW is lower than that of the virtual barrier (VB) region, electrons flow across the virtual potential barrier to the FD, completing the two-step charge transfer.

[0038] The transferred electrons are stored in the FD, which changes the gate potential of the JFET source follower. The TCAD simulation also demonstrated the potential profile of the JFET source follower, which shows that the potential of the FD changes after the charge transfer, which in turn changes the depletion region width in the p-channel.

[0039] The transient simulation results shown in Figure 5 show that 280 electrons are accumulated in the SW during charge integration. After the charge transfer, the SW is fully depleted and the 280 electrons are transferred to the FD. Figure 6 shows that the change in FD potential after the charge transfer is 850mV, which causes a 560mV output voltage change. The source follower gain is 0.65, and the charge-to-voltage conversion gain is 2mV / e-.

[0040] The linearity of the JFET source follower was also tested. After reset, the number of electrons in the FD reaches 335 and saturates at 760, as shown in Figure 7. The output of the FD and source follower have a linear response proportional to the accumulated electrons when the number of electrons is less than about 688.

[0041] In this simulation example, a column bias current of 2 μA is used, and in this design, the bias current can be varied from 100 nA to 5 μA. The bias current can be further increased by changing the FD and p-channel dose. The current drive capability of the JFET SF is determined by the resistivity of the channel, and the current magnitude should be suitable to keep the source voltage lower than the FD potential to avoid gate-source leakage current. As shown in Figure 8, the simulation also demonstrates another variation of the JFET SF that results in a current drive capability of 50 μA.

[0042] Figures 9A, 9B and 9C show the results of yet another TCAD simulation performed on a pixel according to an exemplary embodiment of the present disclosure, in which Figure 9A shows the applied TG and RD signals, Figure 9B shows the corresponding charge stored in SW (transferred to FD), and Figure 9C shows the corresponding FD voltage and source follower source voltage (SF SRC) as well as the measured FD and SF SRC voltage values ​​before and after the charge transfer.

[0043] According to some embodiments, the JFET can be read out using current modulation instead of voltage modulation mode, where a change in the FD (gate of the JFET) potential causes a change in the output current that is detected by readout circuitry that is well understood by those skilled in the art. See, for example, "On-Focal-Plane Signal Processing for Current-Mode Active Pixel Sensors," IEEE Transactions On Electron Devices, October 1997, Vol. 44, No. 10, pp. 1747-1758, which is incorporated herein by reference in its entirety.

[0044] Figures 10 and 11 show two possible layout designs according to some embodiments based on an industrial 65 nm CMOS CIS process. The fabrication of this device does not increase the mask count of the standard process. The first layout has a pitch of 1.3 μm as shown in Figure 10. In this layout, two adjacent jots in one row share one reset drain, which helps reduce the size. The second layout design has a pitch of 1 μm as shown in Figure 11. This layout is configured as a bidirectional shared readout, where four jots in one row share one reset drain. However, it will be understood that an infinite number of layout variations are possible for a given technology node and process.

[0045] 12 is a block diagram of an exemplary CMOS image sensor 40 architecture that can be used to implement embodiments according to the present disclosure, such as those including pixels using FDs that function as gates of JFET SFs according to the disclosures discussed above in connection with FIGS. 1A-1C and 2A-2B. As is well known, a pixel array 42 typically includes many pixels arranged in an M×N array, but the illustrated CMOS image sensor 40 includes a simplified pixel array 42 that includes a 3×3 array of pixels 64, which for ease of explanation is a pixel circuit according to any of the embodiments discussed above, but which may be any of a variety of pixel circuit types configured to implement a JFET SF that includes a FD that functions as a gate of the JFET according to the present disclosure. Also, for example, in some embodiments, the pixels may be shared pixels (e.g., sharing FDs and RDs and possibly additional readout circuitry) and may be further configured for in-pixel binning.

[0046] The row addressing and row driver circuitry 44 generates a transfer gate (TG) control signal on line 51, a row select (RS) signal on line 55, and a reset drain (RD) control signal on line 52. The column readout circuitry 46 includes an analog-to-digital circuitry 43 that samples and digitizes output values ​​read out from the pixel array 42. Notably, the circuitry 43 can be implemented to include multiple A / D converters configured to perform parallel readout of the columns. In some embodiments, the circuitry 43 can be configured such that the readout circuitry associated with each column bus 32 has its own analog-to-digital converter (ADC), although in some embodiments multiple pairs of columns can share an ADC.

[0047] The timing and control circuitry 48 controls both the row addressing and row driver circuitry 44 and the column readout circuitry 43. For example, the timing and control circuitry may control the row addressing and row driver circuitry 44 to select the appropriate row for readout and may provide timing control signals, for example, for a rolling shutter readout or a global shutter readout. As shown in Figure 12, the timing and control circuitry 48 may be communicatively interconnected with a host (e.g., a processor associated with a system that includes the image sensor) to specify various control information, for example, in some implementations.

[0048] As shown generally, circuitry 43 samples and digitizes the signals on column bus 32 and provides digitized pixel values ​​provided by the ADC to a line buffer 45 that may be used to temporarily store the digital signals from circuitry 43 for use by an image processor 47. In general, any number of line buffers 45 may be included, with each line buffer being capable of storing digital signals representative of the charge signals that can be read from each pixel of a given row of pixels in pixel array 42. An image processor 47 may be used to process the digital signals held in the line buffers 45 to generate output image data that may be provided to devices external to image sensor 40.

[0049] As can be understood, there are many possible implementations of image sensor architectures that can embody pixels having FDs according to some embodiments of the present disclosure and JFETs SD with FDs functioning as the gates of the JFETs. As an example, it will be understood that the circuit 46 can be divided into two parts located at the top and bottom of the pixel array.

[0050] In view of the above, it will be appreciated that some embodiments of the disclosed pixels are suitable for shared pixel, i.e., shared pixel architectures that share at least the floating diffusion region and the reset drain / diffusion (and may also share, e.g., source followers, etc.). (As known to those skilled in the art, such shared architectures may be used for in-pixel charge region binning.) As an example, in some embodiments, the size of each pixel (e.g., each jot of the QIS) may be further reduced by using a four-way shared pixel structure / unit (e.g., possibly including seven transistors per shared pixel unit). Also, in some such shared pixel embodiments, the effects of crosstalk between the jots may be mitigated by covering the four jots that share a common FD with a single color filter and microlens. Furthermore, in some such embodiments, each shared pixel unit that includes four jots (and has, e.g., a single color filter and microlens) may be isolated by a single deep trench isolation (DTI) around the set of four jots. That is, the four jots that share a FD are not isolated from each other by DTI, but rather are collectively isolated from other shared pixel units (i.e., units of the other four jots that share a FD) by DTI. Such DTI further reduces crosstalk between the shared pixel units associated with their respective color filters. It will be understood that other configurations of shared pixel units (e.g., different numbers of jots sharing a common FD) can also be implemented accordingly.

[0051] It will also be understood that the FD serving as the gate of the JFET SF of the image sensor pixel according to various embodiments of the present invention can also be implemented in a back-side illuminated (BSI) image sensor or a front-side illuminated image sensor, in other words, the embodiments of the present disclosure are not exclusively limited to only one of back-side illuminated image sensors and front-side illuminated image sensors.

[0052] Furthermore, for example, although pixels according to some embodiments of the present invention are suitable for use in image sensors requiring ultra-high conversion gain (e.g., QIS, qDIS, or other single-bit or multi-bit photoelectron counting sensors), in light of the following disclosure, it will be understood that one or more features and / or embodiments of the present invention are also applicable to conventional CMOS image sensors (e.g., CMOS image sensors currently commercially available for consumer, manufacturing, and / or scientific applications). Similarly, it will be understood that, for example, a FD configured as the gate of a JFET according to the present disclosure is not limited to being used with a pump gate and a distal FD, or necessarily with a gateless reset, regardless of whether the pixel is a QIS type pixel.

[0053] Various embodiments of the present invention can be used in configurations including color filter arrays and microlenses, where individual photoelements can be isolated using shallow or deep trench technology as is common in modern image sensors. Additionally, further signal processing associated with quantum image sensors can be integrated on the same chip as the photodetector array. This image signal processing can be integrated into the stack layers, similar to modern stacked CMOS image sensor arrays, where one chip in the stack is optimized for photodetector element devices and another chip is optimized for mixed signal circuitry, with interconnects between the stack layers.

[0054] Although the present invention has been illustrated and described with respect to certain exemplary embodiments, these embodiments merely illustrate some of the principles of some embodiments of the present invention, and are not intended to be exclusive or limiting of the embodiments. Thus, while the above description of exemplary embodiments of the present invention and various exemplary modifications and features thereof provide many particularities, these enabling details should not be construed as limiting the scope of the present invention, and those skilled in the art will readily appreciate that the present invention is capable of many modifications, adaptations, variations, omissions, additions, and equivalent implementations without departing from the scope and without losing its attendant advantages. For example, no particular order is implied for the steps or stages of the methods or processes described in this disclosure, including the drawings, except to the extent necessary or inherent in the process itself. In many cases, the order of process steps can be changed, and various exemplary steps can be combined, modified, or omitted without changing the purpose, effect, or spirit of the described method. Similarly, the structure and / or function of the elements can be combined into a single element or divided into two or more elements. Furthermore, the terms and expressions are used as descriptive terms rather than limiting terms. There is no intention to use these terms or expressions to exclude any equivalents of the illustrated and described features or portions thereof. Nor can the present invention be practiced without necessarily achieving one or more of the advantages described herein or understood in light of this disclosure and / or realized in some embodiments thereof. Accordingly, any patent application based on and / or corresponding to this disclosure herein and / or claiming priority to this disclosure may present claims based on this disclosure, and the present invention should not be limited to the disclosed embodiments, but should be determined in accordance with such claims. [Explanation of symbols]

[0055] 100 pixels 11 n+ doped region 12 p+ doped region 14 p+ doped region 18 n-type region 20 p-type region

Claims

1. An image sensor having a plurality of pixels, at least one of the pixels comprising: a floating diffusion region formed in a first surface of a semiconductor substrate; a transfer gate configured to selectively cause a transfer of photocharge stored in the pixel to the floating diffusion region; (i) a source and a drain coupled by a channel region; and (ii) a gate including the floating diffusion region, wherein charge selectively transferred to the floating diffusion region by operation of the transfer gate is configured to change a depletion region in the channel region; 1. An image sensor comprising: a first doped region of a first conductivity type configured to conduct electricity between the source and the drain along a lateral direction parallel to a surface of the semiconductor substrate; a floating diffusion region comprising a second doped region of a second conductivity type opposite to the first conductivity type, the second doped region being disposed within a third doped region of the second conductivity type, the third doped region being less doped than the second doped region; and a first doped region of the channel region along a lateral direction between the source and the drain being disposed between the first surface of the semiconductor substrate and an adjacent portion below the second doped region of the floating diffusion region.

2. 2. The image sensor of claim 1, wherein the floating diffusion region and the channel region are configured such that charge selectively transferred to the floating diffusion region by operation of the transfer gate causes a change in potential of the source after causing a change in potential of the gate.

3. 10. The image sensor of claim 1, wherein the capacitance of the floating diffusion region is small enough to provide a conversion gain of at least 500 μV / e-, and the image sensor is configured as a QIS.

4. The image sensor of claim 1 , wherein the channel region is configured as a buried channel.

5. The image sensor of claim 1 , wherein the image sensor is configured as a back-illuminated device.

6. The image sensor of claim 1 , wherein the transfer gate is spaced apart from and does not overlap the floating diffusion region.

7. the floating diffusion region is configured to be reset using a reset drain without a reset gate; 2. The image sensor of claim 1.

8. The image sensor of claim 7 , wherein the transfer gate is spaced apart from and does not overlap the floating diffusion region.

9. 2. The image sensor of claim 1, wherein the pixel includes a photodiode having a charge storage / accumulation region disposed below the transfer gate and configured to store the photocharges selectively transferred to the floating diffusion region using the transfer gate.

10. The image sensor of claim 1 , wherein the pixels are configured as shared pixels.

11. The image sensor of claim 1 , wherein the channel region is a p-type channel.

12. 1. A method of providing an image sensor having a plurality of pixels, comprising the steps of: forming a floating diffusion region in a first surface of a semiconductor substrate; forming a transfer gate configured to selectively cause a transfer of photocharge stored in the pixel to the floating diffusion region; forming in the semiconductor substrate a JFET having (i) a source and a drain coupled by a channel region, and (ii) a gate including the floating diffusion region, wherein selective operation of the transfer gate causes a transfer of photocharges to the floating diffusion region to change a depletion region in the channel region; 11. The method of claim 10, wherein the channel region includes a first doped region of a first conductivity type configured to conduct electricity between the source and the drain along a lateral direction parallel to a surface of the semiconductor substrate, the floating diffusion region includes a second doped region of a second conductivity type opposite to the first conductivity type, the second doped region being disposed within a third doped region of the second conductivity type, the third doped region being less doped than the second doped region, and the first doped region of the channel region along a lateral direction between the source and the drain is disposed between the first surface of the semiconductor substrate and an adjacent portion below the second doped region of the floating diffusion region.

13. 13. The method of claim 12, wherein the floating diffusion region and the channel region are configured such that charge selectively transferred to the floating diffusion region by operation of the transfer gate causes a change in potential of the source after causing a change in potential of the gate.

14. The method of claim 12 , wherein the capacitance of the floating diffusion region is small enough to provide a conversion gain of at least 500 μV / e−, and the image sensor is configured as a QIS.

15. The method of claim 12 , wherein the channel region is configured as a buried channel.

16. The method of claim 12 , wherein the transfer gate is spaced apart from and does not overlap the floating diffusion region.

17. The method of claim 12 , wherein the floating diffusion region is configured to be reset using a reset drain without a reset gate.

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