Method for packaging semiconductor devices

Abstract

The present disclosure relates to a method and apparatus for forming a thin form factor semiconductor device package. In a particular embodiment, a glass or silicon substrate is patterned by laser ablation to form structures for later forming interconnects through the substrate. The substrate is then utilized as a frame for forming a semiconductor device package, in which one or more dies may be embedded. In a particular embodiment, an insulating layer is formed on the substrate by laminating a pre-structured insulating film on the substrate. The insulating film may be pre-structured by laser ablation to form structures therein, and then the sidewalls of the formed structures may be selectively hardened.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to semiconductor device packages and methods of forming the same. More particularly, embodiments described herein relate to thin form factor semiconductor device package structures and methods of forming the same. [Background technology]

[0002] 2. Description of Related Art A long-standing trend in the development of semiconductor device technology has been to result in semiconductor components that are smaller and have increased circuit density. In keeping with the demand for continuing scaling of semiconductor devices with increasing performance capabilities, these components and circuits are being significantly reduced in size and assembled into complex 3D semiconductor device packages, which allows for a significant reduction in the footprint of the device and allows for shorter and faster connections between components. Such packages may, for example, incorporate a semiconductor chip and multiple other electronic components that are mounted on a circuit board of an electronic device.

[0003] Traditionally, semiconductor device packages have been fabricated on organic packaging substrates due to the ease of forming features and connections, as well as the relatively low package manufacturing costs associated with organic composite materials. However, as circuit density increases and semiconductor devices become smaller, the use of organic packaging substrates becomes impractical due to limitations in material structure resolution to maintain device scaling and associated performance requirements.

[0004] Recently, 2.5D and / or 3D packages have been fabricated that utilize passive silicon interposers as redistribution layers to compensate for some of the limitations associated with organic package substrates. The use of silicon interposers is driven by the potential for high bandwidth density, lower power interchip communication, and heterogeneous integration requirements in advanced packaging applications. Nevertheless, the formation of features in silicon interposers, such as through silicon vias (TSVs), remains challenging and costly. In particular, the high aspect ratio silicon via etching, chemical mechanical planarization, and semiconductor back-end-of-line (BEOL) interconnects are costly.

[0005] Thus, there is a need in the art for improved semiconductor device package structures and methods of forming the same for advanced packaging applications. Summary of the Invention

[0006] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to structures for thin form factor semiconductor device packages and methods of forming the same.

[0007] In a particular embodiment, a method of forming a semiconductor device package is provided, the method including: patterning one or more features in a silicon substrate, the one or more features comprising a first via, disposing a pre-structured insulating film over the substrate, the pre-structured insulating film comprising a flowable polymer-based dielectric material, the pre-structured insulating film further comprising a second via formed therein, the second via being aligned with the first via upon disposing the pre-structured insulating film, laminating the pre-structured insulating film over the substrate, curing the pre-structured insulating film, and forming a conductive layer extending through the first via and the second via.

[0008] In a particular embodiment, a method of forming a semiconductor device package is provided, the method including: patterning one or more features on a silicon substrate, the one or more features comprising at least a first via, disposing the substrate on a first pre-structured insulating film, the first pre-structured insulating film comprising a second via, the second via being aligned with the first via upon disposing the substrate, disposing a second pre-structured insulating film on the substrate, the second pre-structured insulating film comprising a third via, the third via being aligned with the first via upon disposing the second pre-structured insulating film, stacking the first pre-structured insulating film and the second pre-structured insulating film on the substrate, curing the first pre-structured insulating film and the second pre-structured insulating film, and forming a conductive layer extending through at least the first via, the second via, and the third via.

[0009] In a particular embodiment, a method of forming a semiconductor device package is provided, the method comprising: patterning one or more features on a silicon substrate, the one or more features comprising at least a first via; disposing the substrate on a first pre-structured insulating film, the first pre-structured insulating film comprising a second via, the second via being aligned with the first via upon disposing the substrate; subjecting the first pre-structured insulating film and the substrate to a first lamination process; and disposing a second pre-structured insulating film on the substrate. the second pre-structured insulating film comprising a third via, the third via being aligned with the first via upon disposition of the second pre-structured insulating film; subjecting the first pre-structured insulating film, the substrate, and the second pre-structured insulating film to a second lamination process; curing the first pre-structured insulating film and the second pre-structured insulating film; and forming a conductive layer extending through at least the first via, the second via, and the third via.

[0010] In order that the manner of features of the present disclosure enumerated above may be understood in detail, the present disclosure briefly summarized above may be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings, with the caveat that the accompanying drawings only illustrate exemplary embodiments and therefore should not be considered as limiting its scope, which may admit of other equally effective embodiments. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a flow diagram of a process for forming a semiconductor device package according to embodiments described herein. [Diagram 2] FIG. 2 is a flow diagram of a process for substrate structuring to form a semiconductor device package according to embodiments described herein. [Figure 3A-3D]3A-3C are schematic cross-sectional views of a substrate at various stages of a substrate structuring process depicted in FIG. 2 according to embodiments described herein. [Figure 4A-4F] 1A-1D are schematic cross-sectional views of a substrate at various stages of feature formation and subsequent damage removal according to embodiments described herein. [Figure 5A-5F] 1A-1D are schematic cross-sectional views of a substrate at various stages of feature formation and subsequent damage removal according to embodiments described herein. [Figures 6A-6E] 1A-1D are schematic cross-sectional views of a substrate at various stages of feature formation and subsequent damage removal according to embodiments described herein. [Figure 7A-7D] 1A-1D are schematic cross-sectional views of a substrate at various stages of feature formation and subsequent damage removal according to embodiments described herein. [Figure 8] Schematic top view of a substrate structured by the process depicted in Figures 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, and 7A-7D according to embodiments described herein. [Figure 9] FIG. 1 is a flow diagram of a process for forming a buried die assembly having through assembly vias and contact holes according to embodiments described herein. [Figures 10A-10K] 10A-10C are schematic cross-sectional views of an embedded die assembly at various stages of the process depicted in FIG. 9 according to embodiments described herein. [Figure 11] FIG. 1 is a flow diagram of a process for forming a buried die assembly having through assembly vias and contact holes according to embodiments described herein. [Figures 12A-12G] 12A-12C are schematic cross-sectional views of an embedded die assembly at various stages of the process depicted in FIG. 11 according to embodiments described herein. [Figure 13] FIG. 1 is a flow diagram of a process for forming interconnects in an embedded die assembly according to embodiments described herein. [Fig. 14A-14H]14A-14C are schematic cross-sectional views of an embedded die assembly at various stages of an interconnect formation process depicted in FIG. 13 according to embodiments described herein. [Figure 15] FIG. 1 is a flow diagram of a process for forming a redistribution layer on an embedded die assembly followed by package singulation according to embodiments described herein. [Fig. 16A-16L] 16A-16C are schematic cross-sectional views of an embedded die assembly at various stages of re-distribution layer formation and subsequent package singulation as depicted in FIG. 15 according to embodiments described herein. [Figure 17] FIG. 13 is a flow diagram of another process for forming a redistribution layer on an embedded die assembly and subsequent singulation according to embodiments described herein. [Figures 18A-18C] 18A-18C are schematic cross-sectional views of an embedded die assembly at various stages of re-distribution layer formation and subsequent package singulation as depicted in FIG. 17 according to embodiments described herein. [Figure 19] FIG. 2 is a flow diagram of a process for pre-structuring an insulating film separate from a substrate of a semiconductor device package according to embodiments described herein. [Figures 20A-20C] 20A-20C are schematic cross-sectional views of an insulating film at various stages of the structuring process depicted in FIG. 19 according to embodiments described herein. [Figure 21A-21B] FIG. 2 is a schematic diagram of an exemplary apparatus for use in the process of FIG. 19 and FIGS. 20A-20C, according to embodiments described herein. [Figure 22] FIG. 2 is a flow diagram of a process for forming an insulating layer over a substrate according to embodiments described herein. [Figures 23A-23G] 23A-23C are schematic cross-sectional views of an embedded die assembly at various stages of the process depicted in FIG. 22 according to embodiments described herein. [Fig. 24A-24B]FIG. 2 is a schematic cross-sectional view of a dynamic random access memory (DRAM) stack including multiple semiconductor device packages formed using the process depicted in FIGS. 1-23G according to embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] For ease of understanding, wherever possible, the same reference numbers have been used for identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further detail.

[0013] The present disclosure relates to methods and apparatus for forming thin form factor semiconductor device packages. In certain embodiments, a substrate is structured or shaped by microblasting to allow for the formation of interconnects through the substrate. In other embodiments, the substrate is structured by direct laser patterning. The substrate is then utilized as a package frame to form one or more semiconductor device packages with dies disposed therein. In yet other embodiments, the substrate is utilized as a frame for a semiconductor device stack, such as a dynamic random access memory (DRAM) stack.

[0014] The methods and apparatus disclosed herein further include novel thin form factor semiconductor device packages intended to replace more conventional package structures utilizing fiberglass filled epoxy frames and silicon interposers as redistribution layers. In general, the scalability of current packages is limited by the stiffness and flatness of the materials (e.g., epoxy molding compounds, FR-4 and FR-5 grade woven fiberglass cloth with epoxy resin binders, etc.) utilized to form the various package structures. Patterning fine (e.g., less than 50 μm) features in these materials is difficult due to their inherent properties. Furthermore, the thermal properties of current package materials may result in a coefficient of thermal expansion (CTE) mismatch between the package substrate and molding compound and any semiconductor die incorporated therein, which requires larger, more widely spaced solder bumps in current package structures to mitigate any warpage resulting from the CTE mismatch. Thus, conventional packages are characterized by low die-to-package area ratios and low overall package bandwidth, resulting in lower overall power efficiency. The methods and apparatus disclosed herein provide a semiconductor device package that overcomes many of the shortcomings associated with conventional package architectures as discussed above.

[0015] 1 shows a flow diagram of an exemplary method 100 of forming a thin form factor semiconductor device package. Method 100 has multiple steps 110, 120, 130, and 140. Each step is described in more detail with reference to FIGS. 2-16L. The method may include one or more additional steps performed before any of the defined steps, between two of the defined steps, or after all of the defined steps (unless the context precludes this possibility).

[0016] Generally, the method 100 includes structuring a substrate to be used as a package frame at step 110, which will be described in more detail with reference to Figures 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, 7A-7D, and 8. At step 120, an embedded die assembly is formed having one or more embedded dies and an insulating layer, which will be described in more detail with reference to Figures 9 and 10A-10K, 11 and 12A-12G, and 22 and 23A-23G. At step 130, one or more interconnects are formed in and / or through the embedded die assembly for interconnecting the embedded die-frame set, which will be described in more detail with reference to Figures 13 and 14A-14H. At step 140, a first redistribution layer is formed on the embedded die assembly to transfer the contacts of the interconnects to desired lateral positions on the embedded die assembly surface. In some embodiments, in addition to the first redistribution layer, one or more additional redistribution layers may be formed before the individual packages are singulated from the embedded die assembly, as will be described in more detail with reference to Figures 15 and 16A-16L, and Figures 1 and 18A-18C.

[0017] Figure 2 shows a flow diagram of an exemplary method 200 for structuring a substrate to be utilized as a frame during the formation of a semiconductor device package. Figures 3A-3D show schematic cross-sectional views of a substrate 302 at various stages of the substrate structuring process 200 depicted in Figure 2. Therefore, for clarity, Figures 2 and 3A-3D are described together herein.

[0018] The method 200 begins at step 210, which corresponds to Figure 3A. A substrate 302 may be a III-V compound semiconductor material, silicon, crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, borosilicate glass, glass, sapphire, alumina, and ceramic. In a particular embodiment, the substrate 302 is a p-type or n-type monocrystalline silicon substrate. In a particular embodiment, the substrate 302 is a p-type or n-type polycrystalline silicon substrate. In another embodiment, the substrate 302 is a p-type or n-type silicon solar substrate. The substrate 302 may further have a polygonal or circular shape. For example, the substrate 302 may comprise a substantially square silicon substrate having a lateral dimension of about 120 mm to about 180 mm, with or without chamfered edges. In another example, the substrate 302 may comprise a circular silicon-containing wafer having a diameter of about 20 mm to about 700 mm, such as about 100 mm to about 500 mm, such as about 300 mm.

[0019] Unless otherwise noted, the embodiments and examples described herein are implemented on a substrate having a thickness of about 50 μm to about 1000 μm, such as about 90 μm to about 780 μm. For example, substrate 302 has a thickness of about 100 μm to about 300 μm, such as about 110 μm to about 200 μm. In another example, substrate 302 has a thickness of about 60 μm to about 160 μm, such as about 80 μm to about 120 μm.

[0020] Prior to step 210, the substrate 302 may be sliced ​​and separated from the bulk material by wire saw cutting, scribing and breaking, mechanical abrasive saw cutting, or laser cutting. Slicing typically causes mechanical defects or deformations in the substrate surface formed therefrom, such as scratches, microcracks, chipping, and other mechanical defects. Thus, the substrate 302 is subjected to a first damage removal process in step 210 to smooth and planarize its surface and remove any mechanical defects in preparation for subsequent structuring and packaging steps. In some embodiments, the substrate 302 may be further thinned by adjusting the process parameters of the first damage removal process. For example, the thickness of the substrate 302 may decrease the longer it is subjected to the first damage removal process.

[0021] The damage removal step in step 210 includes subjecting the substrate 302 to a substrate polishing process and / or an etching process, followed by a rinsing process and a drying process. In some embodiments, step 210 includes a chemical mechanical polishing (CMP) process. In certain embodiments, the etching process is a wet etching process, including a buffered etching process that is selective with respect to removing desired materials (e.g., contaminants and other undesirable compounds). In other embodiments, the etching process is a wet etching process utilizing an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the wet etching process. In certain embodiments, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching.

[0022] In some embodiments, the etching solution is heated to a temperature between about 30° C. and about 100° C., such as between about 40° C. and about 90° C., during the etching process. For example, the etching solution is heated to a temperature of about 70° C. In yet other embodiments, the etching process in step 210 is a dry etching process. An example of a dry etching process is a plasma-based dry etching process. The thickness of the substrate 302 is adjusted by controlling the exposure time of the substrate 302 to an etchant (e.g., an etching solution) used during the etching process. For example, the final thickness of the substrate 302 is thinner as the exposure to the etchant increases. Alternatively, the substrate 302 may have a greater final thickness as the exposure to the etchant decreases.

[0023] In steps 220 and 230, the now planarized and substantially defect-free substrate 302 is patterned with one or more features, such as vias 303 and cavities 305, and smoothed (the cross section of the underside of substrate 302 in FIG. 3B depicts one cavity 305 and four vias 303). The vias 303 are utilized to form direct contact electrical interconnects through substrate 302, and the cavities 305 are utilized to receive and surround (i.e., embed) one or more semiconductor dies therein. Figures 4A-4C, 5A-5C, 6A-6C, and 7A-7B show cross-sectional views of substrate 302 at various stages of a feature formation and damage or defect removal (e.g., smoothing) process according to embodiments described herein. Accordingly, steps 220 and 230 will now be described in more detail with reference to Figures 4A-4C, 5A-5C, 6A-6C, and 7A-7B.

[0024] In embodiments in which the substrate 302 has a thickness of less than about 200 μm, for example, about 100 μm, or about 50 μm, the substrate 302 may first be bonded to an optional carrier plate 406 as depicted in FIGS. 4A and 5A. The carrier plate 406 provides mechanical support to the substrate 302 during the substrate structuring process 200 and prevents breakage of the substrate 302. The carrier plate 406 is formed of any suitable rigid material that is chemically and thermally stable, including, but not limited to, glass, ceramic, metal, and the like. The carrier plate 406 has a thickness of about 1 mm to about 10 mm, for example, about 2 mm to about 5 mm. In certain embodiments, the carrier plate 406 has a textured surface. In other embodiments, the carrier plate 406 has a polished or smoothed surface.

[0025] The substrate 302 may be bonded to the carrier plate 406 via an adhesive layer 408. The adhesive layer 408 may be formed of any suitable temporary bonding material, including, but not limited to, wax, glue, or similar bonding materials. The adhesive layer 408 may be applied onto the carrier plate 406 by mechanical rolling, pressing, lamination, spin coating, or doctor blading. In certain embodiments, the adhesive layer 408 is a water-soluble or solvent-soluble adhesive layer. In other embodiments, the adhesive layer 408 is a UV-release adhesive layer. In yet other embodiments, the adhesive layer 408 is a thermal release adhesive layer. In such embodiments, the bonding properties of the adhesive layer 408 may deteriorate upon thermal treatment, such as exposing the adhesive layer 408 to a temperature above 110° C., e.g., above 150° C. The adhesive layer 408 may further include one or more layers (not shown) of additional films, such as liners, base films, pressure-sensitive films, and other suitable layers.

[0026] In some embodiments, after bonding the substrate 302 to the carrier plate 406, a resist film is applied to the substrate 302 to form the resist layer 404 depicted in Figures 4A and 5A. In embodiments in which the substrate 302 has a thickness greater than about 200 μm, for example about 250 μm, the resist layer 404 is formed on the substrate 302 without first bonding the substrate 302 to the carrier plate 406. The resist layer 404 is used to transfer a desired pattern to the substrate 302 on which the resist layer 404 is formed during a subsequent processing step. When the resist layer 404 is patterned, it protects selected areas of the underlying substrate 302 during subsequent structuring steps.

[0027] The substrate 302 generally has a substantially planar surface on which the resist layer 404 is formed. In some embodiments, such as the embodiment illustrated in FIG. 5A, the resist layer 404 is bonded to the substrate 302 via a resist adhesion layer 409. The resist adhesion layer 409 is formed of any suitable temporary bonding material, including, but not limited to, polyvinyl alcohol, triesters with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and other water-soluble or solvent-soluble materials. In certain embodiments, the resist adhesion layer 409 is formed of a material different from the adhesion layer 408. In certain embodiments, the resist adhesion layer 409 is of substantially similar composition as the adhesion layer 408. The resist adhesion layer 409 is applied onto the substrate 302 by mechanical rolling, pressing, lamination, spin coating, or doctor blading. In other embodiments, the resist layer 404 is formed of a temporary bonding material, such as polyvinyl alcohol, which allows the resist layer 404 to be applied and bonded directly to the surface of the substrate 302. The resist layer 404 may include one or more layers, for example, a first resist layer and a second resist layer (not shown).

[0028] In certain embodiments, such as the embodiment shown in FIG. 4A, the resist layer 404 is a photosensitive layer (e.g., photoresist). The resist layer 404 may include a solvent, a photoresist resin, and a photoacid generator. The photoresist resin may be any positive or negative photoresist resin. Exemplary photoresist resins include acrylates, novolac resins, poly(methyl methacrylate), and poly(olefin sulfone). Other photoresist resins may be used. Upon exposure to electromagnetic radiation, the photoacid generator generates charged species, such as acid cations and acid anions. The photoacid generator may also generate polarized species. The photoacid generator provides the resin with sensitivity to electromagnetic radiation. Exemplary photoacid generators include sulfonate compounds, such as, for example, sulfonated salts, sulfonated esters, and sulfonyloxyketones. Other suitable photoacid generators include onium salts, such as aryl diazonium salts, halonium salts, aromatic sulfonium salts, and sulfoxonium salts, or selenium salts. Other representative photoacid generators include nitrobenzyl esters, s-triazine derivatives, ionic iodonium sulfonates, perfluoroalkanesulfonates, aryl triflates and their derivatives and analogs, pyrogallol derivatives, and alkyl disulfones. Other photoacid generators may also be used. In certain embodiments, such as the embodiment shown in FIG. 5A, the resist layer 404 is a laser-sensitive resist.

[0029] After the formation of the resist layer 404, the substrate 302 with the resist layer 404 formed thereon is exposed to electromagnetic radiation to pattern the resist layer 404 as depicted in FIG. 4B and FIG. 5B. In the embodiment shown in FIG. 4B, the substrate 302 with the resist layer 404 formed thereon is exposed to electromagnetic radiation in the ultraviolet (UV) range. Portions of the resist layer 404 are selectively exposed to UV radiation and portions of the resist layer 404 are selectively not exposed to UV radiation. Upon exposure to UV radiation, the selectively exposed portions of the resist layer 404 are structurally weakened (illustrated by hatching), while the non-selectively exposed portions maintain their structural integrity. In certain embodiments, a mask 412 having a desired pattern is formed on or adjacent to the photosensitive resist layer 404 prior to exposure to UV radiation. In other embodiments, the mask 412 is a reticle that is positioned between the resist layer 404 and a UV radiation source. Mask 412 is configured to transfer a desired pattern of UV radiation into resist layer 404. Mask 412 is formed of any suitable polymeric material, including, but not limited to, PTFE, PVDF, FEP, polyimide, and the like.

[0030] In the embodiment shown in FIG. 5B, the substrate 302 having a laser sensitive resist layer 404 formed thereon is exposed to electromagnetic radiation generated by a laser source 307 instead of a UV radiation source. In this case, patterning is achieved by targeted laser ablation without the use of a mask. The laser source 307 can be any type of laser suitable for patterning the resist layer 404. In some examples, the laser source 307 is a femtosecond green laser. In other examples, the laser source 307 is a femtosecond UV laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning the resist layer 404. For example, the laser source 307 can generate a pulsed laser beam 310 having a frequency between 100 kHz and 1200 kHz, such as between about 200 kHz and about 1000 kHz. The laser source 307 is generally configured to form any desired pattern in the resist layer 404. It is further contemplated that the electromagnetic radiation in operation can alternatively include an electron beam or an ion beam instead of a laser beam.

[0031] The resist layer 404 may be formed of any material that has a suitable hardness after patterning of the resist layer 404, for example, after exposing a negative photoresist to electromagnetic radiation to crosslink materials in the resist. Generally, the resist layer 404 should have one or more desired mechanical properties after patterning (e.g., depositing, exposing, developing) the resist layer 404. In certain embodiments, the resist layer 404 is formed of a material that has a Shore A scale hardness value of 40 to 90, for example, 60 to 70, after patterning. For example, the resist layer 404 is formed of a material that has a Shore A scale hardness value of about 65, after patterning. In certain embodiments, the resist layer 404 is formed of a material that has a tensile strength of about 0.5 MPa to about 10 MPa, for example, about 1 MPa to about 8 MPa, after patterning. For example, the resist layer 404 may be formed of a material that has a tensile strength of about 7 MPa after patterning. In certain embodiments, the resist layer 404 is formed of a polydimethylsiloxane material. In other embodiments, resist layer 404 is formed from polyvinyl alcohol, triesters with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and the like.

[0032] Following patterning of the resist layer 404, the substrate 302 with the resist layer 404 formed thereon is microblasted to form a desired pattern on the substrate 302, as depicted in Figures 4C and 5C. During the microblasting process, a stream of powder particles 309 is propelled toward the substrate 302 by use of a high pressure carrier gas to break off exposed portions of the substrate 302 and / or layers formed thereon. The microblasting process can be carried out using any suitable substrate polishing system.

[0033] The microblasting process is determined by the material properties of the powder particles 309, the momentum of the powder particles impacting the exposed surface of the substrate 302, and the material properties of the substrate 302 and the selectively exposed portions of the resist layer 404, if applicable. Adjustments are made with respect to the type and size of the powder particles 309, the size of the polishing system's applicator nozzle and its distance to the substrate 302, the pressure relative to the velocity and flow rate of the carrier gas utilized to propel the powder particles 309, and the density of the powder particles 309 in the fluid stream to achieve the desired substrate patterning characteristics. For example, the desired fluid pressure of the carrier gas used to propel the powder particles 309 toward the substrate 302 relative to the desired fixed microblasting device nozzle opening size is determined based on the material of the substrate 302 and the powder particles 309. In certain embodiments, the fluid pressure utilized to microblast the substrate 302 ranges from about 50 psi to about 150 psi, such as from about 75 psi to about 125 psi, resulting in carrier gas and particle velocities of about 300 to about 1000 meters per second (m / s), and / or from about 0.001 to about 0.002 cubic meters per second (m 3 A flow rate of about 1000 rpm (m / s) is achieved. For example, the fluid pressure of the inert gas (e.g., nitrogen (N2), CDA, argon) utilized to propel the powder particles 309 during microblasting is about 95 psi to achieve a carrier gas and particle velocity of about 2350 m / s. In a particular embodiment, the applicator nozzle utilized to microblast the substrate 302 has an inner diameter of about 0.1 to about 2.5 millimeters (mm) and is disposed at a distance of about 1 mm to about 5 mm, e.g., about 2 mm to about 4 mm, from the substrate 302. For example, the applicator nozzle is disposed at a distance of about 3 mm from the substrate 302 during microblasting.

[0034] Typically, the microblasting process is performed with powder particles 309 that have sufficient hardness and a high melting point to prevent the particles from adhering upon contact with the substrate 302 and / or any layers formed thereon. For example, the microblasting process is performed utilizing powder particles 309 formed of a ceramic material. In a particular embodiment, the powder particles 309 utilized in the microblasting process are formed of aluminum oxide (Al2O3). In another embodiment, the powder particles 309 are formed of silicon carbide (SiC). Other suitable materials for the powder particles 309 are also contemplated. The powder particles 309 generally range in size from about 15 μm to about 60 μm in diameter, such as from about 20 μm to about 40 μm in diameter. For example, the powder particles 309 have an average particle size of about 27.5 μm in diameter. In another example, the powder particles 309 have an average particle size of about 23 μm in diameter.

[0035] The effectiveness of the microblasting process in step 220 depicted in Figures 4C and 5C further depends on the material properties of the resist layer 404. Utilizing a material with too high a Shore A hardness may result in unwanted bouncing of the powder particles 309 between the sidewalls of the resist layer 404, which may result in a decrease in the rate at which the powder particles 309 impact the substrate 302, and ultimately a decrease in the effectiveness of the powder particles 309 in eroding or detaching exposed areas of the substrate 302. Conversely, utilizing a material with too low a Shore A hardness may result in unwanted adhesion of the powder particles 309 to the resist layer 404. As noted above, it is contemplated that materials for the resist layer 404 may utilize Shore A hardness values ​​of about 40 to about 90.

[0036] In embodiments where the resist layer 404 is a photoresist, such as the embodiment depicted in FIG. 4C, the substrate 302 is not yet exposed to light at the start of the microblasting process. Thus, the powder particles 309 first impact the surface of the photoresist, which causes material to break away and be removed from the UV-exposed, structurally weakened portions of the photoresist. The powder particles 309 eventually penetrate and remove the weakened UV-exposed portions, creating voids in the resist layer 404, such that the desired areas of the substrate 302 are exposed, while other areas remain shielded by the UV-unexposed portions of the photoresist. The microblasting is then continued until the powder particles 309 break away and remove a desired amount or depth of material from the exposed areas of the substrate 302, thereby forming the desired pattern in the substrate 302. In embodiments where the resist layer 404 is patterned by laser ablation, such as the embodiment depicted in FIG. 5C, the desired areas of the substrate 302 are already exposed through the voids in the resist layer 404 prior to the microblasting process. In this case, it is contemplated that minimal or no removal of resist layer 404 occurs during microblasting.

[0037] The above-described process for forming features in the substrate 302 in step 220 may result in undesired mechanical defects such as chipping and cracks on the surface of the substrate 302. Therefore, after performing step 220 for forming desired features in the substrate 302, the substrate 302 is subjected to a second damage removal and cleaning process in step 230 to smooth the surface of the substrate 302 and remove undesired debris, followed by stripping the resist layer 404 from the carrier plate 406 and optional debonding of the substrate 302. Figures 4D-4F and 5D-5F show cross-sectional views of the substrate 302 at various stages of the second damage removal, cleaning, resist stripping, and substrate stripping process according to embodiments described herein. Accordingly, step 230 will now be described in more detail with reference to Figures 4D-4F and 5D-5F.

[0038] The second damage removal process in step 230 is substantially similar to the first damage removal process in step 210 and includes subjecting the substrate 302 to an etching process, followed by rinsing and drying. The etching process proceeds for a predetermined duration to smooth the surface of the substrate 302, particularly the surface that was subjected to the microblasting process. In another embodiment, the etching process is utilized to remove unwanted debris remaining from the microblasting process. Residual powder particles attached to the substrate 302 may be removed during the etching process. Figures 4D and 5D show the substrate 302 after debris removal and surface smoothing.

[0039] In certain embodiments, the etching process is a wet etching process utilizing a buffered etching process that preferentially etches the substrate surface over the material of the resist layer 404. For example, the buffered etching process is selective to polyvinyl alcohol. In other embodiments, the etching process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the wet etching process. In certain embodiments, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching. The etching solution may be further heated to a temperature of about 40° C. to about 80° C. during the etching process, such as about 50° C. to about 70° C. For example, the etching solution is heated to a temperature of about 60° C. The etching process may be isotropic or anisotropic. In yet other embodiments, the etching process in step 230 is a dry etching process. One example of a dry etching process includes a plasma-based dry etching process.

[0040] After the debris is removed and the substrate surface is smoothed, the substrate 302 is subjected to a resist stripping process. The stripping process is utilized to debond the resist layer 404 from the substrate 302, as depicted in FIG. 4E and FIG. 5E. In certain embodiments, a wet process is used to strip the resist layer 404 from the substrate 302 by dissolving / solubilizing the resist adhesion layer 409. Other types of etching processes for stripping the resist adhesion layer 409 are also contemplated. In certain embodiments, a mechanical rolling process is used to physically peel the resist layer 404 or the resist adhesion layer 409 from the substrate 302. In certain embodiments, an ashing process is used to remove the resist layer 404 from the substrate 302, for example, by using an oxygen plasma assisted process.

[0041] After the resist stripping process, the substrate 302 is subjected to an optional carrier debonding process, as depicted in FIG. 4F and FIG. 5F. The use of the carrier stripping process depends on whether the substrate 302 is bonded to a carrier plate 406 and the type of bonding material utilized to bond the substrate 302 and the carrier plate 406. As described above and depicted in FIG. 4A-4F and FIG. 5A-5F, in embodiments in which the substrate 302 has a thickness of less than about 200 μm, the substrate 302 is bonded to the carrier plate 406 for mechanical support during the formation of the features in step 220. The substrate 302 is bonded to the carrier plate 406 via an adhesive layer 408. Thus, after microblasting and subsequent substrate etching and resist stripping, the substrate 302 bonded to the carrier plate 406 is subjected to a carrier stripping process that releases the substrate 302 from the carrier plate 406 by peeling off the adhesive layer 408.

[0042] In certain embodiments, the adhesion layer 408 is released by subjecting the substrate 302 to a bake process. The substrate 302 is exposed to a temperature of about 50° C. to about 300° C., such as a temperature of about 100° C. to about 250° C. For example, the substrate 302 is exposed to a temperature of about 150° C. to about 200° C., such as a temperature of about 160° C., for a desired period of time to release the adhesion layer 408. In other embodiments, the adhesion layer 408 is released by exposing the substrate 302 to UV radiation.

[0043] Figures 4F and 5F show substrate 302 after completion of steps 210-230. The cross-sectional views of substrate 302 in Figures 4F and 5F depict a single cavity 305 formed through the substrate and surrounded on either side by two vias 303. Figure 8 depicts a schematic top view of substrate 302 upon completion of the steps described with reference to Figures 4A-4F and 5A-5F, which are described in more detail below.

[0044] 6A-6E show schematic cross-sectional views of substrate 302 during an alternative sequence of steps 220 and 230 similar to those described above. The alternative sequence depicted for steps 220 and 230 includes patterning substrate 302 on two major surfaces on either side, as opposed to only one surface, which allows for improved efficiency during structuring of substrate 302. The embodiment depicted in FIGS. 6A-6E includes substantially all of the processes described with reference to FIGS. 4A-4F and 5A-5F. For example, FIG. 6A corresponds to FIGS. 4A and 5A, FIG. 6B corresponds to FIGS. 4B and 5B, FIG. 6C corresponds to FIGS. 4C and 5C, FIG. 6D corresponds to FIGS. 4D and 5D, and FIG. 6E corresponds to FIGS. 4F and 5F. Unlike previous embodiments, however, the embodiment of step 220 depicted in Figures 6A-6E includes a substrate 302 having two resist layers 404 formed on opposing major surfaces 606, 608, as opposed to one resist layer 404 formed on a single surface. Thus, the processes performed during steps 210-230 need to be performed at the same time (i.e., simultaneously) or one after the other (i.e., sequentially) on both sides of the substrate during each step. Although Figures 6A-6E only illustrate the formation of vias 303, the processes described herein may also be used to form cavities 305, or cavities 305 and vias 303.

[0045] Accordingly, after the resist layer 404 on one side of the substrate 302, such as the side including the surface 608, is exposed to electromagnetic radiation and patterned, the substrate 302 may optionally be flipped so that the resist layer 404 on the opposing surface 606 is also exposed to electromagnetic radiation and patterned, as depicted in FIG. 6B. Similarly, after performing a microblasting process on the surface 608 of the substrate 302, the substrate 302 may optionally be flipped so that microblasting may be performed on the opposing surface 606, as depicted in FIG. 6C. The substrate 302 is then subjected to a second damage removal and cleaning process and a resist stripping process, as depicted in FIGS. 6D-6E. By utilizing two resist layers 404 on both major surfaces 606, 608 of the substrate 302 and performing a microblasting process on both surfaces 606 and 608, possible tapering of features formed thereon by the microblasting process may be reduced or eliminated, and the efficiency of the process used to structure the substrate 302 may be increased.

[0046] 7A-7D show schematic cross-sectional views of substrate 302 during another alternative sequence of steps 220 and 230, in which a desired pattern is formed on substrate 302 by direct laser ablation. As depicted in FIG. 7A, substrate 302, such as a solar substrate or even a semiconductor wafer, is placed on a stand 706 of a laser ablation system (not shown). Stand 706 can be any suitable rigid surface, flat or textured (e.g., structured), to provide mechanical support to substrate 302 during laser ablation. In some embodiments, stand 706 includes an electrostatic chuck for electrostatically chucking substrate 302 to stand 706. In some embodiments, stand 706 includes a vacuum chuck for vacuum chucking substrate 302 to stand 706. After substrate 302 is placed on stand 706, a desired pattern is formed on substrate 302 by laser ablation, depicted in FIG. 7B.

[0047] The laser ablation system may include any suitable type of laser source 307 for patterning the substrate 302. In some examples, the laser source 307 is an infrared (IR) laser. In some examples, the laser source 307 is a picosecond UV laser. In other examples, the laser source 307 is a femtosecond UV laser. In yet other examples, the laser source 307 is a femtosecond green laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning the substrate 302. For example, the laser source 307 may generate a pulsed laser beam 310 having a frequency of 5 kHz to 500 kHz, such as 10 kHz to about 200 kHz. In one example, the laser source 307 is configured to provide a pulsed laser beam at a wavelength of about 200 nm to about 1200 nm, with a pulse duration of about 10 ns to about 5000 ns, and with a power of about 10 Watts to about 100 Watts. Laser source 307 is configured to form any desired patterns and features in substrate 302 , including cavities 305 and vias 303 .

[0048] Similar to microblasting, the process of direct laser patterning of the substrate 302 may result in undesired mechanical defects, including chipping and cracking, on the surface of the substrate 302. In this case, after direct laser patterning to form the desired features on the substrate 302, the substrate 302 is subjected to a second damage removal and cleaning process substantially similar to the embodiment described above. Figures 7C-7D show the structured substrate 302 before and after performing the second damage removal and cleaning process, which results in a smoothed substrate 302 with one cavity 305 and four vias 303 formed therein.

[0049] 2 and 3D, after removing mechanical defects in the substrate 302 in step 230, in certain embodiments, the substrate 302 may be subjected to an oxidation process in step 240 to grow or deposit an insulating oxide film (i.e., layer) 314 on a desired surface thereof. For example, the oxide film 314 may be formed on all surfaces of the substrate 302 such that it surrounds the substrate 302. The insulating oxide film 314 acts as a passivation layer on the substrate 302, providing an outer protective barrier against corrosion and other forms of damage. In certain embodiments, the oxidation process is a thermal oxidation process. The thermal oxidation process is performed at a temperature between about 800° C. and about 1200° C., such as between about 850° C. and about 1150° C. For example, the thermal oxidation process is performed at a temperature between about 900° C. and about 1100° C., such as between about 950° C. and about 1050° C. In certain embodiments, the thermal oxidation process is a wet oxidation process utilizing water vapor as an oxidizing agent. In certain embodiments, the thermal oxidation process is a dry process that utilizes molecular oxygen as the oxidizing agent. It is contemplated that in step 240, the substrate 302 may be subjected to any suitable oxidation process to form an oxide film 314 on its surface. The oxide layer 314 generally has a thickness of about 100 nm to about 3 μm, such as about 200 nm to about 2.5 μm. For example, the oxide film 314 has a thickness of about 300 nm to about 2 μm, such as about 1.5 μm.

[0050] In certain embodiments, the substrate 302 is subjected to a metallization process in step 240 to form a metal clad layer 316 on one or more surfaces thereof. In certain embodiments, the metal clad layer 316 is formed on substantially all of the outer surfaces of the substrate 302 such that the metal clad layer 316 substantially surrounds the substrate 302. The metal clad layer 316 functions as a reference layer (e.g., a ground layer or a voltage supply layer) and is disposed on the substrate 302 to protect subsequently formed interconnects from electromagnetic interference and to shield electrical signals from the semiconductor material (Si) used to form the substrate 302. In certain embodiments, the metal clad layer 316 comprises a conductive metal layer including nickel, aluminum, gold, cobalt, silver, palladium, tin, and the like. In certain embodiments, the metal clad layer 316 comprises a metal layer including an alloy or pure metal including nickel, aluminum, gold, cobalt, silver, palladium, tin, and the like. Metal cladding layer 316 typically has a thickness of about 50 nm to about 10 μm, for example, about 100 nm to about 5 μm.

[0051] In a particular example, at least a portion of the metal cladding layer 316 comprises a deposited nickel (Ni) layer formed by direct displacement plating or displacement plating on the surface of the substrate 302 (e.g., n-Si substrate or p-Si substrate). For example, the substrate 302 is subjected to a nickel displacement plating bath having a composition including 0.5 M NiSO4 and NH4OH at a temperature of about 60° C. to about 95° C. and a pH of about 11 for a period of about 2 to about 4 minutes. When the silicon substrate 302 is exposed to an aqueous electrolyte with added nickel ions in the absence of a reducing agent, a localized oxidation / reduction reaction occurs at the surface of the substrate 302, resulting in plating of metallic nickel on the surface. In this case, nickel displacement plating allows for selective formation of a pure thin nickel layer on the silicon material of the substrate 400 using a stable solution. Furthermore, the process is self-limiting, and thus the reaction stops once the entire surface of the substrate 302 is plated (e.g., when there is no silicon available on the surface to form nickel). In certain embodiments, the nickel metal clad layer 316 may be utilized as a seed layer for plating additional metal layers, such as nickel or copper by electroless and / or electrolytic plating processes. In further embodiments, the substrate 302 is exposed to an SC-1 pre-clean solution and an HF oxide etch solution prior to the nickel displacement plating bath to promote adhesion of the nickel metal clad layer 316 to the substrate 302.

[0052] In a subsequent packaging step, the metal clad layer 316 may be bonded to one or more connection points, e.g., interconnects, formed in the resulting semiconductor device package for connecting the metal clad layer 316 to a common ground. For example, interconnects may be formed on one or both sides of the resulting semiconductor device package to connect the metal clad layer 316 to ground. Alternatively, the metal clad layer 316 may be connected to a reference voltage, such as a power supply voltage.

[0053] FIG. 8 illustrates a schematic top view of an exemplary structured substrate 302 according to one embodiment. Substrate 302 may be structured during steps 210-240 as described above with reference to FIGS. 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, and 7A-7D. Substrate 302 is illustrated as having two quadrilateral cavities 305, each cavity 305 surrounded by a plurality of vias 303. In a particular embodiment, each cavity 305 is surrounded by two rows 801, 802 of vias 303 disposed along each edge 306a-d of quadrilateral cavity 305. Although ten vias 303 are depicted in each row 801, 802, it is contemplated that any desired number of vias 303 may be formed in a row. Additionally, any desired number and arrangement of cavities 305 and vias 303 may be formed in the substrate 302 during step 220. For example, the substrate 302 may have more than two or fewer cavities 305 formed therein. In another example, the substrate 302 may have more than two or fewer rows of vias 303 formed along each edge 306a-d of the cavity 305. In another example, the substrate 302 may have more than two rows of vias 303, where the vias 303 in each row are staggered with the vias 303 in another row, and are not aligned in a row.

[0054] In certain embodiments, the cavities 305 and vias 303 have a depth equal to the thickness of the substrate 302, resulting in holes being formed on both surfaces of the substrate 302 (e.g., through the thickness of the substrate 302). For example, the cavities 305 and vias 303 formed in the substrate 302 may have a depth of about 50 μm to about 1 mm, such as about 100 μm to about 200 μm, such as about 110 μm to about 190 μm, depending on the thickness of the substrate 302. In other embodiments, the cavities 305 and / or vias 303 may have a depth equal to or less than the thickness of the substrate 302, resulting in holes being formed on only one surface (e.g., side) of the substrate 302.

[0055] In certain embodiments, each cavity 305 has a lateral dimension ranging from about 3 mm to about 50 mm, e.g., from about 8 mm to about 12 mm, e.g., from about 9 mm to about 11 mm, depending on the size of one or more semiconductor dies 1026 (shown in FIG. 10B) to be embedded therein during package fabrication (described in more detail below). Semiconductor dies generally include multiple integrated electronic circuits formed on and / or within a substrate material, such as a semiconductor material. In certain embodiments, the cavity 305 is sized to have a lateral dimension substantially similar to the lateral dimension of the die 1026 to be embedded therein. For example, each cavity 305 is formed with a lateral dimension that exceeds the lateral dimension of the die 1026 by less than about 150 μm, e.g., less than about 120 μm, e.g., less than about 100 μm. Reducing the variation in size of the cavities 305 and the dies 1026 to be embedded therein reduces the amount of gap filler material subsequently used.

[0056] In certain embodiments, each via 303 has a diameter in the range of about 50 μm to about 200 μm, such as about 60 μm to about 130 μm, such as about 80 μm to about 110 μm. The minimum pitch 807 between the center of a via 303 in row 801 and the center of an adjacent via 303 in row 802 is about 70 μm to about 200 μm, such as about 85 μm to about 160 μm, such as about 100 μm to about 140 μm. Although the embodiment is described with reference to FIG. 8, steps 210-240 and the substrate structuring process described above with reference to FIGS. 2, 3A-3B, 4A-4C, 5A-5C, 6A-6C, and 7A-7B can be utilized to form patterned features having any desired depth, lateral dimension, and morphology in substrate 302.

[0057] After structuring the substrate 302, one or more packages are formed around the substrate 302 by utilizing the substrate 302 as a frame. Figures 9 and 11 respectively show flow diagrams of representative methods 900 and 1100 for manufacturing an intermediate embedded die assembly 1002 around the substrate 302 prior to final package formation. Figures 10A-10K generally show cross-sectional views of the substrate 302 at various stages of the method 900 depicted in Figure 9, and Figures 12A-12G generally show cross-sectional views of the substrate 302 at various stages of the method 1100 depicted in Figure 11. For clarity, Figures 9 and 10A-10K are described herein together, and Figures 11 and 12A-12G are described herein together.

[0058] Generally, the method 900 begins with step 902 and FIG. 10A, where a first side 1075 of the substrate 302, at this point having desired features formed thereon (e.g., surface 606 on which an oxide layer or metal clad layer may be formed), is disposed on a first insulating film 1016a. In certain embodiments, the first insulating film 1016a includes one or more layers formed of a polymer-based dielectric material. For example, the first insulating film 1016a includes one or more layers formed of a flowable build-up material. In the embodiment depicted in FIG. 10A, the first insulating film 1016a includes a flowable layer 1018a. The flowable layer 1018a may be formed of a ceramic filler-containing epoxy resin, such as an epoxy resin filled (e.g., containing) silica (SiO2) particles. Other examples of ceramic fillers or particles that may be utilized to form the flowable layer 1018a and other layers of the insulating film 1016a include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 , Zirconium silicate (ZrSiO4), Wollastonite (CaSiO3), Beryllium oxide (BeO), Cerium dioxide (CeO2), Boron nitride (BN), Calcium copper titanium oxide (CaCu3Ti4O 12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), and the like. In some examples, the ceramic filler utilized to form the flowable layer 1018a has particles with a size ranging from about 40 nm to about 1.5 μm, such as from about 80 nm to about 1 μm. For example, the ceramic filler utilized to form the flowable layer 1018a has particles with a size ranging from about 200 nm to about 800 nm, such as from about 300 nm to about 600 nm. In some embodiments, the ceramic filler utilized to form the flowable layer 1018a includes particles with a size less than about 25% of the width or diameter of a desired feature (e.g., a via, a cavity, or a through-assembly via), such as less than about 15% of the width or diameter of a desired feature.

[0059] The flowable layer 1018a typically has a thickness of less than about 60 μm, e.g., between about 5 μm and about 50 μm. For example, the flowable layer 1018a has a thickness of between about 10 μm and about 25 μm. In certain embodiments, the insulating film 1016a further comprises one or more support layers. For example, the insulating film 1016a comprises a support layer 1022a of polyethylene terephthalate (PET) or a similar lightweight plastic. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1016a. In some embodiments, the insulating film 1016a has an overall thickness of less than about 120 μm, e.g., less than about 90 μm.

[0060] The substrate 302 is bonded on its first side 1075 to the insulating film 1016a, specifically to the flowable layer 1018a of the insulating film 1016a, and may be optionally disposed on a carrier 1024 for mechanical support during subsequent processing steps. The carrier is formed of any suitable material that is mechanically and thermally stable. For example, the carrier 1024 is formed of polytetrafluoroethylene (PTFE). In another example, the carrier 1024 is formed of PET.

[0061] In step 904, as depicted in FIG. 10B, one or more semiconductor dies 1026 are placed into the cavity 305 formed in the substrate 302 such that the semiconductor die 1026 is now affixed to the insulating film 1016a on one side (a single semiconductor die 1026 is depicted in FIG. 10B). In certain embodiments, the die 1026 is a multi-purpose die having integrated circuits formed on its active surface 1028. The die 1026 is placed into the cavity 305 and positioned on a surface of the insulating film 1016a exposed through the cavity 305. In certain embodiments, the die 1026 is placed on an adhesion layer (not shown) disposed or formed on the insulating film 1016a.

[0062] After disposing the die 1026 in the cavity 305, a first protective film 1060 is disposed on the second side 1077 (e.g., surface 608) of the substrate 302 in step 906 and FIG. 10C. The protective film 1060 is bonded to the second side 1077 of the substrate 302 opposite the first insulating film 1016a such that the protective film 1060 contacts and covers the active surface 1028 of the die 1026 disposed in the cavity 305. In certain embodiments, the protective film 1060 is formed of a material similar to that of the support layer 1022a. For example, the protective film 1060 is formed of PET, such as biaxial PET. However, the protective film 1060 may be formed of any suitable protective material. In some embodiments, the protective film 1060 has a thickness of about 50 μm to about 150 μm.

[0063] The substrate 302, now attached to the insulating film 1016a on the first side 1075 and the protective film 1060 on the second side 1077, and with the die 1026 disposed therein, is subjected to a lamination process in step 908. During the lamination process, the substrate 302 is exposed to high temperatures, which causes the flowable layer 1018a of the insulating film 1016a to soften and flow into the open voids or volumes between the insulating film 1016a and the protective film 1060, for example, into the gaps 1051 between the inner walls of the vias 303 and cavities 305 and the die 1026. In response, the semiconductor die 1026 becomes at least partially embedded within the material of the insulating film 1016a and the substrate 302, as depicted in FIG.

[0064] In certain embodiments, the lamination process is a vacuum lamination process, which may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80° C. to about 140° C. for a period of about 5 seconds to about 1.5 minutes, such as about 30 seconds to about 1 minute. In some embodiments, the lamination process includes applying a pressure of about 1 psig to about 50 psig to the substrate 302 and the insulating film 1016a while applying a temperature of about 80° C. to about 140° C. for a period of about 5 seconds to about 1.5 minutes. For example, the lamination process is performed at a temperature of about 100° C. to about 120° C., at a pressure of about 5 psig to about 40 psig, for a period of about 10 seconds to about 1 minute. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 20 seconds.

[0065] In step 910, the protective film 1060 is removed and the substrate 302, with the laminated insulating material of the flowable layer 1018a now at least partially surrounding the substrate 302 and one or more dies 1026, is placed on the second protective film 1062. As depicted in FIG. 10E, the second protective film 1062 is bonded to a first side 1075 of the substrate 302 such that the second protective film 1062 is disposed against (e.g., adjacent to) the support layer 1022a of the insulating film 1016a. In some embodiments, the substrate 302, now bonded to the protective film 1062, may be optionally placed on a carrier 1024 to provide additional mechanical support at the first side 1075. In some embodiments, the protective film 1062 is placed on the carrier 1024 prior to bonding the protective film 1062 to the substrate 302, now laminated with the insulating film 1016a. Generally, protective film 1062 is of substantially the same composition as protective film 1060. For example, protective film 1062 may be formed of PET, such as biaxial PET. However, protective film 1062 may be formed of any suitable protective material. In some embodiments, protective film 1062 has a thickness of about 50 μm to about 150 μm.

[0066] Once the substrate 302 is bonded to the second protective film 1062, in step 912 and FIG. 10F, a second insulating film 1016b substantially similar to the first insulating film 1016a is disposed on the second side 1077 of the substrate 302, thereby replacing the protective film 1060. In certain embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 such that the flowable layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the die 1026 in the cavity 305. In certain embodiments, disposing the second insulating film 1016b on the substrate 302 may form one or more voids between the insulating film 1016b and the already deposited insulating material of the flowable layer 1018a that partially surrounds the one or more die 1026. The second insulating film 1016b may include one or more layers formed of a flowable polymer-based dielectric material. 10F, the second insulating film 1016b includes a flowable layer 1018b similar to the flowable layer 1018a described above. The second insulating film 1016b may further include a support layer 1022b formed of a material similar to the support layer 1022a, such as PET or other lightweight plastic material.

[0067] In step 914, a third protective film 1064 is disposed over the second insulating film 1016b, as depicted in FIG. 10G. Generally, the protective film 1064 is of substantially similar composition to the protective films 1060, 1062. For example, the protective film 1064 is formed of PET, such as biaxial PET. However, the protective film 1064 may be formed of any suitable protective material. In some embodiments, the protective film 1064 has a thickness of about 50 μm to about 150 μm.

[0068] The substrate 302, now attached to the insulating film 1016b and support layer 1064 on the second side 1077, and to the protective film 1062 and optional carrier 1024 on the first side 1075, is subjected to a second lamination process in step 916 and Figure 10H. Similar to the lamination process in step 908, the substrate 302 is exposed to high temperatures which causes the flowable layer 1018b of the insulating film 1016b to soften and flow into any open voids or volumes between the insulating film 1016b and the already deposited insulating material of the flowable layer 1018a, thereby integrating the insulating material of the flowable layer 1018a with the flowable layer 1018b. As a result, the cavity 305 and the via 303 become filled (e.g., packed, sealed) with the insulating material, and the semiconductor die 1026 previously placed in the cavity 305 becomes completely embedded within the insulating material of the flowable layers 1018a, 1018b.

[0069] In certain embodiments, the lamination process is a vacuum lamination process, which may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. In some embodiments, the lamination process includes applying a pressure of about 10 psig to about 150 psig to the substrate 302 and the insulating film 1016b while applying a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. For example, the lamination process is performed at a temperature of about 100° C. to about 120° C., at a pressure of about 20 psig to about 100 psig, for a period of about 2 minutes to about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes.

[0070] After lamination, in step 918, the substrate 302 is removed from the carrier 1024 and the protective films 1062, 1064 are removed to obtain the laminated embedded die assembly 1002. As depicted in FIG. 10I, the embedded die assembly 1002 includes a substrate 302 having one or more cavities 305 and / or vias 303 formed therein that are filled with an insulating dielectric material of the flowable layers 1018a, 1018b, and an embedded die 1026 in the cavity 305. The insulating dielectric material of the flowable layers 1018a, 1018b surrounds the substrate 302 such that the insulating material covers at least two surfaces or faces of the substrate 302, e.g., the two major surfaces 606, 608, and covers all sides of the embedded semiconductor die 1026. In some examples, in step 918, the support layers 1022a, 1022b are also removed from the embedded die assembly 1002. Generally, the support layers 1022a and 1022b, the carrier 1024, and the overcoats 1062 and 1064 are removed from the embedded die assembly 1002 by any suitable mechanical process, such as by peeling therefrom.

[0071] Once the support layers 1022a, 1022b and protective films 1062, 1064 are removed, the embedded die assembly 1002 is subjected to a curing process to fully cure (i.e., harden by chemical reaction and cross-linking) the insulating dielectric material of the flowable layers 1018a, 1018b, resulting in the formation of a hardened insulating layer 1018. The insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor die 1026 embedded therein. For example, the insulating layer 1018 contacts or encapsulates at least the sides 1075, 1077 of the substrate 302 (including the surfaces 606, 608) and at least six faces or surfaces of each of the semiconductor die 1026, which has a rectangular prism shape as shown in FIG. 10I (i.e., only four surfaces 1028 and 1029 are shown in a 2D view).

[0072] In certain embodiments, the curing process is performed at an elevated temperature such that the embedded die assembly 1002 is fully cured. For example, the curing process is performed at a temperature of about 140° C. to about 220° C. for a period of about 15 minutes to about 45 minutes, such as at a temperature of about 160° C. to about 200° C. for a period of about 25 minutes to about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process in step 918 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0073] After curing, at step 920, one or more through-assembly vias 1003 are drilled through the embedded die assembly 1002 to form channels through the entire thickness of the embedded die assembly 1002 for subsequent interconnect formation. In some embodiments, the embedded die assembly 1002 may be placed on a carrier, such as carrier 1024, to provide mechanical support during formation of the through-assembly vias 1003 and subsequent contact hole 1032. The through-assembly vias 1003 are drilled through vias 303 formed in the substrate 302 and then filled with an insulating layer 1018. As a result, the through-assembly vias 1003 may be circumferentially surrounded by the insulating layer 1018 filled within the vias 303. By lining the walls of the vias 303 with the ceramic filler-containing epoxy resin material of the insulating layer 1018, capacitive coupling between the conductive silicon base substrate 302 and the interconnects 1444 (described with reference to FIG. 13 and FIGS. 14E-14H), and therefore capacitive coupling between adjacently positioned vias 303 and / or redistribution connections 1644 (described with reference to FIG. 15 and FIGS. 16H-16L) in the completed package 1602 (described with reference to FIG. 15 and FIGS. 16K-16L), is significantly reduced as compared to other conventional interconnect structures that utilize conventional via insulating liners or films. Furthermore, the flowable nature of the epoxy resin material allows for more consistent and reliable encapsulation and insulation, thereby enhancing electrical performance by minimizing leakage current in the completed package 1602.

[0074] In certain embodiments, the through assembly via 1003 has a diameter of less than about 100 μm, such as less than about 75 μm. For example, the through assembly via 1003 has a diameter of less than about 60 μm, such as less than about 50 μm. In certain embodiments, the through assembly via 1003 has a diameter of about 25 μm to about 50 μm, such as a diameter of about 35 μm to about 40 μm. In certain embodiments, the through assembly via 1003 is formed using any suitable mechanical process. For example, the through assembly via 1003 is formed using a mechanical drilling process. In certain embodiments, the through assembly via 1003 is formed through the embedded die assembly 1002 by laser ablation. For example, the through assembly via 1003 is formed using an ultraviolet laser. In certain embodiments, the laser source utilized for laser ablation has a frequency of about 5 kHz to about 500 kHz. In certain embodiments, the laser source is configured to provide a pulsed laser beam with a pulse energy of about 50 microjoules (μJ) to about 500 μJ and a pulse duration of about 10 ns to about 100 ns. Utilizing an epoxy resin material with small ceramic filler particles further facilitates more precise and accurate laser patterning of small diameter vias, such as via 1003, because the inclusion of small ceramic filler particles reduces reflection, scattering, diffraction of laser light during the laser ablation process, and transmission of laser light away from the area where the via is to be formed.

[0075] In step 922 and FIG. 10K, one or more contact holes 1032 are drilled through the insulating layer 1018 to expose one or more contacts 1030 formed on the active surface 1028 of each embedded die 1026. The contact holes 1032 are drilled through the insulating layer 1018 by laser ablation, such that all outer surfaces of the semiconductor die 1026 are covered and surrounded by the insulating layer 1018, and the contacts 1030 are exposed. Thus, the contacts 1030 are exposed by the formation of the contact holes 1032. In certain embodiments, the laser source may generate a pulsed laser beam having a frequency of about 100 kHz to about 1000 kHz. In certain embodiments, the laser source is configured to provide a pulsed laser beam at a wavelength of about 100 nm to about 2000 nm, with a pulse duration of about 10E-4 ns to about 10E-2 ns, and with a pulse energy of about 10 μJ to about 300 μJ. In certain embodiments, the contact holes 1032 are drilled using a CO2 laser, a green laser, or a UV laser. In certain embodiments, the contact holes 1032 have a diameter of about 5 μm to about 60 μm, for example, a diameter of about 20 μm to about 50 μm.

[0076] In step 922, after the formation of the contact holes 1032, the embedded die assembly 1002 is subjected to a desmear process to remove any unwanted residue and / or debris caused by laser ablation during the formation of the through-assembly vias 1003 and the contact holes 1032. The desmear process thus cleans the through-assembly vias 1003 and the contact holes 1032 and fully exposes the contacts 1030 on the active surface 1028 of the embedded die 1026 for subsequent metallization. In a particular embodiment, the desmear process is a wet desmear process. The wet desmear process may utilize any suitable aqueous etchant, solvent, and / or combination thereof. As an example, a potassium permanganate (KMnO4) solution may be utilized as the etchant. Depending on the thickness of the residue, the application of the wet desmear process to the embedded die assembly 1002 in step 922 may be modified. In another embodiment, the desmear process is a dry desmear process. For example, the desmear process may be a plasma desmear process with an O2:CF4 gas mixture. The plasma desmear process may include generating a plasma by applying a power of about 700 W and flowing O2:CF4 at a ratio of about 10:1 (e.g., 100:10 sccm) for a time period between about 60 seconds and about 120 seconds. In a further embodiment, the desmear process is a combination of wet and dry processes.

[0077] After the desmear process in step 922, the embedded die assembly 1002 is ready for formation of interconnect paths, which will be described below with reference to Figures 13 and 14A-14H.

[0078] As discussed above, Figures 9 and 10A-10K illustrate an exemplary method 900 for forming an intermediate embedded die assembly 1002. Figures 11 and 12A-12G illustrate an alternative method 1100 that is substantially similar to method 900 but has fewer steps. Method 1100 generally includes seven steps 1110-1170, except that steps 1110, 1120, 1160, and 1170 of method 1100 are substantially similar to steps 902, 904, 920, and 922, respectively, of method 900. Thus, for clarity, only steps 1130, 1140, and 1150, depicted in Figures 12C, 12D, and 12E, respectively, are described herein.

[0079] After disposing one or more semiconductor dies 1026 on the surface of the insulating film 1016a exposed through the cavity 305, a second insulating film 1016b is positioned on the second side 1077 (e.g., surface 608) of the substrate 302 in step 1130 and FIG. 12C prior to lamination. In some embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 such that the flowable layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the die 1026 in the cavity 305. In some embodiments, a second carrier 1025 is affixed to the support layer 1022b of the second insulating film 1016b to provide additional mechanical support during subsequent processing steps. As depicted in FIG. 12C, one or more voids 1050 are formed between the insulating film 1016a and the insulating film 1016b through the via 303 and the gap 1051 between the semiconductor die 1026 and the inner wall of the cavity 305.

[0080] In step 1140 and FIG. 12D, the substrate 302, now attached to the insulating films 1016a and 1016b and having the die 1026 disposed thereon, is subjected to a single lamination process. During the single lamination process, the substrate 302 is exposed to high temperatures, which causes the flowable layers 1018a and 1018b of both insulating films 1016a, 1016b to soften and flow into the open voids or volumes between the insulating films 1016a, 1016b, for example, into the vias 303 and into the gaps 1051 between the inner walls of the cavity 305 and the die 1026. In this way, the semiconductor die 1026 becomes embedded in the material of the insulating films 1016a, 1016b and the vias 303 become filled with this material.

[0081] Similar to the lamination process described with reference to FIG. 9 and FIG. 10A-10K, the lamination process in step 1140 may be a vacuum lamination process, which may be performed in an autoclave or other suitable device. In another embodiment, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. In some embodiments, the lamination process includes applying a pressure of about 1 psig to about 150 psig to the substrate 302 and the layers of insulating film 1016a, 1016b while applying a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. For example, the lamination process is performed at a temperature of about 100° C. to about 120° C., at a pressure of about 10 psig to about 100 psig, for a period of about 2 minutes to about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes.

[0082] In step 1150, one or more support layers of the insulating films 1016a and 1016b are removed from the substrate 302, resulting in a stacked embedded die assembly 1002. As depicted in FIG. 12E, the embedded die assembly 1002 includes a substrate 302 having one or more cavities 305 and / or vias 303 formed therein that are filled with the insulating dielectric material of the flowable layers 1018a, 1018b, and an embedded die 1026 within the cavity 305. The insulating material surrounds the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302, e.g., surfaces 606, 608. In one example, the support layers 1022a, 1022b are removed from the embedded die assembly 1002, resulting in the embedded die assembly 1002 being removed from the carriers 1024, 1025. Generally, the support layers 1022a, 1022b and carriers 1024, 1025 are removed therefrom by any suitable mechanical process, such as by peeling.

[0083] Once the support layers 1022a, 1022b are removed, the embedded die assembly 1002 is subjected to a curing process to fully harden the insulating dielectric material of the flowable layers 1018a, 1018b. The hardening of the insulating material forms a hardened insulating layer 1018. As depicted in Figure 12E and similar to step 918 corresponding to Figure 10I, the insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor die 1026 embedded therein.

[0084] In certain embodiments, the curing process is performed at an elevated temperature such that the embedded die assembly 1002 is fully cured. For example, the curing process is performed at a temperature of about 140° C. to about 220° C. for a period of about 15 minutes to about 45 minutes, such as at a temperature of about 160° C. to about 200° C. for a period of about 25 minutes to about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process in step 1150 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0085] After curing at step 1150, method 1100 is substantially similar to steps 920 and 922 of method 900. For example, embedded die assembly 1002 has one or more through-assembly vias 1003 and one or more contact holes 1032 drilled through insulating layer 1018. Embedded die assembly 1002 then undergoes a desmear process after which embedded die assembly 1002 is ready for forming interconnect paths therein, as described below.

[0086] Figure 13 illustrates a flow diagram of an exemplary method 1300 of forming electrical interconnects through an embedded die assembly 1002. Figures 14A-14H illustrate schematic cross-sectional views of the embedded die assembly 1002 at various stages in the process of the method 1300 depicted in Figure 13. Thus, for clarity, Figure 13 and Figures 14A-14H are described herein together.

[0087] In a particular embodiment, the electrical interconnects formed through the embedded die assembly 1002 are formed of copper. In this case, the method 1300 may optionally begin with step 1310 and FIG. 14A, where an adhesion layer 1440 and / or a seed layer 1442 are formed on the surface of the embedded die assembly 1002 in which the through-assembly vias 1003 and the contact holes 1032 are formed. A close-up view of a portion of the adhesion layer 1440 and the seed layer 1442 formed on the embedded die assembly 1002 is depicted for reference in FIG. 14H. The adhesion layer 1440 may be formed on the desired surfaces of the insulating layer 1018, such as the major surfaces 1005, 1007 of the embedded die assembly 1002, as well as on the active surfaces 1028 of the contact holes 1032 on each die 1026 and the inner walls of the through-assembly vias 1003, to help promote adhesion and inhibit diffusion of the subsequently formed seed layer 1442 and copper interconnects 1444. As a result, in certain embodiments, adhesive layer 1440 functions as an adhesive layer, and in other embodiments, adhesive layer 1440 functions as a barrier layer, although in either embodiment, adhesive layer 1440 will be referred to hereinafter as an "adhesive layer."

[0088] In certain embodiments, optional adhesion layer 1440 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material, or combinations thereof. In certain embodiments, adhesion layer 1440 has a thickness of about 10 nm to about 300 nm, such as about 50 nm to about 150 nm. For example, adhesion layer 1440 has a thickness of about 75 nm to about 125 nm, such as about 100 nm. Adhesion layer 1440 is formed by any suitable deposition process, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), and the like.

[0089] An optional seed layer 1442 may be formed on the adhesion layer 1440 or directly on the insulating layer 1018 (e.g., without forming an adhesion layer 1440). The seed layer 1442 is formed of a conductive material, such as copper, tungsten, aluminum, silver, gold, or other suitable material, or a combination thereof. In certain embodiments, the seed layer 1442 has a thickness of about 50 nm to about 500 nm, such as about 100 nm to about 300 nm. For example, the seed layer 1442 has a thickness of about 150 nm to about 250 nm, such as about 200 nm. In certain embodiments, the seed layer 1442 has a thickness of about 0.1 μm to about 1.5 μm. Similar to the adhesion layer 1440, the seed layer 1442 is formed by any suitable deposition process, such as dry processes CVD, PVD, PECVD, ALD, wet electroless plating processes, etc. In a particular embodiment, a molybdenum adhesion layer 1440 is formed on the embedded die assembly in combination with a copper seed layer 1442. The Mo-Cu adhesion and seed layer combination allows for improved adhesion to the surface of the insulating layer 1018 and reduces undercutting of the conductive interconnect lines during the subsequent seed layer etching process in step 1370.

[0090] In steps 1320 and 1330, corresponding to Figures 14B and 14C, respectively, a spin-on / spray-on resist film or dry resist film 1450, e.g., photoresist, is applied onto both major surfaces 1005, 1007 of the embedded die assembly 1002 and subsequently patterned. In certain embodiments, the resist film 1450 is patterned via selective exposure to UV radiation. In certain embodiments, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 prior to forming the resist film 1450. The adhesion promoter improves adhesion of the resist film 1450 to the embedded die assembly 1002 by creating an interfacial bonding layer for the resist film 1450 and by removing any moisture from the surface of the embedded die assembly 1002. In some embodiments, the adhesion promoter is formed of bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0091] In step 1340 and FIG. 14D, the embedded die assembly 1002 is subjected to a resist film developing process. As depicted in FIG. 14D, the development of the resist film 1450 results in the exposure of the through-assembly vias 1003 and contact holes 1032, which now have an adhesion layer 1440 and a seed layer 1442 formed thereon. In certain embodiments, the film developing process is a wet process, such as a wet process that includes exposing the resist to a solvent. In certain embodiments, the film developing process is a wet etching process that utilizes an aqueous etching process. In other embodiments, the film developing process is a wet etching process that utilizes a buffered etching process that is selective to the desired material. Any suitable wet solvent or combination of wet etchants may be used for the resist film developing process.

[0092] In steps 1350 and 1360, corresponding to Figures 14E and 14F, respectively, interconnects 1444 are formed through the exposed through-assembly vias 1003 and contact holes 1032, and then the resist film 1450 is removed. The interconnects 1444 are formed by any suitable method, including electroplating and electroless plating. In certain embodiments, the resist film 1450 is removed via a wet process. As depicted in Figures 14E and 14F, the formed interconnects 1444 fill and / or cover the inner walls of the through-assembly vias 1003 and contact holes 1032, and protrude from the surfaces 1005, 1007, and 1028 of the embedded die assembly 1002 when the resist film 1450 is removed. In certain embodiments, the interconnects 1444 are formed of copper. In other embodiments, the interconnects 1444 may be formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, and the like.

[0093] In step 1370 and FIG. 14G, the embedded die assembly 1002 with the interconnects 1444 formed thereon is subjected to an adhesion layer and / or seed layer etch process to remove the adhesion layer 1440 and the seed layer 1442. In certain embodiments, the seed layer etch is a wet etch process that includes rinsing and drying the embedded die assembly 1002. In certain embodiments, the seed layer etch process is a buffered etch process that is selective to a desired material, such as copper, tungsten, aluminum, silver, or gold. In other embodiments, the etch process is an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etch process.

[0094] Following the seed layer etching process in step 1370, one or more electrically functional packages may be singulated from the embedded die assembly 1002. Alternatively, the embedded die assembly 1002 may have one or more redistribution layers 1658 and / or 1660 (shown in FIGS. 16K-16L) formed on its surface as needed to enable rerouting of the contacts of the interconnects 1444 to desired locations on the surface of the embedded die assembly 1002. FIG. 15 illustrates a flow diagram of an exemplary method 1500 of forming a redistribution layer 1658 on the embedded die assembly 1002. FIGS. 16A-16L illustrate schematic cross-sectional views of the embedded die assembly 1002 at various stages of the method 1500 depicted in FIG. 15. Thus, for clarity, FIGS. 15 and 16A-16L are described herein together.

[0095] Method 1500 is substantially similar to methods 900, 1100, and 1300 described above. Generally, method 1500 begins with step 1502 and FIG. 16A, where an insulating film 1616 is placed on and then laminated to the embedded die assembly 1002. The insulating film 1616 may be substantially similar to the insulating film 1016 and includes one or more layers formed of a polymer-based flowable dielectric material. In a particular embodiment, as depicted in FIG. 16A, the insulating film 1616 includes a flowable layer 1618 and one or more support layers 1622. In a particular embodiment, the insulating film 1616 may include a flowable layer 1618 of a ceramic filler-containing epoxy resin and one or more support layers 1622. In another example, the insulating film 1616 may include a flowable layer 1618 of a photosensitive polyimide and one or more support layers 1622. The material properties of photosensitive polyimide allow for smaller (e.g., narrower) vias to be formed through the resulting interconnect layer formed from the photosensitive polyimide. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1616. For example, the insulating film 1616 may include a flowable layer 1618 of non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide, and / or silicon nitride. Examples of suitable materials for the support layer(s) 1622 include PET and polypropylene (PP).

[0096] In some examples, the flowable layer 1618 comprises a different polymer-based flowable dielectric material than the flowable layers 1018a, 1018b described above. For example, the flowable layer 1018 may comprise a ceramic filler-containing epoxy resin, and the flowable layer 1618 may comprise a photosensitive polyimide. In another example, the flowable layer 1618 is formed from a different inorganic dielectric material than the flowable layers 1018a, 1018b. For example, the flowable layers 1018a, 1018b may comprise a ceramic filler-containing epoxy resin, and the flowable layer 1618 may comprise a silicon dioxide layer.

[0097] The insulating film 1616 has a thickness of less than about 200 μm, e.g., a thickness of about 10 μm to about 180 μm. For example, the insulating film 1616, including the flowable layer 1618 and the PET support layer 1622, has a combined thickness of about 50 μm to about 100 μm. In a particular embodiment, the flowable layer 1618 has a thickness of less than about 60 μm, e.g., a thickness of about 5 μm to about 50 μm, e.g., a thickness of about 20 μm. The insulating film 1616 is disposed on a surface, e.g., major surface 1005, of the embedded die assembly 1002 having exposed interconnects 1444 bonded to contacts 1030 on the active surface 1028 of the die 1026 and / or bonded to metallized through-assembly vias 1003.

[0098] After the insulating film 1616 is deposited, the embedded die assembly 1002 is subjected to a lamination process substantially similar to that described with reference to steps 908, 916, and 1140. The embedded die assembly 1002 is exposed to an elevated temperature to soften the flowable layer 1618, which then bonds to the insulating layer 1018 already formed on the embedded die assembly 1002. As a result, in certain embodiments, the flowable layer 1618 merges with and forms an extension of the insulating layer 1018. The merger of the flowable layer 1618 and the insulating layer 1018 results in an extended and integrated insulating layer 1018 that covers the previously exposed interconnects 1444. For this reason, the combined flowable layer 1618 and insulating layer 1018 are collectively referred to herein as the insulating layer 1018. However, in other embodiments, the deposition and subsequent curing of the fluid 1618 forms a second insulating layer (not shown) on the insulating layer 1018. In some examples, the second insulating layer is formed of a different material layer than insulating layer 1018 .

[0099] In certain embodiments, the lamination process is a vacuum lamination process, which may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. In some embodiments, the lamination process includes applying a pressure of 10 psig to about 100 psig to the substrate 302 and the insulating film 1616 while applying a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. For example, the lamination process is performed at a temperature of about 100° C. to about 120° C., at a pressure of about 30 psig to about 80 psig, for a period of about 2 minutes to about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes. In a further example, the lamination process is performed at a pressure of about 30 psig to about 70 psig, such as about 50 psig.

[0100] In step 1504 and FIG. 16B, the support layer 1622 and the carrier 1624 are removed from the embedded die assembly 1002 by a mechanical process. After removing the support layer 1622 and the carrier 1624, the embedded die assembly 1002 is subjected to a curing process to fully cure the newly extended insulating layer 1018. In certain embodiments, the curing process is substantially similar to the curing process described with reference to steps 918 and 1150. For example, the curing process is performed at a temperature of about 140° C. to about 220° C. for a period of about 15 minutes to about 45 minutes, such as at a temperature of about 160° C. to about 200° C. for a period of about 25 minutes to about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process in step 1504 is performed at or near ambient pressure conditions.

[0101] The embedded die assembly 1002 is then selectively patterned by laser ablation in step 1506 and FIG. 16C. The laser ablation in step 1506 forms redistribution vias 1603 through the newly expanded insulating layer 1018 and exposes the desired interconnects 1444 for redistribution of their contacts. In certain embodiments, the redistribution vias 1603 have a diameter of about 5 μm to about 60 μm, such as about 10 μm to about 50 μm, such as about 20 μm to about 45 μm. In certain embodiments, the laser ablation process in step 1506 is performed using a CO2 laser. In certain embodiments, the laser ablation process in step 1506 is performed using a UV laser. In certain embodiments, the laser ablation process in step 1506 is performed using a green laser. For example, the laser source may generate a pulsed laser beam having a frequency of about 100 kHz to about 1000 kHz. In one example, the laser source is configured to provide a pulsed laser beam at a wavelength of about 100 nm to about 2000 nm, with a pulse duration of about 10E-4 ns to about 10E-2 ns, and with a pulse energy of about 10 μJ to about 300 μJ.

[0102] After patterning the embedded die assembly 1002, the embedded die assembly 1002 is subjected to a desmear process substantially similar to the desmear process in steps 922 and 1170. During the desmear process in step 1506, any unwanted residue and debris formed by laser ablation during the formation of the redistribution vias 1603 is removed from the redistribution vias 1603 to clean (e.g., purify) its surface for subsequent metallization. In a particular embodiment, the desmear process is a wet process. The wet desmear process may utilize any suitable aqueous etchant, solvent, and / or combination thereof. As an example, a KMnO4 solution may be utilized as the etchant. In another embodiment, the desmear process is a dry desmear process. For example, the desmear process may be a plasma desmear process with an O2 / CF4 mixed gas. In a further embodiment, the desmear process is a combination of wet and dry processes.

[0103] In step 1508 and FIG. 16D, an optional adhesion layer 1640 and / or seed layer 1642 is formed on the insulating layer 1018. In certain embodiments, the adhesion layer 1640 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material, or combinations thereof. In certain embodiments, the adhesion layer 1640 has a thickness of about 10 nm to about 300 nm, such as about 50 nm to about 150 nm. For example, the adhesion layer 1640 has a thickness of about 75 nm to about 125 nm, such as about 100 nm. The adhesion layer 1640 may be formed by any suitable deposition process, including, but not limited to, CVD, PVD, PECVD, ALD, and the like.

[0104] The optional seed layer 1642 is formed from a conductive material, such as copper, tungsten, aluminum, silver, gold, or other suitable material, or a combination thereof. In certain embodiments, the seed layer 1642 has a thickness of about 50 nm to about 500 nm, such as about 100 nm to about 300 nm. For example, the seed layer 1642 has a thickness of about 150 nm to about 250 nm, such as about 200 nm. In certain embodiments, the seed layer 1642 has a thickness of about 0.1 μm to about 1.5 μm. Similar to the adhesion layer 1640, the seed layer 1642 may be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD, which are dry processes, wet electroless plating processes, etc. In certain embodiments, a molybdenum adhesion layer 1640 and a copper seed layer 1642 are formed on the embedded die assembly 1002 to reduce undercutting of the conductive interconnect lines during the subsequent seed layer etching process in step 1520.

[0105] In steps 1510, 1512, and 1514, which correspond to Figures 16E, 16F, and 16G, respectively, a spin-on / spray-on resist film or dry resist film 1650, e.g., photoresist, is applied over the adhesive and / or seed surfaces of the embedded die assembly 1002, and subsequently patterned and developed. In certain embodiments, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 prior to disposing the resist film 1650. Exposure and development of the resist film 1650 results in opening of the redistribution vias 1603. Thus, patterning of the resist film 1650 may be performed by selectively exposing portions of the resist film 1650 to UV radiation, followed by developing the resist film 1650 by a wet process, such as a wet etching process. In certain embodiments, the resist film developing process is a wet etching process utilizing a buffered etching process selective to the desired material. In other embodiments, the resist film developing process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the resist film development process.

[0106] In steps 1516 and 1518, corresponding to FIGS. 16H and 16I, respectively, redistribution layer 1644 is formed through exposed redistribution vias 1603, and resist film 1650 is then removed. Redistribution layer 1644 is formed by any suitable method, including electroplating and electroless plating. In certain embodiments, resist film 1650 is removed via a wet process. As depicted in FIGS. 16H and 16I, redistribution connection 1644 fills redistribution vias 1603 and protrudes from the surface of embedded die assembly 1002 when resist film 1650 is removed. In certain embodiments, redistribution connection 1644 is formed of copper. In other embodiments, redistribution connection 1644 may be formed of any suitable conductive material, including, but not limited to, aluminum, gold, nickel, silver, palladium, tin, and the like.

[0107] In step 1520 and FIG. 16J, the embedded die assembly 1002 having the rewiring connections 1644 formed thereon is subjected to a seed layer etching process substantially similar to that of step 1370. In certain embodiments, the seed layer etching is a wet etching process that includes rinsing and drying the embedded die assembly 1002. In certain embodiments, the seed layer etching process is a wet etching process utilizing a buffered etching process selective to the desired material of the seed layer 1642. In other embodiments, the etching process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etching process.

[0108] In step 1522, one or more completed packages 1602 are singulated from the embedded die assembly 1002, as depicted in FIG. 16K and FIG. 16L. However, prior to step 1522, additional redistribution layers may be formed on the embedded die assembly 1002 using the sequences and processes described above, as depicted in FIG. 16L (FIG. 16K depicts the completed package 1602 with one additional redistribution layer 1658). For example, one or more additional redistribution layers 1660 may be formed on an opposite side or surface of the embedded die assembly 1002 from the first additional redistribution layer 1658, e.g., on the major surface 1007. Alternatively, one or more additional redistribution layers 1660 may be formed on the same side or surface as the first additional redistribution layer 1658 (not shown), e.g., on the major surface 1005. The completed packages 1602 may then be singulated from the embedded die assembly 1002 after all desired redistribution layers have been formed.

[0109] FIG. 17 is a flow diagram of an alternative method 1700 for disposing and laminating an insulating layer on an embedded die assembly 1002 when forming a redistribution layer. FIGS. 18A-18C illustrate schematic cross-sectional views of an embedded die assembly 1002 at various stages of the method 1700. Thus, for clarity, FIGS. 17 and 18A-18C are described together herein. It should be noted that in performing steps 1702-1706 of method 1700, steps 1508-1522 of method 1500 to complete the formation of the redistribution layer may be performed, e.g., deposition of adhesion and / or seed layers, plating of redistribution connections, etc.

[0110] The method 1700 is substantially similar to one or more of the methods described above. In general, the method 1700 begins with step 1702 and FIG. 18A, where a pre-structured insulating film 1816 is aligned and positioned on the embedded die assembly 1002. Similar to the insulating films 1616, 1016 described above, the insulating film 1816 may include one or more layers formed of a polymer-based flowable dielectric material. For example, in certain embodiments, the insulating film 1816 includes a flowable layer 1818 and one or more support layers 1822. In certain embodiments, the insulating film 1816 includes a flowable layer 1818 of a ceramic filler-containing epoxy resin and one or more support layers 1822. In another example, the insulating film 1816 includes a flowable layer 1818 of a photosensitive polyimide and one or more support layers 1822. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1816, such as those described above with reference to the insulating films 1616 and 1016. For example, in certain embodiments, the flowable layer 1818 may be formed of non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide, and / or silicon nitride. Examples of suitable materials for the support layer(s) 1822 include PET, PP, polyethylene (PE), polycarbonate, polystyrene, and the like.

[0111] In some examples, the flowable layer 1818 is formed from a different polymer-based flowable dielectric material than the flowable layers 1018a, 1018b. For example, the flowable layers 1018a, 1018b may include a ceramic filler-containing epoxy resin layer, while the flowable layer 1818 may include a photosensitive polyimide layer, or vice versa. In another example, the flowable layer 1818 is formed from a different inorganic dielectric material than the flowable layers 1018a, 1018b. For example, the flowable layers 1018a, 1018b may include a ceramic filler-containing epoxy resin layer, while the flowable layer 1818 may include a silicon dioxide layer, or vice versa.

[0112] Flowable layer 1818 typically has a thickness of less than about 120 μm, such as from about 10 μm to about 100 μm. For example, flowable layer 1818 has a thickness of from about 20 μm to about 80 μm. In certain embodiments, insulating film 1816 has a total thickness of less than about 200 μm, such as less than about 160 μm.

[0113] However, unlike the previous examples of the insulating film, the insulating film 1816 is pre-structured, i.e., structured prior to being placed and laminated on the embedded die assembly 1002. For example, the insulating film 1816 has one or more vias 1803 formed therein for subsequent plating of the redistribution connections, the sidewalls of the vias 1803 being selectively hardened. The pre-structuring of the insulating film 1816 is described in more detail with reference to Figures 19, 20A-20C, and 21A-21B. In this case, during placement of the insulating film 1816 on the embedded die assembly 1002, the insulating film 1816 is aligned with the embedded die assembly 1002 such that the pre-structured vias 1803 are aligned with the contacts or pads of the interconnects 1444, thereby enabling connection between the interconnects 1444 and the subsequently formed redistribution connections. In certain embodiments, the insulating film 1816 may have one or more fiducial marks formed on its surface to facilitate alignment with the embedded die assembly 1002, which may have one or more corresponding fiducial marks (e.g., etched areas or areas of deposited material) formed on its mating surface, although any suitable alignment method is contemplated.

[0114] In step 1704 and FIG. 18B, after the placement of the pre-structured insulating film 1816, the embedded die assembly 1002 is subjected to a lamination process substantially similar to that described above. The embedded die assembly 1002 is thus exposed to high temperatures to soften the flowable layer 1818, which then bonds to the insulating layer 1018 already formed on the embedded die assembly 1002. As a result, in certain embodiments, the flowable layer 1818 merges with and forms an extension of the insulating layer 1018. The merger of the flowable layer 1818 and the insulating layer 1018 results in an extended and integrated insulating layer 1018 that covers the previously exposed interconnects 1444. For this reason, the combined flowable layer 1818 and insulating layer 1018 are collectively referred to herein as the insulating layer 1018. However, in other embodiments, the lamination of the flowable layer 1818 forms a second insulating layer (not shown) on the insulating layer 1018. In some examples, the second insulating layer is formed of a different material than insulating layer 1018. In some embodiments, the second insulating layer may have different structural, electrical, or compositional material properties than insulating layer 1018. In other embodiments, the second insulating layer comprises the same material as insulating layer 1018, but has different structural properties (e.g., thickness).

[0115] In certain embodiments, the lamination process is a vacuum lamination process, which may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. In some embodiments, the lamination process includes applying a pressure of 10 psig to about 100 psig to the substrate 302 and the insulating film 1616 while applying a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. For example, the lamination process is performed at a temperature of about 100° C. to about 120° C., at a pressure of about 30 psig to about 80 psig, for a period of about 2 minutes to about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes. In a further example, the lamination process is performed at a pressure of about 30 psig to about 70 psig, such as about 50 psig.

[0116] In step 1706 and FIG. 18C, the support layer 1822 is removed from the flowable layer 1818 laminated onto the embedded die assembly 1002 by a mechanical process. After removing the support layer 1822, in certain embodiments, the embedded die assembly 1002 is subjected to a curing process to fully cure the newly extended insulating layer 1018. In certain embodiments, the curing process is substantially similar to the curing process described above with reference to steps 918 and 1150. For example, the curing process is carried out at a temperature of about 140° C. to about 220° C. for a period of about 15 minutes to about 45 minutes, such as at a temperature of about 160° C. to about 200° C. for a period of about 25 minutes to about 35 minutes. For example, the curing process is carried out at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process in step 1504 is carried out at or near ambient pressure conditions.

[0117] Thereafter, steps 1508-1522 of method 1500 to complete the formation of the redistribution layer, such as deposition of adhesion and / or seed layers, plating of redistribution interconnects, etc., as described above, may be performed.

[0118] Figure 19 illustrates a flow diagram of a method 1900 for pre-structuring an insulating film, e.g., prior to placement on an embedded die assembly or other semiconductor device packaging structure, according to embodiments described herein. Figures 20A-C illustrate schematic cross-sectional views of an insulating film at various stages of the pre-structuring method 1900 depicted in Figure 19. Thus, for clarity, Figure 19 and Figures 20A-C are described herein together.

[0119] Method 1900 begins with step 1902 and corresponding FIG. 20A, where an insulating film, e.g., insulating film 1816, is patterned by laser ablation to form one or more features, such as vias 1803, in its flowable layer. However, in some embodiments, the insulating film is patterned by a lithography and development process, or a mechanical pressing process to form one or more features therein. Unless otherwise noted, the embodiments and examples described herein may be performed on any insulating sheet or insulating film comprising a 10-100 μm thick flowable layer sandwiched between two or more support or cover / protection layers. In the example shown in FIGS. 20A-C, insulating film 1816 includes a flowable layer 1818 attached to a support layer 1822 as described above, and further includes a cover layer 1824 bonded to a side of flowable layer 1818 opposite support layer 1822. In certain embodiments, cover layer 1824 is made of a material similar to that of support layer 1822. For example, the cover layer 1824 may be formed of a lightweight plastic material, such as PET, PP, PE, etc. The cover layer 1824 may be removed during pre-structuring of the insulating film 1816, before disposing the insulating film 1816, for example, on an embedded die assembly or other semiconductor device packaging structure.

[0120] Furthermore, the embodiments and examples described herein may be performed on bulk or pre-singulated insulating films, for example, a roll of insulating film may be pre-structured and then optionally singulated (e.g., in step 1906) so that it can be placed and stacked in batches or as single devices.

[0121] As discussed above, patterning of the insulating film 1816 may be accomplished using a laser ablation system having any suitable type of laser source 2007. In certain embodiments, the laser source 2007 is an infrared (IR) laser. In certain embodiments, the laser source 2007 is a UV laser, such as a 355 nm UV laser or a 248 nm excimer UV laser. For example, the laser source 2007 may be a picosecond or femtosecond UV laser. In certain embodiments, the laser source 2007 is a femtosecond green laser. In yet other embodiments, the laser source 2007 is a CO2 laser. The laser source 2007 may generate a continuous or pulsed laser beam 2010 for patterning the insulating film 1816. For example, in certain embodiments, the laser source 2007 may generate a pulsed laser beam having a frequency of about 100 kHz to about 1000 kHz. In one example, the laser source is configured to provide a pulsed laser beam at a wavelength of about 100 nm to about 2000 nm, with a pulse duration of about 10E-4 ns to about 10E-2 ns, and with a pulse energy of about 10 μJ to about 300 μJ.

[0122] Laser source 2007 is configured to form any desired pattern and / or features in insulating film 1816, including vias 1803, which may be utilized to plate electrical connections through flowable layer 1818. For example, laser source 2007 may be utilized to form vias 1803 having a diameter of about 5 μm to about 60 μm, such as about 10 μm to about 50 μm, such as about 20 μm to about 45 μm. Vias 1803 may be disposed through insulating film 1816 in any desired arrangement / location to enable contact / bonding between electrical connections subsequently plated into vias 1803 and, for example, interconnects and / or rewiring connections in an embedded die assembly or other semiconductor device packaging structure upon which insulating film 1816 is laminated.

[0123] After patterning, the insulating film 1816 is subjected to a selective curing process in step 1904 and FIG. 20B to selectively harden the sidewalls of any patterned features, thereby enabling the patterned features to maintain their morphology during subsequent steps. For example, the curing process in step 1904 may be utilized to harden the sidewalls of the via 1803 (hardened sidewalls shown as 2020 in FIG. 20B ) such that the via 1803 maintains its morphology and structural integrity during placement and lamination, e.g., onto the embedded die assembly 1002, as described with reference to method 1700. In this case, the selective curing process prevents any features patterned in the insulating film 1816 from collapsing, e.g., during placement and lamination.

[0124] Generally, the curing process may be carried out at an elevated temperature, such as at a temperature of about 140° C. to about 220° C., such as at a temperature of about 160° C. to about 200° C., such as at a temperature of about 180° C. In certain embodiments, the curing process is a plasma curing process, and the patterned insulating film 1816 is exposed to a plasma including N2, CH4, H2, CF4, and / or O2 species. In certain other embodiments, the curing process is a UV curing process. The insulating film 1816 may be subjected to the curing process for a period of about 1 to about 60 seconds, such as a period of about 2 to about 30 seconds, such as a period of about 5 to about 20 seconds, such as a period of about 10 seconds.

[0125] In step 1906 and Figure 20C, the patterned and cured insulating film 1816 is optionally singulated for placement and lamination onto a semiconductor device package, although in certain embodiments, the insulating film 1816 may be placed and laminated onto a batch or bulk semiconductor device package structure, and the insulating film 1816 may be singulated into individual packages along with the semiconductor device package structure (after further processing), as described above. In yet other embodiments, the insulating film 1816 is singulated prior to pre-structuring.

[0126] In certain embodiments where pre-structuring is performed on a bulk insulating film, the method 1900 is performed using a roll-to-roll pre-structuring apparatus. FIGS. 21A and 21B show a schematic of an exemplary roll-to-roll pre-structuring apparatus 2100 used during the method 1900. The apparatus 2100 may include an unwinding module 2104, a winding module 2106, and one or more processing stations disposed therebetween. In the example of FIG. 21A, the apparatus 2100 is shown having three processing stations 2110, 2120, and 2130, each of which may be utilized to perform a separate step of the method 1900. For example, the processing station 2110 may be a laser ablation system for performing step 1902, as shown in FIG. 21B, the processing station 2120 may be a curing system such as a processing chamber or oven for performing step 1904, and the optional processing station 2130 may be a singulation station for performing step 1906.

[0127] According to certain embodiments, unwind module 2104 and take-up module 2106, which may each include one or more rollers, work in conjunction to facilitate feeding (e.g., rolling) the insulating film 1816 through each of processing stations 2110, 2120, and 2130. The insulating film 1816 may be passed sequentially through each processing station such that desired regions of the insulating film 1816 are sequentially patterned, cured, and singulated during pre-structuring.

[0128] In addition to being utilized to form a redistribution layer, the pre-structured insulating film 1816 may also be utilized to form an insulating layer that encapsulates the substrate / frame and any semiconductor die of an embedded die assembly or other semiconductor device package structure. For example, by utilizing two pre-structured insulating films 1816, an insulating layer 2318 substantially similar to the insulating layer 1018 can be formed on a substrate / frame, such as the substrate 302 described above. FIG. 22 illustrates a flow diagram of a method 2200 for forming such an insulating layer, according to an embodiment described herein. FIGS. 23A-G illustrate schematic cross-sectional views of the substrate 302 at various stages of the method 2200 depicted in FIG. 22. Therefore, for clarity, FIGS. 22 and 23A-G are described herein together.

[0129] Generally, method 2200 begins at step 2202 and FIG. 23A where a substrate 302, already patterned and having desired features formed thereon, is aligned (e.g., via fiducials) and placed on a first pre-structured insulating film 1816. In certain embodiments, insulating film 1816 is pre-structured, i.e., structured prior to being placed on substrate 302, to include one or more vias 1803 that are laterally aligned with vias 303 formed in substrate 302 such that when flowable layer 1818 of insulating film 1816 is laminated to substrate 302, interconnects, e.g., interconnect 1444, can later be plated through both vias 303 and 1803.

[0130] In certain embodiments, after the substrate 302 is disposed on the insulating film 1816, and in particular on its flowable layer 1818, the substrate 302 and insulating film 1816 may optionally be disposed on a carrier 1024 to provide mechanical support during subsequent processing steps, as described above with reference to similar methods.

[0131] In step 2204, one or more semiconductor dies 1026 are disposed within a cavity 305 formed in the substrate 302, as depicted in FIG. 23B, such that the semiconductor die 1026 is now bounded on one side by the insulating film 1816 and, for example, on four sides by the substrate 302 (a single semiconductor die 1026 is depicted in FIG. 23B). In certain embodiments, the die 1026 is a multi-purpose die having integrated circuits formed on its active surface 1028. The die 1026 is disposed within the cavity 305 and positioned on a surface of the insulating film 1816 exposed through the cavity 305. In certain embodiments, the die 1026 is disposed on an adhesion layer (not shown) disposed or formed on the insulating film 1816.

[0132] In step 2206 and FIG. 23C, the substrate 302, now disposed on the insulating film 1816 and further comprising the die 1026, is subjected to a lamination process. During the lamination process, the substrate 302 is exposed to high temperatures, which causes the flowable layer 1818 of the insulating film 1816 to soften and flow into the gap 1051 between the inner wall of the cavity 305 and the die 1026, while the via 303 of the substrate 302 remains unfilled due to the prior curing of the sidewall 2020 of the via 1803. As discussed above, the selective curing of the sidewall 2020 of the via 1803 maintains its structural integrity, thereby preventing the dielectric material of the flowable layer 1818 from flowing into the via 303 during lamination (e.g., preventing the flowable layer 1818 from blocking the via 3030). As a result, the semiconductor die 1026 becomes at least partially embedded within the material of the insulating film 1816 and the substrate 302, as depicted in Figure 23C. In addition, the substrate 302 becomes affixed to the flowable layer 1818.

[0133] In certain embodiments, the lamination process is a vacuum lamination process, which may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80° C. to about 140° C. for a period of about 5 seconds to about 1.5 minutes, such as about 30 seconds to about 1 minute. In some embodiments, the lamination process includes applying a pressure of about 1 psig to about 50 psig to the substrate 302 and the insulating film 1016a while applying a temperature of about 80° C. to about 140° C. for a period of about 5 seconds to about 1.5 minutes. For example, the lamination process is performed at a temperature of about 100° C. to about 120° C., at a pressure of about 5 psig to about 40 psig, for a period of about 10 seconds to about 1 minute. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 20 seconds.

[0134] In certain embodiments, prior to lamination, a protective film, e.g., protective film 1060, is disposed on an exposed surface, e.g., surface 1077, of substrate 302 as shown in Figure 23C. In certain embodiments, protective film 1060 is formed of a material similar to that of support layer 1022a. For example, protective film 1060 is formed of PET, such as biaxial PET. However, protective film 1060 may be formed of any suitable protective material. Protective film 1060 is removed after lamination and prior to step 2208, discussed below.

[0135] In step 2208 and FIG. 23D, a second pre-structured insulating film 1816 is aligned (e.g., via fiducials) and placed on the opposite side, e.g., side 1077, of the substrate 302. In a particular embodiment, the second insulating film 1816 is positioned such that its flowable layer 1818 contacts and covers the active surface 1028 of the die 1026 in the cavity 305. The second insulating film 1816 may be pre-structured to include one or more vias 1803 laterally aligned with the vias 303 formed in the substrate 302 and one or more vias 1803 laterally aligned with the contacts 1030 formed on the active surface 1028 of each embedded die 1026. In this case, interconnects, e.g., interconnects 1444, may be subsequently plated through both the vias 303 and 1803 and may be further routed to the contacts 1030 for connecting the embedded die 1026 to other devices.

[0136] The substrate 302, now attached to the first insulating film 1816 on the first side 1075 and with the second insulating film 1816 disposed on the second side 1077, is subjected to a second lamination process in step 2210 and FIG. 23E. Similar to the lamination process in step 2206, the substrate 302 is exposed to high temperatures, which causes the flowable layer 1818 of the second insulating film 1816 to soften and flow into the remaining open gap 1051 between the inner wall of the cavity 305 and the die 1026, thereby integrating the insulating material of the flowable layer 1818 of the first insulating film 1816 with the flowable layer 1818. As a result, the cavity 305 becomes filled (e.g., filled, sealed) and the semiconductor die 1026 becomes fully embedded within the insulating material of the flowable layer 1818, while the vias 303 and 1803 remain open.

[0137] In certain embodiments, the second lamination process is a vacuum lamination process, which may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed using a hot press process. In certain embodiments, the lamination process is performed at a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. In some embodiments, the lamination process includes applying a pressure of about 10 psig to about 150 psig to the substrate 302 and the insulating film 1016b while applying a temperature of about 80° C. to about 140° C. for a period of about 1 minute to about 30 minutes. For example, the lamination process is performed at a temperature of about 100° C. to about 120° C., at a pressure of about 20 psig to about 100 psig, for a period of about 2 minutes to about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes.

[0138] In step 2212 and FIG. 23F, the stacked embedded die assembly 1002 is detached from any carrier and / or overcoat, the support layer 1822 is removed, and the embedded die assembly 1002 is subjected to a curing process. Generally, the support layer 1822 and any carrier and / or overcoat are removed from the embedded die assembly 1002 by any suitable mechanical process, such as by peeling therefrom. The embedded die assembly 1002 is then subjected to a curing process to fully cure (i.e., harden by chemical reaction and crosslinking) the insulating dielectric material of the flowable layer 1818, resulting in the formation of a hardened insulating layer 2318. The insulating layer 2318 substantially surrounds the substrate 302 and the semiconductor die 1026 embedded therein, except for the sidewalls of the vias 303. For example, insulating layer 2318 contacts or encapsulates at least sides 1075, 1077 of substrate 302 (including surfaces 606, 608) and at least six faces or surfaces of each semiconductor die 1026, but leaves the sidewalls of vias 303 exposed.

[0139] In certain embodiments, the curing process is carried out at an elevated temperature such that the embedded die assembly 1002 is fully cured. For example, the curing process is carried out at a temperature of about 140° C. to about 220° C. for a period of about 15 minutes to about 45 minutes, such as at a temperature of about 160° C. to about 200° C. for a period of about 25 minutes to about 35 minutes. For example, the curing process is carried out at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process in step 2212 is carried out at or near ambient (e.g., atmospheric) pressure conditions.

[0140] Once cured, the embedded die assembly 1002 is ready for interconnect paths to be formed and singulated to form a completed package as described above with reference to Figures 13 and 14A-14H. An exemplary package 2302 is depicted in Figure 23G for reference. Using the methods described above, interconnects 1444 may be formed through the vias 303 and 1803 of the embedded die assembly 1002 for interconnection of one or more components including the die 1026 and / or other package structures. However, unlike the previously described examples, since no insulating material flows into the vias 303 during the lamination process of method 2200, the interconnects 1444 and / or the adhesion layer 1440 and / or the seed layer 1442 may be formed directly on the sidewalls of the vias 303 (rather than within the through-assembly vias formed in the vias 303). In this case, since an oxide layer may be formed on the sidewalls of via 303 (as described with reference to Figures 2 and 3D), interconnect 1444 may be formed on top of the oxide layer within via 303.

[0141] While described above with separate lamination processes for each of the two pre-structured insulating films 1816, in certain embodiments, the method 2200 includes only a single lamination process for both films, resulting in a reduced amount of steps in the method 2200. For example, in certain embodiments, after the die 1026 is placed in the cavity 305 in step 2204, step 2208 may be performed in which a second insulating film 1816 is placed on the substrate 302. Then, in step 2210, both insulating films 1816 may be laminated simultaneously according to the lamination parameters described above.

[0142] It should be noted that in certain embodiments, method 2200 may be performed with a pre-metallized substrate 302. For example, substrate 302 may include one or more vias 302 (and / or adhesion layer 1440 and / or seed layer 1442) with plated interconnects 1444 already formed therein. In this case, after deposition and curing of pre-structured insulating film 1816 thereon, the pre-metallized interconnects may be extended through vias 1803 by any suitable technique discussed herein.

[0143] As described above with reference to Figures 17, 18A-18C, 19, 20A-20C, 21A-21B, 22, and 23A-23G, the use of pre-structured insulating films provides several advantages over more conventional isolation and / or build-up methods. For example, the use of pre-structured insulating films allows the formation of redistribution vias of significantly reduced dimensions, such as diameters of about 5 μm or less, using short wavelength lasers (e.g., excimer lasers) without damaging the dielectric material. Since the laser ablation of the insulating film is performed prior to the removal of the support layer and / or cover layer deposited thereon, the support layer and / or cover layer will absorb any heat accumulated at the surface of the flowable layer during structuring and can then be removed. Furthermore, since the structuring of the insulating film is performed separately from the substrate, any cutting, alteration, undercutting, and / or carbonization of already metallized contact pads on the substrate / frame may be avoided, and harmful etching or desmearing processes that may be required to remove debris or copper overhangs of previously metallized layers may be unnecessary. Additionally, since some steps (e.g., re-drilling through vias in the substrate / frame after lamination, desmearing, etching, etc.) may be avoided, the total number of steps required to form the semiconductor device package may be reduced, thereby making the manufacture of the semiconductor device package more efficient.

[0144] The package structures formed by the above-described methods, such as packages 1602 and 2302, may be utilized in any suitable configuration in any suitable packaging application. In one exemplary embodiment depicted in FIG. 24A, four packages 1602 are utilized to form a stacked DRAM structure 2400. In this case, each package 1602 includes a memory die 2426 (i.e., memory chip) embedded in the substrate 302 and encapsulated by (e.g., a portion of each side is in contact with) the insulating layer 1018. One or more interconnects 1444 are formed throughout the thickness of each package 1602, which are in direct contact with one or more solder bumps 2446 disposed between the major surfaces 1005 and 1007 of adjacent (i.e., stacked one on top of the other) packages 1602. For example, as depicted in stacked DRAM structure 2400, four or more solder bumps 2446 are disposed between adjacent packages 1602 to bridge (e.g., connect, couple) the interconnects 1444 of each package 1602 to the interconnects 1444 of an adjacent package 1602.

[0145] In certain embodiments, to increase the reliability of the solder bumps 2446, the gap between adjacent packages 1602 connected by the solder bumps 2446 is filled with an encapsulant material 2448. The encapsulant material 2448 can be any suitable type of encapsulant or underfill. In one example, the encapsulant material 2448 includes pre-assembly underfill materials, such as no-flow underfill (NUF) materials, non-conductive paste (NCP) materials, and non-conductive film (NCF) materials. In one example, the encapsulant material 2448 includes post-assembly underfill materials, such as capillary underfill (CUF) materials and molded underfill (MUF) materials. In certain embodiments, the encapsulant material 2448 includes SiO2, AlN, Al2O3, SiC, Si3N4, Sr2Ce2Ti5O 16 , ZrSiO4, CaSiO3, BeO, CeO2, BN, CaCu3Ti4O 12, low expansion filler-containing resins, such as epoxy resins filled with (eg, containing) MgO, TiO2, ZnO, and the like.

[0146] In certain embodiments, the solder bumps 2446 are formed of one or more intermetallic compounds, such as tin (Sn) and lead (Pb), silver (Ag), Cu, or any other suitable metal combinations thereof. For example, the solder bumps 2446 are formed of solder alloys, such as Sn-Pb, Sn-Ag, Sn-Cu, or other suitable materials or combinations thereof. In certain embodiments, the solder bumps 2446 include C4 (controlled collapse chip connection) bumps. In certain embodiments, the solder bumps 2446 include C2 (chip connection, such as Cu pillar with solder cap) bumps. The use of C2 solder bumps allows for smaller pitch between contact pads and improved thermal and / or electrical properties of the stacked DRAM structure 2400. In some embodiments, the solder bumps 2446 have a diameter of about 10 μm to about 150 μm, such as a diameter of about 50 μm to about 100 μm. Solder bumps 2446 may also be formed by any suitable wafer bumping process, including, but not limited to, electrochemical deposition (ECD) and electroplating.

[0147] In another exemplary embodiment depicted in FIG. 24B, a stacked DRAM structure 2401 is formed by stacking four packages 1602 and directly bonding one or more interconnects 1444 of each package 1602 with the interconnects 1444 of one or more adjacent packages 1602. As depicted, the packages 1602 may be joined by hybrid bonding, where the major surfaces 1005 and 1007 of adjacent packages are planarized and in full contact with one another. Thus, the one or more interconnects 1444 of each package 1602 are formed throughout the thickness of each package 1602 and are in direct contact with one or more interconnects 1444 of at least one other adjacent package 1602.

[0148] The stacked DRAM structures 2400 and 2401 provide multiple advantages over conventional DRAM structures, including a thin form factor and high die-to-package volume ratio, which allows for greater I / O scaling to meet the ever-increasing bandwidth and power efficiency demands of artificial intelligence (AI) and high performance computing (HPC). Utilizing a structured silicon frame provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management, and reliability of three-dimensional integrated circuit (3D IC) architectures. Furthermore, the fabrication methods for assembly through-via and via-in-via structures described herein provide high performance and adaptability for 3D integration at relatively low manufacturing costs compared to conventional TSV technology.

[0149] The embodiments described herein advantageously provide improved methods of substrate structuring and die assembly for the manufacture of advanced integrated circuit packages. Using the methods described above, high aspect ratio features can be formed on glass and / or silicon substrates, resulting in thinner and smaller area semiconductor device packages that can be economically manufactured. In addition to high I / O density and improved bandwidth and power, the thin, small form factor packages manufactured using the methods described above also benefit from reduced stress and higher reliability due to reduced weight / inertia and a package architecture that allows flexible solder ball distribution. Additional benefits of the methods described above include economical manufacturing due to double-sided metallization capabilities, and high production yields due to the elimination of flip-chip mounting and overmolding steps that are prone to feature damage in the high volume manufacture of traditional and advanced packages.

[0150] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which is determined by the following claims.

Claims

1. disposing a pre-structured insulating film over the patterned substrate, the pre-structured insulating film comprising a flowable polymer-based dielectric material; the patterned substrate comprising one or more features formed in a silicon substrate, the one or more features comprising a first via; depositing a pre-structured insulating film, the pre-structured insulating film further comprising a second via formed in the pre-structured insulating film, the second via being aligned with the first via upon depositing the pre-structured insulating film; depositing the pre-structured insulating film onto the patterned substrate; curing the pre-structured insulating film; and forming a conductive layer extending through the first via and the second via; 16. A method for forming a semiconductor device package, comprising:

2. The method of claim 1 , further comprising forming the first via in the patterned substrate by a laser ablation process.

3. Structuring an insulating film to form the pre-structured insulating film, patterning one or more features comprising the second via in the insulating film by laser ablation; and selectively hardening sidewalls of the features patterned in the insulating film to harden the sidewalls. The method of claim 1 further comprising:

4. The method of claim 1 , wherein the pre-structured insulating film comprises an epoxy resin.

5. The method of claim 4 , wherein the epoxy resin comprises ceramic particles.

6. 10. The method of claim 1 , wherein the one or more features patterned in the patterned substrate further comprise a cavity, and a semiconductor die is disposed in the cavity prior to disposing the pre-structured insulating film on the patterned substrate.

7. 2. The method of claim 1 , wherein depositing the pre-structured insulating film onto the patterned substrate causes the flowable polymer-based dielectric material to fill gaps between a surface of the semiconductor die and a surface of the cavity.

8. patterning one or more features in a silicon substrate, the one or more features comprising at least a first via; placing the silicon substrate on a first pre-structured insulating film, the first pre-structured insulating film comprising a second via, the second via being aligned with the first via upon placement of the silicon substrate; disposing a second pre-structured insulating film on the silicon substrate, the second pre-structured insulating film comprising a third via, the third via being aligned with the first via upon disposing the second pre-structured insulating film; depositing the first pre-structured insulating film and the second pre-structured insulating film on the silicon substrate; curing the first pre-structured insulating film and the second pre-structured insulating film; forming a conductive layer extending through at least the first via, the second via, and the third via; 16. A method for forming a semiconductor device package, comprising:

9. The method of claim 8 , wherein the silicon substrate is patterned by laser ablation.

10. Structuring an insulating film to form the pre-structured insulating film, patterning one or more features comprising the second via in the insulating film by laser ablation; and selectively hardening sidewalls of the features patterned in the insulating film to harden the sidewalls. The method of claim 8 further comprising:

11. The method of claim 8 , wherein the pre-structured insulating film comprises an epoxy resin.

12. The method of claim 11 , wherein the epoxy resin comprises ceramic particles.

13. 10. The method of claim 8, wherein the one or more features patterned in the silicon substrate further comprise a cavity, and a semiconductor die is disposed in the cavity prior to disposing the pre-structured insulating film over the silicon substrate.

14. 9. The method of claim 8, wherein depositing the pre-structured insulating film onto the silicon substrate results in a flowable polymer-based dielectric material filling gaps between a surface of the semiconductor die and a surface of the cavity.

15. patterning one or more features in a silicon substrate, the one or more features comprising at least a first via; placing the silicon substrate on a first pre-structured insulating film, the first pre-structured insulating film comprising a second via, the second via being aligned with the first via upon placement of the silicon substrate; subjecting the first pre-structured insulating film and the silicon substrate to a first lamination process; disposing a second pre-structured insulating film on the silicon substrate, the second pre-structured insulating film comprising a third via, the third via being aligned with the first via upon disposing the second pre-structured insulating film; subjecting the first pre-structured insulating film, the substrate and the second pre-structured insulating film to a second lamination process; curing the first pre-structured insulating film and the second pre-structured insulating film; forming a conductive layer extending through at least the first via, the second via, and the third via; 16. A method for forming a semiconductor device package, comprising:

16. Structuring an insulating film to form the pre-structured insulating film, patterning one or more features comprising the second via in the insulating film by laser ablation; and selectively hardening sidewalls of the features patterned in the insulating film to harden the sidewalls. The method of claim 15 further comprising:

17. The method of claim 15 , wherein the pre-structured insulating film comprises an epoxy resin.

18. The method of claim 17 , wherein the epoxy resin comprises ceramic particles.

19. 16. The method of claim 15, wherein the one or more features patterned in the silicon substrate further comprise a cavity, and a semiconductor die is disposed in the cavity prior to disposing the pre-structured insulating film over the silicon substrate.

20. 16. The method of claim 15, wherein depositing the pre-structured insulating film onto the substrate causes a flowable polymer-based dielectric material to fill gaps between a surface of the semiconductor die and a surface of the cavity.

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