Photoelectric conversion devices and equipment

Abstract

To reduce the influence of a conductive member transmitting a control signal from a vertical scanning circuit exerted on another conductive wire.SOLUTION: There is provided a photoelectric conversion device in which a first substrate and a second substrate are joined to each other. The first substrate has: a light receiving array in which a plurality of light receiving circuits are arranged in an array form; and a plurality of drive wires for supplying a control signal to the light receiving array. The second substrate has: a first circuit that includes a driver circuit group generating the control signal and functions as a vertical scanning circuit supplying the control signal to at least some of the plurality of drive wires; and a second circuit that includes a circuit group with the same configuration as that of the driver circuit group. In a plan view with respect to a boundary between the first substrate and the second substrate, the second circuit is at a position overlapping the at least some drive wires to which the control signal is supplied by the first circuit. The at least some drive wires to which the control signal is supplied by the first circuit include drive wires not electrically connected with the second circuit. In the plan view with respect to the boundary, the second substrate has a conductive wire used for transmission of a signal different from the control signal or power supply at a position overlapping the second circuit.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] There is known a photoelectric conversion device formed by bonding two substrates together. Patent Document 1 describes a technique for producing one of the substrates of the photoelectric conversion device by combining divided exposure and full-body exposure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-183658 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the light receiving circuit and the vertical scanning circuit are formed on separate substrates, a driving line for supplying a control signal to the light receiving circuit and the vertical scanning circuit are connected by a conductive member. When another conductive line is located near this conductive member extending from the vertical scanning circuit, narrowing the conductive line may increase the resistance value or cause coupling between the conductive member and the conductive line. The present invention aims to reduce the influence of the conductive member that transmits the control signal from the vertical scanning circuit on the other conductive lines. [Means for solving the problem]

[0005] According to some embodiments, there is provided a photoelectric conversion device in which a first substrate and a second substrate are bonded together, the first substrate having a photoelectric array in which a plurality of photoreceiving circuits are arranged in an array, and a plurality of drive lines for supplying control signals to the photoelectric conversion array, the second substrate having a driver circuit group that generates the control signals and a first circuit that functions as a vertical scanning circuit that supplies the control signals to at least some of the drive lines, and a second circuit that includes a circuit group having the same configuration as the driver circuit group, the second circuit being located in a position overlapping at least some of the drive lines to which the control signals are supplied by the first circuit, in a planar view relative to the boundary between the first substrate and the second substrate, the at least some of the drive lines to which the control signals are supplied by the first circuit include drive lines that are not electrically connected to the second circuit, and the second substrate having a conductive line used for transmitting a signal different from the control signal or for supplying power, in a position overlapping with the second circuit, in a planar view relative to the boundary. Effect of the Invention

[0006] By the above means, it is possible to reduce the influence of the conductive member which transmits the control signal from the vertical scanning circuit on other conductive lines. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the arrangement of a photoelectric conversion device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram for explaining an example of a circuit layout of the photoelectric conversion device according to the first embodiment. [Diagram 3] FIG. 2 is a diagram for explaining an example of a circuit configuration of a light receiving circuit according to the first embodiment. [Figure 4] FIG. 2 is a diagram for explaining an example of a circuit configuration of an AD conversion unit according to the first embodiment. [Diagram 5] FIG. 2 is a diagram for explaining an example of the circuit configuration of a vertical scanning circuit according to the first embodiment. [Figure 6] 3 is a diagram for explaining the connection relationship between a vertical scanning circuit and driving lines according to the first embodiment. [Figure 7]3A to 3C are diagrams for explaining an example of the layout of a conductive pattern according to the first embodiment. [Figure 8] FIG. 11 is a diagram for explaining an example of a circuit layout of a photoelectric conversion device according to a second embodiment. [Figure 9] FIG. 11 is a diagram for explaining the connection relationship between a vertical scanning circuit and driving lines according to a second embodiment. [Figure 10] FIG. 13 is a diagram for explaining an example of a circuit layout of a photoelectric conversion device according to a third embodiment. [Figure 11] FIG. 13 is a diagram for explaining the connection relationship between a vertical scanning circuit and driving lines according to a third embodiment. [Figure 12] FIG. 2 is a diagram illustrating an example of the configuration of a device according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0009] First Embodiment An example of the structure of a photoelectric conversion device 100 according to a first embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view focusing on a portion near a side surface 107 of the photoelectric conversion device 100. The photoelectric conversion device 100 is composed of a light-receiving substrate 101 and a circuit substrate 102. The light-receiving substrate 101 and the circuit substrate 102 are superimposed on each other and bonded at a boundary 103 between the light-receiving substrate 101 and the circuit substrate 102. "Bonding" means that the light-receiving substrate 101 and the circuit substrate 102 maintain a state in which they are superimposed on each other, and may be expressed as "bonding" depending on the specific method.

[0010] In the following, an embodiment in which the photoelectric conversion device 100 is used for imaging will be mainly described. In this case, the photoelectric conversion device 100 can be used as an imaging element (image sensor) for generating an image. Other examples of the photoelectric conversion device 100 include a distance measuring element (a sensor used for focus detection or distance measurement using TOF (Time Of Flight), a photometric element (a sensor used for measuring the amount of incident light, etc.), and a LiDAR (Light Detection and Ranging) sensor. The embodiment described below can be applied to photoelectric conversion devices in general.

[0011] The photoelectric conversion device 100 includes a light receiving region 104 and a peripheral region 105 in a plan view relative to the boundary 103. The light receiving region 104 is a region in which a plurality of light receiving circuits 106 are arranged. FIG. 1 illustrates an example in which the light receiving circuit 106 includes a SPAD (Single Photon Avalanche Diode) sensor. Alternatively, the light receiving circuit 106 may include another structure, for example, a CMOS (Complementary Metal Oxide Semiconductor) sensor. An opening 110 is formed in the peripheral region 105, which extends to an electrode pad 111 for external connection.

[0012] The light-receiving substrate 101 includes an optical layer 120, a semiconductor layer 130, a wiring layer 140, and a bonding layer 150. The configuration of each layer of the light-receiving substrate 101 will be specifically described below.

[0013] The semiconductor layer 130 includes a semiconductor substrate 131 in which a plurality of light receiving circuits 106 are formed. The semiconductor substrate 131 is made of, for example, silicon. Impurity regions 132 and 133 are formed in the semiconductor substrate 131. The impurity region 132 functions as an anode of the SPAD sensor. The impurity region 133 functions as a cathode of the SPAD sensor. In this manner, the impurity regions 132 and 133 form the light receiving circuit 106.

[0014] The wiring layer 140 is composed of an interlayer insulating film 141, a plurality of conductive patterns 142-144 embedded in the interlayer insulating film 141, and a plurality of vias 145. Each of the plurality of vias 145 connects different conductive patterns to each other or connects a conductive pattern to an impurity region. Although the example of FIG. 1 shows three layers of conductive patterns 142-144, the number of layers of the conductive patterns is not limited to this. Of the three layers of conductive patterns 142-144, the conductive pattern 144 is closest to the boundary 103, the conductive pattern 143 is next closest to the boundary 103, and the conductive pattern 142 is next closest to the boundary 103 (i.e., the furthest).

[0015] The bonding layer 150 is composed of a via 151, a barrier film 152, a bonding film 153, and a plurality of electrodes 154. All of the plurality of electrodes 154 face the boundary 103. The via 151 connects the electrode 154 and the conductive pattern 144. The electrode 154 and the via 151 are made of a material such as copper.

[0016] The bonding film 153 is disposed around the multiple electrodes 154 and insulates the multiple electrodes 154 from each other. The bonding film 153 faces the boundary 103. The bonding film 153 is made of, for example, an oxide. The barrier film 152 is located between the wiring layer 140 and the bonding film 153. The barrier film 152 is made of, for example, a nitride. The barrier film 152 prevents copper, which is the material of the electrodes 154, from diffusing into the semiconductor layer 130.

[0017] The optical layer 120 is composed of an optical interlayer film 122, an optical separating member 125, a color filter interlayer film 121, a color filter 124, and a microlens 123. The optical separating member 125 is embedded in the optical interlayer film 122. The optical separating member 125 suppresses color mixing between adjacent light receiving circuits 106. The color filter 124 is embedded in the color filter interlayer film 121. The microlens 123 focuses light incident from the optical layer 120 (upper side in FIG. 1) onto the light receiving circuit 106.

[0018] The circuit board 102 has a semiconductor layer 180, a wiring layer 170, and a bonding layer 160. The circuit board 102 has a circuit for generating a control signal for controlling the light receiving circuit 106, a circuit for processing a signal generated in the light receiving circuit 106, and the like.

[0019] The semiconductor layer 180 includes a semiconductor substrate 181. The semiconductor substrate 181 is made of, for example, silicon. An impurity region 182 is formed in the semiconductor substrate 181. A gate electrode 183 is formed so as to cover a part of the surface of the semiconductor substrate 181. The impurity region 182 and the gate electrode 183 form a transistor. In this manner, a plurality of circuit elements are formed in the semiconductor layer 180.

[0020] The wiring layer 170 is composed of an interlayer insulating film 171, a plurality of conductive patterns 172-174 embedded in the interlayer insulating film 171, and a plurality of vias. Of the three layers of conductive patterns 172-174, the conductive pattern 172 is closest to the boundary 103, the conductive pattern 173 is the next closest to the boundary 103, and the conductive pattern 174 is the next closest to the boundary 103 (i.e., the furthest). The conductive patterns 172-174 may be made of aluminum.

[0021] The conductive pattern 172 includes electrode pads 111 for external connection. As described above, the electrode pads 111 are exposed to the outside through the openings 110. When the photoelectric conversion device 100 is mounted in a package, a bonding wire is connected to the electrode pads 111. The electrode pads 111 may be made of aluminum so that wire bonding is possible.

[0022] The bonding layer 160 is composed of a bonding film 161, a barrier film 162, and a plurality of electrodes 163. The bonding film 153 and the bonding film 161 are bonded to each other, and the electrodes 154 and 163 are bonded to each other, whereby the light-receiving substrate 101 and the circuit substrate 102 are bonded to each other.

[0023] With reference to FIG. 2, a circuit layout example of the photoelectric conversion device 100 according to the first embodiment will be described. The circuit layout is a layout in a plan view with respect to the boundary 103. The same applies to the following circuit layouts. FIG. 2(a) shows a layout example of the light receiving substrate 101, and FIG. 2(b) shows a layout example of the circuit substrate 102. In the example shown in FIG. 1, the photoelectric conversion device 100 has a light receiving array 201, a plurality of AD (analog-digital) conversion units 205, a plurality of logic units 206, a plurality of interface (I / F) units 207, and a plurality of vertical scanning circuits 208. In the following description, when focusing on an individual component among a plurality of components, an alphabetic suffix is ​​added after the reference symbol. For example, an AD converter 205a represents a specific one of the plurality of AD converters 205.

[0024] The light receiving array 201 is included in the light receiving substrate 101. The light receiving array 201 has light receiving circuits 106 arranged in a two-dimensional array. The light receiving circuits 106 convert incident light into an electric signal. When the photoelectric conversion device 100 is used as a solid-state imaging device, the light receiving circuits 106 may also be called pixel circuits. The light receiving substrate 101 includes a plurality of drive lines 202 provided for each row of the light receiving array 201, and a plurality of signal lines 203 provided for each column of the light receiving array 201. The row of the light receiving array 201 refers to the plurality of light receiving circuits 106 arranged in the left-right direction in FIG. 1. The column of the light receiving array 201 refers to the plurality of light receiving circuits 106 arranged in the up-down direction in FIG. 1. The drive lines 202 are conductive lines for supplying control signals to the light receiving array 201. The signal lines 203 are conductive lines for transmitting signals generated by the light receiving array 201.

[0025] The AD conversion units 205, the logic units 206, the interface units 207, and the vertical scanning circuits 208 are included in the circuit board 102. The circuit board 102 includes an area 204a in the left half and an area 204b in the right half. Some layers in the areas 204a and 204b may be formed in two separate steps using a common mask set. For example, the semiconductor layer 180, the conductive patterns 173 and 174, and the vias between these layers may be formed by split exposure using a common mask set in the areas 204a and 204b. As a result, the semiconductor layer 180, the conductive patterns 173 and 174, and the vias between these layers have the same circuit configuration in the areas 204a and 204b. On the other hand, the conductive pattern 172 and the vias connected thereto may be formed by one-shot exposure. In the example of FIG. 1(b), the circuit board 102 is divided into two regions 204a and 204b, but the circuit board 102 may be divided into three or more regions having the same configuration except for a portion.

[0026] Each of the vertical scanning circuits 208 can generate a control signal to be supplied to the light receiving circuit 106. The connection relationship between the vertical scanning circuits 208 and the driving lines 202 will be described later. The vertical scanning circuits 208a and 208b are included in the region 204a. The vertical scanning circuits 208c and 208d are included in the region 204b. Since the region 204a and the region 204b have the same circuit configuration, the vertical scanning circuits 208a and 208c have the same circuit configuration, and the vertical scanning circuits 208b and 208d have the same circuit configuration. Furthermore, all of the vertical scanning circuits 208a to 208d may have the same circuit configuration.

[0027] The AD conversion unit 205a converts an analog signal generated by a part of the light receiving circuit 106 of the light receiving array 201 into a digital signal. The logic unit 206a reads out the digital signal from the AD conversion unit 205a and processes the digital signal. For example, the logic unit 206a may perform correction processing or complementation processing on the digital signal. The interface unit 207 outputs the digital signal processed by the logic unit 206a to the outside of the photoelectric conversion device 100. The AD conversion units 205b to 205d, the logic units 206b to 206d, and the interface units 207b to 207d are similar to the AD conversion unit 205a, the logic unit 206a, and the interface unit 207a, and therefore will not be described again.

[0028] The AD conversion unit 205, the logic unit 206, and the interface unit 207 constitute a processing circuit 210 that processes signals obtained by the light receiving array 201. The circuit board 102 has separate processing circuits 210 in the area 204a and the area 204b. Specifically, the area 204a includes a processing circuit 210a, and the area 204b includes a processing circuit 210b. The processing circuits 210a and 210b have the same circuit configuration in the portion of the circuit board 102 below the conductive pattern 173.

[0029] The processing circuits 210a and 210b are electrically connected by a conductive line 209 included in the topmost conductive pattern. In the example of Fig. 2(b), the AD conversion units 205a and 205c are electrically connected by a conductive line 209a, and the AD conversion units 205b and 205d are electrically connected by a conductive line 209b. The conductive lines 209a and 209b are included in the topmost conductive pattern 172 of the circuit board 102 formed by, for example, flood exposure.

[0030] The vertical scanning circuits 208b and 208c are located between the processing circuits 210a and 210b. Therefore, the conductive lines 209a and 209b overlap the vertical scanning circuits 208b and 208c, respectively, in a plan view relative to the boundary 103, and extend to intersect the vertical scanning circuits 208b and 208c. The vertical scanning circuit 208a is located between the processing circuit 210a and the edge of the photoelectric conversion device 100. The vertical scanning circuit 208b is located between the processing circuit 210b and the edge of the photoelectric conversion device 100. Neither of the conductive lines 209a and 209b intersects the vertical scanning circuits 208a and 208d in a plan view relative to the boundary 103. The processing circuit 210a is located between the vertical scanning circuits 208a and 208b, and is also located between the vertical scanning circuits 208a and 208c. The processing circuit 210b is located between the vertical scanning circuit 208d and the vertical scanning circuit 208b, and is also located between the vertical scanning circuit 208d and the vertical scanning circuit 208c. The vertical scanning circuits 208b and 208c are located so as to overlap with the light receiving array 201 in a plan view with respect to the boundary 103. The vertical scanning circuits 208a and 208d are located so as not to overlap with the light receiving array 201 in a plan view with respect to the boundary 103. The vertical scanning circuit 208b is located between the vertical scanning circuit 208c and the processing circuit 210a. The vertical scanning circuit 208c is located between the vertical scanning circuit 208b and the processing circuit 210b.

[0031] A specific example of the circuit configuration of the light receiving circuit 106 will be described with reference to the circuit diagram of Fig. 3. The light receiving circuit 106 can have any configuration that converts incident light into an electrical signal. Although Fig. 3 describes one example, the light receiving circuit 106 may have another configuration.

[0032] In the example illustrated in FIG. 3, the light receiving circuit 106 includes a photoelectric conversion element 301, a transfer transistor 302, an amplification transistor 303, a selection transistor 304, a reset transistor 305, and a gain change transistor 306. In the example illustrated in FIG. 3, four drive lines 202 are arranged for each row of the light receiving array 201. The drive line 202a supplies a control signal SEL. The drive line 202b supplies a control signal RES. The drive line 202c supplies a control signal FDINC. Depending on the configuration of the light receiving circuit 106, two or more drive lines may be arranged for each row, or only one drive line may be arranged.

[0033] The photoelectric conversion element 301 converts incident light into an electric charge and accumulates the electric charge. The photoelectric conversion element 301 may be, for example, a photodiode or a phototransistor. The photoelectric conversion element 301 may be a CMOS sensor or a SPAD sensor.

[0034] The photoelectric conversion element 301 is connected to the floating diffusion 307 through the transfer transistor 302. A control signal TX is supplied to the gate of the transfer transistor 302 from the vertical scanning circuit 208 through a drive line 202d. In response to the control signal TX becoming active level, the transfer transistor 302 becomes conductive. In response to this, the signal charge accumulated in the photoelectric conversion element 301 is transferred to the floating diffusion 307. The charge signal transferred from the photoelectric conversion element 301 is converted into a voltage signal by the parasitic capacitance associated with the floating diffusion 307.

[0035] The floating diffusion 307 is also connected to the gate of the amplification transistor 303. One main electrode of the amplification transistor 303 is connected to the signal line 203 via the selection transistor 304. The other main electrode of the amplification transistor 303 is connected to a power supply line 308 to which a power supply voltage VDD is supplied. A control signal SEL is supplied to the gate of the selection transistor 304 from the vertical scanning circuit 208 through the drive line 202a. In response to the control signal SEL becoming active level, the selection transistor 304 becomes conductive. In response to this, one main electrode of the amplification transistor 303 is connected to a current source 402 (FIG. 4) of the AD conversion unit 205. As a result, the amplification transistor 303 operates as a source follower, and a signal corresponding to the potential of the floating diffusion 307 is read out to the signal line 203.

[0036] The reset transistor 305 is connected between the gain change transistor 306 and a power supply line 308. A control signal RES is supplied to the gate of the reset transistor 305 from the vertical scanning circuit 208 through the drive line 202b. In response to the control signal RES becoming active level, the reset transistor 305 becomes conductive. In response to this, the potential of the floating diffusion 307 is reset to the power supply voltage VDD.

[0037] The gain change transistor 306 is connected between the floating diffusion 307 and the reset transistor 305. A control signal FDINC is supplied to the gate of the gain change transistor 306 from the vertical scanning circuit 208 through the drive line 202c. In response to the control signal FDINC becoming active level, the gain change transistor 306 becomes conductive. When the gain change transistor 306 becomes conductive, the gain of the charge-voltage conversion by the floating diffusion 307 is changed.

[0038] The light receiving circuit 106 is not limited to the above-mentioned configuration. For example, the number of signal lines 203 may be one for each column of the light receiving array 201, or may be two or more. One light receiving circuit 106 may include multiple selection transistors 304. The floating diffusion 307 may be shared by multiple photoelectric conversion elements 301.

[0039] A specific example of the circuit configuration of the AD conversion units 205a and 205c will be described with reference to the circuit diagram in Fig. 4. The AD conversion units 205b and 205d may be similar, so their description will be omitted. The AD conversion unit 205 may have any configuration that converts an analog signal into a digital signal. Although Fig. 4 describes one example, the AD conversion unit 205 may have other configurations.

[0040] The AD conversion units 205a and 205c each have a plurality of AD conversion circuits 400 corresponding to the columns of the light receiving array 201, a ramp signal generating circuit 410, and a counter 420. The AD conversion circuits 400 and the signal line 203 are electrically connected by a conductive member 401. The conductive member 401 extends in a direction perpendicular to the boundary 103. The conductive member 401 is composed of a part of a conductive pattern (such as the conductive pattern 142) included in the wiring layer 140, the bonding layer 150, the bonding layer 160, and the wiring layer 170, a via (such as the via 145), and an electrode (such as the electrode 154).

[0041] The AD conversion circuit 400 includes a current source 402, a comparator 403, and memories 404 and 405. The current source 402 generates a bias current that is supplied to the amplifying transistor 303 of the light receiving circuit 106 through a conductive member 401 and a signal line 203.

[0042] The signal from the light receiving circuit 106 is supplied to the inverting input terminal of the comparator 403, and the ramp signal is supplied from the ramp signal generation circuit 410 to the non-inverting input terminal of the comparator 403. The comparator 403 supplies the comparison result between the signal from the light receiving circuit 106 and the ramp signal to the memory 404. The memory 404 stores the count value of the counter 420 at the time when the output value from the comparator 403 is inverted. This count value represents the digital value of the signal from the light receiving circuit 106. The digital signal stored in the memory 404 is transferred to the memory 405 and then read out by the logic unit 206.

[0043] In FIG. 4, a conductive line 209c for transmitting a ramp signal is shown as an example of the conductive line 209a connecting the AD conversion units 205a and 205c shown in FIG. 2(b). The ramp signal generated by the ramp signal generating circuit 410 included in the AD conversion unit 205a is supplied not only to the AD conversion circuit 400 of the AD conversion unit 205a but also to the AD conversion circuit 400 of the AD conversion unit 205c through the conductive line 209c. By using a common ramp signal, the difference in characteristics between the AD conversion unit 205a and the AD conversion unit 205c is reduced. The ramp signal generating circuit 410 of the AD conversion unit 205c has the same circuit configuration as the ramp signal generating circuit 410 of the AD conversion unit 205a. The ramp signal generating circuit 410 of the AD conversion unit 205c may not be used and may be inoperative. In the example of FIG. 4, a common counter 420 is arranged for the plurality of AD conversion circuits 400. Alternatively, an individual counter 420 may be arranged for each AD conversion circuit 400.

[0044] A specific circuit configuration example of the vertical scanning circuit 208 will be described with reference to the circuit diagram of FIG. 5. Any of the vertical scanning circuits 208a to 208d may have this circuit configuration. The vertical scanning circuit 208 has row driver circuits 500 arranged corresponding to each row of the light receiving array 201, and a shift register 501. One row driver circuit 500 has a driver circuit group including driver circuits 510, 520, 530, and 540. In FIG. 5, the overall configuration of the vertical scanning circuit 208 is shown on the left side, and the configuration of one row driver circuit 500 is shown on the right side.

[0045] The driver circuit 510 generates a control signal SEL in response to a control signal SELIN supplied from the shift register 501, and supplies the control signal SEL to the conductive member 511. The conductive member 511 electrically connects the driver circuit 510 and the drive line 202a. The driver circuit 520 generates a control signal RES in response to a control signal RESIN supplied from the shift register 501, and supplies the control signal RES to the conductive member 521. The conductive member 521 electrically connects the driver circuit 510 and the drive line 202b. The driver circuit 530 generates a control signal FDINC in response to a control signal FDINCIN supplied from the shift register 501, and supplies the control signal FDINC to the conductive member 531. The conductive member 531 electrically connects the driver circuit 510 and the drive line 202c. The driver circuit 540 generates a control signal TX in response to a control signal TXIN supplied from the shift register 501, and supplies the control signal TX to the conductive member 541. The conductive member 541 electrically connects the driver circuit 510 and the drive line 202d.

[0046] The conductive members 511, 521, 531, and 541 all extend from the vertical scanning circuit 208 (specifically, the row driver circuit 500) in a direction perpendicular to the boundary 103. The conductive members 511, 521, 531, and 541 are each composed of a part of a conductive pattern (such as the conductive pattern 142) included in the wiring layer 140, the bonding layer 150, the bonding layer 160, and the wiring layer 170, a via (such as the via 145), and an electrode (such as the electrode 154).

[0047] The connection relationship between the vertical scanning circuit 208 and the driving lines 202 will be described with reference to Fig. 6 and Fig. 7. Fig. 6(a) shows the connection relationship between four driving lines 202a to 202d and four vertical scanning circuits 208a to 208d for one row of the light receiving array 201. The other rows of the light receiving array 201 may have a similar connection relationship. As described above, the conductive line 209a is located between the vertical scanning circuits 208b and 208c and the driving line 202, but is not located between the vertical scanning circuits 208a and 208d and the driving line 202.

[0048] Each of the vertical scanning circuits 208a, 208b, and 208d is electrically connected to all of the four driving lines 202a to 202d for one row of the light receiving array 201. By supplying a control signal to one driving line 202 from both ends and the center of the substrate in this manner, it becomes possible to control the light receiving circuit 106 at high speed. When the other rows of the light receiving array 201 have a similar connection relationship, the vertical scanning circuits 208a, 208b, and 208d are electrically connected to all of the multiple driving lines 202 arranged for the light receiving array 201 and supply control signals.

[0049] On the other hand, the vertical scanning circuit 208c is not electrically connected to any of the four driving lines 202a to 202d for one row of the light receiving array 201. When the other rows of the light receiving array 201 have a similar connection relationship, the vertical scanning circuit 208c is not electrically connected to any of the driving lines 202 arranged for the light receiving array 201. In this specification, a circuit that can generate control signals by having a row driver circuit 500 like the vertical scanning circuit 208c but cannot supply the control signals to any of the driving lines 202 is also referred to as a vertical scanning circuit.

[0050] Fig. 7(a) shows an example of the layout of the conductive pattern 172 (Fig. 2) in the region 601 in Fig. 6(a). In Fig. 7(a), the region 701 represents a position overlapping the vertical scanning circuit 208b in a plan view with respect to the boundary 103, and the region 702 represents a position overlapping the vertical scanning circuit 208c in a plan view with respect to the boundary 103.

[0051] The conductive member 703 is a portion of the conductive pattern 172 that constitutes the conductive member 541. The conductive member 704 is a portion of the conductive pattern 172 that constitutes the conductive member 531. The conductive member 705 is a portion of the conductive pattern 172 that constitutes the conductive member 521. The conductive member 706 is a portion of the conductive pattern 172 that constitutes the conductive member 511. A control signal for one row of the light-receiving array 201 is supplied by four conductive members 703 to 706 arranged in the horizontal direction in FIG. 7(a). FIG. 7(a) shows the conductive members 703 to 706 of four rows of the light-receiving array 201.

[0052] In region 701, conductive members 511, 521, 531, and 541 extend from vertical scanning circuit 208b in a direction perpendicular to boundary 103, so that conductive pattern 172 includes conductive members 703-706. Accordingly, conductive line 209a has a shape in which a portion is narrowed so as to avoid conductive members 703-706. As a result, conductive line 209a has a higher resistance per unit length in region 701 than the surrounding portions.

[0053] On the other hand, in the region 702, since the conductive members 511, 521, 531, and 541 do not need to extend from the vertical scanning circuit 208c in the direction perpendicular to the boundary 103, the conductive pattern 172 does not need to include the conductive members 703-706. Therefore, the resistance value per unit length of the conductive line 209a in the region 702 is the same as that of the surrounding parts. Also, in the region 701, coupling occurs between the conductive line 209a and the conductive members 703-706 and the vias connected thereto. However, in the region 702, since the conductive members 703-706 and the vias connected thereto do not exist, such coupling is reduced.

[0054] 6(a) and 7(a), only one of the vertical scanning circuits 208b and 208c is electrically connected to the drive line 202. This can reduce the resistance and coupling of the conductive line 209a compared to the case where both of the vertical scanning circuits 208b and 208c are electrically connected to the drive line 202. In other words, it can reduce the effect that the conductive member that transmits the control signal from the vertical scanning circuit 208 has on the conductive line 209 that transmits signals other than the control signal.

[0055] In the connection relationship shown in Figures 6(a) and 7(a), the light receiving circuit 106 is controlled at high speed by supplying a control signal to the driving line 202 from one of the vertical scanning circuits 208b and 208c located at a position overlapping the light receiving array 201 in a plan view relative to the boundary 103. Alternatively, both of the vertical scanning circuits 208b and 208c do not need to be electrically connected to any of the multiple driving lines 202. Even in this case, it is possible to supply control signals from the vertical scanning circuits 208a and 208d to all of the multiple driving lines 202. In addition, the influence of the conductive member transmitting the control signal from the vertical scanning circuit 208 on other conductive lines 209 can be further reduced.

[0056] Other connection relationships between the vertical scanning circuit 208 and the driving lines 202 will be described with reference to Fig. 6(b) and Fig. 7(b). Descriptions of configurations that may be similar to Fig. 6(a) and Fig. 7(a) will be omitted. Fig. 6(b) shows the connection relationships between four driving lines 202a to 202d and four vertical scanning circuits 208a to 208d for one row of the light receiving array 201. Similar connection relationships may also be used for other rows of the light receiving array 201.

[0057] Each of the vertical scanning circuits 208a and 208d is electrically connected to all of the four driving lines 202a to 202d for one row of the light receiving array 201. When the other rows of the light receiving array 201 have a similar connection relationship, the vertical scanning circuits 208a and 208d are electrically connected to all of the multiple driving lines 202 arranged for the light receiving array 201 and supply control signals.

[0058] On the other hand, the vertical scanning circuit 208c is electrically connected to some of the four driving lines 202a to 202d for one row of the light receiving array 201, and is not electrically connected to other parts of the four driving lines 202a to 202d. Specifically, the vertical scanning circuit 208c is electrically connected to the driving lines 202a and 202b, and is not electrically connected to the driving lines 202c and 202d. In the connection relationship shown in FIG. 6(b), unlike the connection relationship shown in FIG. 6(a), the vertical scanning circuit 208c functions as a vertical scanning circuit that supplies control signals to some of the multiple driving lines 202.

[0059] On the other hand, the vertical scanning circuit 208b is electrically connected to the driving line 202 that is not electrically connected to the vertical scanning circuit 208c among the four driving lines 202a to 202d for one row of the light receiving array 201. Specifically, the vertical scanning circuit 208b is electrically connected to the driving lines 202c and 202d, and is not electrically connected to the driving lines 202a and 202b. Even with the connection relationship shown in FIG. 6(b), it is possible to control the light receiving circuit 106 at high speed by supplying a control signal to one driving line 202 from both ends and the center of the substrate in this manner.

[0060] FIG. 7(b) shows a layout example of the conductive pattern 172 (FIG. 2) in the region 602 of FIG. 6(b). In this layout example, the influence of the conductive member transmitting the control signal from the vertical scanning circuit 208 on the conductive line 209 transmitting signals other than the control signal can be reduced. With reference to FIG. 6(c) and FIG. 7(c), other connection relationships between the vertical scanning circuit 208 and the driving lines 202 will be described. Descriptions of configurations that may be the same as those in FIG. 6(a) and FIG. 7(a) will be omitted. FIG. 6(c) shows the connection relationship between a total of eight driving lines 202a to 202d for two rows of the light receiving array 201 and two vertical scanning circuits 208b and 208c. The other two rows of the light receiving array 201 may have the same connection relationship. The vertical scanning circuits 208a and 208d may be electrically connected to all the driving lines 202 as in the example of FIG. 6(a), and therefore descriptions thereof will be omitted.

[0061] Of the vertical scanning circuit 208b, a row driver circuit 500a arranged for one row 604 of the light receiving array 201 is not electrically connected to any of the four drive lines 202a to 202d arranged for the row 604. On the other hand, of the vertical scanning circuit 208b, a row driver circuit 500b arranged for another row 605 of the light receiving array 201 is electrically connected to all of the four drive lines 202a to 202d arranged for the row 605. The rows 604 and 605 may be adjacent to each other.

[0062] Of the vertical scanning circuit 208c, the row driver circuit 500c arranged for the row 604 of the light receiving array 201 is electrically connected to all of the four drive lines 202a to 202d arranged for the row 604. On the other hand, of the vertical scanning circuit 208c, the row driver circuit 500d arranged for the row 605 of the light receiving array 201 is not electrically connected to any of the four drive lines 202a to 202d arranged for the row 605.

[0063] Even with the connection relationship of FIG. 6(c), by supplying control signals to one drive line 202 from both ends and the center of the substrate in this manner, it is possible to control the light receiving circuit 106 at high speed.

[0064] Fig. 7(c) shows an example of the layout of the conductive pattern 172 (Fig. 2) in the region 602 in Fig. 6(c). In this layout example as well, it is possible to reduce the influence of the conductive member that transmits the control signal from the vertical scanning circuit 208 on the conductive line 209 that transmits signals other than the control signal. <Second embodiment> An example of the configuration of a photoelectric conversion device 100 according to the second embodiment will be described with reference to Fig. 8 and Fig. 9. Description of configurations that may be similar to those of the first embodiment will be omitted.

[0065] An example of the circuit layout of the photoelectric conversion device 100 according to the second embodiment will be described with reference to Fig. 8. Fig. 8(a) shows an example of the layout of the light receiving substrate 101, and Fig. 8(b) shows an example of the layout of the circuit substrate 102. In the second embodiment, all layers of the circuit substrate 102 may be formed by one-shot exposure. Therefore, the vertical scanning circuit 208 located in the center of the circuit substrate 102 may be only the vertical scanning circuit 208f.

[0066] The vertical scanning circuit 208f is located between the processing circuit 210a and the processing circuit 210b. Therefore, the conductive lines 209a and 209b each overlap the vertical scanning circuit 208f in a plan view relative to the boundary 103 and extend to intersect the vertical scanning circuit 208f. The vertical scanning circuit 208e is located between the processing circuit 210a and the edge of the photoelectric conversion device 100. The vertical scanning circuit 208g is located between the processing circuit 210b and the edge of the photoelectric conversion device 100. Both the conductive lines 209a and 209b intersect the vertical scanning circuit 208f in a plan view relative to the boundary 103, but do not intersect the vertical scanning circuits 208e and 208f. The processing circuit 210a is located between the vertical scanning circuit 208e and the vertical scanning circuit 208f. The processing circuit 210b is located between the vertical scanning circuit 208g and the vertical scanning circuit 208f. The vertical scanning circuit 208f is located so as to overlap the light receiving array 201 in a plan view with respect to the boundary 103. All of the vertical scanning circuits 208e to 208g may have the same circuit configuration.

[0067] The connection relationship between the vertical scanning circuit 208 and the driving lines 202 will be described with reference to Fig. 9. Fig. 9 shows the connection relationship between four driving lines 202a to 202d and three vertical scanning circuits 208e to 208g for one row of the light receiving array 201. The other rows of the light receiving array 201 may have a similar connection relationship. The conductive line 209a is located between the vertical scanning circuit 208f and the driving line 202, but is not located between the vertical scanning circuits 208e and 208g and the driving line 202.

[0068] Each of the vertical scanning circuits 208e and 208f is electrically connected to all of the four driving lines 202a to 202d for one row of the light receiving array 201. When the other rows of the light receiving array 201 have a similar connection relationship, the vertical scanning circuits 208e and 208f are electrically connected to all of the multiple driving lines 202 arranged for the light receiving array 201 and supply control signals.

[0069] On the other hand, the vertical scanning circuit 208f is electrically connected to only some of the four driving lines 202a to 202d for one row of the light receiving array 201. For example, the vertical scanning circuit 208f is electrically connected to the driving lines 202a and 202d, but is not electrically connected to the driving lines 202b and 202c. Therefore, the driving lines 202a and 202d can be controlled at a higher speed than the driving lines 202b and 202c because a control signal is also supplied from the center of the circuit board 102. In addition, since the vertical scanning circuit 208f is not electrically connected to some of the four driving lines 202, the influence of the conductive member that transmits the control signal from the vertical scanning circuit 208 on the conductive line 209 that transmits signals other than the control signal can be reduced.

[0070] <Third embodiment> An example of the configuration of a photoelectric conversion device 100 according to the third embodiment will be described with reference to Fig. 10 and Fig. 11. Description of configurations that may be similar to those of the first embodiment will be omitted.

[0071] An example of the circuit layout of the photoelectric conversion device 100 according to the third embodiment will be described with reference to Fig. 10. Fig. 10(a) shows an example of the layout of the light receiving substrate 101, and Fig. 10(b) shows an example of the layout of the circuit substrate 102. In the third embodiment, all layers of the circuit substrate 102 may be formed by one-shot exposure. In the third embodiment, the circuit substrate 102 does not include a vertical scanning circuit 208 in the center of the circuit substrate 102 (i.e., the position overlapping with the light receiving array 201).

[0072] The circuit board 102 has a pad area 1000a on the left edge where electrode pads for external connection (e.g., electrode pad 111) are arranged. The circuit board 102 has a pad area 1000b on the right edge where electrode pads for external connection (e.g., electrode pad 111) are arranged. The circuit board 102 has vertical scanning circuits 208h and 208i. The vertical scanning circuit 208h is located between the processing circuit 210 and the pad area 1000a. The pad area 1000a is located between the vertical scanning circuit 208h and the edge of the photoelectric conversion device 100. The vertical scanning circuit 208i is located between the processing circuit 210 and the pad area 1000b. The pad area 1000b is located between the vertical scanning circuit 208i and the edge of the photoelectric conversion device 100. The vertical scanning circuits 208h and 208i are located so as not to overlap the light receiving array 201 in a plan view relative to the boundary 103.

[0073] The processing circuit 210 and the electrode pads in the pad region 1000a are electrically connected by conductive lines 1001. The conductive lines 1001 are used for transmitting signals or supplying power. In a plan view relative to the boundary 103, the conductive lines 1001 overlap the vertical scanning circuits 208h and extend so as to intersect with the vertical scanning circuits 208h.

[0074] The processing circuit 210 and the electrode pads in the pad area 1000b are electrically connected by a conductive line 1002. The conductive line 1002 is used for transmitting signals or supplying power. The vertical scanning circuits 208h and 208i may have the same circuit configuration. The conductive line 1002 overlaps the vertical scanning circuit 208i in a plan view relative to the boundary 103 and extends to intersect with the vertical scanning circuit 208i.

[0075] The connection relationship between the vertical scanning circuit 208 and the driving lines 202 will be described with reference to Fig. 11. Fig. 11(a) shows the connection relationship between four driving lines 202a to 202d and two vertical scanning circuits 208h and 208i for one row of the light receiving array 201. The other rows of the light receiving array 201 may have a similar connection relationship. A conductive line 1001 is located between the vertical scanning circuit 208h and the driving line 202, and a conductive line 1002 is located between the vertical scanning circuit 208i and the driving line 202.

[0076] The vertical scanning circuit 208h is electrically connected to all of the four driving lines 202a to 202d for one row of the light receiving array 201. When the other rows of the light receiving array 201 have a similar connection relationship, the vertical scanning circuit 208h is electrically connected to all of the multiple driving lines 202 arranged for the light receiving array 201 and supplies control signals.

[0077] On the other hand, the vertical scanning circuit 208i is electrically connected to only some of the four driving lines 202a to 202d for one row of the light receiving array 201. For example, the vertical scanning circuit 208i is electrically connected to the driving lines 202a and 202d, but is not electrically connected to the driving lines 202b and 202c. Therefore, the driving lines 202a and 202d can be controlled at a higher speed than the driving lines 202b and 202c, since control signals are supplied from both sides of the circuit board 102. In addition, since the vertical scanning circuit 208i is not electrically connected to some of the four driving lines 202, the influence of the conductive member that transmits the control signal from the vertical scanning circuit 208i on the conductive line 1002 can be reduced.

[0078] With reference to Fig. 11(b), another connection relationship between the vertical scanning circuit 208 and the driving lines 202 will be described. A description of a configuration that may be the same as that in Fig. 11(a) will be omitted. Fig. 11(b) shows a connection relationship between four driving lines 202a to 202d and four vertical scanning circuits 208h and 208i for one row of the light receiving array 201. The other rows of the light receiving array 201 may have a similar connection relationship.

[0079] The vertical scanning circuit 208i is electrically connected to some of the four driving lines 202a to 202d for one row of the light receiving array 201, and is not electrically connected to other parts of the four driving lines 202a to 202d. Specifically, the vertical scanning circuit 208i is electrically connected to the driving lines 202a and 202b, and is not electrically connected to the driving lines 202c and 202d.

[0080] On the other hand, the vertical scanning circuit 208h is electrically connected to the driving lines 202 that are not electrically connected to the vertical scanning circuit 208i among the four driving lines 202a to 202d for one row of the light receiving array 201. Specifically, the vertical scanning circuit 208h is electrically connected to the driving lines 202c and 202d, and is not electrically connected to the driving lines 202a and 202b. Even in the connection relationship shown in FIG. 11(b), a control signal is supplied to each of the driving lines 202. In this layout example as well, the influence of the conductive members that transmit the control signals from the vertical scanning circuits 208h and 208i on the conductive lines 1001 and 1002 can be reduced.

[0081] With reference to Fig. 11(c), another connection relationship between the vertical scanning circuit 208 and the driving lines 202 will be described. Description of configurations that may be similar to those in Fig. 11(a) will be omitted. Fig. 11(c) shows the connection relationship between a total of eight driving lines 202a to 202d for two rows of the light receiving array 201 and two vertical scanning circuits 208h and 208i. The other two rows of the light receiving array 201 may have a similar connection relationship.

[0082] In the vertical scanning circuit 208h, a row driver circuit 500a arranged for one row 604 of the light receiving array 201 is not electrically connected to any of the four drive lines 202a to 202d arranged for the row 604. On the other hand, in the vertical scanning circuit 208h, a row driver circuit 500b arranged for another row 605 of the light receiving array 201 is electrically connected to all of the four drive lines 202a to 202d arranged for the row 605. The rows 604 and 605 may be adjacent to each other.

[0083] Of the vertical scanning circuits 208i, the row driver circuit 500c arranged for the row 604 of the light receiving array 201 is electrically connected to all of the four drive lines 202a to 202d arranged for the row 604. On the other hand, of the vertical scanning circuits 208i, the row driver circuit 500d arranged for the row 605 of the light receiving array 201 is not electrically connected to any of the four drive lines 202a to 202d arranged for the row 605.

[0084] 11(c), a control signal is supplied to each driving line 202. In this layout example, the influence of the conductive members that transmit the control signals from the vertical scanning circuits 208h and 208i on the conductive lines 1001 and 1002 can also be reduced.

[0085] <Modification> In the above-described first and second embodiments, the conductive line 209 intersecting the vertical scanning circuit 208 transmits a ramp signal. Alternatively, the conductive line 209 intersecting the vertical scanning circuit 208 may be used to transmit a signal other than the control signal, or may be used to supply power. For example, the conductive line 209 may transmit a power supply voltage or a ground voltage of the AD conversion unit 205, a bias voltage, or a pulse signal.

[0086] In the above embodiment, all the vertical scanning circuits 208 arranged on the circuit board 102 are positioned so as to overlap all of the multiple driving lines 202 in a plan view relative to the boundary 103. Alternatively, the vertical scanning circuits 208 may overlap only a portion of the multiple driving lines 202. For example, the vertical scanning circuit 208a may be divided into two, one of which scans the upper half of the multiple driving lines 202 and the other of which scans the lower half of the driving lines 202.

[0087] <Other embodiments> With reference to FIG. 12(a), an embodiment of a device 1200 including a semiconductor device 1203 will be described in detail. The semiconductor device 1203 may be the photoelectric conversion device of any of the above-mentioned embodiments. The semiconductor device 1203 may include a semiconductor device 1201 and a package 1202 that houses the semiconductor device 1201. The package 1202 may include a base to which the semiconductor device 1201 is fixed, and a cover such as glass that faces the semiconductor device 1201. The package 1202 may further include a bonding member such as a bonding wire or a bump that connects a terminal provided on the base to a terminal (bonding pad) provided on the semiconductor device 1201.

[0088] The device 1200 may include at least one of an optical device 1204, a control device 1205, a processing device 1206, a display device 1207, a storage device 1208, and a mechanical device 1209. The optical device 1204 is, for example, a lens, a shutter, or a mirror. The control device 1205 controls the semiconductor device 1203. The control device 1205 is, for example, a semiconductor device such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0089] The processing device 1206 processes the signal output from the semiconductor device 1203. The processing device 1206 is a semiconductor device such as a CPU (Central Processing Unit) or ASIC for configuring an AFE (Analog Front End) or a DFE (Digital Front End). The display device 1207 is an EL (Electro-Luminescence) display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 1203. The storage device 1208 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 1203. The storage device 1208 is a volatile memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory), or a non-volatile memory such as a flash memory or a hard disk drive.

[0090] The mechanical device 1209 has a moving part or a propulsion part such as a motor or an engine. In the device 1200, the signal output from the semiconductor device 1203 is displayed on a display device 1207, or transmitted to the outside by a communication device (not shown) included in the device 1200. For this purpose, the device 1200 may further include a memory device 1208 and a processing device 1206 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 1203. The mechanical device 1209 may be controlled based on the signal output from the semiconductor device 1203.

[0091] The device 1200 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 1209 in the camera may drive components of the optical device 1204 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1209 in the camera may move the semiconductor device 1203 for vibration isolation.

[0092] Furthermore, the device 1200 may be a transport device such as a vehicle, a ship, or an aircraft. The mechanical device 1209 in the transport device may be used as a moving device. The device 1200 as a transport device may be one that transports the semiconductor device 1203, or one that assists and / or automates driving (piloting) by using a photographing function. The processing device 1206 for assisting and / or automating driving (piloting) may perform processing for operating the mechanical device 1209 as a moving device based on information obtained by the semiconductor device 1203. Alternatively, the device 1200 may be a medical device such as an endoscope, a measuring device such as an analytical distance sensor, an analytical device such as an electron microscope, or an office machine such as a copying machine.

[0093] An embodiment of an imaging system and a moving body will be described with reference to FIG. 12(b) and FIG. 12(c). FIG. 12(b) shows an example of an imaging system 1210 related to an on-vehicle camera. The imaging system 1210 has a photoelectric conversion device 1211. The photoelectric conversion device 1211 may be any of the photoelectric conversion devices of the above-mentioned embodiments. The imaging system 1210 has an image processing unit 1212, which is a processing device that performs image processing on a plurality of image data acquired by the photoelectric conversion device 1211. The imaging system 1210 also has a parallax acquisition unit 1213, which is a processing device that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion device 1211. The imaging system 1210 further has a distance acquisition unit 1214, which is a processing device that calculates a distance to an object based on the calculated parallax, and a collision determination unit 1215, which is a processing device that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 1213 and the distance acquisition unit 1214 are examples of information acquisition means for acquiring information such as distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 1215 may use any of these pieces of distance information to determine the possibility of a collision. The above-mentioned various processing devices may be realized by dedicated hardware, or may be realized by general-purpose hardware that performs calculations based on software modules. In addition, the processing device may be realized by an FPGA, an ASIC, or the like, or may be realized by a combination of these.

[0094] The imaging system 1210 is connected to a vehicle information acquisition device 1216, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 1210 is also connected to a control ECU 1217, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 1215. That is, the control ECU 1217 is an example of a moving body control means that controls a moving body based on distance information. The imaging system 1210 is also connected to an alarm device 1218 that issues an alarm to a driver based on the judgment result of the collision judgment unit 1215. For example, when the judgment result of the collision judgment unit 1215 indicates that a collision is highly likely, the control ECU 1217 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1218 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., and vibrating a seat belt or steering wheel.

[0095] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are captured by the imaging system 1210. Fig. 12(c) shows the imaging system 1210 capturing an image of the area in front of the vehicle (imaging range 1219). The vehicle information acquisition device 1216 sends an instruction to operate the imaging system 1210 to perform imaging.

[0096] In the above description, an example of control to avoid collision with other vehicles has been described, but the system can also be applied to automatic driving control to follow other vehicles, automatic driving control to avoid going out of lanes, etc. Furthermore, the imaging system is not limited to vehicles such as automobiles, but can be applied to moving bodies (transportation equipment) such as ships, aircraft, and industrial robots. The moving devices in moving bodies (transportation equipment) are various types of moving means such as engines, motors, wheels, and propellers. In addition, the system can be applied not only to moving bodies, but also to a wide range of equipment that uses object recognition, such as intelligent transport systems (ITS).

[0097] The above-described embodiments can be modified as appropriate without departing from the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the concepts described in this specification. In other words, if this specification contains a statement that "A is greater than B," for example, this specification discloses that "A is not greater than B" even if the statement that "A is not greater than B" is omitted. This is because when "A is greater than B" is stated, it is assumed that the case where "A is not greater than B" is taken into consideration. Claims are attached to publicize the scope of the invention. [Explanation of symbols]

[0098] 100 Photoelectric conversion device, 101 Light receiving substrate, 102 Circuit substrate, 202 Drive line, 208 Vertical scanning circuit, 209 Conductive line

Claims

1. A photoelectric conversion device in which a first substrate and a second substrate are bonded together, The first substrate is a light receiving array in which a plurality of light receiving circuits are arranged in an array; a plurality of drive lines for supplying control signals to the light receiving array; The second substrate is a first circuit including a driver circuit group that generates the control signal and functions as a vertical scanning circuit that supplies the control signal to at least some of the drive lines; a second circuit including a circuit group having the same configuration as the driver circuit group; the second circuit is located at a position overlapping at least a portion of the drive lines to which the control signal is supplied by the first circuit in a plan view of a boundary between the first substrate and the second substrate; the at least some of the drive lines to which the control signal is supplied by the first circuit include a drive line that is not electrically connected to the second circuit; A photoelectric conversion device characterized in that the second substrate has, in a planar view relative to the boundary, a conductive line used to transmit a signal other than the control signal or to supply power, at a position overlapping the second circuit.

2. The photoelectric conversion device according to claim 1 , wherein the second circuit functions as a vertical scanning circuit that supplies the control signal to at least some of the driving lines.

3. Two or more drive lines are arranged for each row of the light receiving array; The photoelectric conversion device described in claim 2, characterized in that the second circuit is electrically connected to a portion of two or more drive lines for one row of the light receiving array, and is not electrically connected to another portion of the two or more drive lines.

4. Two or more drive lines are arranged for each row of the light receiving array; The second circuit is not electrically connected to any of two or more drive lines for a row of the light receiving array; 3. The photoelectric conversion device according to claim 2, wherein the light receiving array is electrically connected to any one of two or more drive lines for another row of the light receiving array.

5. 2. The photoelectric conversion device according to claim 1, wherein the second circuit is not electrically connected to any of the plurality of drive lines.

6. Two or more drive lines are arranged for each row of the light receiving array; 6. The photoelectric conversion device according to claim 3, wherein the first circuit is electrically connected to all of two or more drive lines for one row of the light receiving array.

7. The photoelectric conversion device according to any one of claims 2 to 6, characterized in that the second substrate further has a processing circuit between the first circuit and the second circuit for processing signals obtained by the light receiving array.

8. The second substrate is a third circuit including a driver circuit group that generates the control signal and functions as a vertical scanning circuit that supplies the control signal to at least a portion of the plurality of drive lines; 8. The photoelectric conversion device according to claim 7, wherein the third circuit is located between the processing circuit and the second circuit.

9. The plurality of drive lines are 9. The photoelectric conversion device according to claim 8, further comprising a drive line that is not electrically connected to the second circuit and is electrically connected to the third circuit.

10. the second substrate includes a semiconductor layer on which a circuit element is formed; the semiconductor layer includes a first region and a second region each having the same circuit configuration; the first circuit is included in the first area; 10. The photoelectric conversion device according to claim 2, wherein the second circuit is included in the second region.

11. 11. The photoelectric conversion device according to claim 10, wherein the conductive line electrically connects a circuit formed in the first region and a circuit formed in the second region.

12. 12. The photoelectric conversion device according to claim 1, wherein the second circuit is positioned so as to overlap the light receiving array in a plan view with respect to the boundary.

13. 10. The photoelectric conversion device according to claim 1, wherein the second circuit is located between the light receiving array and an edge of the photoelectric conversion device in a plan view with respect to the boundary.

14. the second substrate further includes an electrode pad located between a second circuit and an edge of the photoelectric conversion device in a plan view with respect to the boundary, 14. The photoelectric conversion device according to claim 13, wherein the conductive line is electrically connected to the electrode pad.

15. A photoelectric conversion device according to any one of claims 1 to 14, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; A storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

Images