Semiconductor Device

Abstract

To provide a semiconductor device with a higher performance and a higher quality.SOLUTION: A semiconductor device A1 includes a semiconductor element 1, a die pad 3, a plurality of leads 4, a plurality of connecting members 7, and a resin member 2. The semiconductor element 1 is mounted on the die pad 3. The die pad 3 has a die pad main surface, and includes a first portion 31, a second portion 32, a third portion 33, and a fourth portion 34. The first portion 31 has a back surface 31a and overlaps with the semiconductor element 1 when viewed in the thickness direction z. The second portion 32 has a back surface 32a located closer to a side of the die pad main surface than the back surface 31a in the thickness direction z, and is connected to an outer edge 310 of the first portion 31. The third portion 33 has a back surface 33a being flush with the back surface 31a, and extends from an end edge 310b to an end edge 301b of the die pad main surface in one side in a second direction x of the first portion 31. The fourth portion 34 has a back surface 34a being flush with the back surface 31a, and extends from the end edge 310b to the end edge 301b in the other side in the second direction x of the first portion 31.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In order to mount a semiconductor device on a wiring board at high density, there is a surface mount type package that enables surface mounting on the wiring board. For example, a MAP (Mold Array Package) type SON (Small Outlined Non-leaded Package) and a QFN (Quad Flat Non-leaded Package) are known as this surface mount type package. Patent Document 1 discloses a semiconductor device to which a MAP type QFN is applied. The semiconductor device described in Patent Document 1 includes a semiconductor chip, a die pad, leads, a bonding wire, and a sealing resin. The semiconductor chip is bonded to the die pad. The leads are arranged around the die pad. The bonding wire electrically connects the semiconductor chip and the leads. The sealing resin seals the semiconductor chip, the die pad, the leads, and the bonding wire. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-239740 A Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the performance and quality of semiconductor devices, not only are the performance and quality of semiconductor chips required to be improved, but also modifications to the package structure of the semiconductor device are required.

[0005] The present disclosure has been made in view of the above circumstances, and has an object to provide a semiconductor device with improved performance and quality. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes: a semiconductor element having an element main surface and an element back surface spaced apart in a thickness direction, and a plurality of main surface electrodes arranged on the element main surface; a die pad having a die pad main surface on which the semiconductor element is mounted; a first lead arranged on one side of the die pad in a first direction perpendicular to the thickness direction, the plurality of leads arranged around the die pad as viewed in the thickness direction; a first connection member joined to the first lead; and a plurality of connection members electrically connecting the plurality of main surface electrodes and the plurality of leads; and a resin member that seals the semiconductor element, a portion of the die pad, portions of the plurality of leads, and the plurality of connection members, each of the plurality of leads being entirely overlapped with the resin member as viewed in the thickness direction and being arranged along an outer edge of the resin member as viewed in the thickness direction; the die pad includes a first portion, a second portion, a third portion, and a fourth portion, the die pad main surface spans the first portion, the second portion, the third portion, and the fourth portion, the first portion having a first back surface facing the opposite side to the die pad main surface and overlapping the semiconductor element when viewed in the thickness direction, the second portion having a second back surface facing the opposite side to the die pad main surface and located closer to the die pad main surface in the thickness direction than the first back surface and connected to an outer edge of the first portion when viewed in the thickness direction, the third portion having a third back surface facing the opposite side to the die pad main surface and being flush with the first back surface, and extending from an edge on one side of the first portion to an edge on the one side of the die pad main surface in a second direction perpendicular to the thickness direction and the first direction, and the fourth portion having a fourth back surface facing the opposite side to the die pad main surface and being flush with the first back surface, and extending from an edge on the other side of the first portion to an edge on the other side of the die pad main surface in the second direction. Effect of the Invention

[0007] According to the semiconductor device of the present disclosure, it is possible to achieve high performance and high quality of the semiconductor device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view (rear side) showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a plan view of FIG. 2 with the resin member seen through. [Figure 4] FIG. 4 is an enlarged view of a part (first lead) of FIG. [Diagram 5] FIG. 5 is an enlarged view of a part (second lead) of FIG. [Figure 6] FIG. 6 is a plan view of FIG. 3 in which a number of connection members are omitted. [Figure 7] FIG. 7 is a bottom view showing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a front view showing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a side view (right side view) showing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. [Figure 16] FIG. 16 is a plan view showing the semiconductor device according to the second embodiment, in which the resin member is seen through and a number of connecting members are omitted. [Figure 17] FIG. 17 is a plan view showing the semiconductor device according to the third embodiment, in which the resin member is seen through and a number of connecting members are omitted. [Figure 18] FIG. 18 is a plan view showing the semiconductor device according to the fourth embodiment, in which the resin member is seen through and a number of connecting members are omitted. [Figure 19] FIG. 19 is a plan view showing the semiconductor device according to the fifth embodiment, in which the resin member is seen through and a number of connecting members are omitted. [Figure 20] FIG. 20 is a plan view showing the semiconductor device according to the sixth embodiment, in which the resin member is seen through and a number of connecting members are omitted. [Figure 21] FIG. 21 is a plan view showing a semiconductor device according to a modified example of the present disclosure, in which a resin member is shown transparently and a plurality of connecting members are omitted. [Figure 22] FIG. 22 is a cross-sectional view showing a semiconductor device according to a modified example of the present disclosure, and corresponds to the cross section of FIG. [Figure 23] FIG. 23 is a plan view showing a semiconductor device according to a modified example of the present disclosure, seen through a resin member. [Figure 24] FIG. 24 is a plan view showing a semiconductor device according to a modified example of the present disclosure, with a resin member seen through. [Diagram 25] FIG. 25 is a plan view showing a semiconductor device according to a modified example of the present disclosure, with a resin member seen through. [Figure 26] FIG. 26 is a plan view showing a semiconductor device according to a modified example of the present disclosure, with a resin member seen through. [Figure 27] FIG. 27 is an enlarged cross-sectional view of a main portion showing a first lead according to a modified example of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A preferred embodiment of the semiconductor device of the present disclosure will be described below with reference to the drawings. In the following, identical or similar elements will be given the same reference numerals and duplicated descriptions will be omitted. Terms such as "first", "second", and "third" in this disclosure are used merely as labels and are not necessarily intended to assign any order to their objects.

[0010] In this disclosure, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on (an) object B" and "a certain object A is formed on (an) object B with another object interposed between (an) object A and (an) object B" unless otherwise specified. Similarly, "a certain object A is disposed on (an) object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on (an) object B" and "a certain object A is disposed on (an) object B with another object interposed between (an) object A and (an) object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with (an) object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between (an) object A and (an) object B". Additionally, unless otherwise specified, the phrase "when viewed in a certain direction, an object A overlaps an object B" includes "an object A overlaps the entirety of an object B" and "an object A overlaps a part of an object B."

[0011] 1 to 15 show a semiconductor device A1 according to a first embodiment. The semiconductor device A1 includes a semiconductor element 1, a resin member 2, a die pad 3, a plurality of leads 4, a plurality of third leads 43, and a plurality of connection members 7. The plurality of leads 4 include a first lead 5 and a second lead 6, while including a plurality of first lateral leads 41 and a plurality of second lateral leads 42. The plurality of connection members 7 include a plurality of first connection members 71 and a plurality of second connection members 72. In FIG. 6, the semiconductor element 1 is shown by an imaginary line. In FIGS. 3 to 6, the resin member 2 is shown by an imaginary line.

[0012] For ease of explanation, the thickness direction of each of the semiconductor element 1, the resin member 2, the die pad 3, and the multiple leads 4 is referred to as the "thickness direction z." One side of the thickness direction z may be referred to as the upper side, and the other side as the lower side. In addition, in the following explanation, "plan view" refers to a view along the thickness direction z. The direction perpendicular to the thickness direction z is referred to as the "first direction y." The first direction y is the up-down direction in the plan view of the semiconductor device A1 (see Figures 2 and 3). The direction perpendicular to the thickness direction z and the first direction y is referred to as the "second direction x." The second direction x is the left-right direction in the plan view of the semiconductor device A1 (see Figures 2 and 3).

[0013] The semiconductor device A1 is a surface mount package. The package structure of the semiconductor device A1 is, for example, a MAP type QFN. The semiconductor device A1 is rectangular in plan view. The dimension of the semiconductor device A1 in the first direction y is, for example, 3 mm or more and 12 mm or less, and the dimension of the semiconductor device A1 in the second direction x is, for example, 3 mm or more and 12 mm or less. Moreover, the dimension of the semiconductor device A1 in the thickness direction z is, for example, 0.5 mm or more and 1.5 mm or less.

[0014] The semiconductor element 1 is an element that exerts an electrical function of the semiconductor device A1. The semiconductor element 1 is rectangular in plan view. The semiconductor element 1 is, for example, an integrated circuit element, but may be an active function element or a passive function element. In this embodiment, the semiconductor element 1 is a power IC, and includes a power section 101 and a control circuit section 102 as shown in FIG. 3. The power section 101 includes a power element such as a transistor. The control circuit section 102 is a control circuit for controlling the power element of the power section 101. In the example shown in FIG. 3, the power section 101 is disposed on one side of the control circuit section 102 in the first direction y (the lower side in FIG. 3) in plan view. The semiconductor element 1 is not limited to a configuration including the power section 101 and the control circuit section 102, and may include only one of the power section 101 and the control circuit section 102.

[0015] 10 to 12, the semiconductor element 1 has a main surface 10a and a back surface 10b. The main surface 10a and the back surface 10b are spaced apart in the thickness direction z and face opposite each other. The main surface 10a faces upward in the thickness direction z, and the back surface 10b faces downward in the thickness direction z.

[0016] 10 and 11, the semiconductor element 1 has a plurality of principal surface electrodes 11 arranged on the element principal surface 10a. As shown in FIG. 3, the plurality of principal surface electrodes 11 includes a plurality of first principal surface electrodes 12 and a plurality of second principal surface electrodes 13. The plurality of first principal surface electrodes 12 are each electrically connected to the power section 101. The plurality of second principal surface electrodes 13 are each electrically connected to the control circuit section 102. The number, arrangement, shape and planar dimensions of the plurality of principal surface electrodes 11 (the plurality of first principal surface electrodes 12 and the plurality of second principal surface electrodes 13) are not limited to the example shown in FIG. 3, and may be changed as appropriate depending on the semiconductor element 1 used.

[0017] The semiconductor element 1 is bonded to the die pad 3 by, for example, a bonding material (not shown). This bonding material may be insulating or conductive. However, when an electrode is disposed on the element back surface 10b of the semiconductor element 1, the semiconductor element 1 is bonded to the die pad 3 by a conductive bonding material, and the electrode disposed on the element back surface 10b and the die pad 3 are electrically connected via the conductive bonding material.

[0018] The resin member 2 is a sealing material that protects the semiconductor element 1. The resin member 2 is made of an insulating resin material. The resin material is, for example, a black epoxy resin. The resin member 2 covers, for example, the semiconductor element 1, a portion of the die pad 3, each of the multiple leads 4, each of the multiple third leads 43, and the multiple connection members 7. The resin member 2 is rectangular in plan view. The resin member 2 has a resin main surface 21, a resin back surface 22, a pair of first resin side surfaces 23, and a pair of second resin side surfaces 24.

[0019] 8 to 12, the resin main surface 21 and the resin back surface 22 are spaced apart in the thickness direction z and face opposite each other. The resin main surface 21 faces upward in the thickness direction z, and the resin back surface 22 faces downward in the thickness direction z.

[0020] The pair of first resin side faces 23 and the pair of second resin side faces 24 are connected to both the resin main surface 21 and the resin back surface 22, respectively, and are sandwiched therebetween in the thickness direction z. The pair of first resin side faces 23 and the pair of second resin side faces 24 each stand upright from the resin back surface 22, and stand upright in the illustrated example. The pair of first resin side faces 23 are spaced apart in the first direction y and disposed substantially parallel to each other. The pair of first resin side faces 23 face opposite sides to each other. The pair of second resin side faces 24 are spaced apart in the second direction x and disposed substantially parallel to each other. The pair of second resin side faces 24 face opposite sides to each other. As shown in FIG. 2 and FIG. 3, the outer edge 20 of the resin member 2 in a plan view overlaps the pair of first resin side faces 23 and the pair of second resin side faces 24.

[0021] The semiconductor element 1 is mounted on the die pad 3. The die pad 3 has a rectangular shape in a plan view. The die pad 3 is located in the center of the semiconductor device A1 in a plan view. The die pad 3 is made of, for example, copper or a copper alloy.

[0022] As shown in Figures 10 to 12, the die pad 3 has a die pad main surface 30a. Also, as shown in Figures 6, 7, and 10 to 12, the die pad 3 includes a first portion 31, a second portion 32, a third portion 33, and a fourth portion .

[0023] As shown in Figs. 10 to 12, the die pad main surface 30a faces one side (upward) in the thickness direction z. That is, the die pad main surface 30a faces the same direction as the element main surface 10a. The semiconductor element 1 is mounted on the die pad main surface 30a, and the die pad main surface 30a faces the element back surface 10b. As can be seen from Figs. 6 and 10 to 12, the die pad main surface 30a spans the first portion 31, the second portion 32, the third portion 33, and the fourth portion 34. The die pad main surface 30a is composed of the upper surface of the first portion 31, the upper surface of the second portion 32, the upper surface of the third portion 33, and the upper surface of the fourth portion 34. The die pad main surface 30a is plated, for example, with a Ni layer and an Ag layer in this order on the base material, but these plating processes may not be performed, or plating processes with other conductive materials may be performed.

[0024] 6 and 7, the outer edge 301 of the die pad main surface 30a in a plan view has a pair of edges 301a and a pair of edges 301b. The pair of edges 301a are spaced apart in a first direction y and are substantially parallel to each other. Each of the pair of edges 301a extends in a second direction x. The pair of edges 301b are spaced apart in the second direction x and are substantially parallel to each other. Each of the pair of edges 301b extends in the first direction y.

[0025] As shown in FIG. 6 and FIG. 10, the die pad main surface 30a includes a pair of openings 302. One of the pair of openings 302 (the opening 302 on one side in the second direction x) is formed so as to overlap with the boundary between the first portion 31 and the third portion 33 in a plan view, for example. The opening 302 may not be located at the boundary between the first portion 31 and the third portion 33, but may be shifted from this boundary to either the first portion 31 side or the third portion 33 side in the second direction x. The other of the pair of openings 302 (the opening 302 on the other side in the second direction x) is formed so as to overlap with the boundary between the first portion 31 and the fourth portion 34 in a plan view, for example. The opening 302 may not be located at the boundary between the first portion 31 and the fourth portion 34, but may be shifted from this boundary to either the first portion 31 side or the fourth portion 34 side in the second direction x. 6 and the like, each opening 302 is formed in a line extending in the first direction y in a plan view. Unlike this example, each opening 302 may be formed in a dot shape and arranged along the first direction y at the boundary between the first portion 31 and the third portion 33 and at the boundary between the first portion 31 and the fourth portion 34.

[0026] The first portion 31 is a portion on which the semiconductor element 1 is mounted. As shown in FIG. 3 and FIG. 6, the first portion 31 overlaps the semiconductor element 1 in a plan view. The first portion 31 is rectangular in a plan view. The first portion 31 is located at the center of the die pad 3 in a plan view. As shown in FIG. 7 and FIG. 10 to FIG. 12, the first portion 31 has a back surface 31a in a plan view. The back surface 31a faces the opposite side to the die pad main surface 30a in the thickness direction z. As shown in FIG. 10 to FIG. 12, the back surface 31a is flush with the resin back surface 22 and is exposed from the resin member 2 (resin back surface 22). The first portion 31 is rectangular in a plan view. The dimension of the first portion 31 in the thickness direction z, that is, the distance from the die pad main surface 30a to the back surface 31a along the thickness direction z, is, for example, 0.15 mm or more and 0.25 mm or less. The back surface 31a corresponds to a "first back surface" in the claims.

[0027] As shown in FIGS. 6 and 7, the outer edge 310 of the first portion 31 in a plan view includes a pair of edges 310a and a pair of edges 310b. The pair of edges 310a are spaced apart in a first direction y and are substantially parallel to each other. The pair of edges 310a each extend in a second direction x. The pair of edges 310a are parallel to the pair of edges 301a (die pad main surface 30a). The pair of edges 310b are spaced apart in the second direction x and are substantially parallel to each other. The pair of edges 310b each extend in the first direction y. The pair of edges 310b are parallel to the pair of edges 301b (die pad main surface 30a).

[0028] As shown in FIG. 6 and FIG. 7, the second part 32 is disposed around the first part 31 in a plan view and is connected to the outer edge 310 of the first part 31. As shown in FIG. 11 and FIG. 12, the second part 32 has a back surface 32a. The back surface 32a faces the opposite side to the die pad main surface 30a. As shown in FIG. 11 and FIG. 12, the back surface 32a is located closer to the die pad main surface 30a than the back surface 31a in the thickness direction z. In addition, the back surface 32a is covered with the resin member 2. Since the back surface 32a of the second part 32 is covered with the resin member 2, the die pad 3 is prevented from coming off from the resin member 2. The second part 32 is a part that is thinned from the other side (lower side) of the die pad 3 in the thickness direction z. This thinning is processed by, for example, etching (half etching), but may also be performed by pressing. The thickness (dimension in the thickness direction z) of the second part 32 is, for example, about half the thickness (dimension in the thickness direction z) of the first part 31. The dimension of the second portion 32 in the thickness direction z, that is, the distance from the die pad main surface 30a to the back surface 32a along the thickness direction z, is, for example, 0.075 mm or more and 0.125 mm or less. The back surface 32a corresponds to a "second back surface" recited in the claims.

[0029] 6 and 7, the third portion 33 and the fourth portion 34 are each disposed around the first portion 31 in a planar view and extend from an outer edge 310 of the first portion 31. As shown in Fig. 6, for example, the third portion 33 and the fourth portion 34 are disposed around the first portion 31 such that a line segment L1 connecting the center of the third portion 33 in a planar view and the center of the fourth portion 34 in a planar view overlaps the semiconductor element 1. The line segment L1 preferably overlaps the center of the semiconductor element 1 in a planar view.

[0030] The third part 33 extends from one of the pair of edges 310b of the first part 31 and extends to one of the pair of edges 301b of the die pad main surface 30a. In the illustrated example, the third part 33 is connected to the center in the first direction y of one of the pair of edges 310b. As shown in FIG. 10, the third part 33 has a back surface 33a. The back surface 33a faces the opposite side to the die pad main surface 30a. As shown in FIG. 10, the back surface 33a is flush with the back surface 31a in the thickness direction z. The back surface 33a is also flush with the resin back surface 22 and is exposed from the resin member 2 (resin back surface 22). The dimension of the third part 33 in the thickness direction z, that is, the distance from the die pad main surface 30a to the back surface 33a along the thickness direction z, is the same as the dimension of the first part 31 in the thickness direction z. The back surface 33a corresponds to the "third back surface" described in the claims.

[0031] The fourth portion 34 extends from the other of the pair of edges 310b of the first portion 31 and extends to the other of the pair of edges 301b of the die pad main surface 30a. In the illustrated example, the fourth portion 34 is connected to the center in the first direction y of the other of the pair of edges 310b. As shown in FIG. 10, the fourth portion 34 has a back surface 34a. The back surface 34a faces the opposite side to the die pad main surface 30a. As shown in FIG. 10, the back surface 34a is flush with the back surface 31a in the thickness direction z. In addition, the back surface 34a is flush with the resin back surface 22 and is exposed from the resin member 2 (resin back surface 22). The dimension of the fourth portion 34 in the thickness direction z, that is, the distance from the die pad main surface 30a along the thickness direction z to the back surface 34a is the same as the dimension of the first portion 31 in the thickness direction z and the dimension of the third portion 33 in the thickness direction z. The back surface 34a corresponds to a "fourth back surface" in the claims.

[0032] As shown in FIG. 6 and FIG. 7, the third portion 33 includes a tapered portion 331 and a strip portion 332, and the fourth portion 34 includes a tapered portion 341 and a strip portion 342. The tapered portions 331 and 341 are connected to the outer edge 310 (a pair of edges 310b) of the first portion 31. The strip portions 332 and 342 extend from the tapered portions 331 and 341 to the outer edge 301 (a pair of edges 301b) of the die pad main surface 30a. The strip portions 332 and 342 are, for example, rectangular in plan view. In an example in which the third portion 33 and the fourth portion 34 extend from the pair of edges 310b in plan view, both ends of each opening 302 in the first direction y overlap the strip portions 332 and 342 when viewed in the second direction x. The length d302 (see FIG. 6) of each opening 302 in plan view is, for example, 0.3 mm or more and 4.0 mm or less. The length d302 is the dimension of each opening 302 in the direction in which the pair of edges 310a extend (first direction y). The length d302 is, for example, equal to or less than the width of each strip-shaped portion 332, 342 (the dimension in the direction in which the pair of edges 310a extend). The tapered portions 331, 341 narrow in width from the pair of edges 310a toward the strip-shaped portions 332, 342 in plan view. The width in the semiconductor device A1 is the dimension along the first direction y. Unlike the examples shown in FIG. 6 and FIG. 7, the third portion 33 may not include the tapered portion 331 and may be composed of the strip-shaped portion 332. In this case, in a plan view, the band-shaped portion 332 extends from the outer edge 310 (one of the pair of edges 310b) of the first portion 31 to the outer edge 301 (one of the pair of edges 301b) of the die pad main surface 30a. Similarly, the fourth portion 34 may be configured by the band-shaped portion 342 without including the tapered portion 341. In this case, in a plan view, the band-shaped portion 342 extends from the outer edge 310 (the other of the pair of edges 310b) of the first portion 31 to the outer edge 301 (the other of the pair of edges 301b) of the die pad main surface 30a.

[0033] The die pad 3 includes a plurality of recesses 35. As shown in FIG. 10, each recess 35 is recessed from the die pad main surface 30a in the thickness direction z. As shown in FIG. 10, each recess 35 includes one of a pair of openings 302 and extends from one of the pair of openings 302 to the other (downward) in the thickness direction z. The plurality of recesses 35 and the pair of openings 302 are each formed, for example, by etching. These may be formed by a press process called stamping, or may be formed by laser processing, instead of etching. For example, when formed by stamping, each recess 35 may be a V-shaped recess instead of a U-shaped recess as shown in FIG. 10.

[0034] The die pad 3 has a pair of clamp marks 39 formed thereon. Each of the pair of clamp marks 39 is recessed from the die pad main surface 30a in the thickness direction z. Each clamp mark 39 is a pressure mark caused by a clamp member described later, and has a scratch-like form that is slightly recessed from the die pad main surface 30a. One pair of clamp marks 39 is formed on each of the third portion 33 and the fourth portion 34. For example, the pair of clamp marks 39 are formed at the center of the third portion 33 in a plan view and at the center of the fourth portion 34 in a plan view. Note that the die pad 3 does not necessarily need to have the clamp marks 39 formed thereon.

[0035] As shown in Figs. 1 and 2, each of the multiple leads 4 overlaps the resin member 2 entirely when viewed in the thickness direction z. As shown in Fig. 2, the multiple leads 4 are arranged along the outer edge 20 of the resin member 2 when viewed in the thickness direction z. As shown in Fig. 1, each of the multiple leads 4 is exposed from the resin back surface 22. Each of the multiple leads 4 is made of, for example, copper or a copper alloy. The die pad 3 and the multiple leads 4 are formed, for example, from one lead frame. In the semiconductor device A1, the multiple leads 4 include a plurality of first lateral leads 41 and a plurality of second lateral leads 42, as shown in Figs. 1 and 2.

[0036] As shown in FIGS. 1 to 3, 6 and 7, the first lateral leads 41 are arranged on either side of the die pad 3 in the first direction y. Some of the first lateral leads 41 are arranged on one side of the first direction y (upper side in FIGS. 2 and 3) with respect to the die pad 3, and others are arranged on the other side of the first direction y (lower side in FIGS. 2 and 3). The first lateral leads 41 are arranged along the second direction x on both sides of the die pad 3 in the first direction y. Each of the first lateral leads 41 is exposed from one of the pair of first resin side surfaces 23. Some of the first lateral leads 41 are exposed from one of the first resin side surfaces 23, and others are exposed from the other first resin side surface 23. A part of each of the first lateral leads 41 is exposed from the resin back surface 22.

[0037] As shown in FIGS. 1 to 3, 6 and 7, the second lateral leads 42 are arranged on either side of the die pad 3 in the second direction x. Some of the second lateral leads 42 are arranged on one side of the second direction x (the right side in FIGS. 2 and 3) with respect to the die pad 3, while others are arranged on the other side of the second direction x (the left side in FIGS. 2 and 3). The second lateral leads 42 are arranged along the first direction y on both sides of the die pad 3 in the second direction x. Each of the second lateral leads 42 is exposed from one of the pair of second resin side surfaces 24. Some of the second lateral leads 42 are exposed from one of the second resin side surfaces 24, and others are exposed from the other second resin side surface 24. A part of each of the second lateral leads 42 is exposed from the resin back surface 22.

[0038] The multiple leads 4 (multiple first lateral leads 41 and multiple second lateral leads 42) include a first lead 5 and a second lead 6. In the semiconductor device A1, as shown in Figures 3 and 6, the multiple first lateral leads 41 include two first leads 5 and multiple second leads 6, and the multiple second lateral leads 42 include multiple second leads 6.

[0039] As shown in Figures 2 to 4 and 11, each first lead 5 is electrically connected to the first main surface electrode 12 of the semiconductor element 1 via a connection member 7 (first connection member 71). As shown in Figure 3, in the semiconductor device A1, each first lead 5 is arranged closer to the power section 101 than the control circuit section 102 in the first direction y. As shown in Figures 4, 11, 13, etc., each first lead 5 has a first pad surface 50a and includes a plurality of first portions 51 and second portions 52.

[0040] In each first lead 5, the first pad surface 50a faces one side (upward) in the thickness direction z, as shown in FIG. 11, and faces the same direction as the element main surface 10a. A connection member 7 (first connection member 71) is bonded to the first pad surface 50a. The first pad surface 50a spans the first portions 51 and the second portions 52. The first pad surface 50a is composed of the upper surfaces of the first portions 51 and the upper surface of the second portion 52. The first pad surface 50a is, for example, Ni-plated on the base material, but may not be plated. The first pad surface 50a has an edge 501 and an edge 502 as shown in FIG. 4.

[0041] As shown in FIG. 4, the edge 501 overlaps the outer edge 20 (first resin side surface 23) of the resin member 2 when viewed in the thickness direction z. The direction in which the edge 501 extends is referred to as the "first width direction." In each first lead 5 included in the multiple first lateral leads 41, the first width direction coincides with the second direction x. Note that when the first lead 5 is included in the multiple second lateral leads 42, the first width direction in the first lead 5 of this second lateral lead 42 coincides with the first direction y.

[0042] 4, the edge 502 extends from the edge 501 toward the die pad 3 while being perpendicular to the edge 501 when viewed in the thickness direction z. The direction in which the edge 502 extends is referred to as the "first length direction." In each of the first leads 5 included in the multiple first side leads 41, the first length direction coincides with the first direction y. Note that, in the case where the first lead 5 is included in the multiple second side leads 42, the first length direction in the first lead 5 of the second side lead 42 coincides with the second direction x.

[0043] 4, in the semiconductor device A1, on the first pad surface 50a of each first lead 5, the edge 501 is longer than the edge 502. The length d11 of the edge 501 is, for example, 0.75 mm or more and 2.0 mm or less, and the length d12 of the edge 502 is, for example, 0.3 mm or more and 1.2 mm or less. The lengths d11 and d12 of the edge 501 and 502 are not limited to these values ​​and can be changed as appropriate depending on the number of connection members 7 (first connection members 71) joined to each first lead 5.

[0044] The first pad surface 50a includes a plurality of openings 503 as shown in Fig. 3, Fig. 4, and Fig. 6. In the example shown in Fig. 4, etc., the plurality of openings 503 are each formed linearly in a plan view. Unlike this configuration, instead of the linear openings 503, a configuration in which a plurality of dot-shaped openings 503 are arranged linearly may be used. The plurality of openings 503 includes a pair of first openings 503a and a plurality of second openings 503b as shown in Fig. 4.

[0045] As shown in FIG. 4, the pair of first openings 503a are located at the outermost positions on one side and the other side of the plurality of openings 503 in the first width direction (second direction x in this embodiment). The pair of first openings 503a are linear and extend in the first length direction (first direction y in this embodiment) in a plan view. The plurality of second openings 503b are located between the pair of first openings 503a in the first width direction (second direction x in this embodiment). The plurality of second openings 503b are linear and extend in the first width direction (second direction x in this embodiment) in a plan view.

[0046] In each first lead 5, the multiple first parts 51 are arranged in the first width direction. As shown in FIG. 7 and FIG. 13, each of the multiple first parts 51 has a back surface 51a. The back surface 51a faces the opposite side to the first pad surface 50a. The back surface 51a is flush with the resin back surface 22 and is exposed from the resin member 2 (resin back surface 22). The dimension in the thickness direction z of each first part 51, that is, the distance from the first pad surface 50a to the back surface 51a along the thickness direction z, is, for example, 0.15 mm or more and 0.25 mm or less. In an example in which the die pad 3 and the multiple leads 4 are formed from one lead frame, it is desirable that the thickness (dimension in the thickness direction z) of each first part 51 is the same as the thickness (thickness direction z) of the first part 31.

[0047] In each first lead 5, the multiple first portions 51 include a pair of outer parts 511 and one or more inner parts 512 (two inner parts 512 in the semiconductor device A1), as shown in FIG. 4. The pair of outer parts 511 are located at both ends in the first width direction (the second direction x in this embodiment). The inner part 512 is sandwiched between the pair of outer parts 511 in the first width direction. The connection member 7 (first connection member 71) is joined to the inner part 512. In a plan view, the area of ​​each inner part 512 is larger than the area of ​​each of the pair of outer parts 511. The width (the dimension along the first width direction, the dimension in the second direction x in this embodiment) of each inner part 512 is, for example, equal to or larger than the wire diameter (diameter) of the first connection member 71 described below and equal to or smaller than 1.0 mm. By making the width of each inner portion 512 equal to or greater than the wire diameter of the first connecting member 71, the joint portion of the first connecting member 71 is prevented from protruding from the inner portion 512 in a plan view, and the first connecting member 71 is prevented from wobbling. On the other hand, by making the width of each inner portion 512 equal to or less than 1.0 mm, the second portion 52 is prevented from being reduced in size, and the first leads 5 are prevented from coming off the resin member 2. Preferably, the width of each inner portion 512 is about twice the wire diameter of the first connecting member 71.

[0048] 4, in the semiconductor device A1, each of the pair of first openings 503a is formed in the first pad surface 50a of each of the pair of outer portions 511. Each first opening 503a is formed on a side of each outer portion 511 closer to the inner portion 512 in the first width direction (second direction x). Each first opening 503a may be formed in a boundary between the outer portion 511 and the second portion 52 (for example, a connection portion 521 described later) in a plan view.

[0049] In each first lead 5, the second portion 52 is connected to each of the first portions 51. As shown in FIG. 13, the second portion 52 is recessed from the back surface side of the first lead 5 and is thinner than the first portion 51. The second portion 52 is a portion thinned from the other side (lower side) of each first lead 5 in the thickness direction z. This thinning is processed by, for example, etching (half etching), but may also be performed by pressing. The second portion 52 has a back surface 52a. The back surface 52a faces the side opposite to the first pad surface 50a. The back surface 52a is a surface approximately parallel to the first pad surface 50a. The back surface 52a is located closer to the first pad surface 50a than the back surface 51a in the thickness direction z. The back surface 52a is covered with the resin member 2. Since the back surface 52a of the second portion 52 is covered with the resin member 2, the removal of each first lead 5 from the resin member 2 is suppressed. The dimension of each second portion 52 in the thickness direction z, i.e., the distance from the first pad surface 50a to the back surface 52a along the thickness direction z, is, for example, 0.075 mm or more and 0.125 mm or less. In an example in which the die pad 3 and the multiple leads 4 are formed from one lead frame, when the thickness of each first portion 51 is the same as the thickness of the first portion 31, it is desirable that the thickness of each second portion 52 (the dimension in the thickness direction z) be approximately half the thickness of each first portion 51.

[0050] In each first lead 5, the second portion 52 includes a plurality of connection portions 521 and a linking portion 522, as shown in FIG. 4. Each of the plurality of connection portions 521 is connected to two of the plurality of first portions 51 that are adjacent to each other in the first width direction (the second direction x in this embodiment), and is sandwiched between them. In the semiconductor device A1, as shown in FIG. 4, the plurality of connection portions 521 are located between one outer portion 511 and the adjacent inner portion 512, between the two inner portions 512, and between the other outer portion 511 and the adjacent inner portion 512. The linking portion 522 is connected to the plurality of connection portions 521. The linking portion 522 is strip-shaped in a plan view and extends in the first width direction. The linking portion 522 is located closer to the die pad 3 than the plurality of connection portions 521 in the first length direction (the first direction y in this embodiment). The second portion 52 may not include the coupling portion 522 and may be configured by a plurality of connecting portions 521.

[0051] 4, in the semiconductor device A1, each of the above-mentioned multiple second openings 503b is formed in the first pad surface 50a in the second portion 52. In the example shown in Fig. 4, each second opening 503b is formed so as to overlap, for example, with a boundary between each connection portion 521 and the coupling portion 522 in a plan view. Unlike this example, each second opening 503b may be shifted in any direction in the first length direction (first direction y) from the boundary between each connection portion 521 and the coupling portion 522 in a plan view.

[0052] Each first lead 5 includes a plurality of recesses 55. As shown in FIG. 13 and FIG. 14, each of the plurality of recesses 55 is recessed from the first pad surface 50a in the thickness direction z. As shown in FIG. 13 and FIG. 14, each of the plurality of recesses 55 includes any one of a plurality of openings 503 (a plurality of first openings 503a and a plurality of second openings 503b), and extends from each opening 503 in the thickness direction z. Each of the plurality of recesses 55 and the plurality of openings 503 is formed, for example, by etching. These may be formed by a press process called stamping, or may be formed by laser processing, instead of etching. For example, when formed by stamping, each recess 55 may be a V-shaped recess instead of a U-shaped recess as shown in FIG. 13 and FIG. 14.

[0053] 4, in the semiconductor device A1, each first lead 5 has a notch 505 formed therein. In a plan view, the notch 505 is formed along the adjacent third lead 43 and is approximately parallel to the adjacent third lead 43.

[0054] Each first lead 5 has a pair of clamp marks 59 formed thereon. Each of the pair of clamp marks 59 is recessed from the first pad surface 50a in the thickness direction z. The clamp marks 59 are pressure marks caused by a clamp member described later, and have a scratch-like shape that is slightly recessed from the first pad surface 50a. The pair of clamp marks 59 are formed on each of the pair of outer parts 511. Preferably, as shown in FIG. 4, in each first lead 5, the joint portion of each first connection member 71 overlaps with a line segment L2 connecting the pair of clamp marks 59 in a plan view. Note that the clamp marks 59 may not be formed on each first lead 5.

[0055] The second leads 6 are electrically connected to the second main surface electrodes 13 of the semiconductor element 1 via the connection members 7 (second connection members 72). As shown in Figures 5, 11, 15, etc., each second lead 6 has a second pad surface 60a and includes a first portion 61 and a second portion 62.

[0056] In each second lead 6, the second pad surface 60a faces the same direction as the first pad surface 50a. Therefore, the second pad surface 60a faces one side (upward) in the thickness direction z. A connection member 7 (second connection member 72) is bonded to the second pad surface 60a. The second pad surface 60a is plated, for example, with a Ni layer and an Ag layer in that order on the base material, but these plating processes may not be performed, or plating with other conductive materials may be performed. The second pad surface 60a has an edge 601 and an edge 602 as shown in FIG. 5.

[0057] The edge 601 overlaps with the outer edge 20 of the resin member 2 when viewed in the thickness direction z. The direction in which the edge 601 extends is referred to as the "second width direction". In each of the second leads 6 in the multiple first side leads 41, the second width direction coincides with the second direction x, and in each of the second leads 6 in the multiple second side leads 42, the second width direction coincides with the first direction y.

[0058] The edge 602 extends from the edge 601 toward the die pad 3 while being perpendicular to the edge 601 when viewed in the thickness direction z. The direction in which the edge 602 extends is referred to as the "second length direction." In each of the second leads 6 in the multiple first side leads 41, the second length direction coincides with the first direction y, and in each of the second leads 6 in the multiple second side leads 42, the second length direction coincides with the second direction x. As shown in FIG. 5, the edge 601 is shorter than the edge 602. The length d21 of the edge 601 is, for example, 0.15 mm or more and 0.3 mm or less, and the length d22 of the edge 602 is, for example, 0.5 mm or more and 1.0 mm or less.

[0059] In each second lead 6, the first portion 61 is joined to the connection member 7 (second connection member 72) as shown in FIG. 5 and FIG. 11. As shown in FIG. 11, the first portion 61 has a back surface 61a. The back surface 61a faces the opposite side to the second pad surface 60a. The back surface 61a is flush with the resin back surface 22 and is exposed from the resin member 2 (resin back surface 22). The area of ​​the back surface 61a is smaller than the area of ​​the back surface 51a of each inner portion 512 of the first lead 5. The dimension of the first portion 61 in the thickness direction z, that is, the distance from the second pad surface 60a to the back surface 61a along the thickness direction z, is, for example, 0.15 mm or more and 0.25 mm or less. In an example in which the die pad 3 and the multiple leads 4 are formed from one lead frame, it is desirable that the thickness of each first portion 61 (the dimension in the thickness direction z) is the same as the thickness of the first portion 31.

[0060] In each second lead 6, the second portion 62 is connected to the first portion 61 as shown in FIG. 5 and FIG. 11. As shown in FIG. 11, the second portion 62 is recessed from the back surface side of the second lead 6 and is thinner than the first portion 61. The second portion 62 is a portion that is thinned from the other side (lower side) of each second lead 6 in the thickness direction z. This thinning is processed by, for example, etching (half etching), but may also be performed by pressing. As shown in FIG. 11, the second portion 62 has a back surface 62a. The back surface 62a faces the side opposite to the second pad surface 60a. The back surface 62a is a surface that is approximately parallel to the second pad surface 60a. The back surface 62a is located closer to the second pad surface 60a than the back surface 61a in the thickness direction z. The back surface 62a is covered with the resin member 2. Since the back surface 62a of the second portion 62 is covered with the resin member 2, the second leads 6 are prevented from coming off the resin member 2. The dimension of the second portion 62 in the thickness direction z, i.e., the distance from the second pad surface 60a to the back surface 62a along the thickness direction z, is, for example, 0.075 mm or more and 0.125 mm or less. In an example in which the die pad 3 and the multiple leads 4 are formed from one lead frame, when the thickness of the first portion 61 is the same as the thickness of the first portion 31, it is desirable that the thickness of the second portion 62 (the dimension in the thickness direction z) be approximately half the thickness of the first portion 61.

[0061] 3 and 6, the area of ​​the first pad surface 50a is larger than the area of ​​the second pad surface 60a. In this embodiment, the length d12 of the edge 502 is approximately the same as the length d22 of the edge 602, and the length d11 of the edge 501 is larger than the length d21 of the edge 601. For example, the length d11 of the edge 501 is 3 times or more and 20 times or less than the length d21 of the edge 601.

[0062] As shown in FIGS. 2, 3, 6, and 7, the third leads 43 extend from the outer edge of the die pad 3 (the outer edge 301 of the die pad main surface 30a) toward the outer edge 20 of the resin member 2 in a plan view. In the semiconductor device A1, the third leads 43 extend from the four corners of the die pad 3 and toward the four corners of the resin member 2 in a plan view. The third leads 43 are each integrally formed with the die pad 3. The third leads 43 each have a smaller dimension in the thickness direction z than the die pad 3. Both sides of the third leads 43 in the thickness direction z are covered by the resin member 2. The third leads 43 are so-called hanging leads. As shown in FIGS. 12 and 15, both sides of the third leads 43 in the thickness direction z are covered by the resin member 2. An upper surface (a surface facing one side in the thickness direction z) of each third lead 43 is flush with the die pad main surface 30a, and a lower surface (a surface facing the other side in the thickness direction z) of each third lead 43 is flush with the rear surface 32a of the second portion 32. In a plan view, an end surface of each third lead 43 overlapping an outer edge 20 (a pair of first resin side surfaces 23 and a pair of second resin side surfaces 24) of the resin member 2 is exposed from the resin member 2. Each of the multiple third leads 43 is made of, for example, copper or a copper alloy.

[0063] The multiple connection members 7 provide electrical continuity between two separated portions. Each of the multiple connection members 7 electrically connects one of the multiple main surface electrodes 11 to one of the multiple leads 4. The multiple connection members 7 include a multiple number of first connection members 71 and a multiple number of second connection members 72.

[0064] Each of the multiple first connection members 71 is, for example, a bonding wire, and contains aluminum or an aluminum alloy as a constituent material. Each of the multiple first connection members 71 is bonded to one of the multiple first principal surface electrodes 12 and one of the multiple first leads 5, and conducts them. Each of the first connection members 71 is bonded by, for example, wedge bonding. Note that the material and bonding method of each of the first connection members 71 are not limited to the above-mentioned example. For example, the constituent material of each of the first parts 61 may contain gold or a gold alloy, or copper or a copper alloy, instead of aluminum or an aluminum alloy. Also, each of the first connection members 71 may be bonded by ball bonding. Furthermore, each of the multiple first connection members 71 may be, for example, a bonding ribbon instead of a bonding wire.

[0065] Each of the second connection members 72 is, for example, a bonding wire, and includes gold or a gold alloy, or copper or a copper alloy as a constituent material. Each of the second connection members 72 is bonded to one of the second principal surface electrodes 13 and one of the second leads 6, and electrically connects them. Each of the second connection members 72 is bonded by, for example, ball bonding. Note that the material and bonding method of each of the second connection members 72 are not limited to the above-mentioned examples.

[0066] In the example shown in FIGS. 2, 3 and 11, each of the plurality of first connection members 71 has a wire diameter larger than each of the plurality of second connection members 72, for example, but is not limited to this.

[0067] In the semiconductor device A1, as described above, each of the first connection members 71 is bonded by wedge bonding. In the wedge bonding, the first connection member 71 is pressed against the object to be bonded (the first main surface electrode 12 and the first lead 5) while ultrasonic vibration is applied, thereby bonding the first connection member 71 and the object to be bonded. In order to suppress the oscillation of the object to be bonded due to the pressing force and ultrasonic vibration at this time, the object to be bonded is fixed by a clamp member. The clamp member has a tip portion formed in a thin rod shape, and the object to be bonded is fixed by pressing the tip portion. In this embodiment, since each of the first connection members 71 is bonded to the first main surface electrode 12 and the first lead 5, the die pad 3 and the first lead 5 are fixed by the clamp member. At this time, by pressing the die pad 3 with (the tip portion of) the clamp member, a pair of clamp marks 39 is formed by the pressing force of the clamp member. Furthermore, by holding the first lead 5 with (the tip portion of) the clamp member, a pair of clamp marks 59 are formed by the pressing force of the clamp member. Note that, even when joining the second connecting member 72, ultrasonic vibration may be applied while pressing the second connecting member 72 against the joined object (the main surface electrode 11 and the second lead 6). However, the pressing force and ultrasonic vibration at that time are weaker than the pressing force and ultrasonic vibration required for joining the first connecting member 71, and therefore it is not necessary to use the clamp member when joining the second connecting member 72. Note that the joining of each second connecting member 72 is performed after the joining of each first connecting member 71.

[0068] The functions and effects of the semiconductor device A1 are as follows.

[0069] In the semiconductor device A1, the die pad 3 has a die pad main surface 30a and includes a first portion 31, a second portion 32, a third portion 33, and a fourth portion 34. The die pad main surface 30a spans the first portion 31, the second portion 32, the third portion 33, and the fourth portion 34. The back surface 31a of the first portion 31, the back surface 33a of the third portion 33, and the back surface 34a of the fourth portion 34 are flush with each other, and the back surface 32a of the second portion 32 is located closer to the die pad main surface 30a in the thickness direction z than the back surface 31a. In this configuration, the second portion 32 is thinner than the first portion 31, and the third portion 33 and the fourth portion 34 have the same thickness as the first portion 31. When the first connection member 71 is joined, the die pad 3 (and the semiconductor element 1 mounted thereon) may be fixed, for example, by a clamp member. At this time, the clamp member presses the periphery of the first part 31 on which the semiconductor element 1 is mounted. Unlike the semiconductor device A1, in a semiconductor device in which the die pad 3 does not have the third part 33 and the fourth part 34, the second part 32 is disposed around the entire periphery of the first part 31. In this case, the die pad 3 is fixed by pressing the second part 32 with the clamp member. However, since the second part 32 is thinner than the first part 31, there is a risk that the die pad 3 may be deformed and cracked due to the pressing force of the clamp member. If the die pad 3 is deformed by the pressing force of the clamp member, the semiconductor element 1 mounted on the die pad 3 may peel off. Therefore, in the semiconductor device A1, the third part 33 and the fourth part 34 having the same thickness as the first part 31 are provided around the first part 31, so that the third part 33 and the fourth part 34 can be pressed with the clamp member. Therefore, the semiconductor device A1 is a package structure preferable for improving quality because it can suppress deformation and cracking of the die pad 3.

[0070] In the semiconductor device A1, when the first connection member 71 is joined to the first principal surface electrode 12, the third portion 33 and the fourth portion 34 are fixed with a clamp member, thereby fixing the semiconductor element 1. Therefore, in the semiconductor device A1, the third portion 33 and the fourth portion 34 are arranged on either side of the first portion 31 in the second direction x. At this time, in a plan view, a line segment L1 connecting the center of the third portion 33 and the center of the fourth portion 34 overlaps with the semiconductor element 1. With this configuration, when the die pad 3 is fixed with a clamp member, the semiconductor element 1 can be fixed in a stable position. In other words, the semiconductor device A1 has a preferable package structure for appropriately fixing the semiconductor element 1.

[0071] In the semiconductor device A1, a pair of openings 302 is formed in the die pad main surface 30a of the die pad 3. The pair of openings 302 is formed, for example, at the boundary between the first portion 31 and the third portion 33 and at the boundary between the first portion 31 and the fourth portion 34. With this configuration, it is possible to determine the positions of the third portion 33 and the fourth portion 34, that is, the clampable region, with reference to the pair of openings 302. For example, in the example shown in FIG. 6, it is possible to determine that the portion outside the pair of openings 302 is the position of the third portion 33 and the fourth portion 34, that is, the clampable region, with reference to the pair of openings 302.

[0072] In the semiconductor device A1, the third portion 33 includes a tapered portion 331, and an opening 302 is formed at the boundary between the third portion 33 and the first portion 31. In the die pad 3, the opening 302 is a portion recessed from the die pad main surface 30a in the thickness direction z, and the second portion 32 is a portion recessed from below in the thickness direction z. Therefore, in a plan view, if the distance between the opening 302 and the second portion 32 adjacent to the opening 302 is not appropriately secured, the rigidity of the die pad 3 may decrease. Therefore, in the semiconductor device A1, by including the tapered portion 331 in the third portion 33, it is possible to appropriately secure the distance between the opening 302 and the second portion 32 adjacent to the opening 302, and the rigidity of the die pad 3 can be suppressed from decreasing. This is also true in a configuration in which the fourth portion 34 includes a tapered portion 341. In other words, the semiconductor device A1 has a package structure that is favorable for preventing a decrease in the rigidity of the die pad 3 when the pair of openings 302 are formed.

[0073] In the semiconductor device A1, the multiple leads 4 include a first lead 5 and a second lead 6. The first lead 5 has a first pad surface 50a to which the first connection member 71 is bonded, and the second lead 6 has a second pad surface 60a to which the second connection member 72 is bonded. In addition, the first pad surface 50a is larger than the second pad surface 60a when viewed in the thickness direction z. With this configuration, it is possible to bond more first connection members 71 to the first lead 5 or to bond a connection member 7 having a large wire diameter. Therefore, it is possible to pass a larger current through the semiconductor element 1. In addition, since the first lead 5 is larger than the second lead 6, the conductivity is good. Therefore, the semiconductor device A1 has a package structure preferable for achieving high performance.

[0074] In the semiconductor device A1, the semiconductor element 1 includes a power section 101 and a control circuit section 102. The power section 101 often operates with a relatively larger current than the control circuit section 102. Therefore, in the semiconductor device A1, providing the first lead 5 on the multiple leads 4 is a preferable package structure for mounting such a semiconductor element 1.

[0075] In the semiconductor device A1, the first lead 5 is disposed at a position closer to the power section 101 than the control circuit section 102. With this configuration, the distance between the first main surface electrode 12 of the semiconductor element 1 and the first lead 5 can be shortened, which is preferable for joining the first connection member 71.

[0076] In the semiconductor device A1, the first lateral leads 41 include a first lead 5, and the second lateral leads 42 do not include a first lead 5. Each first connection member 71 is joined to each first lead 5 and the semiconductor element 1 (each first principal surface electrode 12) by wedge bonding. When the first connection member 71 is wedge bonded to the first leads 5 of the first lateral leads 41 and the semiconductor element 1 (first principal surface electrode 12), for example, both ends of the die pad 3 in the second direction x are held down by a clamp member. At this time, for example, the clamp member holds down an end of the die pad 3 on one side in the second direction x from one side of the end in the second direction x, and holds down an end of the die pad 3 on the other side in the second direction x from the other side of the end in the second direction x. In the semiconductor device A1, the end of the die pad 3 on one side in the second direction x is the third part 33, and the end of the die pad 3 on the other side in the second direction x is the fourth part 34. In such a holding manner, due to the arrangement of the clamp member, it becomes difficult to connect the semiconductor element 1 and the second lateral leads 42 with the first connection member 71. Therefore, in the semiconductor device A1, the second lateral leads 42 are configured not to include the first lead 5, so that it is not necessary to join each of the first connection members 71 to the second lateral leads 42, and it is possible to suppress the above-mentioned problem of difficulty in joining the first connection member 71 to the second lateral leads 42. In other words, in order to suppress such a problem, the third part 33 and the fourth part 34 are arranged on the side where the second lateral leads 42 not including the first lead 5 are arranged with respect to the first part 31.

[0077] In the semiconductor device A1, the first leads 5 have a plurality of first exposed surfaces each facing the opposite side to the first pad surface 50a in the thickness direction z and each exposed from the resin back surface 22. In the semiconductor device A1, the first exposed surfaces are the back surfaces 51a of the inner parts 512. The second leads 6 have second exposed surfaces facing the opposite side to the second pad surface 60a in the thickness direction z and exposed from the resin back surface 22. In the semiconductor device A1, the second exposed surface is the back surface 61a of the first part 61. In addition, the back surfaces 51a (each first exposed surface) of the inner parts 512 are larger than the back surface 61a (second exposed surface) in the thickness direction z. With this configuration, when the semiconductor device A1 is mounted on a circuit board of an electronic device or the like, the bonding area between the back surface 51a of each inner part 512 of the first part 51 and the circuit board is larger than the bonding area between the back surface 61a of the second lead 6 and the circuit board. Therefore, the semiconductor device A1 can provide better conductivity from the first lead 5 to the circuit board than conductivity from the second lead 6 to the circuit board. Also, in the semiconductor device A1, as described above, the first pad surface 50a of the first lead 5 is larger than the second pad surface 60a of the second lead 6, so that it is easy to make the back surface 51a of each inner portion 512 larger than each back surface 61a.

[0078] In the semiconductor device A1, the first lead 5 has a first pad surface 50a and includes a first portion 51 and a second portion 52. The first pad surface 50a spans the first portion 51 and the second portion 52. The back surface 52a of the second portion 52 is located closer to the first pad surface 50a than the back surface 51a of the first portion 51 in the thickness direction z. In this configuration, the second portion 52 is thinner than the first portion 51. Therefore, when the first connection member 71 is joined to the second portion 52, there is a risk that the first lead 5 will be deformed and cracked. This is because, when the first connection member 71 is joined, the first connection member 71 is pressed against the first lead 5, and this pressing force is applied to the first lead 5, causing stress in the first lead 5. In addition, when the first connection member 71 is joined, the first lead 5 may be pressed down by a clamp member to fix the first lead 5. At this time, if the second portion 52 is pressed by the clamp member, the first lead 5 may be deformed and cracked due to the pressing force of the clamp member. If the first lead 5 is deformed by the pressing force of the clamp member, there is a possibility that the bonding strength of the first connection member 71 may not be adequately secured. Therefore, in the semiconductor device A1, by forming a plurality of openings 503 on the first pad surface 50a, it becomes possible to determine the position of the first portion 51 by referring to the plurality of openings 503. In other words, the semiconductor device A1 can determine a position suitable for bonding the first connection member 71 and a position suitable for clamping with the clamp member. Therefore, the semiconductor device A1 has a package structure preferable for achieving high quality because it can suppress deformation and cracking of the first lead 5.

[0079] In the semiconductor device A1, the multiple openings 503 include multiple first openings 503a and multiple second openings 503b. With this configuration, the multiple first openings 503a can be used to determine the area to be held by the clamp member (the position of the pair of outer parts 511), and the multiple second openings 503b can be used to determine the area to be joined to the first connecting member 71 (the position of the inner part 512). For example, in the example shown in FIG. 4 and the like, it can be determined that the portions on both outer sides of the pair of first openings 503a are the positions of the pair of outer parts 511, that is, the areas that can be clamped, with reference to the multiple second openings 503b. Also, for example, in the example shown in FIG. 4 and the like, it can be determined that the portion outside the second openings 503b is the position of the connection part 521 (second part 52), that is, the area where joining of the first connecting member 71 is inappropriate.

[0080] Next, another embodiment of the semiconductor device according to the present disclosure will be described.

[0081] 16 shows a semiconductor device A2 according to the second embodiment. As shown in the figure, in the semiconductor device A2, the third portion 33 and the fourth portion 34 are each rectangular in a plan view. That is, in the semiconductor device A2, compared to the semiconductor device A1, the third portion 33 does not include a tapered portion 331, and the fourth portion 34 does not include a tapered portion 341.

[0082] The semiconductor device A2 also has the same effect as the semiconductor device A1. However, in the semiconductor device A2, the third portion 33 and the fourth portion 34 do not include the tapered portions 331, 341, so the distance between each opening 302 and the second portion 32 adjacent to each opening 302 may be short. Therefore, in order to suppress a decrease in the rigidity of the die pad 3, it is preferable to increase the widths of the third portion 33 and the fourth portion 34 (the dimensions in the second direction x in FIG. 16) or reduce the lengths of each opening 302 (the dimensions in the second direction x in FIG. 16).

[0083] FIG. 17 shows a semiconductor device A3 according to the third embodiment. As shown in the figure, the semiconductor device A3 includes a die pad 3 including two third parts 33 and two fourth parts 34. The two third parts 33 are arranged along the first direction y on one side of the die pad 3 in the second direction x. In the example shown in FIG. 17, the two third parts 33 are connected to both ends of one of the pair of edges 310b in the first direction y. Similarly, the two fourth parts 34 are arranged along the first direction y on the other side of the second direction x of the die pad 3. In the example shown in FIG. 17, the two fourth parts 34 are connected to both ends of the other of the pair of edges 310b in the first direction y.

[0084] In the semiconductor device A3, when the die pad 3 is fixed by a clamp member, a total of four locations, that is, two third portions 33 and two fourth portions 34, can be held by the clamp member.

[0085] 17, in the semiconductor device A3, in a plan view, two line segments L1 connecting the third portion 33 and the fourth portion 34 arranged at each diagonal corner of the first portion 31 overlap the semiconductor element 1. In particular, in a plan view, the intersection of the two line segments L1 overlaps the center of the semiconductor element 1.

[0086] The semiconductor device A3 also achieves the same effects as the semiconductor device A1. In the semiconductor device A3, when the die pad 3 is fixed with a clamp member, the clamp member holds it at four points. Therefore, the semiconductor device A3 has a package structure that is more suitable for more stably fixing the die pad 3 (and the semiconductor element 1 mounted thereon) than the semiconductor device A1. In particular, the intersection of the two line segments L1 overlaps with the center of the semiconductor element 1 in a plan view, making it suitable for fixing the semiconductor element 1.

[0087] In the third embodiment, an example of the semiconductor device A3 is shown in which the die pad 3 has two third portions 33 and two fourth portions 34, but the number of third portions 33 and the number of fourth portions 34 may be three or more.

[0088] Fig. 18 shows a semiconductor device A4 according to a fourth embodiment. As shown in the figure, in the semiconductor device A4, the third portion 33 and the fourth portion 34 are arranged to be shifted from each other in the first direction y. In the example shown in Fig. 18, the third portion 33 is shifted toward the other side in the first direction y (the lower side in Fig. 18) from the center in the first direction y of one of the pair of edges 310b. On the other hand, the fourth portion 34 is shifted toward the one side in the first direction y (the upper side in Fig. 18) from the center in the first direction y of the other of the pair of edges 310b.

[0089] The semiconductor device A4 can also achieve the same effect. As can be understood from the semiconductor device A4, in the semiconductor device of the present disclosure, the positional relationship between the third portion 33 and the fourth portion 34 is not limited to overlapping with each other as viewed in the second direction x.

[0090] FIG. 19 shows a semiconductor device A5 according to the fifth embodiment. As shown in the figure, in the semiconductor device A5, the third portion 33 and the fourth portion 34 are arranged on either one side or the other side of the first direction y. The first connection member 71 is joined to the first principal surface electrode 12, and ultrasonic vibrations when wedge bonding the first connection member 71 are transmitted from the first principal surface electrode 12. Therefore, in the semiconductor device A5, the third portion 33 and the fourth portion 34 are arranged based on each of the first principal surface electrodes 12. In the example shown in FIG. 19, the third portion 33 and the fourth portion 34 are arranged so that the line segment L1 connecting them overlaps each of the first principal surface electrodes 12 in a plan view.

[0091] The semiconductor device A5 can also achieve the same effect. As can be understood from the semiconductor device A5, the semiconductor device of the present disclosure is not limited to the semiconductor device in which the third portion 33 and the fourth portion 34 are each connected to the center of each edge 310a in the first direction y.

[0092] In the example shown in Figs. 17 to 19, each of the third portions 33 does not include a tapered portion 331, similar to the semiconductor device A2. Unlike this configuration, in each of the semiconductor devices A3 to A5, each of the third portions 33 may include a tapered portion 331, similar to the semiconductor device A1. In the example shown in Figs. 17 to 19, each of the fourth portions 34 does not include a tapered portion 341, similar to the semiconductor device A2. Unlike this configuration, in each of the semiconductor devices A3 to A5, each of the fourth portions 34 may include a tapered portion 341, similar to the semiconductor device A1.

[0093] FIG. 20 shows a semiconductor device A6 according to the sixth embodiment. As shown in the figure, in the semiconductor device A6, the third part 33 is connected over the entire length of one of the pair of edges 310b. Similarly, in the semiconductor device A6, the fourth part 34 is connected over the entire length of the other of the pair of edges 310b. The third part 33 and the fourth part 34 each coincide with the first part 31 when viewed in the second direction x. In this configuration, the second part 32 is disposed on one side and the other side of the first direction y, sandwiching the first part 31, in a plan view. The die pad 3 of the semiconductor device A6 is formed, for example, by not performing half etching on the opposite sides of the die pad 3 in the second direction x in a plan view.

[0094] The semiconductor device A6 also has the same effect as the semiconductor device A1. In the semiconductor device A6, the planar area of ​​each of the third portion 33 and the fourth portion 34 is larger than that of the semiconductor device A1. In other words, the semiconductor device A6 has an area suitable for holding the die pad 3 with the clamp member enlarged compared to the semiconductor device A1. As a result, in the semiconductor device A6, it is possible to more stably fix the die pad 3 and the semiconductor element 1 by providing more points to be held by the clamp member and by making the tip portion of the clamp member larger. Note that FIG. 20 shows a case where a pair of openings 302 and a pair of clamp marks 39 are formed in the same manner as the semiconductor device A1, but this can be appropriately changed by increasing the number of points to be held by the clamp member and changing the tip portion of the clamp member.

[0095] In the first to sixth embodiments, an example was shown in which each opening 302 is linear in plan view extending in the first direction y. Unlike this configuration, each opening 302 may be dot-shaped in plan view. In this case, it is preferable to arrange a plurality of openings 302 along the first direction y at each of the boundaries between the first portion 31 and the third portion 33 and between the first portion 31 and the fourth portion 34. For example, FIG. 21 shows an example in which a plurality of dot-shaped openings 302 are formed at each of the aforementioned boundaries in the semiconductor device A1. In the example shown in FIG. 21, three openings 302 are formed at each of the aforementioned boundaries, and the three openings 302 are arranged along the first direction y. The number of openings 302 formed at each boundary is not limited to three as shown in FIG. 21. In an example in which the third portion 33 and the fourth portion 34 extend from a pair of edges 310b in a plan view, at each boundary described above, a pair of openings 302 located at both ends in the first direction y among the multiple openings 302 overlap with the third portion 33 (strip portion 332) and the fourth portion 34 (strip portion 342) when viewed in the second direction x. Even in the example shown in FIG. 21 , the positions of the third portion 33 and the fourth portion 34 can be determined based on the multiple openings 302.

[0096] In the first to sixth embodiments, examples have been shown in which a plurality of recesses 35 are formed in the die pad 3, but through holes may be formed instead of the recesses 35. The through holes are configured to include openings 302 formed in the die pad main surface 30a, and penetrate the die pad 3 in the thickness direction z. For example, Fig. 22 shows an example in which a through hole 36 including an opening 302 is formed in the die pad 3. Fig. 22 is a cross-sectional view, and corresponds to the cross section of Fig. 10.

[0097] In the first to sixth embodiments, the number, arrangement, and size of the first leads 5 and the second leads 6 in the multiple leads 4 may be appropriately changed according to the configuration of the semiconductor element 1. The configuration of the semiconductor element 1 refers to the number and arrangement of the power sections 101, the number and arrangement of the control circuit sections 102, and the number and arrangement of the multiple principal surface electrodes 11 (the first principal surface electrodes 12 and the second principal surface electrodes 13). For example, as shown in FIG. 23, the multiple first lateral leads 41 may include the multiple first leads 5 without including the second leads 6. In the example shown in FIG. 23, for example, when the first principal surface electrodes 12 are respectively arranged on both sides of the semiconductor element 1 in the first direction y, the distance from each first principal surface electrode 12 to each first lead 5 can be shortened. Alternatively, as shown in FIG. 24, the multiple first lateral leads 41 may include the first leads 5 and the second leads 6, and the multiple second lateral leads 42 may include the first leads 5 and the second leads 6. 24, for example, when a plurality of first principal surface electrodes 12 are arranged collectively on the other side (lower side in the figure) of the semiconductor element 1 in the first direction y in a plan view, the distance from each first principal surface electrode 12 to each first lead 5 can be shortened. Furthermore, in the semiconductor device A1 (see FIG. 3, etc.) and the examples shown in FIGS. 23 and 24, two first leads 5 are arranged along one of the pair of first resin side surfaces 23, but the number of first leads 5 arranged along either one of the pair of first resin side surfaces 23 or the pair of second resin side surfaces 24 is not limited to two and may be one, or three or more.

[0098] In the first to sixth embodiments, each of the semiconductor devices A1 to A6 includes one semiconductor element 1. However, unlike this configuration, each of the semiconductor devices A1 to A6 may include a plurality of semiconductor elements 1. For example, FIG. 25 shows an example in which two semiconductor elements 1 are included. In the example shown in FIG. 25, the two semiconductor elements 1 include a semiconductor element 1A including a power section 101 and a semiconductor element 1B including a control circuit section 102. The semiconductor element 1A is, for example, a power element such as a transistor. The semiconductor element 1B is a driver IC that controls the switching operation of the semiconductor element 1A. The semiconductor device shown in FIG. 25 includes a third connection member 73 that connects the semiconductor element 1A and the semiconductor element 1B. The third connection member 73 is, for example, a bonding wire. A detection signal from the semiconductor element 1A to the semiconductor element 1B and a drive signal for controlling the switching operation from the semiconductor element 1B to the semiconductor element 1A are transmitted via the third connection member 73. Although FIG. 25 shows an example in which two semiconductor elements 1 are provided, the number of semiconductor elements 1 may be three or more.

[0099] In the first to sixth embodiments, the semiconductor devices A1 to A6 have a MAP type QFN package structure, but may have other package structures (for example, MAP type SON). FIG. 26 shows an example of a MAP type SON package structure. The semiconductor device shown in FIG. 26 is a SON package, and therefore the multiple leads 4 do not include the second lateral leads 42. As can be seen from the example shown in FIG. 26, the semiconductor device of the present disclosure is not limited to QFN, and can be applied to other package structures. In the example shown in FIG. 26, similar to the semiconductor devices A1 to A6, the multiple third leads 43 are formed to extend from the four corners of the die pad 3 to the four corners of the resin member 2 in a plan view. Unlike this example, each of the third leads 43 may extend from the four corners of the die pad 3 in parallel to the second direction x. Alternatively, unlike this example, the two third leads 43 may extend from the third part 33 and the fourth part 34 of the die pad 3 along the second direction x, respectively.

[0100] In the first to sixth embodiments, each of the semiconductor devices A1 to A6 includes a plurality of third leads 43, but unlike this configuration, each of the semiconductor devices A1 to A6 may not include the third lead 43. Such a configuration not including the third lead 43 can also be applied to the other modified examples (FIGS. 21 to 26) described above.

[0101] In the first to sixth embodiments, an example has been shown in which the first lead 5 has the notch 505 formed therein, but unlike this configuration, the first lead 5 may not have the notch 505. In a configuration without the notch 505, the first lead 5 has, for example, a rectangular shape in a plan view.

[0102] In the first to sixth embodiments, examples in which a plurality of recesses 55 are formed in the first lead 5 are shown, but through holes may be formed instead of the recesses 55. The through holes are configured to include the openings 503 (the first opening 503a or the second opening 503b) formed in the first pad surface 50a, and penetrate the first lead 5 in the thickness direction z. For example, FIG. 27 shows an example in which a through hole 56 including the second opening 503b is formed in the first lead 5. FIG. 27 is an enlarged cross-sectional view of a main part, and corresponds to the cross section of FIG. 14. The second part 52 is formed by half-etching from the lower surface in the thickness direction z in the first lead 5. Therefore, when the second openings 503b are formed in the second part 52 by half-etching from the first pad surface 50a, the through hole 56 penetrating the second part 52 is easily formed as shown in FIG. 27.

[0103] In the first to sixth embodiments, an example has been shown in which a plurality of second openings 503b are arranged in each first lead 5 so as to indicate an area in which joining to the first connection member 71 is inappropriate. However, contrary to this example, a plurality of second openings 503b may be arranged so as to indicate an area in which joining to the first connection member 71 is appropriate. For example, a plurality of second openings 503b may be arranged at the boundary between the inner portion 512 and the coupling portion 522, or a plurality of second openings 503b may be arranged at the boundary between the inner portion 512 and the coupling portion 522.

[0104] In the first to sixth embodiments, a pair of openings 302 are formed in the die pad main surface 30a of the die pad 3, but unlike this configuration, the openings 302 may not be formed. Similarly, a plurality of openings 503 are formed in the first pad surface 50a of the first lead 5, but unlike this configuration, the openings 503 may not be formed.

[0105] In the first to sixth embodiments, the first lateral leads 41 include the first lead 5, but unlike this configuration, the first lateral leads 41 may not include the first lead 5. That is, the multiple leads 4 (the multiple first lateral leads 41 and the multiple second lateral leads 42) may all be composed of the second lead 6. In such an example in which the multiple leads 4 are all composed of the second lead 6, wedge bonding may not be performed. However, the die pad 3 may be fixed with a clamp member when stabilizing the posture of the die pad 3 during manufacturing and when mounting the semiconductor element 1 on the die pad 3. Therefore, even if the configuration does not require wedge bonding, the third part 33 and the fourth part 34 may be provided on the die pad 3.

[0106] The semiconductor device according to the present disclosure is not limited to the above-mentioned embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. For example, the semiconductor device according to the present disclosure includes the following embodiments. [Appendix 1] a semiconductor element having a main surface and a back surface spaced apart in a thickness direction, the main surface having a plurality of main surface electrodes disposed thereon; a die pad having a die pad main surface on which the semiconductor element is mounted; a first lead disposed on one side of the die pad in a first direction perpendicular to the thickness direction, the first lead being disposed around the die pad as viewed in the thickness direction; a plurality of connection members including a first connection member joined to the first lead, electrically connecting the plurality of principal surface electrodes and the plurality of leads; a resin member that seals the semiconductor element, a portion of the die pad, each of the plurality of leads, and the plurality of connection members; Equipped with each of the plurality of leads entirely overlaps the resin member as viewed in the thickness direction and is disposed along an outer edge of the resin member as viewed in the thickness direction; the die pad includes a first portion, a second portion, a third portion, and a fourth portion; the die pad main surface extends across the first portion, the second portion, the third portion, and the fourth portion, the first portion has a first back surface facing a side opposite to the die pad main surface, and overlaps the semiconductor element when viewed in the thickness direction; the second portion has a second back surface facing a side opposite to the die pad main surface and located closer to the die pad main surface in the thickness direction than the first back surface, and is connected to an outer edge of the first portion when viewed in the thickness direction; the third portion has a third back surface facing a side opposite to the die pad main surface and flush with the first back surface, and extends from an edge on one side of the first portion to an edge on the one side of the die pad main surface in a second direction perpendicular to the thickness direction and the first direction, the fourth portion has a fourth back surface facing the opposite side to the die pad main surface and flush with the first back surface, and extends in the second direction from the other edge of the first portion to the other edge of the die pad main surface. [Appendix 2] 2. The semiconductor device according to claim 1, wherein the first portion, the third portion, and the fourth portion have surfaces opposite to the main surface of the die pad that are exposed from the resin member. [Appendix 3] the die pad main surface includes a plurality of openings, 3. The semiconductor device according to claim 1, wherein the plurality of openings are formed in a portion where the first portion and the third portion are connected and in a portion where the first portion and the fourth portion are connected. [Appendix 4] the die pad has a plurality of recesses recessed in the thickness direction from the main surface of the die pad, 4. The semiconductor device according to claim 3, wherein each of the recesses includes a corresponding one of the openings. [Appendix 5] each of the third portion and the fourth portion includes a tapered portion connected to an outer edge of the first portion and a band-shaped portion extending from the tapered portion to an outer edge of the die pad; 5. The semiconductor device according to claim 1, wherein the tapered portion has a width that narrows from an outer edge of the first portion toward the strip portion when viewed in the thickness direction. [Appendix 6] the plurality of leads further includes a second lead; the plurality of connection members further includes a second connection member, the first lead has a first pad surface to which the first connection member is joined; the second lead has a second pad surface to which the second connection member is joined; 6. The semiconductor device according to claim 1, wherein the first pad surface is larger than the second pad surface when viewed in the thickness direction. [Appendix 7] the resin member has a resin back surface, a pair of first resin side surfaces, and a pair of second resin side surfaces; the rear surface of the resin faces the same direction as the rear surface of the element in the thickness direction, The pair of first resin side surfaces are spaced apart in the first direction, The pair of second resin side surfaces are spaced apart in the second direction, 7. The semiconductor device according to claim 6, wherein each of the plurality of leads is exposed from the back surface of the resin. [Appendix 8] the plurality of leads include a plurality of first lateral leads arranged on either side of the die pad in the first direction and each exposed from one of the pair of first resin side surfaces; The semiconductor device described in Appendix 7, wherein the plurality of first side leads include at least one or more of the first leads. [Appendix 9] the plurality of leads include a plurality of second lateral leads arranged on either side of the die pad in the second direction and each exposed from one of the pair of second resin side surfaces; The semiconductor device described in Appendix 8, wherein the plurality of second side leads include at least one or more of the second leads. [Appendix 10] 10. The semiconductor device of claim 9, wherein the plurality of second side leads do not include the first lead. [Appendix 11] 11. The semiconductor device according to claim 6, wherein the plurality of main surface electrodes include a first main surface electrode to which the first connection member is joined and a second main surface electrode to which the second connection member is connected. [Appendix 12] The semiconductor device includes a power section including a power element, and a control circuit section constituting a control circuit for the power element, the first principal surface electrode is electrically connected to the power section, 12. The semiconductor device according to claim 11, wherein the second principal surface electrode is electrically connected to the control circuit section. [Appendix 13] 13. The semiconductor device according to claim 11, wherein the first principal surface electrode is located between the third portion and the fourth portion when viewed in the thickness direction. [Appendix 14] 14. The semiconductor device according to claim 6, wherein the first connection member is a bonding wire joined by wedge bonding. [Appendix 15] 15. The semiconductor device according to claim 1, further comprising a plurality of third leads extending from an outer edge of the die pad toward an outer edge of the resin member when viewed in the thickness direction. [Appendix 16] the die pad has a rectangular shape when viewed in the thickness direction, 16. The semiconductor device according to claim 15, wherein the third leads extend from each of four corners of the die pad when viewed in the thickness direction. [Appendix 17] 17. The semiconductor device according to claim 15, wherein each of the third leads is connected to the second portion when viewed in the thickness direction. [Explanation of symbols]

[0107] A1 to A6: Semiconductor device 1, 1A, 1B: Semiconductor element 10a: element main surface 10b: Back side of element 101: Power section 102: Control circuit section 11: Main surface electrode 12: First principal surface electrode 13: Second principal surface electrode 2: Resin material 20:Outer edge 21: Resin main surface 22: Resin back 23: First resin side 24: Second resin side 3: Die pad 30a: Main surface of die pad 301: Outer edge 301a, 301b: Edge 302: Opening 31: Part 1 31a: Back side 310: Outer edge 310a, 310b: Edge 32: Part 2 32a: Back side 33: Part 3 33a: Back side 331: Tapered section 332: Belt 34: Part 4 34a: Back 341: Tapered section 342: Belt 35: Recess 36:Through hole 39: Clamp marks 4: Lead 41: First lateral lead 42: Second lateral lead 43: 3rd lead 5: 1st lead 50a: 1st pad surface 501,502: Edge 503: Opening 503a: 1st opening 503b: 2nd opening 505: Notch 51: Part 1 51a: Back side 511: Outer part 512: Inner part 52: Part 2 52a: Back 521: Connection 522 :Connection part 55: Recess 56:Through hole 59: Clamp marks 6: 2nd lead 60a: Second pad surface 601,602: Edge 61: Part 1 61a: Back 62: Part 2 62a: Back 7: Connection parts 71: First connecting member 72: Second connecting member 73: Third connecting member

Claims

1. a semiconductor element having a main surface and a back surface spaced apart in a thickness direction, the main surface having a plurality of main surface electrodes disposed thereon; a die pad having a die pad main surface on which the semiconductor element is mounted; a first lead disposed on one side of the die pad in a first direction perpendicular to the thickness direction, the first lead being disposed around the die pad as viewed in the thickness direction; a plurality of connection members including a first connection member joined to the first lead, electrically connecting the plurality of principal surface electrodes and the plurality of leads; a resin member that seals the semiconductor element, a portion of the die pad, each of the plurality of leads, and the plurality of connection members; Equipped with each of the plurality of leads entirely overlaps the resin member as viewed in the thickness direction and is disposed along an outer edge of the resin member as viewed in the thickness direction; the die pad includes a first portion, a second portion, a third portion, and a fourth portion; the die pad main surface extends across the first portion, the second portion, the third portion, and the fourth portion, the first portion has a first back surface facing a side opposite to the die pad main surface and overlaps the semiconductor element when viewed in the thickness direction; the second portion has a second back surface facing a side opposite to the die pad main surface and located closer to the die pad main surface in the thickness direction than the first back surface, and is connected to an outer edge of the first portion when viewed in the thickness direction; the third portion has a third back surface facing a side opposite to the die pad main surface and flush with the first back surface, and extends from an edge on one side of the first portion to an edge on the one side of the die pad main surface in a second direction perpendicular to the thickness direction and the first direction, the fourth portion has a fourth back surface facing a side opposite to the die pad main surface and flush with the first back surface, and extends in the second direction from an edge on the other side of the first portion to an edge on the other side of the die pad main surface, each of the third portion and the fourth portion includes a tapered portion connected to an outer edge of the first portion and a band-shaped portion extending from the tapered portion to an outer edge of the die pad; The tapered portion has a width that narrows from an outer edge of the first portion toward the band-shaped portion when viewed in the thickness direction. Semiconductor device.

2. the first portion, the third portion, and the fourth portion have surfaces opposite to the die pad main surface that are exposed from the resin member; The semiconductor device according to claim 1 .

3. the die pad main surface includes a plurality of openings, The plurality of openings are formed in a portion where the first portion and the third portion are connected and in a portion where the first portion and the fourth portion are connected, 3. The semiconductor device according to claim 1.

4. the die pad has a plurality of recesses recessed in the thickness direction from the main surface of the die pad, Each of the plurality of recesses includes a respective one of the plurality of openings. The semiconductor device according to claim 3 .

5. the plurality of leads further includes a second lead; The plurality of connection members further includes a second connection member, the first lead has a first pad surface to which the first connection member is joined; the second lead has a second pad surface to which the second connection member is joined; The first pad surface is larger than the second pad surface in the thickness direction.

5. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

6. the resin member has a resin back surface, a pair of first resin side surfaces, and a pair of second resin side surfaces; the rear surface of the resin faces the same direction as the rear surface of the element in the thickness direction, The pair of first resin side surfaces are spaced apart in the first direction, The pair of second resin side surfaces are spaced apart in the second direction, Each of the plurality of leads is exposed from the rear surface of the resin. The semiconductor device according to claim 5 .

7. the plurality of leads include a plurality of first lateral leads arranged on either side of the die pad in the first direction and each exposed from one of the pair of first resin side surfaces; The plurality of first lateral leads includes at least one or more of the first leads. The semiconductor device according to claim 6.

8. the plurality of leads include a plurality of second side leads arranged on either side of the die pad in the second direction and each exposed from one of the pair of second resin side surfaces; the plurality of second lateral leads includes at least one or more of the second leads; The semiconductor device according to claim 7.

9. the second plurality of lateral leads does not include the first lead; The semiconductor device according to claim 8.

10. the plurality of principal surface electrodes include a first principal surface electrode to which the first connection member is joined and a second principal surface electrode to which the second connection member is connected; 10. The semiconductor device according to claim 5, wherein the first insulating layer is a first insulating layer.

11. The semiconductor device includes a power section including a power element, and a control circuit section constituting a control circuit for the power element, the first principal surface electrode is electrically connected to the power section; The second principal surface electrode is electrically connected to the control circuit unit. The semiconductor device according to claim 10.

12. the first principal surface electrode is located between the third portion and the fourth portion as viewed in the thickness direction; The semiconductor device according to claim 10 or 11.

13. The first connection member is a bonding wire that is bonded by wedge bonding. The semiconductor device according to claim 5 .

14. a plurality of third leads extending from an outer edge of the die pad toward an outer edge of the resin member as viewed in the thickness direction; The semiconductor device according to claim 1 .

15. the die pad has a rectangular shape when viewed in the thickness direction, the third leads extend from each of the four corners of the die pad when viewed in the thickness direction. The semiconductor device according to claim 14.

16. Each of the third leads is connected to the second portion as viewed in the thickness direction.

16. The semiconductor device according to claim 14 or 15.

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