Semiconductor Package

Abstract

In this semiconductor package that forms vias, a decrease in yield is suppressed.　The semiconductor package comprises: a solid-state image sensor; a circuit layer; a wiring layer; and a support substrate. In the semiconductor package, the solid-state image sensor produces image data. A signal processing circuit that performs a predetermined signal process on the image data is disposed on the circuit layer. An output-side via of which the other end is connected to the external terminal penetrates the support substrate. The wiring layer is disposed between the support substrate and the circuit layer, and a signal line connecting a signal processing circuit and one end of the output-side via is wired.

Description

[Technical field]

[0001] The present technology relates to a semiconductor package, and more particularly to a semiconductor package provided with a solid-state imaging element. [Background technology]

[0002] Conventionally, in order to facilitate the handling of semiconductor integrated circuits, semiconductor packages have been used in which the semiconductor integrated circuits are mounted on a substrate and sealed. For example, a semiconductor package has been proposed in which a solid-state imaging element is mounted as the semiconductor integrated circuit, and the solid-state imaging element, a wiring layer, a logic circuit, and a support substrate are stacked in this order from the light receiving side (see, for example, Patent Document 1). In this semiconductor package, the logic circuit and the solid-state imaging element are connected through wiring in the wiring layer, and data is output from the wiring layer to an external terminal through a via that penetrates the support substrate and the logic circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-99582 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional technology, the functionality of the semiconductor package is improved by arranging a logic circuit in addition to the solid-state imaging element. However, in the above-mentioned semiconductor package, the vias penetrate the support substrate and the logic circuit, and the process of forming the vias is more complicated than when the vias penetrate only the support substrate. Therefore, there is a risk of a decrease in yield when mass-producing the semiconductor packages.

[0005] This technology was developed in light of these circumstances, and aims to prevent a decrease in yield in semiconductor packages in which vias are formed. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor package including a solid-state imaging element that generates image data, a circuit layer in which a signal processing circuit that performs predetermined signal processing on the image data is arranged, a support substrate through which an output side via having one end connected to an external terminal penetrates, and a wiring layer in which a signal line is arranged between the support substrate and the circuit layer and connects the signal processing circuit and the other end of the output side via, thereby improving the yield of the semiconductor package.

[0007] In addition, in the first aspect, the solid-state imaging device may further include glass, and a resin dam formed between the glass and a periphery of a pixel array portion of the light receiving surface of the solid-state imaging device, thereby providing an effect of forming a cavity.

[0008] In addition, in the first aspect, the liquid crystal display device may further include glass, and a transparent resin embedded between the solid-state imaging element and the glass, thereby providing an effect of eliminating a cavity.

[0009] In the first aspect, the output side vias may be arranged in an area of ​​the surface of the support substrate that corresponds to the signal processing circuit and an area that does not correspond to the signal processing circuit, thereby preventing a shortage of external terminals.

[0010] In addition, in the first aspect, the semiconductor device may further include a ceramic substrate, and the output-side via may penetrate the support substrate and the ceramic substrate, thereby improving the yield of the ceramic package.

[0011] In addition, in the first aspect, an embedded element may be further disposed on the circuit layer, and an opening extending from the light receiving surface of the solid-state imaging element to the embedded element may be formed in the solid-state imaging element and the circuit layer, thereby improving the functionality of the semiconductor package.

[0012] A second aspect of the present technology is a semiconductor package including a solid-state imaging element that generates image data and inputs the image data to one end of an input via, a wiring layer in which a signal line is wired to connect a signal processing circuit that performs a predetermined signal processing on the image data to the other end of the input via, and a circuit layer that is disposed between the solid-state imaging element and the wiring layer and in which the input via and the signal processing circuit are provided, thereby improving the yield of the semiconductor package.

[0013] In addition, in the second aspect, the semiconductor device may further include a ceramic substrate through which an output via having one end connected to an external terminal penetrates, thereby improving the yield of the ceramic package.

[0014] In the second aspect, the ceramic substrate and the wiring layer may be connected by a wire, thereby improving the yield of semiconductor packages that have been wire-bonded.

[0015] In the second aspect, the ceramic substrate and the wiring layer may be connected by bumps, thereby improving the yield of semiconductor packages in which flip chip connections are performed.

[0016] In addition, in the second aspect, the present invention may further include a glass, a spacer resin formed between the periphery of the pixel array portion of the solid-state imaging element and the glass, and an interposer, and the interposer and the wiring layer may be connected by wires, thereby improving the yield of the semiconductor package subjected to wire bonding.

[0017] In addition, in the second aspect, the semiconductor device may further include a redistribution layer on which signal lines are wired to connect the bonding bumps and the external terminals, and the wiring layer is connected to the redistribution layer by the bumps, thereby improving the yield of semiconductor packages having flip-chip connections.

[0018] In addition, in the second aspect, the semiconductor device may further include a frame and an interposer bonded to the frame, and the interposer and the wiring layer may be connected by wires, thereby improving the yield of semiconductor packages that have been wire-bonded.

[0019] In the second aspect, an embedded element may be further disposed on the circuit layer, and an opening extending from the light receiving surface of the solid-state imaging element to the embedded element may be formed in the solid-state imaging element and the circuit layer, thereby improving the functionality of the semiconductor package.

[0020] In addition, in the second aspect, the semiconductor device may further include a framed substrate having a frame formed on its outer periphery, and the wiring layer and the framed substrate may be connected by wires, thereby improving the yield of semiconductor packages that have been wire-bonded.

[0021] In addition, in the second aspect, the semiconductor device may further include a ceramic substrate, and the ceramic substrate and the wiring layer may be connected by a wire, thereby improving the yield of ceramic packages that have been wire-bonded.

[0022] In addition, in the second aspect, an additional circuit may be provided on the light-receiving surface of the wiring layer, thereby improving the functionality of the semiconductor package.

[0023] In the second aspect, the additional circuit may be embedded in a sealing resin, thereby improving the reliability of the semiconductor package.

[0024] In addition, in the second aspect, a transparent resin for protecting the light receiving surface of the solid-state imaging element may be further provided, thereby providing an effect of reducing the thickness of the semiconductor package.

[0025] In the second aspect, the display device may further include glass connected to the sealing resin via a rib, thereby providing an effect of protecting the light receiving surface of the solid-state imaging element. [Brief description of the drawings]

[0026] [Figure 1] 1 is a block diagram showing a configuration example of an electronic device according to a first embodiment of the present technology. [Diagram 2] 1 is a cross-sectional view showing a configuration example of a semiconductor package according to a first embodiment of the present technology. [Diagram 3] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to a first embodiment of the present technology. [Figure 4] FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor package in a comparative example. [Diagram 5] FIG. 11 is a cross-sectional view showing a schematic configuration of a semiconductor package in a comparative example. [Figure 6] 2A to 2C are diagrams for explaining a process up to a step of thinning a logic circuit and the like in the first embodiment of the present technology. [Figure 7] 4A to 4C are diagrams for explaining steps up to the step of forming an input side via in the first embodiment of the present technology. [Figure 8] 4A to 4C are diagrams for explaining steps up to forming an output-side via, rewiring, and an external terminal according to the first embodiment of the present technology. [Figure 9] 4 is a flowchart showing an example of a method for manufacturing a semiconductor package according to the first embodiment of the present technology. [Figure 10] 1 is a cross-sectional view showing a configuration example of a semiconductor package according to a first modified example of the first embodiment of the present technology. [Figure 11] 11 is a cross-sectional view showing a configuration example of a semiconductor package according to a second modified example of the first embodiment of the present technology. FIG. [Figure 12] 11 is a cross-sectional view showing a configuration example of a semiconductor package according to a third modified example of the first embodiment of the present technology. FIG. [Figure 13] 11 is a cross-sectional view showing a configuration example of a semiconductor package according to a second embodiment of the present technology. FIG. [Figure 14] 11 is a cross-sectional view illustrating a schematic configuration of a sensor chip according to a second embodiment of the present technology. FIG. [Figure 15] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a first modified example of the second embodiment of the present technology. FIG. [Figure 16] 13 is a cross-sectional view illustrating a schematic configuration of a sensor chip according to a first modified example of the second embodiment of the present technology. FIG. [Figure 17] 13 is a cross-sectional view of a semiconductor package and an optical unit 110 in a first modified example of the second embodiment of the present technology. FIG. [Figure 18] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a second modified example of the second embodiment of the present technology. FIG. [Figure 19] 13A to 13C are diagrams for explaining steps up to a process of mounting glass in a second modified example of the second embodiment of the present technology. [Figure 20] 13A to 13C are diagrams for explaining steps up to a step of forming an external terminal in a second modified example of the second embodiment of the present technology. [Figure 21] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a third modified example of the second embodiment of the present technology. FIG. [Figure 22] 13A and 13B are a top view and a bottom view of a semiconductor package according to a third modified example of the second embodiment of the present technology. [Figure 23] FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a fourth modified example of the second embodiment of the present technology. [Figure 24] FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a fifth modified example of the second embodiment of the present technology. [Diagram 25] FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a sixth modified example of the second embodiment of the present technology. [Figure 26] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a third embodiment of the present technology. FIG. [Figure 27] 13 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to a third embodiment of the present technology. FIG. [Figure 28] 13A to 13C are diagrams for explaining a process up to a step of thinning a logic circuit and the like in the third embodiment of the present technology. [Figure 29] 13A to 13C are diagrams for explaining steps up to a step of connecting a supporting substrate according to a third embodiment of the present technology. [Diagram 30] 13A to 13C are views for explaining a step of forming an opening in the third embodiment of the present technology. [Diagram 31] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a first modified example of the third embodiment of the present technology. FIG. [Diagram 32] FIG. 13 is a cross-sectional view illustrating a schematic configuration of a sensor chip according to a first modified example of the third embodiment of the present technology. [Diagram 33] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a second modified example of the third embodiment of the present technology. FIG. [Diagram 34] FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a third modified example of the third embodiment of the present technology. [Diagram 35] 13 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to a third modified example of the third embodiment of the present technology. FIG. [Diagram 36] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a fourth embodiment of the present technology. FIG. [Figure 37] 13 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to a fourth embodiment of the present technology. FIG. [Figure 38]13A to 13C are diagrams for explaining a process up to a step of thinning a logic circuit and the like in the fourth embodiment of the present technology. [Figure 39] 13A to 13C are diagrams for explaining a process up to forming a wiring layer in the fourth embodiment of the present technology. [Diagram 40] 13A to 13C are diagrams for explaining steps up to forming a color filter and an on-chip lens according to a fourth embodiment of the present technology. [Diagram 41] 13A to 13C are diagrams for explaining a process up to wire bonding in a fourth embodiment of the present technology. [Diagram 42] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a first modified example of a fourth embodiment of the present technology. FIG. [Diagram 43] 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a second modified example of the fourth embodiment of the present technology. FIG. [Diagram 44] 13A to 13C are diagrams for explaining a process up to wire bonding in a second modified example of the fourth embodiment of the present technology. [Diagram 45] FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a third modified example of the fourth embodiment of the present technology. [Figure 46] FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor package in a fourth modified example of the fourth embodiment of the present technology. [Figure 47] FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor package according to a fifth modified example of the fourth embodiment of the present technology. [Figure 48] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 49] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example in which vias penetrate only the supporting substrate) 2. Second embodiment (example in which a via is inserted through a supporting substrate and the device is mounted in a ceramic package, etc.) 3. Third embodiment (embedded light emitting element) 4. Fourth embodiment (example of adding circuits and components) 5. Application examples for mobile objects

[0028] <1. First embodiment> [Example of electronic device configuration] 1 is a block diagram showing an example of a configuration of an electronic device according to a first embodiment of the present technology. The electronic device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state imaging element 220, and a DSP (Digital Signal Processing) circuit 120. The electronic device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. Examples of the electronic device 100 include digital cameras such as digital still cameras, as well as smartphones, personal computers, and vehicle-mounted cameras.

[0029] The optical unit 110 collects light from a subject and guides it to the solid-state imaging element 220. The solid-state imaging element 220 photoelectrically converts the incident light in synchronization with a vertical synchronization signal to generate image data. Here, the vertical synchronization signal is a periodic signal of a predetermined frequency that indicates the timing of imaging. The solid-state imaging element 220 supplies the generated image data to the DSP circuit 120.

[0030] The DSP circuit 120 executes a predetermined signal processing on the image data from the solid-state imaging device 220. The DSP circuit 120 outputs the processed image data via a bus 150 to a frame memory 160 or the like.

[0031] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0032] The bus 150 is a common path for the optical unit 110, the solid-state imaging device 220, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170 and the power supply unit 180 to exchange data with one another.

[0033] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging element 220, the DSP circuit 120, the display unit 130, and the like.

[0034] In the above-mentioned configuration, for example, the solid-state imaging element 220 and the DSP circuit 120 are mounted in a semiconductor package.

[0035] [Example of semiconductor package configuration] 2 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to the first embodiment of the present technology. In this semiconductor package 200, a glass 210, a solid-state imaging element 220, a circuit layer 230, a wiring layer 240, and a support substrate 250 are provided in this order from the top, assuming that the light-receiving side is the upper side.

[0036] The glass 210 protects the solid-state imaging element 220. Incident light from the optical unit 110 is incident on the light receiving surface of the glass 210. The arrow in the figure indicates the incident direction of the incident light.

[0037] Hereinafter, the optical axis of the incident light is referred to as the "Z axis." A specific direction perpendicular to the Z axis is referred to as the "X axis," and a direction perpendicular to the X and Z axes is referred to as the "Y axis." The figure is a cross-sectional view seen from the Y axis direction.

[0038] The solid-state imaging element 220 generates image data by photoelectric conversion. A resin dam 261 is formed of a photosensitive resin or the like between the periphery of a pixel array portion, in which pixels are arranged, of the light receiving surface of the solid-state imaging element 220 and the glass 210. This resin dam 261 forms a cavity 262, which is a space surrounded by the resin dam 261, the light receiving surface of the solid-state imaging element 220, and the glass 210.

[0039] The circuit layer 230 is disposed between the solid-state imaging element 220 and the wiring layer 240, and is a layer in which a plurality of input side vias such as the input side vias 231 and 234, the logic circuit 232, and the memory 233 are embedded in an insulating film. The input side vias 231 and 234 are TSVs (Through Silicon Vias) that extend along the Z axis and penetrate a portion of the circuit layer 230 in which circuits such as the logic circuit 232 and the memory 233 are not disposed. One end of the input side vias 231 and 234 is connected to the solid-state imaging element 220.

[0040] The logic circuit 232 performs a predetermined process on the image data. For example, the DSP circuit 120 is arranged as the logic circuit 232. The memory 233 temporarily holds the image data. The logic circuit 232 is an example of a signal processing circuit described in the claims.

[0041] The wiring layer 240 is disposed between the support substrate 250 and the circuit layer 230. A predetermined number of signal lines 242 are wired in the wiring layer 240. Pads 241 and 243 are also disposed in the wiring layer 240. These signal lines 242 include a signal line that connects the other end of the input side vias 231, etc. to the logic circuit 232, and a signal line that connects the logic circuit 232 and the memory 233. These signal lines 242 also include a signal line that connects the logic circuit 232 to the pads 241 and 243.

[0042] The support substrate 250 is a substrate through which a plurality of output side vias, such as output side vias 251 and 254, penetrate. The output side vias 251 and 254 extend in the Z direction in the support substrate 250 and penetrate portions corresponding to the pads 241 and 243 (i.e., portions corresponding to the periphery of the logic circuit 232, etc.). In addition, a predetermined number of external terminals 253 are provided on the lower surface of the support substrate 250, with the light receiving side being the upper side. For example, solder balls are used as the external terminals 253.

[0043] Further, rewiring 252 is wired on the support substrate 250, and one end of the output side vias 251 and 254 is connected to an external terminal 253 via the rewiring 252. The other end of the output side vias 251 and 253 is connected to a signal line 242 in the wiring layer 240 via a pad 241 or 243.

[0044] 3 is a cross-sectional view showing a schematic configuration of a semiconductor package 200 according to a first embodiment of the present technology, in which the resin dam 261, the signal line 242, and the rewiring 252 are omitted.

[0045] As illustrated in the figure, with the light receiving side facing up, a glass 210, a solid-state imaging element 220, a circuit layer 230, a wiring layer 240, and a support substrate 250 are provided in this order from the top.

[0046] The solid-state imaging element 220 generates image data by photoelectric conversion and inputs it to one end of the input side vias 231 and 234. The logic circuit 232 receives the image data via the input side vias 231 etc. and signal lines in the wiring layer 240, and performs signal processing on the image data. In this signal processing, the logic circuit 232 accesses the memory 233 via the wiring layer 240 and writes and reads the image data. In addition, the logic circuit 232 outputs the processed data to the external terminal 253 via the wiring layer 240 and the output side vias 251 etc.

[0047] Here, as a comparative example, a semiconductor package is assumed in which, from the top, a glass 210, a solid-state imaging element 220, a wiring layer 240, a circuit layer 230, and a support substrate 250 are arranged.

[0048] FIG. 4 is a cross-sectional view showing a configuration example of a semiconductor package in the comparative example.

[0049] FIG. 5 is a cross-sectional view showing a schematic configuration of a semiconductor package in a comparative example.

[0050] 4 and 5, in the comparative example, a wiring layer 240 is disposed between the solid-state imaging element 220 and the circuit layer 230. This wiring layer 240 is manufactured using wiring within the solid-state imaging element 220. Furthermore, signal lines connecting the logic circuit 232 and the memory 233 are wired in the wiring layer 240. For this reason, it is necessary to design the wiring within the solid-state imaging element 220 according to the logic circuit 232 and memory 233 to be mounted, and there is a risk that the degree of freedom in the wiring design of the solid-state imaging element 220 will decrease.

[0051] 2 and 3, the circuit layer 230 is disposed between the solid-state imaging element 220 and the wiring layer 240. This eliminates the need to change the wiring of the solid-state imaging element 220 depending on the logic circuit 232 and memory 233 to be mounted, thereby improving the freedom of wiring design.

[0052] In the comparative example, in order to output data from the external terminal 253, vias are formed that penetrate the support substrate 250 and the logic circuit 232 or memory 233. In this configuration, pads for penetrating the vias must be arranged in the logic circuit 232 or memory 233, and the area of ​​the logic circuit 232 or the like must be increased accordingly. In addition, if the logic circuit 232 or the like is an externally procured product, there is a risk that the pads cannot be provided. Furthermore, compared to the case where only the support substrate 250 is penetrated, the process of forming the vias becomes more complicated, and there is a risk that the yield rate will decrease when the semiconductor package 200 is mass-produced. In addition, the vias penetrating the logic circuit 232 or the like may cause the characteristics of the logic circuit 232 or the like to fluctuate, and the yield rate may decrease due to the characteristic fluctuation.

[0053] In contrast, in the semiconductor package 200 illustrated in FIG. 2 and FIG. 3, the output side vias 251 and the like are formed to penetrate only the support substrate 250. This eliminates the need to provide pads for penetrating the vias in the logic circuit 232 and the memory 233, and the area of ​​the logic circuit 232 and the like can be reduced accordingly. In addition, since there is no need to provide pads, it is easy to use externally procured items for the logic circuit 232 and the like. Furthermore, compared to the case where the output side vias 251 and the like penetrate the support substrate 250 and the logic circuit 232 and the memory 233, the process of forming the output side vias 251 and the like is simplified, and the yield can be improved. In addition, since the output side vias 251 and the like do not penetrate the logic circuit 232 and the like, the characteristics of the logic circuit 232 and the like do not fluctuate, and the decrease in yield caused by the characteristic fluctuation can be suppressed.

[0054] Next, a method for manufacturing the semiconductor package 200 will be described.

[0055] [Semiconductor package manufacturing method] 6 is a diagram for explaining the process up to the step of thinning the logic circuit 232 etc. in the first embodiment of the present technology. In the figure, "a" is a diagram for explaining the process of forming the wiring layer 240. In the figure, "b" is a diagram for explaining the process of connecting the logic circuit 232 etc. In the figure, "c" is a diagram for explaining the process up to the step of thinning the logic circuit 232 etc.

[0056] As shown in FIG. 1A, the manufacturing system for the semiconductor package 200 first forms a wiring layer 240 for each chip region on a wafer-like support substrate 250 divided into a plurality of chip regions. Then, as shown in FIG. 1B, the manufacturing system connects the logic circuit 232 and the memory 233 to the wiring layer 240 by Cu-Cu bonding or the like. This process is called C2W (Chip to Wafer) connection. Next, as shown in FIG. 1C, the manufacturing system thins the logic circuit 232 and the memory 233 as necessary.

[0057] 7 is a diagram for explaining the process up to forming the input side via 231 etc. in the first embodiment of the present technology. In the figure, "a" is a diagram for explaining the process of embedding the logic circuit 232 etc. in the insulating film. In the figure, "b" is a diagram for explaining the process of planarizing the circuit layer. In the figure, "c" is a diagram for explaining the process of forming the input side via 231 etc.

[0058] As shown in FIG. 1A, the manufacturing system forms a circuit layer 230 by embedding logic circuits 232 and the like with an insulating film. Then, as shown in FIG. 1B, the manufacturing system flattens the circuit layer 230. Next, as shown in FIG. 1C, the manufacturing system forms input side vias 231 and 234 that penetrate regions of the circuit layer 230 where the logic circuits 232 and the like are not arranged.

[0059] 8 is a diagram for explaining the process up to forming the output-side via 251, the rewiring 252, and the external terminal 253 in the first embodiment of the present technology. In the figure, "a" is a diagram for explaining the process of connecting the solid-state imaging element 220. In the figure, "b" is a diagram for explaining the process of forming the color filter and the on-chip lens. In the figure, "c" is a diagram for explaining the process up to forming the output-side via 251, the rewiring 252, and the external terminal 253.

[0060] As shown in FIG. 1A, the manufacturing system prepares a wafer on which a plurality of solid-state imaging elements 220 are provided, and connects the solid-state imaging elements 220 to input side vias 231 of a wafer-like support substrate 250 by Cu-Cu bonding or the like. This process is called WoW (Wafer on Wafer) connection. As shown in FIG. 1B, the manufacturing system forms a plurality of pixels 221 on the solid-state imaging element 220, and forms a color filter (not shown) and an on-chip lens 222 for each pixel 221. As shown in FIG. 1C, the manufacturing system then forms output side vias 251 and 254, rewiring 252, and external terminals 253 on the support substrate 250. As shown in FIG. 1C, the manufacturing system also forms a resin dam 261 and seals the solid-state imaging elements 220 with glass 210. The manufacturing system then dices the solid-state imaging elements 220 into individual chip regions.

[0061] As illustrated in FIGS. 6 to 8, a semiconductor package 200 manufactured at the wafer level is called a WLCSP (Wafer Level Chip Size Package).

[0062] FIG. 9 is a flowchart showing an example of a method for manufacturing the semiconductor package 200 according to the first embodiment of the present technology.

[0063] The manufacturing system first forms the wiring layer 240 on the support substrate 250 (step S901), and connects the logic circuit 232 and the memory 233 to the wiring layer 240 by Cu-Cu bonding or the like (step S902). The manufacturing system then thins the logic circuit 232 and the memory 233 (step S903), buries the logic circuit 232 and the like in an insulating film, and forms the circuit layer 230 (step S904). Next, the manufacturing system flattens the circuit layer 230 (step S905), and forms the input side vias 231 and 234 (step S906).

[0064] The manufacturing system connects the solid-state imaging element 220 by Cu-Cu bonding or the like (step S907). The manufacturing system forms a plurality of pixels 221 in the solid-state imaging element 220, and forms a color filter and an on-chip lens 222 for each pixel 221 (step S908). Next, the manufacturing system forms output side vias 251 and 254, rewiring 252, and external terminals 253 in the support substrate 250, and seals the solid-state imaging element 220 with glass 210 (step S909). After step S909, the manufacturing system performs dicing, inspection, and the like, and completes the manufacture of the semiconductor package 200.

[0065] As described above, according to the first embodiment of the present technology, the output-side vias 251 and the like penetrate only the support substrate 250, and therefore, the vias can be formed by a simple process compared to the case where the vias penetrate the support substrate 250 and the logic circuit 232. This makes it possible to improve the yield of the semiconductor package 200 compared to the case where the vias penetrate the support substrate 250 and the logic circuit 232.

[0066] [First Modification] In the above-described first embodiment, the resin dam 261 provides the cavity 262 in the semiconductor package 200, but there is a risk that a part of the wall surface of the resin dam 261 may peel off and fall onto the image plane of the solid-state imaging element 220. The semiconductor package 200 of the first modified example of the first embodiment differs from the first embodiment in that the cavity 262 is eliminated by filling it with a transparent resin.

[0067] 10 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a first modified example of the first embodiment of the present technology. The semiconductor package 200 in the first modified example of the first embodiment differs from the first embodiment in that a transparent resin 263 is formed instead of the resin dam 261. The transparent resin 263 is embedded between the glass 210 and the solid-state imaging element 220. This eliminates the cavity 262 and makes it possible to prevent the wall surface of the resin dam 261 from peeling off.

[0068] Thus, according to the first modified example of the first embodiment of the present technology, the transparent resin 263 is embedded between the glass 210 and the solid-state imaging element 220, thereby eliminating the cavity 262 and preventing peeling of the wall surface of the resin dam 261.

[0069] [Second modified example] In the above-described first embodiment, the output side vias 251 and the like are arranged in the portions corresponding to the periphery of the logic circuit 232 and the like, but this configuration may result in an insufficient number of external terminals 253. The semiconductor package 200 of the second modified example of the first embodiment differs from the first embodiment in that the output side vias are also arranged directly below the logic circuit 232 and the like.

[0070] 11 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a second modified example of the first embodiment of the present technology. The semiconductor package 200 in the second modified example of the first embodiment differs from the first embodiment in that a predetermined number of output side vias 255 are arranged in the supporting substrate 250 not only in areas not corresponding to the logic circuit 232 or the memory 233 but also in areas corresponding to the logic circuit 232 or the memory 233. In other words, the output side vias 255 are arranged also directly below the logic circuit 232, etc. in the supporting substrate 250. This increases the number of output side vias, and prevents a shortage of external terminals 253.

[0071] In this way, according to the second modified example of the first embodiment of the present technology, the output side vias 255 are also formed in the areas corresponding to the logic circuit 232 and the memory 233, so that the number of output side vias can be increased and a shortage of external terminals 253 can be prevented.

[0072] [Third modified example] In the second modified example of the first embodiment described above, a cavity 262 is provided in the semiconductor package 200 by the resin dam 261, but there is a risk that a part of the wall surface of the resin dam 261 may peel off and fall onto the image plane of the solid-state imaging element 220. The semiconductor package 200 of the third modified example of the first embodiment differs from the second modified example of the first embodiment in that the cavity 262 is eliminated by filling it with a transparent resin.

[0073] 12 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a third modified example of the first embodiment of the present technology. The semiconductor package 200 in the third modified example of the first embodiment differs from the second modified example of the first embodiment in that a transparent resin 263 is formed instead of the resin dam 261. This eliminates the cavity 262 and makes it possible to prevent peeling of the wall surface of the resin dam 261.

[0074] In this manner, according to the third modified example of the first embodiment of the present technology, the transparent resin 263 is embedded between the glass 210 and the solid-state imaging element 220, thereby eliminating the cavity 262 and preventing peeling of the wall surface of the resin dam 261.

[0075] <2. Second embodiment> In the above-described first embodiment, the yield of the semiconductor package 200 manufactured at the wafer level is improved, but it is also possible to improve the yield of a ceramic package mounted on a ceramic substrate. The semiconductor package 200 of this second embodiment differs from the first embodiment in that it is a ceramic package.

[0076] 13 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to the second embodiment of the present technology. In the semiconductor package 200 according to the second embodiment, a glass 210, a sensor chip 310, and a ceramic substrate 320 are provided.

[0077] The sensor chip 310 is a chip in which, from the top, a solid-state imaging element 220, a circuit layer 230, a wiring layer 240, and a support substrate 250 are laminated, with the light receiving side being the upper side. The configuration of each layer is the same as that of the first embodiment. However, the output side via 255 of the second embodiment is different from that of the first embodiment in that it penetrates both the support substrate 250 and the ceramic substrate 320.

[0078] A space is provided within the ceramic substrate 320, and the sensor chip 310 is provided within the space. The space is also sealed with glass 210.

[0079] 14 is a cross-sectional view showing a schematic configuration of a sensor chip 310 according to the second embodiment of the present technology. As shown in the figure, the logic circuit 232 outputs data to the outside through an output-side via 255 penetrating the support substrate 250 and the ceramic substrate 320.

[0080] As described above, according to the second embodiment of the present technology, the sensor chip 310 is disposed in the ceramic substrate 320 through which the output-side vias 255 penetrate, so that the yield of ceramic packages can be improved.

[0081] [First Modification] In the above-described second embodiment, the sensor chip 310 is connected to the ceramic substrate 320 by the output-side vias 255, but the connection can also be made by wires. The semiconductor package 200 of the first modified example of the second embodiment differs from the second embodiment in that the sensor chip 310 is connected to the ceramic substrate 320 by wires.

[0082] 15 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a first modified example of the second embodiment of the present technology. The semiconductor package 200 in the first modified example of the second embodiment differs from the second embodiment in that it is connected to a ceramic substrate 320 by a wire 331.

[0083] Furthermore, the ceramic substrate 320 is provided with an output via 321, rewiring 322, and an external terminal 253. The output via 321 penetrates the ceramic substrate 320, and one end of the output via 321 is connected to the wire 331. Furthermore, the output via 321 and the rewiring 322 are connected to the external terminal 253.

[0084] 16 is a cross-sectional view showing a schematic configuration of a sensor chip 310 according to a second embodiment of the present technology. As shown in the figure, the output side via 255 is not formed in the support substrate 250. Therefore, the via does not penetrate the logic circuit 232, etc., and the characteristics of the logic circuit 232, etc. do not fluctuate due to the penetration of the via. Therefore, it is possible to suppress a decrease in yield caused by the characteristic fluctuation.

[0085] Moreover, the areas of the wiring layer 240 and the support substrate 250 as viewed from the Z-axis direction are smaller than those of the solid-state imaging element 220 and the circuit layer 230. Therefore, with the light-receiving side facing up, a space is generated around the area of ​​the upper surface of the wiring layer 240 that corresponds to the solid-state imaging element 220. A predetermined number of pads, such as pads 244 and 245, are provided in this space. These pads are connected to wires 331. The logic circuit 232 outputs data to the ceramic substrate 320 via the wires 331.

[0086] 17 is a cross-sectional view of a semiconductor package 200 and an optical unit 110 in a first modified example of the second embodiment of the present technology. As illustrated in the figure, a glass 210 of the semiconductor package 200 is attached to the optical unit 110 including a lens and a lens holder. Note that the semiconductor package 200 other than the first modified example of the second embodiment is also attached as illustrated in the figure.

[0087] In this way, in the first modified example of the second embodiment of the present technology, the wiring layer 240 below the logic circuit 232, etc. is connected to the ceramic substrate 320 by the wire 331, so there is no need to make vias penetrate the logic circuit 232, etc. This prevents the characteristics of the logic circuit 232, etc. from fluctuating due to the penetration of the vias, and it is possible to suppress a decrease in yield caused by the characteristic fluctuation.

[0088] [Second modified example] In the above-described second embodiment, the sensor chip 310 is disposed within the ceramic substrate 320 and sealed with the glass 210, but it is also possible to mount the glass 210 directly on the sensor chip 310 via a resin without providing a ceramic substrate. Such a semiconductor package is called a GoC (Glass on Chip) package. The semiconductor package 200 of the second modified example of the second embodiment differs from the second embodiment in that it is a GoC package.

[0089] 18 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a second modified example of the second embodiment of the present technology. The semiconductor package 200 in the second modified example of the second embodiment differs from the second embodiment in that an interposer 345 is provided instead of the ceramic substrate 320. The configuration of the sensor chip 310 in the second modified example of the second embodiment is similar to that of the second embodiment and the first modified example.

[0090] With the light receiving side facing up, the lower surface of the sensor chip 310 is attached to an interposer 345 by an adhesive 344. In addition, the sensor chip 310 is connected to the interposer 345 by wires 331.

[0091] In addition, external terminals 253 are formed on the lower surface of the interposer 345. Vias and rewiring are formed in the interposer 345, and connect the wires 331 to the external terminals 253. As the interposer 345, for example, an organic substrate is used.

[0092] Moreover, potting resin 342 is embedded around the sensor chip 310 when viewed from the Z direction. A mold resin 341 having a flat top is formed on the potting resin 342. Moreover, a spacer resin 343 is formed between the periphery of the pixel array portion on the top surface of the sensor chip 310 and the glass 210.

[0093] As shown in the figure, a semiconductor package having a structure in which glass 210 is placed on a chip (sensor chip 310) is called a GoC package.

[0094] 19 is a diagram for explaining a process up to the step of mounting glass in the second modified example of the second embodiment of the present technology. In the figure, a is a diagram for explaining a configuration for mounting a sensor chip 310. In the figure, b is a diagram for explaining a wire bonding process. In the figure, c is a diagram for explaining a process for forming a spacer resin 343. In the figure, d is a diagram for explaining a process for mounting glass 210.

[0095] As shown in FIG. 11A, the manufacturing system places and bonds the sensor chip 310 on the upper surface of a wafer-like interposer 345. Then, as shown in FIG. 11B, the manufacturing system connects the sensor chip 310 to the interposer 345 with wires 331. Then, as shown in FIG. 11C, the manufacturing system forms a spacer resin 343 around the pixel array section, and as shown in FIG. 11D, the manufacturing system places and fixes the glass 210 on the spacer resin 343.

[0096] 20 is a diagram for explaining up to a step of forming an external terminal 253 in a second modified example of the second embodiment of the present technology. In the figure, "a" is a diagram for explaining a step of forming a potting resin 342. In the figure, "b" is a diagram for explaining a step of forming a mold resin 341. In the figure, "c" is a diagram for explaining a step of forming an external terminal 253.

[0097] As shown in FIG. 1A, the manufacturing system forms potting resin 342 around the sensor chip 310 and embeds wires 331. Then, as shown in FIG. 1B, the manufacturing system forms molding resin 341 on top of the potting resin 342 and smooths it out. Next, as shown in FIG. 1C, the manufacturing system provides a predetermined number of external terminals 253 (solder balls, etc.) on the lower surface of the interposer 345. Next, the manufacturing system separates the interposer 345 into a plurality of packages by dicing.

[0098] In this way, according to the second modification of the second embodiment of the present technology, since the sensor chip 310 is connected to the interposer 345 by the wire 331, it is not necessary to make vias penetrate the logic circuit 232, etc. This eliminates the need for vias to penetrate the logic circuit 232, etc., and makes it possible to suppress a decrease in yield caused by the characteristic fluctuation.

[0099] [Third modified example] In the above-described second embodiment, the sensor chip 310 is connected to the ceramic substrate 320 by the output-side vias 255, but flip-chip connection is also possible. The semiconductor package 200 of the third modified example of the second embodiment differs from the second embodiment in that the sensor chip 310 is connected to the rewiring layer by bumps.

[0100] 21 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a third modified example of the second embodiment of the present technology. The semiconductor package 200 in the third modified example of the second embodiment differs from the second embodiment in that a rewiring layer 354 is provided instead of the ceramic substrate 320. The configuration of the sensor chip 310 in the third modified example of the second embodiment is similar to that of the first modified example of the second embodiment. However, the sensor chip 310 is provided with bumps 353 instead of the pads 244 and the like.

[0101] With the light receiving side facing up, a rewiring layer 354 is formed on the lower surface of the glass 210 except for the region corresponding to the pixel array section. This rewiring layer 354 is provided with rewiring 351, a seal ring 352, and external terminals 253 (such as solder balls).

[0102] In addition, the sensor chip 310 is connected (that is, flip-chip connected) to the rewiring layer 354 by the bumps 353. The connection points of the bumps 353 are sealed by the seal rings 352.

[0103] 22 is a top view and a bottom view of a semiconductor package 200 in a third modified example of the second embodiment of the present technology. In the figure, a is a top view of the semiconductor package 200. In the figure, b is a bottom view of the semiconductor package 200.

[0104] As shown in FIG. 21A, when the semiconductor package 200 is viewed from above, the rewiring 351 can be seen through the glass 210. As shown in FIG. 21B, external terminals 253 are arranged along the outer periphery on the lower surface of the semiconductor package 200. The package having the configuration shown in FIG. 21 and FIG. 22 is called a FOCSP (Fan-Out Chip Size / Scale Package).

[0105] As described above, according to the third modified example of the second embodiment of the present technology, since the sensor chip 310 is flip-chip connected to the rewiring layer 354, it is not necessary to make vias penetrate the logic circuit 232, etc. This eliminates the need for vias to penetrate the logic circuit 232, etc., and makes it possible to suppress a decrease in yield caused by the characteristic fluctuation.

[0106] [Fourth Variation] In the above-described second embodiment, the sensor chip 310 is connected to the ceramic substrate 320, but it can also be attached to an interposer with a frame. The semiconductor package 200 of the fourth modification of the second embodiment differs from the second embodiment in that the sensor chip 310 is attached to an interposer with a frame.

[0107] 23 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a fourth modified example of the second embodiment of the present technology. The semiconductor package 200 in the fourth modified example of the second embodiment differs from the second embodiment in that a frame 362 and a ceramic interposer 364 are provided instead of the ceramic substrate 320. The configuration of the sensor chip 310 in the fourth modified example of the second embodiment is similar to that of the first modified example of the second embodiment.

[0108] With the light receiving side facing up, the lower surface of the sensor chip 310 is attached to the ceramic interposer 364 by an adhesive 344. In addition, the sensor chip 310 is connected to the ceramic interposer 364 by wires 331.

[0109] Furthermore, external terminals 365 such as lands are formed on the lower surface of the ceramic interposer 364. Vias and rewiring are formed in the ceramic interposer 364, and the wires 331 and the external terminals 365 are connected by them.

[0110] The upper surface of the ceramic interposer 364, around the sensor chip 310, is connected to the frame 362 by a sealant 363. The frame 362 is a member having a cone-shaped inner wall and a reference plane perpendicular to the Z-axis formed on the outer wall. The thick wavy line in the figure indicates the reference plane. This reference plane is attached to a camera module or the like. The upper surface of the frame 362 is connected to the glass 210 by a sealant 361.

[0111] As described above, according to the third modified example of the second embodiment of the present technology, since the sensor chip 310 is connected to the ceramic interposer 364 by the wires 331, it is not necessary to make vias penetrate the logic circuit 232, etc. This eliminates the need for vias to penetrate the logic circuit 232, etc., and makes it possible to suppress a decrease in yield caused by the characteristic fluctuation.

[0112] [Fifth Variation] In the above-described second embodiment, solder balls are provided as external terminals 253, but pads can be provided instead of solder balls. The semiconductor package 200 of the fifth modified example of the second embodiment differs from the second embodiment in that pads are provided as external terminals.

[0113] 24 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a fifth modified example of the second embodiment of the present technology. The semiconductor package 200 in the fifth modified example of the second embodiment of the present technology differs from the second embodiment in that pads are provided as external terminals 371 instead of external terminals 253 (solder balls).

[0114] In this manner, according to the fifth modification of the second embodiment of the present technology, since pads are provided instead of solder balls, wire bonding and the like can be performed.

[0115] [Sixth Variation] In the above-described second embodiment, the sensor chip 310 is connected to the ceramic substrate 320 by the output-side vias 255, but it is also possible to connect the sensor chip 310 to the ceramic substrate 320 by flip-chip connection. The semiconductor package 200 of the sixth modified example of the second embodiment differs from the second embodiment in that the sensor chip 310 is connected to the ceramic substrate 320 by flip-chip connection.

[0116] 25 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a sixth modified example of the second embodiment of the present technology. The semiconductor package 200 in the sixth modified example of the second embodiment differs from the second embodiment in that the sensor chip 310 is connected to the ceramic substrate 320 by bumps 381. The configuration of the sensor chip 310 in the sixth modified example of the second embodiment is similar to that of the first modified example of the second embodiment.

[0117] The ceramic substrate 320 covers the periphery of the pixel array portion on the upper surface of the sensor chip 310 and the side surfaces of the sensor chip 310 .

[0118] In this way, according to the sixth modified example of the second embodiment of the present technology, since the wiring layer 240 below the logic circuit 232 etc. is connected to the ceramic substrate 320 by the bump 381, it is not necessary to make vias penetrate the logic circuit 232 etc. This prevents the characteristics of the logic circuit 232 etc. from fluctuating due to the penetration of the vias, and it is possible to suppress a decrease in yield caused by the characteristic fluctuation.

[0119] <3. Third embodiment> In the above-described first embodiment, the logic circuit 232 and the memory 233 are provided below the solid-state imaging element 220, but a light-emitting element is required to realize a distance measurement function using a ToF (Time of Flight) method. The semiconductor package 200 of the third embodiment differs from the first embodiment in that a light-emitting element is provided.

[0120] 26 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to a third embodiment of the present technology. The semiconductor package 200 according to the third embodiment differs from the first embodiment in that a light emitting element 411 is further provided.

[0121] The light emitting element 411 emits light such as infrared light. For example, an LED (Light Emitting Diode) or a laser diode is used as the light emitting element 411. The light emitting element 411 is provided on the circuit layer 230.

[0122] Moreover, an opening 410 that penetrates from the upper surface (i.e., the light receiving surface) of the solid-state imaging element 220 to the light emitting element 411 along the Z direction with the light receiving side facing up is formed in the solid-state imaging element 220 and the circuit layer 230. The light emitting element 411 can emit light through this opening 410. The arrow in the figure indicates the emission direction of light from the light emitting element 411.

[0123] As illustrated in the figure, by embedding the light emitting element 411 in the circuit layer 230, the number of lead-out terminals from the sensor chip can be reduced. This contributes to reducing the size of the ToF module using the semiconductor package 200 and reducing the cost when an interposer is provided. Furthermore, by embedding the light emitting element 411 in the circuit layer 230, the distance between the light receiving element (solid-state imaging element 220) and the light emitting element 411 can be reduced in the X-axis direction and the Y-axis direction. This improves the distance measurement accuracy.

[0124] Although the light emitting element 411 is embedded, it is also possible to embed elements other than the light emitting element 411. For example, it is also possible to embed a temperature sensor, a humidity sensor, or an air pressure sensor. By embedding these sensors, the circuitry within the semiconductor package (such as the logic circuit 232) and the external circuitry can detect the presence or absence of an abnormality within the semiconductor package 200 and feed back the information to the drive of the sensor.

[0125] The light emitting element 411 is an example of an embedded element as defined in the claims.

[0126] FIG. 27 is a cross-sectional view illustrating a schematic configuration of a semiconductor package 200 according to the third embodiment of the present technology.

[0127] The logic circuit 232 controls the light emitting element 411 to irradiate the object with the irradiation light. The solid-state imaging element 220 receives reflected light of the irradiation light, and the logic circuit 232 measures the distance to the object by the ToF method. The logic circuit 232 outputs the measurement data to the outside via the external terminal 253. Note that instead of the logic circuit 232, a control circuit outside the semiconductor package 200 can also control the light emitting operation of the light emitting element 411.

[0128] 28 is a diagram for explaining a process up to thinning the logic circuit 232 etc. in the third embodiment of the present technology. In the figure, "a" is a diagram for explaining a process of forming the solid-state imaging element 220. In the figure, "b" is a diagram for explaining a process of connecting the logic circuit 232 etc. In the figure, "c" is a diagram for explaining a process up to thinning the logic circuit 232 etc.

[0129] As shown in FIG. 1A, the manufacturing system forms a solid-state imaging element 220 for each chip area on a wafer divided into a plurality of chip areas. Then, as shown in FIG. 1B, the manufacturing system connects a logic circuit 232, a memory 233, and a light-emitting element 411 to the solid-state imaging element 220 by Cu-Cu bonding or the like. Next, as shown in FIG. 1C, the manufacturing system thins the logic circuit 232 and the like as necessary.

[0130] 29 is a diagram for explaining the process up to the step of connecting the support substrate 250 in the third embodiment of the present technology. In the figure, "a" is a diagram for explaining the step of embedding the logic circuit 232 and the like in the insulating film. In the figure, "b" is a diagram for explaining the step of planarizing the circuit layer 230. In the figure, "c" is a diagram for explaining the step of connecting the support substrate 250.

[0131] As shown in FIG. 1A, the manufacturing system forms a circuit layer 230 by embedding logic circuits 232 and the like in an insulating film. Then, as shown in FIG. 1B, the manufacturing system flattens the circuit layer 230. Next, as shown in FIG. 1C, the manufacturing system places the circuit layer 230 face down and connects the circuit layer 230 to a wafer-like support substrate 250 by Cu-Cu bonding or the like.

[0132] 30 is a diagram for explaining a process of forming an opening 410 in the third embodiment of the present technology. As illustrated in the figure, the manufacturing system forms an opening 410 penetrating to a light emitting element 411. The manufacturing system also forms a plurality of pixels 221 in the solid-state imaging element 220, and forms a color filter (not shown) and an on-chip lens 222 for each pixel 221.

[0133] Thereafter, the manufacturing system forms output side vias 251 and 254, rewiring 252, and external terminals 253 in the support substrate 250. The manufacturing system also forms a resin dam 261, seals the solid-state imaging element 220 with glass 210, and performs dicing.

[0134] Thus, according to the third embodiment of the present technology, the light-emitting element 411 is embedded in the circuit layer 230 within the semiconductor module 200, so that the size of the ToF module can be reduced compared to when the light-emitting element 411 is disposed outside the semiconductor module 200.

[0135] [First Modification] As described above, in the third embodiment, the sensor chip 310 is connected to the support substrate 250 by the output side vias 255, but it is also possible to connect the sensor chip 310 to the framed substrate by wires. The semiconductor package 200 of the first modified example of the third embodiment differs from the third embodiment in that the sensor chip 310 is connected to the framed substrate by wires.

[0136] 31 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a first modified example of the third embodiment of the present technology. The semiconductor package 200 in the first modified example of the third embodiment differs from the third embodiment in that a framed substrate 421 is further provided.

[0137] The framed substrate 421 is a substrate having a frame formed around its periphery. The sensor chip 310 is provided on the bottom surface of the framed substrate 421. The glass 210 is connected to the frame portion of the framed substrate 421.

[0138] The sensor chip 310 is a chip in which, from the top, the solid-state imaging element 220, the circuit layer 230, the wiring layer 240, and the support substrate 250 are laminated, with the light receiving side facing up. The configuration of each layer is the same as in the first embodiment. However, the sensor chip 310 is connected to the framed substrate 421 by a wire 331.

[0139] 32 is a cross-sectional view showing a schematic configuration of a sensor chip 310 in a first modified example of the third embodiment of the present technology. As shown in the figure, the output side via 255 is not formed in the support substrate 250. Therefore, the via does not penetrate the logic circuit 232, etc., and the characteristics of the logic circuit 232, etc. do not fluctuate due to the penetration of the via. Therefore, it is possible to suppress a decrease in yield caused by the characteristic fluctuation.

[0140] In this way, according to the first modified example of the third embodiment of the present technology, since the sensor chip 310 is wire-bonded to the framed substrate 421, it is not necessary to make vias penetrate the logic circuit 232, etc. This eliminates the need to make the characteristics of the logic circuit 232, etc. fluctuate due to the penetration of the vias, and it is possible to suppress a decrease in yield caused by the characteristic fluctuation.

[0141] [Second modified example] In the above-described third embodiment, the light emitting element 411 is provided in the semiconductor package 200 manufactured at the wafer level, but the light emitting element 411 may also be provided in a ceramic package mounted on a ceramic substrate. The semiconductor package 200 of the second modification of the third embodiment differs from the third embodiment in that it is a ceramic package.

[0142] 33 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a second modified example of the third embodiment of the present technology. The semiconductor package 200 in the second modified example of the third embodiment differs from the third embodiment in that a ceramic substrate 431 is further provided.

[0143] A space is provided in the ceramic substrate 431, and the sensor chip 310 is provided in the space. The space is sealed by glass 210. The configuration of the sensor chip 310 in the second modified example of the third embodiment is similar to that in the first modified example of the third embodiment. In the second modified example of the third embodiment, the wiring layer 240 in the sensor chip 310 is connected to the ceramic substrate 431 by the wire 331, similar to the first modified example of the third embodiment.

[0144] In this manner, according to the second modification of the third embodiment of the present technology, the light emitting element 411 is provided in the sensor chip 310 in the ceramic substrate 431, so that the size of the ToF module using a ceramic package can be reduced.

[0145] [Third modified example] In the above-described third embodiment, the circuit layer 230 is disposed between the solid-state imaging element 220 and the wiring layer 240, but the wiring layer 240 can also be disposed between the solid-state imaging element 220 and the circuit layer 230. The semiconductor package 200 of the third modified example of the third embodiment differs from the third embodiment in that the wiring layer 240 is disposed between the solid-state imaging element 220 and the circuit layer 230.

[0146] 34 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a third modified example of the third embodiment of the present technology. The semiconductor package 200 in the third modified example of the third embodiment differs from the third embodiment in that a wiring layer 240 is disposed between a solid-state imaging element 220 and a circuit layer 230. In this configuration, an output-side via 251 is formed penetrating the support substrate 250 and the circuit layer 230.

[0147] 35 is a cross-sectional view showing a schematic configuration of a semiconductor package according to a third modified example of the third embodiment of the present technology. As shown in the figure, an opening 410 is formed penetrating the solid-state imaging element 220 and the wiring layer 240 to the light-emitting element 411.

[0148] Thus, according to the third variant of the third embodiment of the present technology, the wiring layer 240 is disposed between the solid-state imaging element 220 and the circuit layer 230, so that irradiation light can be irradiated through the opening 410 penetrating the solid-state imaging element 220 and the wiring layer 240.

[0149] <4. Fourth embodiment> In the above-described first embodiment, the logic circuit 232 and the memory 233 are provided below the solid-state imaging element 220, but a light-emitting element is required to realize a distance measurement function using a ToF (Time of Flight) method. The semiconductor package 200 of the fourth embodiment differs from the first embodiment in that a light-emitting element is provided.

[0150] 36 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to a fourth embodiment of the present technology. The semiconductor package 200 according to the fourth embodiment further includes a frame 510, LEDs 521 and 522, and a package substrate 550. Also, a support substrate 540 with a wiring layer is provided in place of the wiring layer 240 and the support substrate 250.

[0151] With the light receiving side facing up, a frame 510 is provided around the periphery of the upper surface of the package substrate 550. Glass 210 is bonded to the upper part of the frame 510. Furthermore, on the upper surface of the package substrate 550, a solid-state imaging element 220, a circuit layer 230, and a support substrate 540 with a wiring layer are laminated in this order from the top. As the package substrate 550, for example, a ceramic substrate, an organic substrate, or a flexible substrate is used.

[0152] The support substrate with wiring layer 540 is a support substrate having a wiring layer formed on the upper part thereof. The area of ​​the support substrate with wiring layer 540 is larger than the solid-state imaging element 220 and the circuit layer 230. Therefore, a space is generated around the support substrate with wiring layer 540. Elements and components such as LEDs 521 and 522 are disposed in this space. The LEDs 521 and 522 are connected to the support substrate with wiring layer 540 by wires 531, and the support substrate with wiring layer 540 is connected to the package substrate 550 by wires 532.

[0153] The LEDs 521 and 522 are light-emitting elements that emit light such as infrared light. The arrows in the figure indicate the direction of light irradiation from the LEDs 521, etc. Although the LEDs 521 and 522 are arranged on the wiring layer 240, elements and components other than the LEDs 521, etc. may also be arranged.

[0154] As illustrated in the figure, by providing the LED 521 and the like in the semiconductor package 200, it is possible to reduce the size of the ToF module using the semiconductor package 200. Also, the distance between the light receiving element (solid-state imaging element 220) and the light emitting element 411 can be reduced in the X-axis direction and the Y-axis direction. This improves the distance measurement accuracy.

[0155] FIG. 37 is a cross-sectional view illustrating a schematic configuration of a semiconductor package according to the fourth embodiment of the present technology.

[0156] The logic circuit 232 controls the LED 521 and the like to irradiate the object with irradiation light. The solid-state imaging element 220 receives reflected light of the irradiated light, and the logic circuit 232 measures the distance to the object by the ToF method. The logic circuit 232 outputs the measurement data to the outside via the wire 532. Note that instead of the logic circuit 232, a control circuit outside the semiconductor package 200 can also control the light emitting operation of the LED 521 and the like.

[0157] 38 is a diagram for explaining a process up to thinning the logic circuit 232 etc. in the fourth embodiment of the present technology. In the figure, "a" is a diagram for explaining a process of forming the solid-state imaging element 220. In the figure, "b" is a diagram for explaining a process of connecting the logic circuit 232 etc. In the figure, "c" is a diagram for explaining a process up to thinning the logic circuit 232 etc.

[0158] As shown in FIG. 1A, the manufacturing system forms a solid-state imaging element 220 for each chip area on a wafer divided into a plurality of chip areas. Then, as shown in FIG. 1B, the manufacturing system connects a logic circuit 232 and a memory 233 to the solid-state imaging element 220 by Cu-Cu bonding or the like. Next, as shown in FIG. 1C, the manufacturing system thins the logic circuit 232 and the like as necessary.

[0159] 39 is a diagram for explaining the process up to forming the wiring layer 240 in the fourth embodiment of the present technology. In the figure, "a" is a diagram for explaining the process of embedding the logic circuit 232 and the like in the insulating film. In the figure, "b" is a diagram for explaining the process of planarizing the circuit layer. In the figure, "c" is a diagram for explaining the process of forming the wiring layer.

[0160] As shown in FIG. 1A, the manufacturing system forms a circuit layer 230 by embedding logic circuit 232 and the like with an insulating film. Then, as shown in FIG. 1B, the manufacturing system flattens circuit layer 230. Next, as shown in FIG. 1C, the manufacturing system forms a wiring layer on the upper part of the support substrate to form support substrate 540 with a wiring layer.

[0161] 40 is a diagram for explaining the process up to forming a color filter and an on-chip lens in the fourth embodiment of the present technology. In the figure, a is a diagram for explaining the process of connecting a support substrate 540 with a wiring layer. In the figure, b is a diagram for explaining the process of opening up to the support substrate 540 with a wiring layer. In the figure, c is a diagram for explaining the process up to forming a color filter and an on-chip lens.

[0162] As illustrated in FIG. 13A, the manufacturing system connects the solid-state imaging element 220 and the circuit layer 230 to the support substrate 540 with the wiring layer by Cu-Cu bonding. Then, as illustrated in FIG. 13B, the periphery of the central portion of the solid-state imaging element 220 and the circuit layer 230 where the circuit is formed is opened up to the support substrate 540 with the wiring layer. Next, as illustrated in FIG. 13C, the manufacturing system forms a plurality of pixels 221 in the solid-state imaging element 220, and forms a color filter (not shown) and an on-chip lens 222 for each pixel 221.

[0163] 41 is a diagram for explaining a process up to wire bonding in the fourth embodiment of the present technology. In the diagram, "a" is a diagram for explaining a process for forming LEDs 521 and 522. In the diagram, "b" is a diagram for explaining the wire bonding process.

[0164] As illustrated in FIG. 13A, the manufacturing system forms LEDs 521 and 522 around the solid-state imaging element 220 and the circuit layer 230 on the upper surface of the support substrate 540 with the wiring layer. Then, as illustrated in FIG. 13B, the manufacturing system connects the LEDs 521 and the like to the support substrate 540 with the wiring layer by wires 531, and connects the support substrate 540 with the wiring layer by wires 532.

[0165] The manufacturing system then forms a frame 510 around the periphery of the upper surface of the package substrate 550, bonds glass 210 to the top of the frame 510, and performs dicing.

[0166] As described above, according to the fourth embodiment of the present technology, since the LED 521 and the like are provided on the support substrate 540 with a wiring layer in the semiconductor package 200, the size of the ToF module can be reduced and the distance measurement accuracy can be improved.

[0167] [First Modification] In the above-described fourth embodiment, the LED 521 and the like are provided on the support substrate 540 with the wiring layer, but a laser diode can be provided instead of the LED 521 and the like. The semiconductor package 200 of the first modified example of the fourth embodiment differs from the fourth embodiment in that a laser diode is provided on the support substrate 540 with the wiring layer.

[0168] 42 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a first modified example of the fourth embodiment of the present technology. The semiconductor package 200 in the first modified example of the fourth embodiment differs from the fourth embodiment in that laser diodes 523 and 524 are provided instead of LEDs 521 and 522.

[0169] In this way, according to the fourth embodiment of the present technology, the laser diode 523 and the like are provided on the support substrate 540 with a wiring layer within the semiconductor package 200, so that the size of the ToF module can be reduced and the distance measurement accuracy can be improved.

[0170] [Second modified example] In the above-described fourth embodiment, the LEDs 521 and the like are provided on the support substrate 540 with the wiring layer, but circuits and components other than the LEDs can also be added. The semiconductor package 200 of the first modified example of the fourth embodiment differs from the fourth embodiment in that additional circuits and components are provided on the support substrate 540 with the wiring layer.

[0171] 43 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a second modified example of the fourth embodiment of the present technology. The semiconductor package 200 in the second modified example of the fourth embodiment differs from the fourth embodiment in that a logic circuit 525 and an active component 526 are provided instead of the LEDs 521 and 522.

[0172] It is possible to mount components that cannot withstand high-temperature wafer processing as the logic circuit 525 and active components 526. By adding the logic circuit 525 and the like, the functionality of the semiconductor package 200 can be improved.

[0173] An additional memory may be arranged in place of the logic circuit 525. For example, a hybrid memory cube (HMC) may be used as the memory. Also, instead of the active component 526, a passive component may be arranged.

[0174] The LED 521, the LED 522, the laser diode 523, the laser diode 524, the logic circuit 525, and the active component 526 are examples of additional circuits defined in the claims.

[0175] Furthermore, there is no limitation on the method of connecting these additional circuits to the wiring layer-attached support substrate 540. For example, the additional circuits can be connected by solder connection, conductive wire connection, or connection using a conductive material.

[0176] 44 is a diagram for explaining a process up to wire bonding in the second modified example of the fourth embodiment of the present technology. In the diagram, "a" is a diagram for explaining a process for forming a logic circuit 525 and an active component 526. In the diagram, "b" is a diagram for explaining the wire bonding process.

[0177] 38 to 40 are performed in the second modified example of the fourth embodiment as in the fourth embodiment. Then, as illustrated in FIG. 44A, the manufacturing system forms a logic circuit 525 and active components 526 around the solid-state imaging element 220 and the circuit layer 230 on the upper surface of the support substrate 540 with the wiring layer. Then, as illustrated in FIG. 44B, the manufacturing system connects the support substrate 540 with the wiring layer to the package substrate 550 by wires 532.

[0178] In this manner, according to the second modified example of the fourth embodiment of the present technology, the additional logic circuit 525 and active components 526 are provided on the support substrate 540 with the wiring layer, thereby improving the functionality of the semiconductor package 200.

[0179] [Third modified example] In the second modification of the fourth embodiment described above, logic circuit 525 and active components 526 are formed, and supporting substrate 540 with wiring layer is connected by wires 532, but from the viewpoint of reliability and ease of handling, it is desirable to seal these with resin. Semiconductor package 200 of the third modification of the fourth embodiment differs from the second modification of the fourth embodiment in that logic circuit 525 and the like and wires 532 are embedded in sealing resin.

[0180] 45 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a third modified example of the fourth embodiment of the present technology. The semiconductor package 200 in the third modified example of the fourth embodiment differs from the second modified example of the fourth embodiment in that a logic circuit 525, an active component 526, and wires 532 are embedded in a sealing resin 560. This can improve the reliability of the semiconductor package 200 and facilitate its handling.

[0181] In this manner, according to the third modified example of the fourth embodiment of the present technology, the logic circuit 525 and the like are embedded in the sealing resin 560, thereby improving the reliability of the semiconductor package 200 and making it easier to handle.

[0182] [Fourth Variation] In the second modified example of the fourth embodiment described above, glass 210 is disposed above the light receiving surface of solid-state imaging element 220, but transparent resin may be provided instead of glass 210. Semiconductor package 200 of the fourth modified example of the fourth embodiment differs from the second modified example of the fourth embodiment in that the light receiving surface of solid-state imaging element 220 is protected by transparent resin.

[0183] 46 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a fourth modified example of the fourth embodiment of the present technology. The semiconductor package 200 in the fourth modified example of the fourth embodiment differs from the second modified example of the fourth embodiment in that a transparent resin 570 is formed instead of the frame 510 and the glass 210.

[0184] Transparent resin 570 is a transparent resin that protects the light receiving surface of solid-state imaging element 220. By protecting the light receiving surface with transparent resin 570, the size in the Z-axis direction (i.e., thickness) of semiconductor package 200 can be made smaller than in the case where glass 210 is provided.

[0185] In this way, according to the fourth modification of the fourth embodiment of the present technology, the light receiving surface of the solid-state imaging element 220 is protected by the transparent resin 570, so that the thickness of the semiconductor package 200 can be made smaller.

[0186] [Fifth Variation] In the second modification of the fourth embodiment described above, glass 210 is disposed above solid-state imaging element 220 via frame 510, but glass can also be disposed via ribs. Semiconductor package 200 of the fifth modification of the fourth embodiment differs from the second modification of the fourth embodiment in that ribs and glass are provided.

[0187] 47 is a cross-sectional view showing a configuration example of a semiconductor package 200 in a fifth modified example of the fourth embodiment of the present technology. The semiconductor package 200 in the fifth modified example of the fourth embodiment differs from the second modified example of the fourth embodiment in that a rib 581 and an AR (Anti Reflection) coated seal glass 580 are provided instead of the frame 510 and the glass 210.

[0188] The rib 581 is attached to the sealing resin 560. In addition, the AR coated seal glass 580 is connected to the sealing resin 560 via the rib 581. The AR coated seal glass 580 protects the light receiving surface of the solid-state imaging element 220.

[0189] The AR coated seal glass 580 is an example of the glass described in the claims.

[0190] In this manner, according to the fifth modified example of the fourth embodiment of the present technology, the AR coated seal glass 580 is connected to the sealing resin 560 via the rib 581, so that the light receiving surface of the solid-state imaging element 220 can be protected.

[0191] <Applications to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0192] FIG. 48 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology of the present disclosure can be applied.

[0193] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 48, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0194] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0195] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0196] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0197] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0198] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0199] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0200] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0201] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0202] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 48, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0203] FIG. 49 is a diagram showing an example of the installation position of the imaging unit 12031.

[0204] In FIG. 49, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0205] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0206] 49 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0207] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0208] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0209] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0210] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0211] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the semiconductor package 200 in FIG. 2 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to improve the yield and reduce the cost of the system.

[0212] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology.

[0213] The processing procedures described in the above embodiments may be regarded as a method having a series of these procedures, or as a program for causing a computer to execute the series of procedures or a recording medium for storing the program. For example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray (registered trademark) Disc, etc. may be used as this recording medium.

[0214] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0215] The present technology can also be configured as follows. (1) a solid-state imaging element for generating image data; a circuit layer in which a signal processing circuit that performs a predetermined signal processing on the image data is disposed; a support substrate through which an output side via, one end of which is connected to an external terminal, penetrates; a wiring layer disposed between the support substrate and the circuit layer, on which a signal line is wired to connect the signal processing circuit and the other end of the output side via; A semiconductor package comprising: (2) Glass; a resin dam formed between the glass and a periphery of a pixel array portion of the light receiving surface of the solid-state imaging device; The semiconductor package according to (1) above, further comprising: (3) Glass; a transparent resin embedded between the solid-state imaging element and the glass; The semiconductor package according to (1) above, further comprising: (4) The output side vias are arranged in an area of ​​the surface of the support substrate that corresponds to the signal processing circuit and an area that does not correspond to the signal processing circuit. A semiconductor package according to any one of (1) to (3). (5) Further comprising a ceramic substrate; The output side via penetrates the support substrate and the ceramic substrate. The semiconductor package according to (1) above. (6) an embedded element is further disposed on the circuit layer; An opening is formed in the solid-state imaging element and the circuit layer, the opening penetrating from the light receiving surface of the solid-state imaging element to the embedded element. The semiconductor package according to (1) above. (7) a solid-state imaging element that generates image data and inputs the image data to one end of an input-side via; a wiring layer in which a signal line is wired to connect a signal processing circuit that performs a predetermined signal processing on the image data to the other end of the input side via; a circuit layer disposed between the solid-state imaging element and the wiring layer, the circuit layer including the input via and the signal processing circuit; A semiconductor package comprising: (8) Further comprising a ceramic substrate through which an output side via penetrates, one end of which is connected to an external terminal. The semiconductor package according to (7) above. (9) The ceramic substrate and the wiring layer are connected by wires. The semiconductor package according to (8) above. (10) The ceramic substrate and the wiring layer are connected by bumps. The semiconductor package according to (8) above. (11) Glass and a spacer resin formed between a periphery of a pixel array portion of the solid-state imaging device and the glass; An interposer, The interposer and the wiring layer are connected by wires. The semiconductor package according to (7) above. (12) Further comprising a rewiring layer on which signal lines for connecting the bonding bumps and the external terminals are wired, The wiring layer is connected to the rewiring layer by the bump. The semiconductor package according to (7) above. (13) A frame; an interposer attached to the frame; The interposer and the wiring layer are connected by wires. The semiconductor package according to (7) above. (14) The circuit layer further includes an embedded element disposed thereon; An opening is formed in the solid-state imaging element and the circuit layer, the opening penetrating from the light receiving surface of the solid-state imaging element to the embedded element. The semiconductor package according to (7) above. (15) A framed substrate having a frame formed on its outer periphery is further provided. The wiring layer and the framed substrate are connected by wires. The semiconductor package according to (14) above. (16) A ceramic substrate is further provided, The ceramic substrate and the wiring layer are connected by wires. The semiconductor package according to (14) above. (17) Further comprising an additional circuit provided on the light receiving surface of the wiring layer. The semiconductor package according to (7) above. (18) The additional circuit is embedded in a sealing resin. The semiconductor package according to (17) above. (19) The solid-state imaging device further includes a transparent resin for protecting a light receiving surface of the solid-state imaging device. The semiconductor package according to (18) above. (20) Further comprising glass connected to the sealing resin via a rib. The semiconductor package according to (18) above. [Explanation of symbols]

[0216] 100 Electronic equipment 110 Optics Department 120 DSP (Digital Signal Processing) circuit 130 Display section 140 Operation section 150 Bus 160 Frame Memory 170 Storage section 180 Power supply section 200 Semiconductor Packages 210 Glass 220 Solid-state image sensor 221 pixels 222 On-chip lens 230 circuit layer 231, 234 Input side via 232, 525 logic circuits 233 Memory 240 wiring layer 241, 243, 244, 245 Pads 242 Signal Line 250 Support Board 251, 254, 255, 321 Output side via 252, 322, 351 rewiring 253, 365, 371 External terminals 261 Resin Dam 262 Cavity 263, 570 Transparent resin 310 Sensor Chip 320, 431 Ceramic substrate 331, 531, 532 Wires 341 Molding resin 342 Potting Resin 343 Spacer Resin 344 Adhesive 345 Interposer 352 Seal ring 353, 381 Bump 354 Redistribution layer 361, 363 Sealant 362, 510 frames 364 Ceramic Interposer 410 Opening 411 Light emitting element 421 Framed circuit board 521, 522 LEDs 523, 524 Laser diode 526 Active Components 540 Support substrate with wiring layer 550 Package Substrate 560 Sealing resin 580 AR coated sealed glass 581 Rib 12031 Imaging unit

Claims

1. a wiring layer forming step of forming, on a support substrate, a wiring layer on which signal lines are wired, the signal lines connecting a signal processing circuit that performs a predetermined signal processing on image data and an output side via having one end connected to an external terminal at the other end; a circuit layer forming step of forming a circuit layer in which the signal processing circuit is arranged on the wiring layer; a connection step of connecting a solid-state imaging element for generating the image data to the circuit layer; an output via forming step of forming the output side via so as to penetrate the support substrate; A method for manufacturing a semiconductor package comprising the steps of:

2. The method further includes a glass mounting step of forming a resin dam around a pixel array portion of the light receiving surface of the solid-state imaging device and mounting glass on the resin dam. The method for manufacturing the semiconductor package according to claim 1.

3. The output side vias are arranged in an area of ​​the surface of the support substrate that corresponds to the signal processing circuit and an area that does not correspond to the signal processing circuit. The method for manufacturing the semiconductor package according to claim 1.

4. forming an opening in the solid-state imaging element and the circuit layer, the opening penetrating from a light receiving surface of the solid-state imaging element to an embedded element; The embedded element is further disposed on the circuit layer, The opening forming step is performed between the connecting step and the output via forming step. The method for manufacturing the semiconductor package according to claim 1.

5. A wiring layer forming step of forming a wiring layer on a support substrate, the wiring layer having signal lines that connect a signal processing circuit that performs a predetermined signal processing on image data to the other end of the input side via; a circuit layer forming step of forming a circuit layer in which the input side via and the signal processing circuit are provided on the wiring layer; a connection step of connecting a solid-state image sensor for generating the image data to the circuit layer; A method for manufacturing a semiconductor package comprising the steps of:

6. a bonding step of bonding a sensor chip including the wiring layer, the support substrate, the circuit layer, and the solid-state imaging element to an interposer; a wire bonding step of connecting the interposer and the wiring layer with wires; a glass mounting step of forming a spacer resin around a pixel array portion of the solid-state imaging device and mounting glass on the spacer resin; The method for manufacturing a semiconductor package according to claim 5 , further comprising:

7. The method further comprises a frame bonding step of bonding the interposer to a frame. The method for manufacturing a semiconductor package according to claim 6.

8. The method further includes a bump connection step of connecting a rewiring layer, on which a signal line for connecting a bump to an external terminal is wired, to the wiring layer by the bump. The method for manufacturing a semiconductor package according to claim 5 .

9. forming an opening in the solid-state imaging element and the circuit layer, the opening penetrating from a light receiving surface of the solid-state imaging element to an embedded element; The embedded element is further disposed on the circuit layer, The opening forming step is performed after the connecting step. The method for manufacturing a semiconductor package according to claim 5.

10. The method further includes a wire bonding step of connecting the framed substrate having a frame formed on its outer periphery and the wiring layer by wires. The method for manufacturing a semiconductor package according to claim 9.

11. The method further includes a wire bonding step of connecting the ceramic substrate and the wiring layer with wires. The method for manufacturing a semiconductor package according to claim 9.

12. The method further includes the step of forming an additional circuit on the light receiving surface of the wiring layer. The method for manufacturing a semiconductor package according to claim 5.

13. The method further includes the step of embedding the additional circuit in a sealing resin. The method for manufacturing a semiconductor package according to claim 12.

14. The method further includes a transparent resin forming step of forming a transparent resin for protecting a light receiving surface of the solid-state imaging element. The method for manufacturing a semiconductor package according to claim 13.

15. The method further includes a glass connection step of connecting glass to the sealing resin via a rib. The method for manufacturing a semiconductor package according to claim 13.

Images