Sensor device, distance measuring device

Abstract

The sensor device according to the present invention comprises: a first chip that has a first semiconductor substrate and a first wire forming layer, and has a pixel configured to include a photoelectric conversion element, and a first transfer gate element and a second transfer gate element for transferring stored charge of the photoelectric conversion element; and a second chip that has a second semiconductor substrate and a second wire forming layer. The sensor device also has a first wire electrically connected to the first transfer gate element, a second wire electrically connected to the second transfer gate element, and a third wire electrically connected to ground, wherein each of the first wire, second wire, and third wire is formed by bonding a first portion which is formed on the first wire forming layer and extends in a first direction to a second portion which is formed on the second wire forming layer and extends in the first direction. Selected drawing: FIG. 10

Description

[Technical field]

[0001] The present technology relates to a sensor device having a pixel including a photoelectric conversion element and a first transfer gate element and a second transfer gate element for transferring accumulated charge in the photoelectric conversion element, and a distance measuring device having the sensor device and measuring the distance to an object, and in particular to a wiring technology in the sensor device. [Background technology]

[0002] Various distance measurement techniques for measuring the distance to an object are known, and in recent years, distance measurement techniques using the ToF (Time of Flight) method, for example, have been attracting attention. ToF methods are broadly divided into direct ToF and indirect ToF. The direct ToF method is a method for calculating distance based on the results of measuring the round-trip time of light irradiated to an object using a time measurement device such as a TDC (Time-to-Digital Converter). On the other hand, the indirect ToF method is a method for calculating distance based on the amount of light reflected from the object, without measuring the round-trip time of light as described above.

[0003] In a sensor device used in the indirect ToF method, the reflected light from the target is photoelectrically converted by a photoelectric conversion element such as a photodiode. The signal charge obtained by this photoelectric conversion is distributed to two floating diffusions by a pair of transfer gate elements that are alternately turned on. In the indirect ToF method, the above-mentioned charge allocation is repeated a predetermined number of times, such as several thousand times, during a specified light receiving period, and the distance is calculated based on the difference between the signal charges accumulated in the two floating diffusions as a result.

[0004] As a related prior art, the following Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2009-8537 A Summary of the Invention [Problem to be solved by the invention]

[0006] Here, in a sensor device in which charge is distributed to two floating diffusions by two transfer gate elements provided for a photoelectric conversion element, such as a sensor device used in the indirect ToF method described above, if the two transfer gate elements do not operate accurately, charge will not be distributed appropriately to each floating diffusion, resulting in a deterioration in distance measurement performance.

[0007] The present technology has been made in consideration of the above circumstances, and aims to improve the operation accuracy and distance measurement performance of a sensor device used for distance measurement using, for example, an indirect ToF method. [Means for solving the problem]

[0008] The sensor device according to the present technology includes a first chip having a first semiconductor substrate and a first wiring formation layer, and having a pixel configured to include a photoelectric conversion element and a first transfer gate element and a second transfer gate element for transferring accumulated charge of the photoelectric conversion element, and a second chip having a second semiconductor substrate and a second wiring formation layer, in which a first wiring electrically connected to the first transfer gate element, a second wiring electrically connected to the second transfer gate element, and a third wiring electrically connected to ground are formed, and each of the first wiring, the second wiring, and the third wiring is formed by joining a first portion formed in the first wiring formation layer and extending in a first direction to a second portion formed in the second wiring formation layer and extending in the first direction. According to the above configuration, the first wiring for the first transfer gate element, the second wiring for the second transfer gate element, and the third wiring as a ground wiring are all formed as inter-chip joining wiring for joining the first chip and the second chip. That is, the first wiring, the second wiring, and the third wiring are formed of the same type of wiring as inter-chip joining wiring, so that it is possible to make the wiring resistances equal.

[0009] The sensor device according to the present technology described above may be configured as a distance measurement sensor using an indirect ToF method. The indirect ToF method employs a technique in which the accumulated charge of a photoelectric conversion element is distributed to two floating diffusions by first and second transfer gate elements.

[0010] In the sensor device according to the present technology described above, it is considered that the first wiring, the second wiring, and the third wiring are each configured such that the first portion and the second portion are connected by Cu-Cu. Cu-Cu connections are suitable as a connection technology between chips in terms of track record and reliability.

[0011] In the sensor device according to the present technology described above, it is considered that the first wiring and the second wiring are configured to be arranged symmetrically with the photoelectric conversion element therebetween. This makes it possible to make the wiring lengths of the first intermediate wiring, which is the wiring connecting the first transfer gate element and the first wiring, and the second intermediate wiring, which is the wiring connecting the second transfer gate element and the second wiring, equal, and therefore makes it possible to make the wiring resistances equal.

[0012] In the sensor device according to the present technology described above, it is possible to configure the first wiring, the second wiring, and the third wiring to have substantially the same wiring width. This makes it possible to make the wiring resistances of the first wiring, the second wiring, and the third wiring equal to each other.

[0013] In the sensor device according to the present technology described above, it is considered that the first wiring, the second wiring, and the third wiring may have substantially the same cross-sectional area. This makes it possible to make the wiring resistances of the first wiring, the second wiring, and the third wiring equal to each other.

[0014] In the sensor device related to the above-mentioned technology, it is possible to configure the sensor device such that at least a portion of the first wiring overlaps with the first transfer gate element, and at least a portion of the second wiring overlaps with the second transfer gate element, in a direction perpendicular to the stacking direction of the first chip and the second chip. This eliminates the need to route the first intermediate wiring, which is a wiring connecting the first wiring and the first transfer gate element, and the second intermediate wiring, which is a wiring connecting the second wiring and the second transfer gate element, in a direction perpendicular to the stacking direction, thereby making it possible to reduce the wiring resistance of both wirings and also to reduce the line capacitance between adjacent wirings.

[0015] In the sensor device related to the above-mentioned present technology, it is possible to configure the first wiring and the first transfer gate element, and the second wiring and the second transfer gate element to be connected by a connection portion consisting of one or more vias and extending approximately linearly in the stacking direction. As a result, the wiring lengths of the first intermediate wiring, which is a wiring connecting the first wiring and the first transfer gate element, and the second intermediate wiring, which is a wiring connecting the second wiring and the second transfer gate element, can be set to a length equivalent to the separation distance in the stacking direction between the first wiring and the first transfer gate element, and a length equivalent to the separation distance in the stacking direction between the second wiring and the second transfer gate element, making it possible to minimize the wiring resistance of the first and second intermediate wirings and the inter-line capacitance between adjacent wirings.

[0016] In the sensor device related to the above-mentioned present technology, it is possible to configure the distance between the first wiring and the third wiring adjacent to the first wiring, and the distance between the second wiring and the third wiring adjacent to the second wiring, to be approximately equal. This makes the line capacitance between the first wiring and the third wiring (parasitic capacitance acting on the first wiring) and the line capacitance between the second wiring and the third wiring (parasitic capacitance acting on the second wiring) approximately equal, preventing the dulling of the drive waveforms of the first and second transfer gate elements from becoming unbalanced, and enabling accurate distribution of charge to the two floating diffusions.

[0017] In the sensor device related to the above-mentioned technology, a wiring layer in which the first wiring, the second wiring, and the first portion of the third wiring are formed, and an intermediate wiring layer other than the wiring layer are formed in the first wiring formation layer, at least a portion of the third wiring overlaps with the pixel in a direction perpendicular to the stacking direction of the first chip and the second chip, and the third wiring is connected within the pixel to an intermediate ground wiring, which is a wiring formed in the intermediate wiring layer and connected to a ground within the pixel. This makes it possible to increase the cross-sectional area of ​​the third wiring (ground wiring).

[0018] In addition, a distance measuring device according to the present technology includes a light emitting unit that emits light to be irradiated onto an object, and a sensor unit that receives reflected light of the irradiated light from the object, the sensor unit including a first chip having a first semiconductor substrate and a first wiring forming layer, and having a pixel including a photoelectric conversion element and a first transfer gate element and a second transfer gate element for transferring an accumulated charge of the photoelectric conversion element, and a second chip having a second semiconductor substrate and a second wiring forming layer, in which a first wiring electrically connected to the first transfer gate element, a second wiring electrically connected to the second transfer gate element, and a third wiring electrically connected to ground are formed, and each of the first wiring, the second wiring, and the third wiring is formed by joining a first portion formed in the first wiring forming layer and extending in a first direction, and a second portion formed in the second wiring forming layer and extending in the first direction. With such a distance measuring device, the same effect as that of the sensor device according to the present technology described above can be obtained. [Brief description of the drawings]

[0019] [Figure 1] 1 is a block diagram for explaining a configuration example of a distance measuring device according to an embodiment of the present technology. [Diagram 2] 1 is a block diagram showing an example of an internal circuit configuration of a sensor device (sensor unit) according to an embodiment; [Diagram 3] 2 is an equivalent circuit diagram of a pixel included in the sensor device according to the embodiment; FIG. [Figure 4] FIG. 2 is a top view showing a schematic structure of a pixel in the embodiment. [Diagram 5] 1 is a cross-sectional view showing a schematic structure of a pixel in an embodiment. [Figure 6] 1 is a schematic cross-sectional view showing a chip structure of a sensor device according to an embodiment. [Figure 7] FIG. 1 is an explanatory diagram of bonding between chips by wiring. [Figure 8] 4 is an equivalent circuit diagram of a circuit system relating to driving of a transfer gate element. FIG. [Figure 9] 4A and 4B are diagrams showing waveform images of a transfer drive signal and a ground potential. [Figure 10] 1 is a cross-sectional view for explaining a method for bonding chips according to an embodiment; [Figure 11] 13 is a diagram showing an example of the layout of inter-chip connection wiring in a pixel array portion; FIG. [Figure 12] 12 is a diagram for explaining a schematic cross-sectional structure of a sensor portion corresponding to the wiring arrangement example shown in FIG. 11. [Figure 13] FIG. 13 is an explanatory diagram of a first modified example relating to the arrangement of inter-chip connecting wires. [Figure 14] FIG. 13 is an explanatory diagram of a second modified example relating to the arrangement of inter-chip connecting wires. [Figure 15] FIG. 13 is an explanatory diagram of a third modified example relating to the arrangement of inter-chip connecting wires. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, with reference to the accompanying drawings, embodiments of the present technology will be described in the following order. <1. Configuration of distance measuring device> <2. Circuit configuration of the sensor section> <3. Circuit configuration of pixel array section> <4. Structure of the sensor unit> <5. Chip-to-chip bonding as an embodiment> <6. Modifications Related to Arrangement of Inter-Chip Bonding Wiring> <7. Other variations> <8. Summary of the embodiment> <9. This Technology>

[0021] <1. Configuration of distance measuring device> FIG. 1 is a block diagram for explaining an example configuration of a distance measuring device 10 according to an embodiment of the present technology. The distance measuring device 10 includes a sensor unit 1, a light emitting unit 2, a control unit 3, a distance image processing unit 4, and a memory 5. The distance measuring device 10 is a device that performs distance measurement using a ToF (Time of Flight) method. Specifically, the distance measuring device 10 in this example performs distance measurement using an indirect ToF method. The indirect ToF method is a distance measuring method that calculates the distance to an object Ob based on the phase difference between light Li irradiated onto the object Ob and reflected light Lr obtained by reflecting the irradiated light Li from the object Ob.

[0022] The light emitting unit 2 has one or more light emitting elements as a light source, and emits irradiation light Li to the object Ob. In this example, the light emitting unit 2 emits infrared light having a wavelength in the range of 780 nm to 1000 nm as the irradiation light Li.

[0023] The control unit 3 controls the light emission operation of the light emitter 2 to emit the irradiation light Li. In the case of the indirect ToF method, the irradiation light Li is intensity-modulated light whose intensity changes at a predetermined cycle. Specifically, in this example, pulsed light is repeatedly emitted at a predetermined cycle as the irradiation light Li. Hereinafter, the emission cycle of such pulsed light is referred to as an "emission cycle Cl." In addition, the period between the emission start timings of pulsed light when the pulsed light is repeatedly emitted according to the emission cycle Cl is referred to as "one modulation period Pm" or simply as a "modulation period Pm." The control unit 3 controls the light emitting operation of the light emitting unit 2 so that the light emitting unit 2 emits the irradiation light Li only for a predetermined light emitting period in each modulation period Pm. Here, in the indirect ToF method, the light emission cycle Cl is set to a relatively high speed, for example, from several tens of MHz to several hundreds of MHz.

[0024] The sensor unit 1 receives the reflected light Lr and outputs distance measurement information by the indirect ToF method based on the phase difference between the reflected light Lr and the irradiated light Li. As will be described later, the sensor unit 1 in this example has a pixel array section 11 in which multiple pixels Px are arranged two-dimensionally, each pixel Px comprising a photoelectric conversion element (photodiode PD) and a first transfer gate element (transfer transistor TG-A) and a second transfer gate element (transfer transistor TG-B) for transferring the accumulated charge of the photoelectric conversion element, and distance measurement information is obtained for each pixel Px using the indirect ToF method. In the following, information that represents distance measurement information (distance information) for each pixel Px in this manner will be referred to as a "distance image."

[0025] Here, as is well known, in the indirect ToF method, the signal charge accumulated in the photoelectric conversion element in the pixel Px is distributed to two floating diffusions (FD) by a first transfer gate element and a second transfer gate element that are alternately turned on. At this time, the cycle in which the first transfer gate element and the second transfer gate element are alternately turned on is the same as the light emission cycle Cl of the light emitting section 2. In other words, the first transfer gate element and the second transfer gate element are each turned on once every modulation period Pm, and the above-mentioned distribution of the signal charge to the two floating diffusions is repeated every modulation period Pm. In this example, the transfer transistor TG-A as the first transfer gate element is turned on during the light emission period of the irradiation light Li in the modulation period Pm, and the transfer transistor TG-B as the second transfer gate element is turned on during the non-light emission period of the irradiation light Li in the modulation period Pm.

[0026] As described above, the light emission cycle Cl is relatively fast, so the amount of signal charge accumulated in each floating diffusion by one allocation using the first and second transfer gate elements as described above is relatively small. For this reason, in the indirect ToF method, the emission of the illumination light Li is repeated several thousand to tens of thousands of times per distance measurement (i.e., for obtaining one distance image), and while the illumination light Li is repeatedly emitted in this manner, the sensor unit 1 repeatedly allocates the signal charge to each floating diffusion using the first and second transfer gate elements as described above.

[0027] As can be understood from the above description, in the sensor unit 1, the first transfer gate element and the second transfer gate element are driven for each pixel Px at a timing synchronized with the light emission cycle of the irradiation light Li. For this reason, a synchronization signal Ss indicating a timing synchronized with the light emission cycle Cl is input from the control unit 3 to the sensor unit 1, and is used to drive the first and second transfer gate elements in each pixel Px.

[0028] The distance image processor 4 receives the distance image obtained by the sensor unit 1 , performs predetermined signal processing such as compression encoding, and outputs the result to the memory 5 . Memory 5 is a storage device such as a flash memory, a solid state drive (SSD), or a hard disk drive (HDD), and stores the distance image processed by distance image processor 4.

[0029] <2. Circuit configuration of the sensor section> FIG. 2 is a block diagram showing an example of the internal circuit configuration of the sensor unit 1. As shown in FIG. As shown in the figure, the sensor unit 1 includes a pixel array unit 11, a transfer gate driver 12, a vertical driver 13, a system controller 14, a column processor 15, a horizontal driver 16, a signal processor 17, and a data storage unit 18.

[0030] The pixel array unit 11 has a configuration in which a plurality of pixels Px are two-dimensionally arranged in a matrix in the row and column directions. Each pixel Px has a photodiode PD, which will be described later, as a photoelectric conversion element. The details of the pixels Px will be described later with reference to FIG. 3. Here, the row direction refers to the horizontal arrangement direction of the pixels Px, and the column direction refers to the vertical arrangement direction of the pixels Px. In the drawing, the row direction is the horizontal direction, and the column direction is the vertical direction. In this example, the formation pitch of the pixels Px in the pixel array section 11 is set to 5.0 μm or less. Specifically, in this example, the formation pitch of the pixels Px is set to about 3.5 μm.

[0031] In the pixel array unit 11, a pixel drive line 20 is wired in the row direction for each pixel row in the matrix-like pixel arrangement, and two gate drive lines 21 and two vertical signal lines 22 are wired in the column direction for each pixel column. For example, the pixel drive line 20 transmits a drive signal for driving when reading out a signal from the pixel Px. Note that, although FIG. 2 shows the pixel drive line 20 as one line, the number of lines is not limited to one. One end of the pixel drive line 20 is connected to an output terminal of the vertical drive unit 13 corresponding to each row.

[0032] The system control unit 14 is composed of a timing generator that generates various timing signals, and controls the driving of the transfer gate driving unit 12, the vertical driving unit 13, the column processing unit 15, and the horizontal driving unit 16, etc., based on the various timing signals generated by the timing generator.

[0033] The transfer gate driving section 12 drives the two transfer gate elements provided for each pixel Px through the gate driving lines 21, two of which are provided for each pixel column as described above, based on the control of the system control section 14. As described above, the two transfer gate elements are alternately turned on every modulation period Pm. Therefore, the system control unit 14 controls the on / off timing of the two transfer gate elements by the transfer gate driving unit 12 based on the synchronization signal Ss described in FIG.

[0034] The vertical driving unit 13 is composed of a shift register, an address decoder, etc., and drives the pixels Px of the pixel array unit 11 simultaneously for all pixels or in units of rows, etc. In other words, the vertical driving unit 13, together with a system control unit 14 that controls the vertical driving unit 13, constitutes a driving unit that controls the operation of each pixel Px of the pixel array unit 11.

[0035] A detection signal output (read) from each pixel Px in a pixel row in response to driving control by the vertical driving unit 13, specifically, a signal corresponding to the signal charge accumulated in each of two floating diffusions provided for each pixel Px, is input to the column processing unit 15 through the corresponding vertical signal line 22. The column processing unit 15 performs predetermined signal processing on the detection signal read from each pixel Px through the vertical signal line 22, and temporarily holds the detection signal after signal processing. Specifically, the column processing unit 15 performs noise removal processing, A / D (Analog to Digital) conversion processing, and the like as signal processing.

[0036] Here, the two detection signals (detection signals for each floating diffusion) from each pixel Px are read out once for every predetermined number of repeated emissions of the illumination light Li (every several thousand to tens of thousands of repeated emissions as mentioned above). Therefore, the system control unit 14 also controls the vertical drive unit 13 based on the synchronization signal Ss with respect to the read timing of the detection signal from each pixel Px.

[0037] The horizontal driving unit 16 is composed of a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 15. Through selective scanning by this horizontal driving unit 16, detection signals that have been signal-processed for each unit circuit in the column processing unit 15 are sequentially output.

[0038] The signal processing unit 17 has at least an arithmetic processing function, and performs various signal processing such as distance calculation processing corresponding to the indirect ToF method based on the detection signal output from the column processing unit 15. Note that a known method can be used for calculating distance information by the indirect ToF method based on two types of detection signals (detection signals for each floating diffusion) for each pixel Px, and the description thereof will be omitted here.

[0039] The data storage unit 18 temporarily stores data necessary for signal processing in the signal processing unit 17 .

[0040] The sensor unit 1 configured as above outputs a distance image representing the distance to an object Ob for each pixel Px. A distance measuring device 10 having such a sensor unit 1 can be applied to, for example, an in-vehicle system that is mounted on a vehicle and measures the distance to an object Ob outside the vehicle, or a gesture recognition device that measures the distance to an object such as a user's hand and recognizes the user's gesture based on the measurement result.

[0041] <3. Circuit configuration of pixel array section> FIG. 3 shows an equivalent circuit of the pixels Px arranged two-dimensionally in the pixel array section 11. Each pixel Px has one photodiode PD as a photoelectric conversion element and one OF (overflow) gate transistor OFG, and also has two transfer transistors TG, floating diffusions FD, reset transistors RST, amplifier transistors AMP, and selection transistors SEL as transfer gate elements.

[0042] Here, when distinguishing between the transfer transistors TG, floating diffusion FD, reset transistor RST, amplification transistor AMP, and selection transistor SEL, of which two are provided in each pixel Px, they will be referred to as transfer transistors TG-A and TG-B, floating diffusions FD-A and FD-B, reset transistors RST-A and RST-B, amplification transistors AMP-A and RST-B, and selection transistors SEL-A and SEL-B, as shown in Figure 3. The OF gate transistor OFG, the transfer transistor TG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are configured, for example, of N-type MOS transistors.

[0043] The OF gate transistor OFG is turned on when an OF gate signal SOFG supplied to the gate is turned on. When the OF gate transistor OFG is turned on, the photodiode PD is clamped to a predetermined reference potential VDD and the accumulated charge is reset. The OF gate signal SOFG is supplied from the vertical driver 13, for example.

[0044] The transfer transistor TG-A becomes conductive when a transfer drive signal STG-A supplied to its gate is turned on, and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD-A. The transfer transistor TG-B becomes conductive when a transfer drive signal STG-B supplied to its gate is turned on, and transfers the charge accumulated in the photodiode PD to the floating diffusion FD-B. The transfer drive signals STG-A and STG-B are supplied from the transfer gate driver 12 via gate drive lines 21-A and 21-B, which are provided as one of the gate drive lines 21 shown in FIG.

[0045] The floating diffusions FD-A and FD-B are charge holding units that temporarily hold the charges transferred from the photodiode PD.

[0046] The reset transistor RST-A becomes conductive when the reset signal SRST supplied to its gate is turned on, and resets the potential of the floating diffusion FD-A to the reference potential VDD. Similarly, the reset transistor RST-B becomes conductive when the reset signal SRST supplied to its gate is turned on, and resets the potential of the floating diffusion FD-B to the reference potential VDD. The reset signal SRST is supplied from the vertical drive unit 13, for example.

[0047] The amplifier transistor AMP-A has a source connected to the vertical signal line 22-A via the selection transistor SEL-A, and a drain connected to a reference potential VDD (constant current source) to form a source follower circuit. The amplifier transistor AMP-B has a source connected to the vertical signal line 22-B via the selection transistor SEL-B, and a drain connected to a reference potential VDD (constant current source) to form a source follower circuit. Here, the vertical signal lines 22-A and 22-B are each provided as one of the vertical signal lines 22 shown in FIG.

[0048] The selection transistor SEL-A is connected between the source of the amplification transistor AMP-A and the vertical signal line 22-A, and when the selection signal SSEL supplied to the gate is turned on, the selection transistor SEL-A becomes conductive and outputs the charge held in the floating diffusion FD-A to the vertical signal line 22-A via the amplification transistor AMP-A. The selection transistor SEL-B is connected between the source of the amplification transistor AMP-B and the vertical signal line 22-B, and when the selection signal SSEL supplied to the gate is turned on, it becomes conductive and outputs the charge held in the floating diffusion FD-B to the vertical signal line 22-B via the amplification transistor AMP-A. The selection signal SSEL is supplied from the vertical drive unit 13 via a pixel drive line 20.

[0049] The operation of the pixel Px will now be briefly described. First, before starting light reception, a reset operation is performed on all pixels to reset the charges of the pixels Px. That is, for example, the OF gate transistor OFG, each reset transistor RST, and each transfer transistor TG are turned on (conductive state), and the accumulated charges of the photodiode PD and each floating diffusion FD are reset.

[0050] After the accumulated charge is reset, the light receiving operation for distance measurement is started in all pixels. The light receiving operation here means the light receiving operation performed for one distance measurement. In other words, during the light receiving operation, the operation of alternately turning on the transfer transistors TG-A and TG-B is repeated a predetermined number of times (several thousand to several tens of thousands of times in this example). Hereinafter, the period of the light receiving operation performed for one distance measurement is referred to as the "light receiving period Pr."

[0051] In the light-receiving period Pr, within one modulation period Pm of the light-emitting unit 2, for example, a period during which the transfer transistor TG-A is on (i.e., a period during which the transfer transistor TG-B is off) continues throughout the light-emitting period of the irradiated light Li, and then the remaining period, i.e., the non-light-emitting period of the irradiated light Li, is a period during which the transfer transistor TG-B is on (i.e., a period during which the transfer transistor TG-A is off). That is, in the light-receiving period Pr, an operation of distributing the charge of the photodiode PD between the floating diffusions FD-A and FD-B is repeated a predetermined number of times within one modulation period Pm.

[0052] Then, when the light receiving period Pr ends, each pixel Px of the pixel array unit 11 is selected line-sequentially. In the selected pixel Px, the selection transistors SEL-A and SEL-B are turned on. As a result, the charge accumulated in the floating diffusion FD-A is output to the column processing unit 15 via the vertical signal line 22-A. Also, the charge accumulated in the floating diffusion FD-B is output to the column processing unit 15 via the vertical signal line 22-B.

[0053] With the above, one light receiving operation is completed, and the next light receiving operation is executed, starting from a reset operation.

[0054] Here, the reflected light received by pixel Px is delayed according to the distance to object Ob from the timing when light-emitting unit 2 emits irradiation light Li. Since the distribution ratio of the charges accumulated in two floating diffusions FD-A and FD-B changes depending on the delay time according to the distance to object Ob, the distance to object Ob can be obtained from the distribution ratio of the charges accumulated in these two floating diffusions FD-1 and FD-B.

[0055] <4. Structure of the sensor unit> The structure of the sensor unit 1 will be described with reference to FIGS. Figures 4 and 5 are diagrams illustrating the schematic structure of a pixel Px, specifically, diagrams illustrating the positional relationship of a photodiode PD, OF gate transistor OFG, transfer transistors TG-A, TG-B, and floating diffusions FD-A, FD-B formed in the region of one pixel Px on a semiconductor substrate, with Figure 4 being a top view and Figure 5 being a cross-sectional view taken at position X-X' shown in Figure 4. Note that pixel transistors such as the reset transistor RST and the amplification transistor AMP are omitted from Figures 4 and 5.

[0056] The photodiode PD is formed inside the semiconductor substrate, has a substantially rectangular shape when viewed from above, and is formed substantially in the center of the plane of the pixel Px. Here, "in-plane" means a plane parallel to the horizontal direction (row direction) and vertical direction (column direction) described above. Note that the horizontal direction corresponds to the lateral direction of the paper in Figs. 4 and 5. The vertical direction corresponds to the longitudinal direction of the paper in Fig. 4.

[0057] The transfer transistors TG-A and TG-B are formed on a semiconductor substrate and have a substantially rectangular shape in top view. The positions of the transfer transistors TG-A and TG-B in the plane are near one of the corresponding ends of the photodiode PD in the horizontal or vertical direction. Specifically, in this example, the positions of the transfer transistors TG-A and TG-B in the plane are such that they partially overlap one of the corresponding ends of the photodiode PD in the horizontal direction (the lateral direction on the paper). The positions of the transfer transistors TG-A and TG-B in the vertical direction are substantially the same.

[0058] The floating diffusions FD-A and FD-B are formed inside the semiconductor substrate and have a substantially rectangular shape in top view. The floating diffusion FD-A is positioned in the plane so as to partially overlap with the outer edge of the transfer transistor TG-A, i.e., the edge opposite to the edge overlapping with the photodiode PD as described above. The floating diffusion FD-B is positioned in the plane so as to partially overlap with the outer edge of the transfer transistor TG-B (the edge opposite to the edge overlapping with the photodiode PD). The vertical positions of the floating diffusions FD-A and FD-B are substantially the same.

[0059] The OFG gate transistor OFG is formed on a semiconductor substrate, has a substantially rectangular shape in a top view, and is positioned in the plane so as to overlap a part of one of the four edges of the photodiode PD that does not overlap with the transfer transistors TG-A and TG-B. That is, in this example, the OFG gate transistor OFG is positioned so as to overlap a part of one of the two edges of the photodiode PD in the vertical direction.

[0060] FIG. 6 is a schematic cross-sectional view showing the chip structure of the sensor unit 1. As shown in FIG. The sensor unit 1 has a structure in which a first chip Cp1 and a second chip Cp2 are bonded together. The first chip Cp1 is a chip on which the pixel array unit 11 is formed, among the components of the sensor unit 1 shown in Fig. 2. The second chip Cp2 is a chip on which circuit units other than the pixel array unit 11 are formed, that is, a transfer gate driver 12, a vertical driver 13, a system controller 14, a column processor 15, and a circuit unit for driving pixels as a horizontal driver 16, and a signal processor 17 and a circuit unit for calculating distance as a data storage unit 18.

[0061] The first chip Cp1 includes a first semiconductor substrate Bs1 and a first wiring-forming layer Ar1 laminated on the first semiconductor substrate Bs1. The first semiconductor substrate Bs1 corresponds to the semiconductor substrate described in Fig. 4 and Fig. 5. The first wiring-forming layer Ar1 is a layer in which various wirings are formed, and is formed by laminating a plurality of wiring layers. The second chip Cp2 includes a second semiconductor substrate Bs2 and a second wiring-forming layer Ar2 laminated on the second semiconductor substrate Bs2. The second wiring-forming layer Ar2 is a layer in which various wirings are formed, similar to the first wiring-forming layer Ar1, and is formed by laminating a plurality of wiring layers.

[0062] The sensor unit 1 is formed by bonding the first chip Cp1 and the second chip Cp2 together in such a direction that the first wiring formation layer Ar1 of the first chip Cp1 and the second wiring formation layer Ar2 of the second chip Cp2 face each other.

[0063] <5. Chip-to-chip bonding as an embodiment> In this embodiment, the first chip Cp1 and the second chip Cp2 are bonded together by joining the wiring formed in the first wiring formation layer Ar1 and the wiring formed in the second wiring formation layer Ar2. FIG. 7 is an explanatory diagram of such bonding between chips by wiring, and shows a schematic cross-sectional view of an area of ​​one pixel Px in the sensor unit 1. In FIG. The chip-to-chip bonding wiring W21-A and the chip-to-chip bonding wiring W21-B in the figure are wirings that bond the first chip Cp1 and the second chip Cp2. The chip-to-chip bonding wiring W21-A constitutes a part of the gate drive line 21-A (see FIG. 3) for supplying a transfer drive signal STG-A to the transfer transistor TG-A, and the chip-to-chip bonding wiring W21-B constitutes a part of the gate drive line 21-B for supplying a transfer drive signal STG-B to the transfer transistor TG-B. The inter-chip bonding wiring W21-A is formed by bonding a first portion p1-A formed in the first wiring formation layer Ar1 of the first chip Cp1 to a second portion p2-A formed in the second wiring formation layer Ar2 of the second chip Cp2. The inter-chip bonding wiring W21-B is formed by bonding a first portion p1-B formed in the first wiring formation layer Ar1 to a second portion p2-B formed in the second wiring formation layer Ar2.

[0064] In this example, the Cu-Cu connection (copper-copper connection) technology is used as the inter-chip connection technology for these inter-chip connection wirings W21-A and W21-B. The Cu-Cu connection is a technology that connects the Cu conductive materials formed on each chip to each other, ensuring electrical continuity between these conductive materials and achieving physical connection between the chips.

[0065] Here, in the sensor unit 1 at the current development stage, the inter-chip connection wiring as the wiring connecting the chips is applied only to the gate drive lines 21-A and 21-B as the inter-chip connection wiring W21-A and 21-B shown in Fig. 7, and the wiring on the ground side (Vss wiring) is applied to the conventional local wiring and intermediate wiring. Here, the local wiring and intermediate wiring are wiring formed in a layer different from the layer in which the inter-chip connection wiring is formed in the first wiring formation layer Ar1, the local wiring means a wiring that is completed within the pixel Px, and the intermediate wiring means a wiring formed across the pixels Px.

[0066] In order to ensure the bonding strength, the width and cross-sectional area of ​​the inter-chip bonding wiring are considerably larger than those of the local wiring and intermediate wiring. Therefore, if the inter-chip bonding wiring is applied only to the gate drive lines 21-A and 21-B as described above, a difference in wiring resistance (impedance mismatch) occurs between the drive signal wiring side and the ground wiring side of the transfer transistor TG, and the problem of the ground potential becoming unstable due to this difference in wiring resistance occurs.

[0067] FIG. 8 is an equivalent circuit diagram of a circuit system related to driving the transfer transistor TG. 8, the boundary between the first chip Cp1 and the second chip Cp2 is shown by a dotted line. A transfer drive signal STG for driving the transfer transistor TG is generated in a transfer drive signal generation circuit (transfer gate drive unit 12) provided on the second chip Cp2 side. As shown in this equivalent circuit diagram, the transfer transistor TG generates a capacitance as a transfer gate capacitance. Therefore, if there is a difference in wiring resistance between the drive signal wiring and the ground wiring as described above, specifically, if the wiring resistance of the drive signal wiring is small and the wiring resistance of the ground wiring is large as shown in the diagram, when the transfer transistor TG is turned off, the voltage on the drive signal wiring side drops instantly, but charges remain in the transfer gate capacitance, so that on the ground wiring side, the ground potential swings to the negative polarity side of 0V due to the influence of the remaining charges. FIG. 9 shows an image of the waveforms of the voltages of the transfer drive signals STG-A and STG-B and the change in ground potential at this time.

[0068] As described above, when the ground potential swings to the negative polarity side and becomes unstable, the voltages of the transfer drive signals STG-A and STG-B also change relatively, impairing the accuracy of the operation of the transfer transistors TG-A and TG-B. When the transfer transistors TG-A and TG-B no longer operate accurately, the accuracy of the charge distribution operation to the two floating diffusions FD-A and FD-B is also impaired, resulting in a deterioration of distance measurement performance.

[0069] Therefore, in this embodiment, the inter-chip joining wiring is also applied to the ground wiring side as shown in the cross-sectional view of Fig. 10. Note that Fig. 10 shows a schematic cross-sectional view of an area for one pixel Px in the sensor unit 1, similar to Fig. 7. In the sensor unit 1 of this embodiment, the interchip bonding wiring Wg in the figure is provided as the interchip bonding wiring electrically connected to the ground. The interchip bonding wiring Wg is an interchip bonding wiring by Cu-Cu connection like the interchip bonding wirings W21-A and 21-B, and is formed by bonding a first portion p1-g formed in the first wiring formation layer Ar1 and a second portion p2-g formed in the second wiring formation layer Ar2.

[0070] By applying the inter-chip connection wiring to the ground wiring side as well, the drive signal wiring of the transfer transistor TG and the ground wiring are formed with the same type of wiring as the inter-chip connection wiring, and it is possible to make the wiring resistance of these drive signal wiring and ground wiring equal. Therefore, it is possible to prevent the accuracy of the operation of the transfer transistors TG-A and TG-B from being impaired due to an imbalance in wiring resistance between the drive signal wiring and the ground wiring (causing impedance mismatch), thereby improving distance measurement performance.

[0071] Here, as shown in FIG. 10, the first wiring formation layer Ar1 in the first chip Cp1 has a wiring layer in which the first portions (p1-A, p1-B, p1-g) of the inter-chip bonding wirings W21-A, W21-B, and Wg are formed, and this wiring layer is hereinafter referred to as the "wiring layer Ly1." In addition, the second wiring formation layer Ar2 in the second chip Cp2 has a wiring layer in which the second parts (p2-A, p2-B, p2-g) of the inter-chip joining wirings W21-A, W21-B, Wg are formed, and this wiring layer will be referred to as the "wiring layer Ly2" below.

[0072] FIG. 11 shows an example of the layout of the inter-chip connecting wires W21-A, W21-B, and Wg in the pixel array section 11. In FIG. The inter-chip connecting wirings W21-A, W21-B, and Wg are each disposed as wirings extending in the vertical direction (column direction) of the pixel array section 11. In this example, the inter-chip connecting wirings Wg are formed so that two of them pass through each pixel Px. Specifically, the inter-chip connecting wirings Wg are disposed in the boundary regions between the pixels Px that are horizontally adjacent to each other as shown in the figure, and two of them pass through each pixel Px.

[0073] In this example, the wiring widths of the interchip bonding wirings W21-A, W21-B, and Wg are set to be approximately the same, which allows the wiring resistances of the interchip bonding wirings W21-A, W21-B, and Wg to be equal, thereby preventing the accuracy of the operation of the transfer transistors TG-A and TG-B from being impaired due to an imbalance in the wiring resistances between the interchip bonding wirings W21-A, W21-B, and Wg.

[0074] In this example, the cross-sectional areas of the interchip bonding wirings W21-A, W21-B, and Wg are substantially the same, which allows the wiring resistances of the interchip bonding wirings W21-A, W21-B, and Wg to be equal, and prevents the accuracy of the operation of the transfer transistors TG-A and TG-B from being impaired due to an imbalance in the wiring resistances between the interchip bonding wirings W21-A, W21-B, and Wg.

[0075] In this example, the distance between the interchip bonding wiring W21-A and the interchip bonding wiring Wg adjacent to the interchip bonding wiring W21-A is approximately equal to the distance between the interchip bonding wiring W21-B and the interchip bonding wiring Wg adjacent to the interchip bonding wiring W21-B. The "distance" between adjacent wirings here means the distance between the adjacent ends of both wirings. Note that the "layout distance" of wirings means the distance between the centers of the wirings.

[0076] As described above, the spacing between the chip-to-chip bonding wirings W21-A and Wg is approximately equal to the spacing between the chip-to-chip bonding wirings W21-B and Wg, so that the line capacitance between the chip-to-chip bonding wiring W21-A and the chip-to-chip bonding wiring Wg (i.e., the parasitic capacitance acting on the chip-to-chip bonding wiring W21-A) and the line capacitance between the chip-to-chip bonding wiring W21-B and the chip-to-chip bonding wiring Wg (i.e., the parasitic capacitance acting on the chip-to-chip bonding wiring W21-B) are approximately equal. The drive signals (drive pulses) of the transfer transistors TG-A and TG-B are blunted due to the line capacitance with the chip-to-chip bonding wiring Wg, but by making the line capacitances approximately equal as described above, it is possible to prevent the blunting of the drive waveforms of the transfer transistors TG-A and TG-B from becoming unbalanced, and it is possible to accurately distribute charges to the two floating diffusions FD-A and FD-B. As described above, in this example, the wiring widths of the inter-chip bonding wirings W21-A, W21-B, and Wg are approximately the same, and therefore, as described above, the spacing between the inter-chip bonding wirings W21-A, Wg and the spacing between the inter-chip bonding wirings W21-B, Wg are approximately equal, and therefore the arrangement spacing of the inter-chip bonding wirings W21-A, W21-B, and Wg is approximately equal.

[0077] In this example, at least a portion of the inter-chip bonding wiring W21-A overlaps with the transfer transistor TG-A in the in-plane direction, and at least a portion of the inter-chip bonding wiring W21-B overlaps with the transfer transistor TG-B. The in-plane direction can be said to be a direction perpendicular to the stacking direction of the first chip Cp1 and the second chip Cp2. The advantage of overlapping parts of the inter-chip joining wires W21-A and W21-B with parts of the transfer transistors TG-A and TG-B in this manner will be described later.

[0078] Fig. 12 is a diagram for explaining a schematic cross-sectional structure of the sensor unit 1 corresponding to the wiring arrangement example shown in Fig. 11, and shows a schematic cross-sectional appearance of a region for one pixel Px in the sensor unit 1. Specifically, it shows specific structural examples of a wiring connecting between the chip-to-chip bonding wiring W21-A and the transfer transistor TG-A, a wiring connecting between the chip-to-chip bonding wiring W21-B and the transfer transistor TG-B, and a wiring connecting between the chip-to-chip bonding wiring Wg and the ground in the pixel Px. Hereinafter, the wiring layers other than the wiring layer Ly1 in the first wiring formation layer Ar1 will be referred to as "intermediate wiring layer Lym." In addition, the wiring connecting the inter-chip bonding wiring W21-A and the transfer transistor TG-A is referred to as the "first intermediate wiring," and the wiring connecting the inter-chip bonding wiring W21-B and the transfer transistor TG-B is referred to as the "second intermediate wiring."

[0079] In the intermediate wiring layer Lym, local wiring and intermediate wiring that function as part of the drive signal wiring of each of the transfer transistors TG-A and TG-B, and local wiring and intermediate wiring that function as part of the ground wiring are formed.

[0080] In this example, as described above, at least a part of the inter-chip connection wiring W21-A overlaps with the transfer transistor TG-A in the in-plane direction. Therefore, as surrounded by the thick dashed line X in the figure, the first intermediate wiring connecting between the inter-chip connection wiring W21-A and the transfer transistor TG-A can be formed as a connection part 30 extending substantially linearly in the stacking direction of the first chip Cp1 and the second chip Cp2. Specifically, the connection part 30 is made up of a plurality of vias v penetrating between the intermediate wiring layers Lym, and for example, the central axes of these vias v are substantially aligned with each other, so that the connection part 30 extends substantially linearly in the stacking direction. Note that the number of vias v in the connection part 30 is not limited to a plurality, and may be a single number. In addition, in this example, on the transfer transistor TG-B side, at least a portion of the inter-chip junction wiring W21-B overlaps with the transfer transistor TG-B in the in-plane direction, and although the symbol is omitted from the illustration, a similar connection is made by connection portion 30 on the transfer transistor TG-B side as well.

[0081] By forming the connection portion 30 extending approximately linearly in the stacking direction as described above, the wiring length of each of the first intermediate wiring and the second intermediate wiring can be set to a length equivalent to the separation distance in the stacking direction between the chip-to-chip connecting wiring W21-A and the transfer transistor TG-A, and a length equivalent to the separation distance in the stacking direction between the chip-to-chip connecting wiring W21-B and the transfer transistor TG-B, thereby minimizing the wiring resistance of the first and second intermediate wirings. Therefore, distortion of the drive waveforms of the transfer transistors TG-A, TG-B can be suppressed, and higher frequency transfer drive signals STG-A, STG-B can be transmitted.

[0082] In this example, at least a portion of the inter-chip bonding wiring W21-A overlaps with the transfer transistor TG-A in the in-plane direction, and at least a portion of the inter-chip bonding wiring W21-B overlaps with the transfer transistor TG-B in the in-plane direction, making it possible to form the connection portion 30 that extends in a substantially straight line in the stacking direction as described above, which eliminates the need to route the first intermediate wiring and the second intermediate wiring in the in-plane direction (see FIGS. 11 and 12), making it possible to reduce the wiring resistance of the first and second intermediate wirings. It also makes it possible to reduce the line capacitance between adjacent wirings. By reducing the wiring resistance and inter-line capacitance, it is possible to suppress distortion of the drive waveforms of the transfer transistors TG-A and TG-B, and it is possible to transmit higher frequency transfer drive signals STG-A and STG-B.

[0083] In this example, the chip-to-chip connecting wiring Wg is connected to the intermediate ground wiring 31 in the pixel Px as surrounded by the thick dashed line Y in the figure. The intermediate ground wiring 31 is a wiring formed in the intermediate wiring layer Lym and connected to the ground in the pixel Px. In this example, the intermediate ground wiring 31 extends in the vertical direction at the horizontal end of the pixel Px so as to run parallel to the chip-to-chip connecting wiring Wg. In this example, the above-mentioned connection between the intermediate ground wiring 31 and the chip-to-chip connecting wiring Wg is made in each pixel Px.

[0084] As described above, by connecting the inter-chip connecting wire Wg to the intermediate ground wire 31 within the pixel Px, it is possible to increase the cross-sectional area of ​​the inter-chip connecting wire Wg (ground wire). Increasing the cross-sectional area of ​​the ground wiring allows the wiring width of the ground wiring to be narrowed without increasing impedance. Narrowing the wiring width of the ground wiring allows the capacitance between the inter-chip bonding wiring W21-A, W21-B and the ground wiring to be reduced, and distortion of the drive pulse waveform can be suppressed.

[0085] <6. Modifications Related to Arrangement of Inter-Chip Bonding Wiring> FIG. 13 is an explanatory diagram of a first modification relating to the arrangement of inter-chip connecting wires. In this first modified example, the pitch at which chip-to-chip connection wiring is formed per pixel is changed from three lines per pixel in FIG. 11 to two lines per pixel. Specifically, in this case, the horizontal arrangement of the inter-chip bonding wiring is such that the inter-chip bonding wirings W21-A, W21-B are arranged alternately, and the inter-chip bonding wiring Wg is arranged between the inter-chip bonding wirings W21-A, W21-B. In this case, the arrangement interval of the chip-to-chip connecting wires W21-A and the arrangement interval of the chip-to-chip connecting wires W21-B are two pixels each, and the arrangement interval of the chip-to-chip connecting wires Wg is one pixel. As shown in the figure, the chip-to-chip connection wirings W21-A and W21-B are disposed at the boundary between two adjacent pixels Px in the horizontal direction, and are formed so as to overlap each of these two adjacent pixels Px. The chip-to-chip connection wiring Wg is disposed so as to be positioned at the center of each pixel Px in the horizontal direction. In this example, the wiring widths of the chip-to-chip connection wirings W21-A, W21-B, and Wg are approximately the same. In addition, in this first modified example, since the inter-chip connecting wirings W21-A, W21-B are arranged alternately, a structure is adopted in which the formation positions of the transfer transistors TG-A, TG-B are reversed between two horizontally adjacent pixels Px.

[0086] In this first modified example, in each pixel Px, the chip-to-chip bonding wirings W21-A and W21-B are arranged symmetrically with respect to the photodiode PD. Specifically, the chip-to-chip bonding wirings W21-A and W21-B are arranged in line symmetry with respect to the center line of the photodiode PD in the horizontal direction. By arranging the inter-chip bonding wiring W21-A, W21-B symmetrically on either side of the photodiode PD, it becomes possible to make the wiring lengths and wiring resistances of the first intermediate wiring (represented by a left-downward diagonal line in the figure) connecting between the transfer transistor TG-A and the inter-chip bonding wiring W21-A and the second intermediate wiring (represented by a right-downward diagonal line in the figure) connecting between the transfer transistor TG-B and the inter-chip bonding wiring W21-B equal. Therefore, it is possible to prevent the drive signals from becoming unbalanced between the transfer transistors TG-A, TG-B, and it becomes possible to accurately distribute the electric charges to the two floating diffusions FD-A, FD-B.

[0087] For confirmation, the configuration shown in FIG. 11 also corresponds to a configuration in which the inter-chip joining wires W21-A and W21-B are arranged symmetrically with the photodiode PD therebetween.

[0088] Also in the first modified example, similarly to the case of FIG. 11, the distance between the chip-to-chip connecting wires W21-A, Wg is approximately equal to the distance between the chip-to-chip connecting wires W21-B, Wg. Therefore, also in the first modified example, the line capacitance between the interchip bonding wiring W21-A and the interchip bonding wiring Wg can be made substantially equal to the line capacitance between the interchip bonding wiring W21-B and the interchip bonding wiring Wg.

[0089] FIG. 14 is an explanatory diagram of a second modification relating to the arrangement of inter-chip connecting wires. 13 is that the inter-chip bonding wirings W21-A and W21-B are arranged so that a part of each of them overlaps with the corresponding transfer transistor TG in the horizontal direction. That is, the inter-chip bonding wiring W21-A is arranged so that a part of it overlaps with the transfer transistor TG-A, and the inter-chip bonding wiring W21-B is arranged so that a part of it overlaps with the transfer transistor TG-B. As in the case of Figure 13, the second modified example also satisfies the condition that the spacing between the inter-chip connecting wirings W21-A, Wg and the spacing between the inter-chip connecting wirings W21-B, Wg are approximately equal. Therefore, by arranging the inter-chip connecting wirings W21-A, W21-B as described above, the inter-chip connecting wiring Wg in this case is not disposed in the horizontal center of the pixel Px, but at a position horizontally shifted from the center.

[0090] FIG. 15 is an explanatory diagram of a third modified example relating to the arrangement of inter-chip connecting wires. In the third modified example, the pitch of the inter-chip bonding wires is narrowed to five wires per pixel. Specifically, the five inter-chip bonding wires for each pixel Px in this case are broken down into one each of inter-chip bonding wires W21-A and W21-B and three inter-chip bonding wires Wg, and as shown in the figure, the inter-chip bonding wires W21-A and W21-B are disposed at positions where they partially overlap with the corresponding transfer transistors TG, as in the case of Fig. 11, and the inter-chip bonding wires Wg are disposed as follows: one between the inter-chip bonding wires W21-A and W21-B, one outside the inter-chip bonding wire W21-A, and one outside the inter-chip bonding wire W21-B.

[0091] By narrowing the formation pitch of the inter-chip bonding wiring, the bonding strength between the chips can be improved.

[0092] <7. Other variations> It should be noted that the embodiment is not limited to the specific example described above, and various modifications are possible. For example, although the above example shows that the inter-chip connection wiring is arranged in a horizontal direction, it may be arranged in a vertical direction. Also, although each inter-chip connection wiring is shown as a wiring extending in a straight line, it may be partially bent or curved, or partially extending in an oblique direction.

[0093] Furthermore, the pitch at which the inter-chip connection wiring is formed is not limited to the above example. Here, as described above, the formation pitch of the pixels Px in this example is 5.0 μm or less, specifically about 3.5 μm, and in this case, with a ratio of three wires per pixel as illustrated in Fig. 11, the formation pitch of the chip-to-chip connection wiring is approximately 1.7 (5.0÷3) μm or less, specifically about 1.2 μm (3.5÷3). Also, with a ratio of two wires per pixel as illustrated in Fig. 13, the formation pitch of the chip-to-chip connection wiring is approximately 2.5 (5.0÷2) μm or less, specifically about 1.8 μm (3.5÷2).

[0094] In addition, in the above example, the signal processing unit 17 that performs the calculation for calculating the distance is provided inside the sensor unit 1, but the signal processing unit 17 can also be provided outside the sensor unit 1.

[0095] <8. Summary of the embodiment> As described above, the sensor device (sensor unit 1) of the embodiment has a first semiconductor substrate (Bs1) and a first wiring formation layer (Ar1), and is equipped with a first chip (Cp1) having a pixel including a photoelectric conversion element (photodiode PD) and a first transfer gate element (transfer transistor TG-A) and a second transfer gate element (transfer transistor TG-B) for transferring accumulated charges of the photoelectric conversion element, and a second chip (Cp2) having a second semiconductor substrate (Bs2) and a second wiring formation layer (Ar2). Then, a first wiring (inter-chip connecting wiring W21-A) electrically connected to the first transfer gate element, a second wiring (inter-chip connecting wiring W21-B) electrically connected to the second transfer gate element, and a third wiring (inter-chip connecting wiring Wg) electrically connected to ground are formed, and each of the first wiring, second wiring, and third wiring is formed by joining a first portion (p1-A, p1-B, p1-g) formed in the first wiring formation layer and extending in the first direction to a second portion (p2-A, p2-B, p2-g) formed in the second wiring formation layer and extending in the first direction. According to the above configuration, the first wiring for the first transfer gate element, the second wiring for the second transfer gate element, and the third wiring as a ground wiring are all formed as inter-chip joining wiring for joining the first chip and the second chip. That is, the first wiring, the second wiring, and the third wiring are formed of the same type of wiring as inter-chip joining wiring, so that it is possible to make the wiring resistances equal. Therefore, it is possible to prevent the accuracy of the operation of the first and second transfer gate elements from being impaired due to an imbalance in wiring resistance between the first wiring, the second wiring, and the third wiring, and it is possible to improve the performance of distance measurement using the sensor device.

[0096] Moreover, the sensor device according to the embodiment is a distance measurement sensor using an indirect ToF method. The indirect ToF method employs a technique in which the accumulated charge of a photoelectric conversion element is distributed to two floating diffusions by first and second transfer gate elements. Therefore, by applying the present technology, it is possible to prevent the accuracy of the operations of the first and second transfer gate elements from being impaired, thereby improving distance measurement performance.

[0097] Furthermore, in the sensor device according to the embodiment, the first wiring, the second wiring, and the third wiring are each formed by connecting the first portion and the second portion by Cu-Cu connection. Cu-Cu connections are suitable as a connection technology between chips in terms of track record and reliability. Therefore, the sensor device according to this embodiment can be easily realized.

[0098] Furthermore, in the sensor device according to the embodiment, the first wiring and the second wiring are disposed symmetrically with respect to the photoelectric conversion element. This makes it possible to make the wiring lengths of the first intermediate wiring, which is the wiring connecting the first transfer gate element and the first wiring, and the second intermediate wiring, which is the wiring connecting the second transfer gate element and the second wiring, equal, and therefore makes it possible to make the wiring resistances equal. Therefore, it is possible to prevent the drive signals from becoming unbalanced between the first and second transfer gate elements, and it is possible to accurately distribute the charges to the two floating diffusions, thereby improving the distance measurement performance.

[0099] In the sensor device according to the embodiment, the first wiring, the second wiring, and the third wiring have substantially the same wiring width. This makes it possible to make the wiring resistances of the first wiring, the second wiring, and the third wiring equal to each other. Therefore, it is possible to prevent the accuracy of the operation of the first and second transfer gate elements from being impaired due to an imbalance in wiring resistance between the first wiring, the second wiring, and the third wiring, and it is possible to improve the performance of distance measurement using the sensor device.

[0100] Furthermore, in the sensor device according to the embodiment, the cross-sectional areas of the first wiring, the second wiring, and the third wiring are substantially the same. This makes it possible to make the wiring resistances of the first wiring, the second wiring, and the third wiring equal to each other. Therefore, it is possible to prevent the accuracy of the operation of the first and second transfer gate elements from being impaired due to an imbalance in wiring resistance between the first wiring, the second wiring, and the third wiring, and it is possible to improve the performance of distance measurement using the sensor device.

[0101] Furthermore, in the sensor device as an embodiment, in a direction perpendicular to the stacking direction of the first chip and the second chip, at least a portion of the first wiring overlaps with the first transfer gate element, and at least a portion of the second wiring overlaps with the second transfer gate element. This eliminates the need to route the first intermediate wiring, which is a wiring connecting the first wiring and the first transfer gate element, and the second intermediate wiring, which is a wiring connecting the second wiring and the second transfer gate element, in a direction perpendicular to the stacking direction, thereby making it possible to reduce the wiring resistance of both wirings and also to reduce the line capacitance between adjacent wirings. By reducing the wiring resistance and the line capacitance, it is possible to suppress distortion of the drive waveforms of the first and second transfer gate elements, and it is possible to transmit a transfer drive signal of a higher frequency.

[0102] In addition, in the sensor device as an embodiment, the first wiring and the first transfer gate element, and the second wiring and the second transfer gate element are connected by a connection portion (30) consisting of one or more vias (v) and extending approximately linearly in the stacking direction. As a result, the wiring lengths of the first intermediate wiring, which is a wiring connecting the first wiring and the first transfer gate element, and the second intermediate wiring, which is a wiring connecting the second wiring and the second transfer gate element, can be set to a length equivalent to the separation distance in the stacking direction between the first wiring and the first transfer gate element, and a length equivalent to the separation distance in the stacking direction between the second wiring and the second transfer gate element, making it possible to minimize the wiring resistance of the first and second intermediate wirings and the inter-line capacitance between adjacent wirings. Therefore, it is possible to suppress distortion of the drive waveforms of the first and second transfer gate elements, and it is possible to transmit a transfer drive signal of a higher frequency.

[0103] Furthermore, in the sensor device of the embodiment, the distance between the first wiring and the third wiring adjacent to the first wiring is approximately equal to the distance between the second wiring and the third wiring adjacent to the second wiring. This makes the line capacitance between the first wiring and the third wiring (parasitic capacitance acting on the first wiring) and the line capacitance between the second wiring and the third wiring (parasitic capacitance acting on the second wiring) approximately equal, preventing the dulling of the drive waveforms of the first and second transfer gate elements from becoming unbalanced, and enabling accurate distribution of charge to the two floating diffusions. Therefore, the distance measurement performance can be improved.

[0104] Furthermore, in the sensor device as an embodiment, a wiring layer in which the first wiring, the second wiring, and a first portion of the third wiring are formed, and an intermediate wiring layer other than the wiring layer are formed in the first wiring formation layer, at least a portion of the third wiring overlaps with the pixel in a direction perpendicular to the stacking direction of the first chip and the second chip, and the third wiring is connected within the pixel to an intermediate ground wiring, which is a wiring formed in the intermediate wiring layer and connected to a ground within the pixel. This makes it possible to increase the cross-sectional area of ​​the third wiring (ground wiring). Increasing the cross-sectional area of ​​the ground wiring allows the wiring width of the ground wiring to be narrowed without increasing impedance. Narrowing the wiring width of the ground wiring allows the capacitance between the first and second wirings and the ground wiring to be reduced, suppressing waveform distortion of the drive pulse and realizing transmission of a higher frequency transfer signal.

[0105] In addition, a distance measuring device (10) as an embodiment includes a light emitting unit (2) that emits light (Li) to be irradiated onto an object, and a sensor unit (1) that receives reflected light (Lr) of the irradiated light from the object, and the sensor unit includes a first chip having a first semiconductor substrate and a first wiring forming layer, and a pixel including a photoelectric conversion element and a first transfer gate element and a second transfer gate element for transferring the accumulated charge of the photoelectric conversion element, and a second chip having a second semiconductor substrate and a second wiring forming layer, and a first wiring electrically connected to the first transfer gate element, a second wiring electrically connected to the second transfer gate element, and a third wiring electrically connected to ground are formed, and each of the first wiring, the second wiring, and the third wiring is formed by joining a first portion formed in the first wiring forming layer and extending in a first direction, and a second portion formed in the second wiring forming layer and extending in the first direction. With the distance measuring device of this embodiment, it is possible to obtain the same functions and effects as the sensor device of the above embodiment.

[0106] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0107] <9. This Technology> The present technology can also be configured as follows. (1) a first chip having a first semiconductor substrate and a first wiring formation layer, and having a pixel including a photoelectric conversion element and a first transfer gate element and a second transfer gate element for transferring accumulated charges of the photoelectric conversion element; a second chip having a second semiconductor substrate and a second wiring formation layer; a first wiring electrically connected to the first transfer gate element; a second wiring electrically connected to the second transfer gate element; a third wiring electrically connected to the ground is formed; Each of the first wiring, the second wiring, and the third wiring is formed by joining a first portion formed in the first wiring formation layer and extending in a first direction to a second portion formed in the second wiring formation layer and extending in the first direction. Sensor device. (2) It is a distance measurement sensor using the indirect ToF method. The sensor device according to (1) above. (3) The first wiring, the second wiring, and the third wiring are each formed by connecting the first portion and the second portion with Cu-Cu. The sensor device according to (1) or (2). (4) The first wiring and the second wiring are disposed symmetrically with respect to the photoelectric conversion element. The sensor device according to any one of (1) to (3). (5) The first wiring, the second wiring, and the third wiring have substantially the same wiring width. The sensor device according to any one of (1) to (4). (6) The first wiring, the second wiring, and the third wiring have substantially the same cross-sectional area. The sensor device according to any one of (1) to (5). (7) In a direction perpendicular to a stacking direction of the first chip and the second chip, at least a part of the first wiring overlaps with the first transfer gate element, and at least a part of the second wiring overlaps with the second transfer gate element. The sensor device according to any one of (1) to (6). (8) The first wiring and the first transfer gate element, and the second wiring and the second transfer gate element are connected by a connection portion that is made of one or a plurality of vias and extends substantially linearly in the stacking direction. The sensor device according to (7) above. (9) A distance between the first wiring and the third wiring adjacent to the first wiring is approximately equal to a distance between the second wiring and the third wiring adjacent to the second wiring. The sensor device according to any one of (1) to (8). (10) The first wiring formation layer includes: a wiring layer in which the first wiring, the second wiring, and the first portion of the third wiring are formed, and an intermediate wiring layer other than the wiring layer are formed; At least a portion of the third wiring overlaps with the pixel in a direction perpendicular to a stacking direction of the first chip and the second chip, The third wiring is connected in the pixel to an intermediate ground wiring, which is a wiring formed in the intermediate wiring layer and connected to a ground in the pixel. The sensor device according to any one of (1) to (9). (11) A light emitting unit that emits light to irradiate an object; a sensor unit that receives reflected light of the irradiation light from the object, The sensor unit includes: a first chip having a first semiconductor substrate and a first wiring formation layer, and having a pixel including a photoelectric conversion element and a first transfer gate element and a second transfer gate element for transferring accumulated charges of the photoelectric conversion element; a second chip having a second semiconductor substrate and a second wiring formation layer; a first wiring electrically connected to the first transfer gate element; a second wiring electrically connected to the second transfer gate element; a third wiring electrically connected to the ground is formed; Each of the first wiring, the second wiring, and the third wiring is formed by joining a first portion formed in the first wiring formation layer and extending in a first direction to a second portion formed in the second wiring formation layer and extending in the first direction. Ranging device. [Explanation of symbols]

[0108] 1. Sensor section (sensor device) 2 Light emitting unit 10 Ranging device Ob Object Li irradiation light Lr reflected light 11 Pixel array section 20 Pixel drive lines 21 Gate drive line 22 Vertical signal line Px Pixels PD Photodiode FD Floating Diffusion TG transfer transistor RST Reset transistor Cp1 First chip Cp2 Second Chip Bs1 First semiconductor substrate Bs2 Second semiconductor substrate Ar1 first wiring formation layer Ar2 second wiring formation layer W21-A, W21-B, Wg Inter-chip connection wiring p1-A, p1-B, p1-g First part p2-A, p2-B, p2-g second part Lym intermediate wiring layer v via 30 Connection 31 Intermediate ground wiring

Claims

1. a first chip having a first semiconductor substrate and a first wiring formation layer, and having a pixel including a photoelectric conversion element and a first transfer gate element and a second transfer gate element for transferring accumulated charges of the photoelectric conversion element; a second chip having a second semiconductor substrate and a second wiring formation layer; a first wiring electrically connected to the first transfer gate element; a second wiring electrically connected to the second transfer gate element; a third wiring electrically connected to the ground of the pixel is formed; each of the first wiring, the second wiring, and the third wiring is formed by joining a first portion formed in the first wiring formation layer and extending in a first direction perpendicular to a layer thickness direction, and a second portion formed in the second wiring formation layer and extending in the first direction; A distance between the first wiring and the third wiring adjacent to the first wiring is equal to a distance between the second wiring and the third wiring adjacent to the second wiring. Sensor device.

2. It is a distance measurement sensor using the indirect ToF method. The sensor device according to claim 1 .

3. The first wiring, the second wiring, and the third wiring are each formed by connecting the first portion and the second portion with Cu-Cu. The sensor device according to claim 1 .

4. The first wiring and the second wiring are disposed symmetrically with respect to the photoelectric conversion element. The sensor device according to claim 1 .

5. The first wiring, the second wiring, and the third wiring have the same wiring width. The sensor device according to claim 1 .

6. The first wiring, the second wiring, and the third wiring have the same cross-sectional area. The sensor device according to claim 1 .

7. In a direction perpendicular to a stacking direction of the first chip and the second chip, at least a part of the first wiring overlaps with the first transfer gate element, and at least a part of the second wiring overlaps with the second transfer gate element. The sensor device according to claim 1 .

8. The first wiring and the first transfer gate element, and the second wiring and the second transfer gate element are connected by a connection portion that is made of one or a plurality of vias and extends substantially linearly in the stacking direction. The sensor device according to claim 7.

9. The first wiring formation layer includes: a wiring layer in which the first wiring, the second wiring, and the first portion of the third wiring are formed, and an intermediate wiring layer other than the wiring layer are formed; At least a portion of the third wiring overlaps with the pixel in a direction perpendicular to a stacking direction of the first chip and the second chip, The third wiring is connected in the pixel to an intermediate ground wiring, which is a wiring formed in the intermediate wiring layer and connected to a ground in the pixel. The sensor device according to claim 1 .

10. A light emitting unit that emits light to irradiate an object; a sensor unit that receives reflected light of the irradiation light from the object, The sensor unit includes: a first chip having a first semiconductor substrate and a first wiring formation layer, and having a pixel including a photoelectric conversion element and a first transfer gate element and a second transfer gate element for transferring accumulated charges of the photoelectric conversion element; a second chip having a second semiconductor substrate and a second wiring formation layer; a first wiring electrically connected to the first transfer gate element; a second wiring electrically connected to the second transfer gate element; a third wiring electrically connected to the ground of the pixel is formed; each of the first wiring, the second wiring, and the third wiring is formed by joining a first portion formed in the first wiring formation layer and extending in a first direction perpendicular to a layer thickness direction, and a second portion formed in the second wiring formation layer and extending in the first direction; A distance between the first wiring and the third wiring adjacent to the first wiring is equal to a distance between the second wiring and the third wiring adjacent to the second wiring. Ranging device.

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