Method for manufacturing a display device

Abstract

To reduce the manufacturing cost of a display device comprising micro LEDs in a display element, and to manufacture the display device comprising micro LEDs in the display element.SOLUTION: The manufacture method of display device includes: forming a plurality of transistors on a substrate in matrix; forming a conductor electrically connected to the transistor on the substrate; forming a plurality of light-emitting elements on a film in matrix, each of the light-emitting elements having an electrode on one surface, and the other surface being in contact with the film; making the conductor and the electrode face each other; extruding an extrusion mechanism from a film side toward a substrate side to bring the conductor into contact with the electrode; and electrically connecting the conductor to the electrode.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device, a manufacturing method of the display device, and an apparatus for manufacturing the display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, and the like are examples of semiconductor devices. In addition, imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, and the like), and electronic devices may include semiconductor devices. [Background technology]

[0004] In recent years, the uses of display devices have become more diverse, and display devices are used in, for example, portable information terminals, home television devices (also called televisions or television receivers), digital signage (digital signage), and public information displays (PIDs). Representative examples of display devices include display devices equipped with light-emitting elements such as organic electroluminescence (EL) elements and light-emitting diodes (LEDs), display devices equipped with liquid crystal elements, and electronic paper that displays images using an electrophoretic method or the like. Furthermore, the brightness required of display devices is increasing year by year so that they can withstand outdoor use.

[0005] An active matrix type micro LED display device has been disclosed that uses small LEDs (also called micro LEDs) as light emitting elements and transistors as switching elements connected to each pixel electrode (Patent Document 1). Also, active matrix type display devices that use transistors with a metal oxide (hereinafter also called oxide semiconductor) exhibiting semiconductor properties as a channel formation region as switching elements connected to each pixel electrode are known (Patent Documents 2 and 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent Publication No. 2017 / 0179092 [Patent Document 2] JP 2007-123861 A [Patent Document 3] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0007] Display devices that use micro LEDs as display elements require a long time to mount the LEDs on a circuit board, making it difficult to reduce manufacturing costs. In addition, the more pixels a display device has, the more LEDs it requires, and the longer it takes to mount them. In addition, the higher the resolution of the display device, the more difficult it is to mount the LEDs.

[0008] In view of the above, an object of one embodiment of the present invention is to reduce the manufacturing cost of a display device using a micro LED as a display element. Another object of one embodiment of the present invention is to manufacture a display device using a micro LED as a display element with high yield. Another object of one embodiment of the present invention is to provide a manufacturing apparatus for manufacturing a display device using a micro LED as a display element with low manufacturing cost. Another object of one embodiment of the present invention is to provide a manufacturing apparatus for manufacturing a display device using a micro LED as a display element with high yield.

[0009] An object of one embodiment of the present invention is to provide a display device with high luminance. Another object of one embodiment of the present invention is to provide a display device with high contrast. Another object of one embodiment of the present invention is to provide a display device with high response speed. Another object of one embodiment of the present invention is to provide a display device with low power consumption. Another object of one embodiment of the present invention is to provide a display device with low manufacturing costs. Another object of one embodiment of the present invention is to provide a display device with a long lifetime. Another object of one embodiment of the present invention is to provide a novel display device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a method for manufacturing a display device, in which a plurality of transistors are formed in a matrix on a substrate, a conductor electrically connected to the transistors is formed on the substrate, a plurality of light-emitting elements are formed in a matrix on a film, each of the light-emitting elements has an electrode on one side and is in contact with the film on the other side, the conductor and the electrode are opposed to each other, and an extrusion mechanism is extruded from the film side to the substrate side to bring the conductor and the electrode into contact with each other, and the conductor and the electrode are electrically connected to each other.

[0012] In the above-described method for manufacturing a display device, it is preferable that after the conductor and the electrode are brought into contact with each other, ultrasonic waves are applied to the conductor and the electrode via an extrusion mechanism to pressure-bond the conductor and the electrode.

[0013] In the above-mentioned method for producing a display device, the film preferably has a tensile modulus of elasticity of 3 GPa or more and 18 GPa or less.

[0014] In the above-mentioned method for producing a display device, it is preferable to use a plurality of films each having a plurality of light-emitting elements formed thereon.

[0015] In the above-described method for manufacturing a display device, at least one of the plurality of light-emitting elements is preferably a micro LED.

[0016] In the above-described method for manufacturing a display device, at least one of the plurality of transistors preferably has a metal oxide in a channel formation region.

[0017] Another embodiment of the present invention is an apparatus for manufacturing a display device, the apparatus having a stage, a gripping mechanism, and an extrusion mechanism, the stage having a function of holding a substrate on which a plurality of transistors are formed in a matrix, a conductor electrically connecting to the transistors being formed on the substrate, the gripping mechanism having a function of gripping a film on which a plurality of light-emitting elements are formed in a matrix, each of the light-emitting elements having an electrode on one surface and in contact with the film on the other surface, the gripping mechanism having a function of bringing the conductor and the electrode into contact with each other, and the extrusion mechanism having a function of pushing from the film side to the substrate side to bring the conductor and the electrode into contact with each other and electrically connecting the conductor and the electrode. Effect of the Invention

[0018] According to one embodiment of the present invention, the manufacturing cost of a display device using a micro LED as a display element can be reduced. Alternatively, according to one embodiment of the present invention, a display device using a micro LED as a display element can be manufactured with a high yield. Alternatively, according to one embodiment of the present invention, a manufacturing apparatus for manufacturing a display device using a micro LED as a display element at low manufacturing cost can be provided. Alternatively, according to one embodiment of the present invention, a manufacturing apparatus for manufacturing a display device using a micro LED as a display element at a high yield can be provided.

[0019] According to one embodiment of the present invention, a display device with high luminance can be provided. According to one embodiment of the present invention, a display device with high contrast can be provided. According to one embodiment of the present invention, a display device with high response speed can be provided. According to one embodiment of the present invention, a display device with low power consumption can be provided. According to one embodiment of the present invention, a display device with low manufacturing cost can be provided. According to one embodiment of the present invention, a display device with long lifetime can be provided. According to one embodiment of the present invention, a novel display device can be provided. According to one embodiment of the present invention, a novel manufacturing method for a display device can be provided. According to one embodiment of the present invention, a novel manufacturing device for a display device can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a plan view and a perspective view showing a display device. [Diagram 2] 2A1 and 2B1 are perspective views showing a method for manufacturing a display device, and 2A2 and 2B2 are cross-sectional views showing the method for manufacturing a display device. [Diagram 3] Figures 3A1 and 3B1 are perspective views showing a method for producing a display device, and Figures 3A2 and 3B2 are cross-sectional views showing the method for producing a display device. [Figure 4]Figures 4A1 and 4B1 are perspective views showing a method for manufacturing a display device, and Figures 4A2 and 4B2 are cross-sectional views showing a method for manufacturing a display device. [Diagram 5] Figures 5A1 and 5B1 are perspective views showing a method for producing a display device, and Figures 5A2 and 5B2 are cross-sectional views showing a method for producing a display device. [Figure 6] Figures 6A1 and 6B1 are perspective views showing a method for manufacturing a display device, and Figures 6A2 and 6B2 are cross-sectional views showing a method for manufacturing a display device. [Figure 7] FIG. 7 is a perspective view of the device. [Figure 8] FIG. 8 is a schematic diagram showing the configuration of the device. [Figure 9] 9A, 9B, and 9C are cross-sectional views showing a method for manufacturing a display device. [Figure 10] 10A, 10B, 10C, and 10D are cross-sectional views showing a method for manufacturing a display device. [Figure 11] FIG. 11 is a perspective view of the device. [Figure 12] 12A, 12B, and 12C show configuration examples of the display device. [Figure 13] 13A, 13B, and 13C show configuration examples of the display device. [Figure 14] 14A, 14B, and 14C show configuration examples of a light-emitting element. [Figure 15] 15A, 15B, and 15C show configuration examples of a light-emitting element. [Figure 16] 16A, 16B, and 16C show configuration examples of the display device. [Figure 17] 17A, 17B, and 17C are top views of the display device. [Figure 18] FIG. 18 is a cross-sectional view of the display device. [Figure 19] FIG. 19 is a cross-sectional view of the display device. [Figure 20] 20A, 20B, and 20C are diagrams illustrating a method for manufacturing a display device. [Figure 21]21A and 21B are diagrams illustrating a method for manufacturing a display device. [Figure 22] FIG. 22 is a diagram illustrating a method for manufacturing a display device. [Diagram 23] 23A and 23B are diagrams illustrating a method for manufacturing a display device. [Figure 24] FIG. 24 is a cross-sectional view of the display device. [Diagram 25] 25A and 25B are diagrams illustrating a method for manufacturing a display device. [Figure 26] 26A and 26B are diagrams illustrating a method for manufacturing a display device. [Figure 27] 27A1, 27A2, 27B1, 27B2, 27C1, and 27C2 are diagrams illustrating transistors. [Figure 28] 28A1, 28A2, 28B1, 28B2, 28C1, and 28C2 are diagrams illustrating transistors. [Figure 29] 29A1, 29A2, 29B1, 29B2, 29C1, and 29C2 are diagrams illustrating transistors. [Diagram 30] 30A1, 30A2, 30B1, 30B2, 30C1, and 30C2 are diagrams illustrating transistors. [Diagram 31] Fig. 31A is a block diagram of a display device, and Fig. 31B is a circuit diagram of the display device. [Diagram 32] 32A, 32B, and 32C are circuit diagrams of the display device. [Diagram 33] Figures 33A, 33C and 33D are circuit diagrams of the display device, and Figure 33B is a timing chart of the display device. [Diagram 34] 34A, 34B, 34C, 34D, and 34E are diagrams for explaining an information processing device. [Diagram 35] 35A, 35B, 35C, 35D, and 35E are diagrams for explaining an information processing device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be used.

[0024] In addition, in each figure described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0025] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components and do not limit the numbers.

[0026] A transistor is a type of semiconductor element that can amplify current or voltage, and perform switching operations to control conduction or non-conduction, etc. In this specification and the like, the term "transistor" includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0027] In the following, expressions indicating directions such as "up" and "down" are basically used in accordance with the directions in the drawings. However, for the purpose of facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. As an example, when explaining the stacking order (or formation order) of a laminate, even if the surface on the side where the laminate is provided (the surface to be formed, the supporting surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the direction may be expressed as "down" and the opposite direction as "up."

[0028] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0029] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or a substrate having an IC mounted thereon using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0030] (Embodiment 1) In this embodiment, a manufacturing method and an apparatus for manufacturing a display device which are one embodiment of the present invention will be described.

[0031] First, an example of a display device that can be manufactured by a manufacturing method of a display device according to one embodiment of the present invention is shown in Figure 1. The left side of Figure 1 is a top view of the display device, and the right side is an enlarged perspective view of a part of a pixel portion. A display device 700 shown in Figure 1 includes a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 over a substrate 800. A plurality of light-emitting elements 17 are provided in the pixel portion 702.

[0032] The substrate 800 is preferably provided with a circuit for driving the light-emitting element 17. The substrate 800 includes, for example, a circuit including a transistor, a capacitor, a wiring, an electrode, and the like. It is more preferable that an active matrix system in which one or more transistors are connected to each of the light-emitting elements 17 is applied. In the pixel portion 702, the transistor is electrically connected to the electrode 21 and the electrode 23. The electrode 21 and the electrode 23 are electrically connected to the light-emitting element 17. That is, the pixel circuit is electrically connected to the light-emitting element 17 through the electrode 21 and the electrode 23. Note that FIG. 1 illustrates an example in which each light-emitting element 17 is electrically connected to two electrodes, the electrode 21 and the electrode 23, but one embodiment of the present invention is not limited to this. Electrodes electrically connected to the pixel circuit may be formed according to the number of electrodes included in the light-emitting element 17. Note that in this embodiment, the light-emitting element 17 is illustrated as one of the components provided on the substrate 800, but the light-emitting element can be referred to as a light-emitting device. Similarly, the capacitor can be referred to as a capacitance device.

[0033] Next, a method for manufacturing a display device will be described with reference to Fig. 2 to Fig. 11. Each diagram shown in Fig. 2 to Fig. 11 is a perspective view and a cross-sectional view at each stage of a process related to the method for manufacturing a display device 700. In the embodiment, an example in which an LED chip is used as the light-emitting element 17 will be shown.

[0034] The emission color of the LED chip that can be used in the manufacturing method of the display device according to one embodiment of the present invention is not particularly limited. For example, the method can be applied to an LED chip that emits white light. The method can also be applied to an LED chip that emits light in the visible wavelength region, such as red, green, or blue. The method can also be applied to an LED chip that emits light in the near-infrared or infrared wavelength region.

[0035] LED chips that can be used in the manufacturing method of a display device according to one embodiment of the present invention include macro LEDs (also called giant LEDs), mini LEDs, micro LEDs, and the like, starting from the large size. Here, LED chips with a side dimension of more than 1 mm are called macro LEDs, those with a side dimension of more than 100 μm and 1 mm or less are called mini LEDs, and those with a side dimension of 100 μm or less are called micro LEDs. As the LED chip to be applied to pixels, it is particularly preferable to use mini LEDs or micro LEDs. By using micro LEDs, a display device with extremely high resolution can be realized.

[0036] The transistors in the display device preferably have a metal oxide in the channel formation region. A transistor using a metal oxide can reduce power consumption. Therefore, by combining a transistor with a micro LED, a display device with extremely low power consumption can be realized.

[0037] A plurality of LED chips are formed on the LED chip substrate. An example of the LED chip substrate 900 is shown in FIG. 2A1 and FIG. 2A2. FIG. 2A1 is a perspective view of the LED chip substrate 900, and FIG. 2A2 is a cross-sectional view taken along the dashed line X1-X2 shown in FIG. 2A1. The LED chip is formed on a substrate 71A, a semiconductor layer 81 having an n-type semiconductor layer, a light-emitting layer, a p-type semiconductor layer, and the like, an electrode 85 functioning as a cathode, and an electrode 87 functioning as an anode. A plurality of LED chips are formed on the LED chip substrate 900, and a plurality of LED chips can be fabricated by dividing the LED chip substrate 900 along the LED chip sections 51A.

[0038] The substrate 71A of the LED chip substrate 900 is ground to thin the substrate 71A to a desired thickness (FIGS. 2B1 and 2B2). By thinning the substrate 71A, it becomes easier to separate the substrate 71A into individual LED chips. Alternatively, the substrate 71A may be removed from the LED chip substrate 900.

[0039] Grinding will be described in detail. First, the electrode 85 and electrode 87 side of the LED chip substrate 900 is bonded to the plate 903. The bonded LED chip substrate 900 and plate 903 are placed on a table 905. At this time, the plate side is brought into contact with the table, and the LED chip substrate 900 and plate 903 are fixed to the table 905 by a vacuum chuck or the like. Next, while rotating the table 905 within the surface of the table 905, a grindstone 907 provided on a grindstone wheel 909 is brought into contact with the substrate 71A, and the substrate 71A is ground to obtain the substrate 71. During grinding, the grindstone wheel 909 and grindstone 907 may be rotated.

[0040] Next, it is preferable to polish the ground surface with an abrasive (also called a slurry) to flatten the surface of the substrate 71 (FIGS. 3A1 and 3A2). By flattening the surface of the substrate 71, it is possible to prevent a decrease in the yield in the subsequent steps.

[0041] In addition, when grinding and polishing, it is preferable to provide and fix a film 901 for protection on the electrode 85 and the electrode 87 side, and then perform polishing (see FIG. 2B2). After polishing, the film 901 is removed.

[0042] Next, a first film 919 is provided on the electrode 85 and the electrode 87 side, and the LED chip substrate 900 and the first film 919 are fixed to a first fixture 921 (FIGS. 3B1 and 3B2). As the first film 919, a film having a property of stretching when pulled (also called an expandable film) is preferably used. As the first film 919, vinyl chloride resin, silicon resin, polyolefin resin, etc. can be used. In addition, it is preferable that the first film 919 has an adhesive provided on its surface and has a property that its adhesive strength weakens when irradiated with light. Specifically, as the first film 919, a film whose adhesive strength weakens when irradiated with ultraviolet light can be preferably used. As the first fixture 921, for example, a ring-shaped jig as shown in FIG. 3B1 can be preferably used.

[0043] Next, scribe lines 911 are formed along the LED chip sections 51A of the LED chip substrate 900 (FIGS. 4A1 and 4A2). A machine scribing method can be used to form the scribe lines 911. In the machine scribing method, a scribing tool is pressed against the substrate 71 to mechanically form grooves (also called scribe lines or markings) in the substrate 71. A diamond blade or the like can be used as the scribing tool.

[0044] Laser scribing may also be used to form the scribe lines 911. Laser scribing is a method in which the substrate 71 is irradiated with laser light to locally heat it, and then rapidly cooled, thereby generating thermal stress that causes an altered layer in the substrate 71, forming the scribe lines 911. In the laser scribing method, the scribe lines 911 may be formed on the surface of the substrate 71, or may be formed inside the surface of the substrate 71. In the machine scribing method, the scribing tool wears out and must be replaced, but in the laser scribing method, there is no need to replace the scribing tool.

[0045] Alternatively, the substrate 71 may be cut along the LED chip sections 51A using a blade dicing method. In the blade dicing method, a blade (also called a blade) is rotated at high speed to cut into an object, and diamond may be used for the blade. When the blade dicing method is used, half cuts may be performed by cutting the substrate 71 halfway in the thickness direction, or full cuts may be performed by cutting the substrate 71 and the semiconductor layer 81 completely in the thickness direction.

[0046] Next, the LED chip substrate 900 is separated into each LED chip. To separate into each LED chip, for example, the LED chip substrate 900 is placed on a receiving base 913 having an opening 914, and a blade 915 is driven along a scribe line 911, so that the LED chip substrate 900 can be separated into each LED chip (FIGS. 4B1 and 4B2). Alternatively, the LED chip substrate 900 may be sandwiched between rollers, and each LED chip may be separated by providing the rollers with surfaces having different inclination angles. When separating into each LED chip, a sheet 923 (also called a scribe sheet) for protection may be provided on the substrate 71 side, and then each LED chip may be separated. The LED chip substrate 900 after separation into each LED chip is shown in FIG. 5A1 and FIG. 5A2.

[0047] Next, the first film 919 is pulled to separate the LED chips 51, and the spacing between the LED chips 51 is increased (FIGS. 5B1 and 5B2). By increasing the spacing between the LED chips 51, subsequent handling becomes easier. To separate the LED chips 51, for example, a plate 924 having an area larger than the area where the LED chips 51 are provided is pushed up from the first film 919 side toward the LED chips 51 side, whereby the first film 919 is pulled and each LED chip 51 can be separated.

[0048] Next, the second film 927 is fixed to the second fixture 925, and the second film 927 and the second fixture 925 are provided on the substrate 71 side (FIGS. 6A1 and 6A2).

[0049] In addition, when using LED chips 51 that have already been separated, the manufacturing of the display device may start from the process shown in FIG. 6A1 and FIG. 6A2. The second film 927 is provided on the substrate 71 side of the separated LED chips 51, and the second film 927 is fixed to the second fixture 925, so that the manufacturing process can proceed to the process described below. In this case, as shown in FIG. 6A1 and FIG. 6A2, if a gap is provided between each LED chip 51, the accuracy of the later mounting process is improved, and the display device can be manufactured with a high yield, which is preferable. In addition, by arranging many LED chips 51 in a matrix shape within the second film 927, the manufacturing cost of the later mounting process can be reduced.

[0050] Next, ultraviolet light is applied from the first film 919 side, and the first film 919 and the first fixing tool 921 are separated from the LED chip 51 (FIGS. 6B1 and 6B2). In the process of separating the LED chip described above, the first film 919 may stretch and warp. By separating the LED chip 51 from the first film 919 and re-fixing it to the second film 927 with less warping, the accuracy of the subsequent mounting process can be improved, and display devices can be manufactured with a high yield.

[0051] It is preferable to use a film having elasticity as the second film 927. A film having elasticity is deformed by applying a force, and tends to return to its original shape when the force is removed. A film having a high tensile elasticity can be preferably used as the second film 927. Polyamide resin, polyimide resin, polyethylene naphthalate resin, etc. can be used as the second film 927. Furthermore, it is preferable that the second film 927 has high heat resistance. In addition, an adhesive is provided on the surface of the second film 927, and the LED chip substrate 900 can be fixed to the second film 927. For example, a ring-shaped jig as shown in FIG. 6B1 can be preferably used as the second fixing tool 925.

[0052] Here, it is preferable to inspect the LED chip 51. A visual inspection can be used to inspect the LED chip 51. Alternatively, a voltage may be applied between the electrodes 85 and 87 to inspect the light emission state from the LED chip 51. It is preferable to obtain position information within the second film 927 for LED chips 51 that are determined to be defective in the inspection. By obtaining the position information of the defective chips, the defective chips can be excluded from being mounted in the subsequent mounting process.

[0053] Next, a method for mounting the LED chip 51 on the circuit-bearing substrate 800 will be described.

[0054] 7 and 8 show an example of an apparatus 950 that can be used in the process of mounting an LED chip 51 on a substrate 800 having a circuit. Fig. 7 is a perspective view of the apparatus 950, and Fig. 8 is a schematic diagram showing the configuration of the apparatus 950. The apparatus 950 has a stage 951, a uniaxial robot 953 for the X-axis, a uniaxial robot 955 for the Y-axis, a gripping mechanism 959, a push-out mechanism 929, and a control device 961.

[0055] The stage 951 has a function of fixing the substrate 800. For example, a vacuum suction mechanism can be used to fix the substrate 800. The stage 951 can be moved in the XY directions on a plane parallel to the surface of the substrate 800 by the single-axis robot 953 and the single-axis robot 955.

[0056] The gripping mechanism 959 grips the second fixture 925 that fixes the LED chip 51 and the second film 927. The gripping mechanism 959 also has a function of moving the second fixture 925 that fixes the LED chip 51 and the second film 927 to an arbitrary position.

[0057] The push-out mechanism 929 has a function of moving up and down to place the LED chip 51 on the substrate 800. The push-out mechanism 929 has a columnar (including a cylindrical or polygonal columnar) shape, and may have a shape that is tapered on the side that comes into contact with the LED chip 51. The diameter of the tip of the push-out mechanism 929 that comes into contact with the LED chip 51 is preferably smaller than the width of the LED chip 51.

[0058] The control device 961 has a function of controlling the single-axis robot 953, the single-axis robot 955, the gripping mechanism 959, and the push-out mechanism 929. In addition, position information of LED chips determined to be defective in the previous inspection process of the LED chips 51 is input to the control device 961. By inputting the position information of the defective chips into the control device 961, the defective chips can be excluded from the targets for mounting.

[0059] The apparatus 950 is preferably provided with an alignment mechanism such as a camera 957. The position of the second fixture 925 is controlled based on an alignment marker or the like provided on the substrate 800.

[0060] A method for mounting the LED chip 51 on the circuit-bearing substrate 800 will be described in detail with reference to FIGS.

[0061] First, the LED chips 51 fixed to the second film 927 are opposed to the substrate 800 having the circuit. When the LED chips 51 are opposed to each other, it is preferable to detect the outline of the LED chips 51 by the camera 957 and obtain the position information of the LED chips 51. From the position information of the LED chips 51, the position of the LED chips 51 is adjusted by the gripping mechanism 959, and the positions of the electrodes 85 and 87 of the LED chips 51 and the electrodes 21 and 23 on the substrate 800 are aligned (FIG. 9A). It is preferable that the gripping mechanism 959 can move in the X direction, Y direction, and θ direction on a plane parallel to the surface of the substrate 800. By moving in the X direction, Y direction, and θ direction, the positions of the electrodes 85 and 87 of the LED chips 51 and the electrodes 21 and 23 on the substrate 800 can be aligned with high accuracy.

[0062] 8 shows a configuration in which the camera 957 is disposed above the second film 927 and detects the positions of the electrodes 85 and 87 of the LED chip 51 from above the second film 927, but an aspect of the present invention is not limited to this. Furthermore, a camera (not shown) may be disposed below the substrate 800 and the positions of the electrodes 85 and 87 of the LED chip 51 and the positions of the electrodes 21 and 23 on the substrate 800 may be detected from below the substrate 800.

[0063] Next, the extrusion mechanism 929 is pushed from the second film 927 side toward the substrate 800, so that the electrodes 85 and 21, and the electrodes 87 and 23 are brought into contact with each other. Then, ultrasonic waves are applied to the extrusion mechanism 929, and the electrodes 85 and 21, and the electrodes 87 and 23 are pressed together (FIG. 9B). Alternatively, the extrusion mechanism 929 may be heated, and the electrodes 85 and 21, and the electrodes 87 and 23 may be pressed together by heat. Alternatively, the electrodes may be pressed together by using ultrasonic waves and heat. When the extrusion mechanism 929 is heated, it is preferable to set the temperature of the extrusion mechanism 929 to a temperature equal to or lower than the heat-resistant temperature of the second film 927. By setting the temperature of the extrusion mechanism 929 to a temperature equal to or lower than the heat-resistant temperature of the second film 927, it is possible to prevent the second film 927 from being deformed and warped.

[0064] The extrusion mechanism 929 is connected to a unit 963 shown in Fig. 8. The unit 963 has an ultrasonic oscillator and can apply ultrasonic waves to the extrusion mechanism 929. Alternatively, the unit 963 has a heating mechanism and can apply heat to the extrusion mechanism 929. Alternatively, the unit 963 has an ultrasonic oscillator and a heating mechanism and may apply ultrasonic waves and heat to the extrusion mechanism 929. The unit 963 is connected to a control device 961, and the control device 961 controls the timing of application of ultrasonic waves and heating.

[0065] Alternatively, conductive bumps may be provided on the electrodes 21 and 23, and the LED chip 51 may be brought into contact with the bumps.

[0066] Next, the push-out mechanism 929 is moved away from the second film 927 (FIG. 9C). Since the electrodes 85 and 21, and the electrodes 87 and 23 are respectively pressed against each other, the LED chips 51 mounted on the electrodes 21 and 23 are separated from the second film 927. It is preferable that the adhesive strength of the adhesive provided on the surface of the second film 927 is smaller than the pressing force between the electrodes 85 and 21, and between the electrodes 87 and 23. By using an adhesive having an adhesive strength weaker than the pressing force for the second film 927, the LED chips 51 can be efficiently mounted on the substrate 800, and the manufacturing cost of the display device can be reduced.

[0067] Here, if the second film 927 is warped, it becomes difficult to align the electrodes 85 and 87 of the LED chip 51 with the electrodes 21 and 23 on the substrate 800, and poor conduction between the electrodes 85 and 87 and the electrodes 21 and 23 may occur. In one aspect of the present invention, the second film 927 has elasticity, and when the extrusion mechanism 929 is separated from the second film 927, the second film 927 can return to its original shape. By the second film 927 returning to its original shape, it is possible to suppress the second film 927 from warping, and it is possible to accurately align the positions of the electrodes 85 and 87 with the positions of the electrodes 21 and 23. The tensile elastic modulus of the second film 927 is preferably 3 GPa or more and 18 GPa or less, more preferably 5 GPa or more and 16 GPa or less, and even more preferably 7 GPa or more and 14 GPa or less. By setting the tensile modulus of the second film 927 within the aforementioned range, the second film 927 stretches appropriately when the LED chip 51 is brought into contact with the electrodes 21 and 23, and the sagging of the second film 927 can be reduced when the LED chip 51 is aligned, so that the display device can be manufactured with a high yield and the manufacturing costs can be reduced.

[0068] Next, the LED chip 51 fixed to the second film 927 is aligned with the electrodes 21 and 23 on which the LED chip 51 is not provided (FIG. 10A). At the time of alignment, any one or more of the stage 951, the gripping mechanism 959, and the extrusion mechanism 929 may be moved. It is more preferable to move any two or more of the stage 951, the gripping mechanism 959, and the extrusion mechanism 929. By moving any two or more of the stage 951, the gripping mechanism 959, and the extrusion mechanism 929, the accuracy of alignment between the electrodes 85 and 87 of the LED chip 51 and the electrodes 21 and 23 on the substrate 800 can be improved.

[0069] Next, the push-out mechanism 929 is pushed from the second film 927 side toward the substrate 800, so that the electrodes 85 and 21, and the electrodes 87 and 23 come into contact with each other. Then, the electrodes 85 and 21, and the electrodes 87 and 23 are pressed together ( FIG. 10B ). Then, the push-out mechanism 929 is moved away from the second film 927. As a result, the LED chips 51 mounted on the electrodes 21 and 23 are separated from the second film 927.

[0070] The above-mentioned operation is repeated to mount LED chips on the entire surface of the pixel portion of the substrate 800. Note that LED chips 51B determined to be defective in the inspection process of LED chips 51 have their position information input to the control device 961 and are not mounted on the substrate 800 (FIGS. 10C and 10D). By inputting the positions of the defective LED chips to the control device 961, only non-defective LED chips 51 can be mounted on the substrate 800.

[0071] In the manufacturing method of the display device according to one embodiment of the present invention, it is also possible to provide a plurality of types of LED chips 51 emitting colors in different wavelength regions on the substrate 800. For example, a case where an LED chip 51 emitting light in a red wavelength region (hereinafter referred to as red light), an LED chip 51 emitting light in a green wavelength region (hereinafter referred to as green light), and an LED chip 51 emitting light in a blue wavelength region (hereinafter referred to as blue light) are provided on the substrate 800 will be described. The LED chips 51 emitting red light are mounted on the substrate 800 using a second film 927 and a second fixture 925 to which the LED chips 51 are fixed. Next, the LED chips 51 emitting green light are mounted on the substrate 800 using a second film 927 and a second fixture 925 to which the LED chips 51 are fixed. Next, the LED chips 51 emitting blue light are mounted on the substrate 800 using the second film 927 to which the LED chips 51 are fixed and the second fixture 925. In this manner, the LED chips 51 emitting red light, the LED chips 51 emitting green light, and the LED chips 51 emitting blue light can be provided on the substrate 800. The order in which the types of LED chips are mounted is not particularly limited.

[0072] Although an example in which the LED chip 51 is mounted on the substrate 800 through one set of the second film 927 and the second fixture 925 has been shown, one aspect of the present invention is not limited to this. As shown in FIG. 11, a configuration in which the LED chip 51 is mounted on a plurality of sets of the second film 927 and the second fixture 925 may be used. With such a configuration, the display device 700 can be manufactured with high productivity. Also, FIG. 11 shows an example in which the LED chip 51 is mounted on four sets of the second film 927 and the second fixture 925, but any number of sets may be used.

[0073] The above is the description of the method for manufacturing the display device.

[0074] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0075] (Embodiment 2) In this embodiment, an example of a display device that can be manufactured by the manufacturing method of a display device according to one embodiment of the present invention described in Embodiment 1 will be described.

[0076] <Configuration example 1> FIG. 12A shows an example of a cross-sectional structure of a display device 10 that can be manufactured by the manufacturing method of a display device according to one embodiment of the present invention.

[0077] The display device 10 has a functional layer 15, a light-emitting element 17, a phosphor layer 35, a colored layer CFR, a colored layer CFG, and a colored layer CFB between a substrate 11 and a substrate 13. In Fig. 12A, the substrate 11 side corresponds to the display surface side of the display device 10.

[0078] As the light-emitting element 17, for example, a self-luminous light-emitting element such as an OLED (Organic Light Emitting Diode), an LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser can be used. In particular, since an LED has high brightness and contrast and a fast response speed, it can be suitably used as the light-emitting element 17, and a display device 10 with high brightness, contrast, and a fast response speed can be obtained. Since an LED is a self-luminous element, a backlight is not required, and a polarizing plate is also not required, so a display device with high brightness and low power consumption can be obtained. In addition, since the light-emitting layer of an LED is made of an inorganic material, it is less likely to deteriorate, and a display device with a long life can be obtained.

[0079] The functional layer 15 is a layer including a circuit for driving the light-emitting element 17. For example, the functional layer 15 includes a pixel circuit including a transistor, a capacitance element, wiring, an electrode, and the like. The functional layer 15 is electrically connected to the electrodes 21 and 23. That is, the functional layer 15 is electrically connected to the light-emitting element 17 via the electrodes 21 and 23.

[0080] Further, an insulating layer 25 is provided between the electrodes 21 and 23 and the functional layer 15. The electrodes 21 and 23 are electrically connected to the functional layer 15 through openings provided in the insulating layer 25. This electrically connects the functional layer 15 and the light-emitting element 17.

[0081] The display device 10 has an adhesive layer 27 between the electrodes 21 and 23 and the substrate 11. It can be said that the substrate 11 and the substrate 13 are bonded together by the adhesive layer 27. The adhesive layer 27 also functions as a sealing layer that seals the light-emitting element 17. In this way, the display device 10 has the light-emitting element 17 and the functional layer 15 that drives the light-emitting element between the pair of substrates.

[0082] On the substrate 13 side of the substrate 11, colored layers CFR, CFG, and CFB are provided at positions overlapping the light emitting elements 17. The colored layers CFR, CFG, and CFB function as color filters that transmit, for example, red, green, or blue light, respectively. Materials that can be used for the colored layers CFR, CFG, and CFB include metal materials, resin materials, and resin materials containing pigments or dyes.

[0083] A phosphor layer 35 is provided between the colored layers CFR, CFG, and CFB and each of the light-emitting elements 17. An organic resin layer mixed with a phosphor can be used as the phosphor layer 35. The phosphor contained in the phosphor layer 35 can be a material that is excited by the light emitted by the light-emitting element 17 and emits light of a complementary color to the light emitted by the light-emitting element 17. With this configuration, the light emitted by the light-emitting element 17 and the light emitted by the phosphor are combined, and the phosphor layer 35 can emit white light.

[0084] For example, the phosphor layer 35 has a phosphor that emits yellow light, and the light emitting element 17 emits blue light, so that white light is emitted from the phosphor layer 35. Therefore, the light emitted from the light emitting element 17 provided with the colored layer CFR passes through the phosphor layer 35 and the colored layer CFR, and is emitted to the display surface side as red light 20R. Similarly, the light emitted from the light emitting element 17 provided with the colored layer CFG is emitted as green light 20G, and the light emitted from the light emitting element 17 provided with the colored layer CFB is emitted as blue light 20B. This allows color display using one type of light emitting element 17. In addition, since only one type of light emitting element 17 is used in the display device, the manufacturing process can be simplified. In other words, according to one embodiment of the present invention, a display device with high brightness and contrast, high response speed, and low power consumption can be obtained at low manufacturing costs.

[0085] For example, the phosphor layer 35 may have a phosphor that emits red light, and the light emitting element 17 may emit blue-green light, so that white light is emitted from the phosphor layer 35.

[0086] In addition, the phosphor layer 35 may be configured to have a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light, and the light-emitting element 17 may be configured to emit near-ultraviolet light or purple light, so that white light is emitted from the phosphor layer 35.

[0087] Although a configuration in which one color is expressed by three sub-pixels of red (R), green (G), and blue (B) has been shown, one embodiment of the present invention is not limited to this. There is no particular limitation on the color elements, and colors other than RGB may be used. For example, it may be composed of yellow (Y), cyan (C), magenta (M), etc.

[0088] Also, as in the display device 10A shown in FIG. 12B, it is preferable to provide a light-shielding layer 33 adjacent to the light-emitting element 17. It is preferable to provide the light-shielding layer 33 between adjacent light-emitting elements 17. By providing the light-shielding layer 33 between adjacent light-emitting elements 17, it is possible to suppress light leakage to adjacent pixels and color mixing between pixels. The light-shielding layer 33 can be made of a resin containing a pigment, a dye, or carbon black. Furthermore, it is preferable that the side surface of the light-emitting element 17 is in contact with the light-shielding layer 33. By covering the side surface of the light-emitting element 17 with the light-shielding layer 33, it is possible to suppress light leakage to adjacent pixels and color mixing between pixels. Note that, although FIG. 12B shows a configuration in which the height of the upper surface of the light-shielding layer 33 and the height of the upper surface of the light-emitting element 17 are approximately the same, one embodiment of the present invention is not limited thereto. The height of the upper surface of the light-shielding layer 33 may be lower than the height of the upper surface of the light-emitting element 17. It may also be higher than the height of the upper surface of the light-emitting element 17. By making the height of the upper surface of the light-shielding layer 33 approximately equal to or higher than the height of the upper surface of the light-emitting element 17, light leakage into adjacent pixels and color mixing between pixels can be efficiently suppressed.

[0089] 12B shows a case where there is a gap between the light-emitting element 17 and the phosphor layer 35, but one embodiment of the present invention is not limited thereto. As in a display device 10B shown in FIG. 12C, the light-emitting element 17 may be in contact with the phosphor layer 35. With this configuration, the distance between the colored layer CFR, the colored layer CFG, and the colored layer CFB and each of the light-emitting elements 17 is shortened, and light leakage to adjacent pixels and color mixing between pixels can be suppressed.

[0090] Also, as in the display device 10C shown in FIG. 13A, a light-shielding layer 31 may be provided. The light-shielding layer 31 is provided between adjacent colored layers. Also, the light-shielding layer 31 has an opening in an area overlapping with the light-emitting element 17. The light-shielding layer 31 blocks light emitted from the adjacent light-emitting element 17 and suppresses color mixing between the adjacent light-emitting elements 17. Here, by providing each end of the colored layer CFR, the colored layer CFG, and the colored layer CFB so as to overlap with the light-shielding layer 31, light leakage can be suppressed. As the light-shielding layer 31, a material that blocks light emitted from the light-emitting element 17 can be used, and for example, a metal material or a resin material containing a pigment or dye can be used.

[0091] Also, as in the display device 10D shown in FIG. 13B, each colored layer may be configured to partially overlap with the adjacent colored layer. Each area where the colored layers overlap functions as a light-shielding layer. Note that, in FIG. 13B, an example is shown in which one end of the colored layer CFR overlaps one end of the colored layer CFG, the other end of the colored layer CFG overlaps one end of the colored layer CFB, and the other end of the colored layer CFB overlaps the other end of the colored layer CFR, but one embodiment of the present invention is not limited thereto.

[0092] 13C, a pixel not including a colored layer may be formed, and white light 20W may be emitted from the pixel. With this configuration, one color may be expressed by four sub-pixels of R (red), G (green), B (blue), and W (white). With this configuration, the current flowing through the light-emitting element 17 may be reduced compared to a configuration in which one color is expressed by three sub-pixels of red (R), green (G), and blue (B), resulting in a display device with low power consumption.

[0093] A light emitting diode chip (hereinafter also referred to as an LED chip) that can be used as the light emitting element 17 will be described.

[0094] The LED chip has a light emitting diode. The structure of the light emitting diode is not particularly limited, and may be a MIS (Metal Insulator Semiconductor) junction, or a homo structure, hetero structure, or double hetero structure having a PN junction or a PIN junction. Also, a superlattice structure, or a single quantum well structure or a multi-quantum well (MQW: Multi Quantum Well) structure in which thin films that generate a quantum effect are stacked may be used. Also, an LED chip using nanocolumns may be used.

[0095] Examples of LED chips are shown in Figs. 14A and 14B. Fig. 14A shows a cross-sectional view of the LED chip 51, and Fig. 14B shows a top view of the LED chip 51. The LED chip 51 has a semiconductor layer 81 and the like. The semiconductor layer 81 has an n-type semiconductor layer 75, a light-emitting layer 77 on the n-type semiconductor layer 75, and a p-type semiconductor layer 79 on the light-emitting layer 77. As a material for the p-type semiconductor layer 79, a material having a band gap energy larger than that of the light-emitting layer 77 and capable of confining carriers in the light-emitting layer 77 can be used. In addition, the LED chip 51 has an electrode 85 functioning as a cathode on the n-type semiconductor layer 75, an electrode 83 functioning as a contact electrode on the p-type semiconductor layer 79, and an electrode 87 functioning as an anode on the electrode 83. In addition, it is preferable that the upper surface and side surface of the electrode 83 are covered with an insulating layer 89. The insulating layer 89 functions as a protective film for the LED chip 51.

[0096] Fig. 14C shows an example of an enlarged view of semiconductor layer 81. As shown in Fig. 14C, n-type semiconductor layer 75 may have an n-type contact layer 75a on the substrate 71 side and an n-type clad layer 75b on the light emitting layer 77 side. P-type semiconductor layer 79 may have a p-type clad layer 79a on the light emitting layer 77 side and a p-type contact layer 79b on p-type clad layer 79a.

[0097] The light-emitting layer 77 may have a multiple quantum well (MQW) structure in which barrier layers 77a and well layers 77b are stacked multiple times. The barrier layers 77a are preferably made of a material having a larger band gap energy than the well layers 77b. With this configuration, energy can be confined in the well layers 77b, improving the quantum efficiency and the light-emitting efficiency of the LED chip 51.

[0098] In the face-up type LED chip 51, the electrode 83 may be made of a material that transmits light, such as oxides such as ITO (In2O3-SnO2), AZO (Al2O3-ZnO), In-Zn oxide (In2O3-ZnO), GZO (GeO2-ZnO), and ICO (In2O3-CeO2). In the face-up type LED chip 51, light is mainly emitted toward the electrode 87. In the face-down type LED chip 51, the electrode 83 may be made of a material that reflects light, such as metals such as silver, aluminum, and rhodium. In the face-down type LED chip 51, light is mainly emitted toward the substrate 71.

[0099] The substrate 71 may be made of oxide single crystals such as sapphire single crystal (Al2O3), spinel single crystal (MgAl2O4), ZnO single crystal, LiAlO2 single crystal, LiGaO2 single crystal, MgO single crystal, Si single crystal, SiC single crystal, GaAs single crystal, AlN single crystal, GaN single crystal, or boride single crystal such as ZrB2. In the face-down type LED chip 51, the substrate 71 is preferably made of a light-transmitting material, and may be made of, for example, sapphire single crystal.

[0100] A buffer layer (not shown) may be provided between the substrate 71 and the n-type semiconductor layer 75. The buffer layer has a function of reducing the difference in lattice constant between the substrate 71 and the n-type semiconductor layer 75.

[0101] The LED chip 51 that can be used as the light-emitting element 17 preferably has a horizontal structure in which the electrodes 85 and 87 are arranged on the same surface side as shown in FIG. 14A. By providing the electrodes 85 and 87 of the LED chip 51 on the same surface side, connection with the electrodes 21 and 23 is facilitated, and the structures of the electrodes 21 and 23 can be simplified. Furthermore, the LED chip 51 that can be used as the light-emitting element 17 is preferably a face-down type. By using a face-down type LED chip 51, light emitted from the LED chip 51 is efficiently emitted to the display surface side of the display device, resulting in a display device with high brightness. A commercially available LED chip may be used as the LED chip 51.

[0102] The phosphor contained in the phosphor layer 35 may be an organic resin layer with a phosphor printed or painted on the surface, an organic resin layer mixed with a phosphor, etc. The phosphor layer 35 may be made of a material that is excited by the light emitted by the LED chip 51 and emits light of a complementary color to the light emitted by the LED chip 51. With this configuration, the light emitted by the light emitting element 17 and the light emitted by the phosphor are combined, and white light can be emitted from the phosphor layer 35.

[0103] For example, by using an LED chip 51 that emits blue light and a phosphor that emits yellow light, which is the complementary color of blue, it is possible to configure the phosphor layer 35 to emit white light. A representative example of the LED chip 51 capable of emitting blue light is a diode made of a group 13 nitride-based compound semiconductor. One example is an In x Al y Ga 1-x-y N (x is 0 or more and 1 or less, y is 0 or more and 1 or less, x + y is 0 or more and 1 or less). A typical example of a phosphor that is excited by blue light and emits yellow light is Y3Al5O 12 :Ce(YAG:Ce), (Ba,Sr,Mg)2SiO4:Eu,Mn, etc.

[0104] For example, a configuration can be made in which LED chip 51 that emits blue-green light and a phosphor that emits red light, which is the complementary color of blue-green, are used, and white light is emitted from phosphor layer 35.

[0105] The phosphor layer 35 may have a plurality of types of phosphors, and each of the phosphors may emit light of a different color. For example, the phosphor layer 35 may be configured to emit white light by using an LED chip 51 that emits blue light, a phosphor that emits red light, and a phosphor that emits green light. Representative examples of phosphors that are excited by blue light and emit red light include (Ca,Sr)S:Eu, Sr2Si7Al3ON 13 Representative examples of phosphors that are excited by blue light and emit green light are SrGa2S4:Eu, Sr3Si 13 Al3O2N 21 :Eu, etc.

[0106] Also, by using the LED chip 51 that emits near-ultraviolet light or violet light, and a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light, a configuration can be made in which white light is emitted from the phosphor layer 35. Representative examples of phosphors that are excited by near-ultraviolet light or violet light and emit red light include (Ca,Sr)S:Eu, Sr2Si7Al3ON 13 Representative examples of phosphors that are excited by near-ultraviolet or violet light and emit green light include SrGa2S4:Eu, Sr3Si 13 Al3O2N 21 A typical example of a phosphor that is excited by near-ultraviolet or violet light and emits blue light is Sr 10 (PO4)6Cl2:Eu, (Sr,Ba,Ca) 10 (PO4)6Cl2:Eu, etc.

[0107] In addition, the near-ultraviolet light has a maximum peak at a wavelength of 200 nm to 380 nm in the emission spectrum. In addition, the violet light has a maximum peak at a wavelength of 380 nm to 430 nm in the emission spectrum. In addition, the blue light has a maximum peak at a wavelength of 430 nm to 490 nm in the emission spectrum. In addition, the green light has a maximum peak at a wavelength of 490 nm to 550 nm in the emission spectrum. In addition, the yellow light has a maximum peak at a wavelength of 550 nm to 590 nm in the emission spectrum. In addition, the red light has a maximum peak at a wavelength of 640 nm to 770 nm in the emission spectrum.

[0108] When the phosphor layer 35 has a phosphor that emits yellow light and the LED chip 51 that emits blue light is used, the light emitted by the LED chip 51 preferably has a maximum peak at a wavelength of 330 nm to 500 nm in the emission spectrum, more preferably has a maximum peak at a wavelength of 430 nm to 490 nm, and even more preferably has a maximum peak at a wavelength of 450 nm to 480 nm. This allows the phosphor to be excited efficiently. Furthermore, since the light emitted by the LED chip 51 has a maximum peak at 430 nm to 490 nm in the emission spectrum, the blue light that is the excitation light and the yellow light from the phosphor can be mixed to produce white light. Furthermore, since the light emitted by the LED chip 51 has a maximum peak at 450 nm to 480 nm, a highly pure white light can be produced.

[0109] Various optical members may be disposed on the outside of the substrate 11. Examples of optical members include a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light collecting film. In addition, an antistatic film that suppresses adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, etc. may be disposed on the outside of the substrate 11.

[0110] Furthermore, a touch sensor may be provided outside the substrate 11. This allows a configuration including the display device 10 and the touch sensor to function as a touch panel.

[0111] <Configuration example 2> A structure different from the above-described display device will be described below. An LED package can be used as the light-emitting element 17 included in the display device which is one embodiment of the present invention.

[0112] An LED package that can be used for the light emitting element 17 will be described.

[0113] The light emitting element 17 may be a conventional LED package such as a bullet type or a surface mount (SMD: Surface Mount Device) type LED package. It is particularly preferable to use a surface mount type LED package as the light emitting element 17. An example of a surface mount type LED package is shown in FIG. 15A and FIG. 15B. FIG. 15A shows a cross-sectional view of an LED package 50, and FIG. 15B shows a top view of the LED package 50. The LED package 50 has an LED chip 51 on a substrate 52, an electrode 55, and an electrode 57. The LED chip 51 is electrically connected to the electrode 55 and the electrode 57 via a wire 59 and a wire 61. In addition, a phosphor 65 and a resin layer 63 having translucency are provided on the LED chip 51. The substrate 52 and the LED chip 51 are bonded together with an adhesive layer 67. A commercially available LED package may be used as the light emitting element 17.

[0114] The LED package that can be used for the light emitting element 17 has a light emitting area of ​​1 mm 2 Less than 10000μm, preferably 2 Less than or equal to 3000 μm, more preferably 3000 μm 2 Less than 700 μm, more preferably 2 In this specification, the area of ​​the light emitting region is 10,000 μm or less. 2 The following LED packages may be referred to as micro LEDs.

[0115] The substrate 52 may be a glass epoxy resin substrate, a polyimide substrate, a ceramic substrate, an alumina substrate, an aluminum nitride substrate, or the like.

[0116] The phosphor 65 may be an organic resin layer with a phosphor printed or painted on the surface, or an organic resin layer mixed with a phosphor. The phosphor 65 may be a material that is excited by the light emitted by the LED chip 51 and emits light of a complementary color to the light emitted by the LED chip 51. With this configuration, the LED package 50 can emit white light. The phosphor 65 will not be described in detail because the description of the phosphor contained in the phosphor layer 35 can be applied.

[0117] For example, a configuration can be made in which the LED package 50 emits white light by using an LED chip 51 that emits blue-green light and a phosphor that emits red light, which is the complementary color of blue-green.

[0118] In addition, a configuration in which white light is emitted from the LED package 50 can be made using an LED chip 51 that emits near-ultraviolet light or purple light, a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light.

[0119] When the LED chip 51 that emits blue light and the phosphor 65 that emits yellow light are used as the LED package 50, the light emitted by the LED chip 51 preferably has a maximum peak at a wavelength of 330 nm to 500 nm in the emission spectrum, more preferably has a maximum peak at a wavelength of 430 nm to 490 nm, and even more preferably has a maximum peak at a wavelength of 450 nm to 480 nm. This allows the phosphor 65 to be excited efficiently. Furthermore, since the light emitted by the LED chip 51 has a maximum peak at 430 nm to 490 nm in the emission spectrum, the blue light that is the excitation light and the yellow light from the phosphor 65 can be mixed to produce white light. Furthermore, since the light emitted by the LED chip 51 has a maximum peak at 450 nm to 480 nm, a highly pure white light can be produced.

[0120] The resin layer 63 is formed of a light-transmitting organic resin. There is no particular limitation on the type of organic resin, and typically, an ultraviolet-curable resin such as an epoxy resin or a silicone resin, a visible-light-curable resin, or the like can be used as appropriate. Note that, although the upper surface of the resin layer 63 is shown to have a flat shape in FIG. 15A, one embodiment of the present invention is not limited thereto. For example, the upper surface of the resin layer 63 may have a convex shape. An appropriate shape can be selected depending on the desired directivity.

[0121] The wires 59 and 61 may be thin metal wires made of gold, an alloy containing gold, copper, or an alloy containing copper.

[0122] The electrodes 55 and 57 are conductive layers electrically connected to the electrodes of the LED chip 51, and are made of an element selected from nickel, copper, silver, platinum, or gold, or an alloy material containing 50% or more of the element. The electrodes 55 and 57 are connected to the electrodes of the LED chip 51 by wire bonding using thermocompression bonding or ultrasonic bonding.

[0123] It is preferable to arrange a reflector 53 made of ceramic or the like around the LED chip 51, and to reflect a part of the light emitted from the LED chip 51, so that more light is emitted from the LED package 50. Note that, although Fig. 15A shows the reflector 53 in a tapered shape that spreads upward, one embodiment of the present invention is not limited to this. An appropriate shape can be selected depending on the desired light directivity.

[0124] Note that, although the LED package 50 shown in FIG. 15A has a configuration using a face-up type LED chip that emits light to the electrode side of the LED chip 51, the configuration of the LED package 50 that can be used in one embodiment of the present invention is not particularly limited.

[0125] An example different from the LED package illustrated in FIG. 15A is shown in FIG. 15C. FIG. 15C is a cross-sectional view of the LED package 50. FIG. 15B can be used as the top view. The LED package 50 shown in FIG. 15C is a flip-chip type LED package in which the electrode of the LED chip 51 faces the electrode 55 and the electrode 57. The electrode of the LED chip 51 faces the electrode 55 and the electrode 57 via a conductive bump 90. The LED package 50 shown in FIG. 15C shows a configuration using a face-down type LED chip that emits light to the opposite side of the electrode of the LED chip 51. In addition, although FIG. 15A and FIG. 15C show the LED chip 51 with a horizontal structure, one aspect of the present invention is not limited to this. The LED chip 51 of the LED package 50 may have a vertical structure in which the electrode 85 and the electrode 87 are arranged on the opposite sides.

[0126] 15 shows an example in which the LED package 50 has one LED chip 51, but the configuration of the LED package 50 that can be used in one embodiment of the present invention is not limited to this. The LED package 50 may have multiple LED chips 51. Also, a configuration without phosphor 65 is possible. For example, a configuration without phosphor 65 may be used in which an LED chip 51 that emits red light, an LED chip 51 that emits green light, and an LED chip 51 that emits green light are included, so that white light is emitted from the LED package 50.

[0127] The configuration of a display device that uses an LED package 50 as the light emitting element 17 will be described.

[0128] An example of a cross-sectional configuration of a display device according to one embodiment of the present invention is shown in FIG. 16A. The display device 10F shown in FIG. 16A has a functional layer 15, a light-emitting element 17, a colored layer CFR, a colored layer CFG, and a colored layer CFB between a substrate 11 and a substrate 13. The display device 10F is mainly different from the display devices using LED chips for the light-emitting element 17 shown in FIG. 12A to FIG. 12C and FIG. 13A to FIG. 13C in that the display device 10F does not have a phosphor layer 35 and a light-shielding layer 33. In FIG. 16A, the substrate 11 side corresponds to the display surface side of the display device 10F.

[0129] The LED package 50 has a reflector 53 to enhance the directivity of light, and when the LED package 50 is used as the light-emitting element 17, light leakage to adjacent pixels and color mixing between pixels can be suppressed without providing a light-shielding layer 33. In addition, by using the LED package 50 that emits white light as the light-emitting element 17, color display can be achieved without providing a phosphor layer 35.

[0130] 16A shows a case where there is a gap between the colored layer CFR, the colored layer CFG, and the colored layer CFB and the light-emitting element 17, but one embodiment of the present invention is not limited to this. The colored layer CFR, the colored layer CFG, and the colored layer CFB may be in contact with the light-emitting element 17. With this configuration, the distance between the colored layer CFR, the colored layer CFG, and the colored layer CFB and each of the light-emitting elements 17 is shortened, and light leakage to adjacent pixels and color mixing between pixels can be suppressed.

[0131] Also, as in the display device 10G shown in FIG. 16B, a light-shielding layer 31 may be provided. The light-shielding layer 31 is provided between adjacent colored layers. Also, the light-shielding layer 31 has an opening in an area overlapping with the light-emitting element 17. The light-shielding layer 31 blocks light emitted from the adjacent light-emitting element 17 and suppresses color mixing between the adjacent light-emitting elements 17. Here, by providing the ends of the colored layer CFR, the colored layer CFG, and the colored layer CFB so as to overlap with the light-shielding layer 31, light leakage can be suppressed. As the light-shielding layer 31, a material that blocks light emitted from the light-emitting element 17 can be used, and for example, a metal material or a resin material containing a pigment or dye can be used.

[0132] Also, as in the display device 10H shown in FIG. 16C, each colored layer may be configured to partially overlap with the adjacent colored layer. Each area where the colored layers overlap functions as a light-shielding layer. Note that FIG. 16C shows an example in which one end of the colored layer CFR overlaps one end of the colored layer CFG, the other end of the colored layer CFG overlaps one end of the colored layer CFB, and the other end of the colored layer CFB overlaps the other end of the colored layer CFR, but one embodiment of the present invention is not limited thereto.

[0133] Furthermore, a pixel not including a colored layer can be formed, and a configuration in which white light is emitted from the pixel can be adopted. With such a configuration, one color can be expressed by four sub-pixels of R (red), G (green), B (blue), and W (white). With such a configuration, the current flowing through the light-emitting element 17 can be reduced compared to a configuration in which one color is expressed by three sub-pixels of red (R), green (G), and blue (B), and a display device with low power consumption can be obtained.

[0134] The above is a description of the configuration example.

[0135] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0136] (Embodiment 3) In this embodiment, an example of the display device illustrated in the above embodiment will be described in detail.

[0137] <Configuration example> 17A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 attached to each other with a sealant 712. A pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided over the first substrate 701 in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0138] In addition, an FPC terminal portion 708 to which an FPC 716 is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. The FPC 716 supplies various signals and the like to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 via the FPC terminal portion 708 and signal lines 710.

[0139] There may be a plurality of gate driver circuits 706. The gate driver circuits 706 and the source driver circuits 704 may each be formed separately on a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0140] The configuration of the transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is not particularly limited. As the semiconductor layer of the transistor, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used. In addition, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, or an organic semiconductor can be used.

[0141] When an organic semiconductor is used as the semiconductor layer, a low molecular weight organic material having an aromatic ring, a π-electron conjugated conductive polymer, etc., can be used, such as rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylenevinylene, etc.

[0142] The transistor used in this embodiment preferably has an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies is suppressed. The off-state current of the transistor can be reduced. Thus, the retention time of an electric signal such as an image signal can be increased, and the writing interval in an on state can be set to be long. Thus, the frequency of a refresh operation can be reduced, which leads to an effect of reducing power consumption.

[0143] In addition, the transistor used in this embodiment mode can achieve high-speed operation because it has a relatively high field-effect mobility. For example, by using such a transistor capable of high-speed operation in a display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. In other words, a configuration without using a driver circuit formed using a silicon wafer or the like is possible, and the number of components in a semiconductor device can be reduced. In addition, by using a transistor capable of high-speed operation in the pixel portion, a high-quality image can be provided.

[0144] A display device 700A shown in FIG. 17B is an example of a display device in which a flexible resin layer 743 is applied instead of the first substrate 701 and which can be used as a flexible display.

[0145] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in region P1 in FIG. 17B, the pixel section 702 and the resin layer 743 have cutouts formed by cutting out parts of the pixel section 702 and the resin layer 743. A pair of gate driver circuit sections 706 are provided on both sides of the pixel section 702. The gate driver circuit sections 706 are provided at the corners of the pixel section 702 along the arc-shaped contour.

[0146] The resin layer 743 has a protruding shape at a portion where the FPC terminal portion 708 is provided. A portion of the resin layer 743 including the FPC terminal portion 708 can be folded back to the rear side in an area P2 in Fig. 17B. By folding back a portion of the resin layer 743, the display device 700A can be mounted on an electric device with the FPC 716 disposed so as to overlap the rear side of the pixel portion 702, thereby enabling space saving of the electronic device.

[0147] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. In this case, the source driver circuit unit 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.

[0148] 17C is a display device that can be suitably used in electronic devices having large screens, such as television devices, monitor devices, personal computers (including notebook and desktop computers), tablet terminals, and digital signage.

[0149] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.

[0150] The multiple source driver ICs 721 are each attached to an FPC 723. One terminal of each of the multiple FPCs 723 is connected to the substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on the electrical device, thereby enabling space saving in the electronic device.

[0151] On the other hand, the gate driver circuit section 722 is formed on the substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0152] With this configuration, a large-sized, high-resolution display device can be realized. For example, a display device with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more can be realized. Also, a display device with an extremely high resolution such as 4K2K or 8K4K resolution can be realized.

[0153] <Cross-section configuration example 1> FIG. 18 is a cross-sectional view taken along dashed line QR shown in FIG. 17A.

[0154] 17A and 18 includes a wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752.

[0155] The capacitor 790 shown in FIG. 18 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has a low resistance like the source and drain regions of the transistor 750. A part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower and upper electrodes. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. A wiring obtained by processing the same film as the source and drain electrodes of the transistor is connected to the upper electrode.

[0156] Further, an insulating layer 770 is provided over the transistor 750, the transistor 752, and the capacitor 790. The insulating layer 770 functions as a planarizing film and can flatten the top surfaces of the conductive layer 772 and the conductive layer 774 provided over the insulating layer 770. Since the conductive layer 772 and the conductive layer 774 are located on the same plane and the top surfaces of the conductive layer 772 and the conductive layer 774 are flat, the conductive layer 772 and the conductive layer 774 can be easily electrically connected to the light-emitting element 782.

[0157] The conductive layers 772 and 774 are electrically connected to the light-emitting element 782 via conductive bumps 791 and 793. Fig. 18 shows a configuration in which the heights of the cathode side electrode and the anode side electrode of the light-emitting element 782 are different, and the heights of the bumps 791 and 793 are also different. Note that when the heights of the cathode side electrode and the anode side electrode of the light-emitting element 782 are the same, the heights of the bumps 791 and 793 can be approximately the same.

[0158] 18, the transistor 750 included in the pixel portion 702 is preferably provided so as to overlap under the conductive layer 772. By having the transistor 750, particularly a region where the channel formation region and the conductive layer 772 overlap, light emitted from the light-emitting element 782 and external light can be prevented from reaching the transistor 750, and fluctuations in the electrical characteristics of the transistor 750 can be suppressed.

[0159] The transistor 750 in the pixel portion 702 and the transistor 752 in the source driver circuit portion 704 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other. Note that the gate driver circuit portion 706 is similar to the source driver circuit portion 704.

[0160] The signal line 710 is formed of the same conductive film as the source and drain electrodes of the transistors 750 and 752. In this case, it is preferable to use a low-resistance material such as a material containing copper, because signal delays caused by wiring resistance are small and display on a large screen is possible.

[0161] The FPC terminal portion 708 has a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752.

[0162] A flexible substrate such as a glass substrate or a plastic substrate can be used as the first substrate 701 and the second substrate 705. When a flexible substrate is used as the first substrate 701, an insulating layer having a barrier property against water and hydrogen is preferably provided between the first substrate 701 and the transistor 750 or the like.

[0163] Further, on the second substrate 705 side, a light-shielding layer 738, a coloring layer 736, and a phosphor layer 797 are provided. The coloring layer 736 is provided on the light-emitting element 782. The phosphor layer 797 is provided between the light-emitting element 782 and the coloring layer 736. Further, the phosphor layer 797, the light-emitting element 782, and the coloring layer 736 have mutually overlapping regions. As shown in FIG. 18, it is preferable that the end of the phosphor layer 797 is located outside the end of the light-emitting element 782, and the end of the coloring layer 736 is located outside the end of the phosphor layer 797. With such a configuration, it is possible to suppress light leakage to adjacent pixels and color mixing between pixels. Furthermore, by providing the light-shielding layer 738 between adjacent coloring layers 736, it is possible to reduce reflection of external light and provide a display device with high contrast.

[0164] For example, the phosphor layer 797 has a phosphor that emits yellow light, and the light-emitting element 782 emits blue light, so that white light is emitted from the phosphor layer 797. Light emitted from the light-emitting element 782 provided in a region overlapping with the coloring layer 736 that transmits red light passes through the phosphor layer 797 and the coloring layer 736, and is emitted to the display surface side as red light. Similarly, light emitted from the light-emitting element 782 provided in a region overlapping with the coloring layer 736 that transmits green light is emitted as green light. Light emitted from the light-emitting element 782 provided in a region overlapping with the coloring layer 736 that transmits blue light is emitted as blue light. This allows color display to be performed using one type of light-emitting element 782. In addition, since only one type of light-emitting element 782 is used in the display device, the manufacturing process can be simplified. In other words, according to one embodiment of the present invention, a display device that has high luminance and contrast, a fast response speed, and low power consumption at low manufacturing cost can be obtained.

[0165] For example, phosphor layer 797 may have a phosphor that emits red light, and light emitting element 782 may emit blue-green light, so that white light is emitted from phosphor layer 797.

[0166] In addition, the phosphor layer 797 may have a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light, and the light-emitting element 782 may be configured to emit near-ultraviolet light or purple light, so that white light is emitted from the phosphor layer 797.

[0167] The display device 700 shown in Fig. 18 has a light emitting element 782. As the light emitting element 782, it is preferable to use a horizontally structured, face-down type LED chip as exemplified in Fig. 14.

[0168] The colored layer 736 is provided at a position overlapping with the light-emitting element 782, and the light-shielding layer 738 is provided at a position overlapping with an end of the colored layer 736, in the lead-out wiring portion 711, and in the source driver circuit portion 704. The spaces between the phosphor layer 797, the colored layer 736, and the light-shielding layer 738 and the light-emitting element 782 are filled with a sealing film 732.

[0169] The light-shielding layer 795 is provided adjacent to the light-emitting element 782. The light-shielding layer 795 is preferably provided between adjacent light-emitting elements 782. By providing the light-shielding layer 795 between adjacent light-emitting elements 782, light leakage to adjacent pixels and color mixing between pixels can be suppressed. The light-shielding layer 795 can be made of a resin containing a pigment, a dye, carbon black, or the like. Furthermore, it is preferable that the side surface of the light-emitting element 782 be in contact with the light-shielding layer 795. By covering the side surface of the light-emitting element 782 with the light-shielding layer 795, light leakage to adjacent pixels and color mixing between pixels can be suppressed. Note that FIG. 18 shows a configuration in which the height of the top surface of the light-shielding layer 795 and the height of the top surface of the light-emitting element 782 are approximately the same, but one embodiment of the present invention is not limited thereto. The height of the top surface of the light-shielding layer 795 may be lower than the height of the top surface of the light-emitting element 782 or higher than the height of the top surface of the light-emitting element 782. By making the height of the upper surface of the light-shielding layer 795 approximately equal to or higher than the height of the upper surface of the light-emitting element 782, light leakage into adjacent pixels and color mixing between pixels can be efficiently suppressed.

[0170] A configuration of a display device that can be suitably applied to a flexible display is shown in Fig. 19. Fig. 19 is a cross-sectional view taken along dashed line ST in display device 700A shown in Fig. 17B.

[0171] 19 has a stacked structure of a supporting substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 instead of the substrate 701 shown in FIG. 19. The transistor 750, the capacitor 790, and the like are provided over the insulating layer 744 provided over the resin layer 743.

[0172] The support substrate 745 is a substrate that contains an organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer that contains an organic resin such as polyimide or acrylic. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0173] 19 has a protective layer 740 instead of the substrate 705 shown in FIG. 18. The protective layer 740 is bonded to a sealing film 732. A glass substrate, a resin film, or the like can be used as the protective layer 740. In addition, an optical member such as a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be used as the protective layer 740.

[0174] FIG. 19 also shows a bendable region P2. In the region P2, in addition to the support substrate 745 and the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. By providing as little inorganic insulating film as possible in the bendable region P2 and by using a configuration in which only a conductive layer containing a metal or alloy and a layer containing an organic material are laminated, it is possible to prevent cracks from occurring when the display device 700A is bent. Furthermore, by not providing the support substrate 745 in the region P2, a part of the display device 700A can be bent with an extremely small radius of curvature.

[0175] A description will be given of an example of a method for manufacturing the display device 700 shown in Fig. 18. Each of the drawings shown in Fig. 20 to Fig. 23 is a schematic cross-sectional view at each stage of the process related to the method for manufacturing the display device 700.

[0176] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the display device can be formed by sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. The CVD method may be plasma enhanced chemical vapor deposition (PECVD) or thermal CVD. As an example of the thermal CVD method, metal organic chemical vapor deposition (MOCVD) may be used.

[0177] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the display device can be formed by spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, knife coating, etc.

[0178] In addition, when processing the thin film constituting the display device, it can be processed using a photolithography method or the like. Alternatively, an island-shaped thin film may be formed by a film formation method using a shielding mask. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. There are, for example, two photolithography methods. One is a method in which a photosensitive resist material is applied onto the thin film to be processed, exposed through a photomask, and developed to form a resist mask, and the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into a desired shape.

[0179] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0180] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0181] <Formation of transistors, etc.> First, the conductive layer 301, the conductive layer 303, and the conductive layer 305 are formed over a substrate 701. The conductive layer 301, the conductive layer 303, and the conductive layer 305 can be formed in such a manner that a conductive film is formed, a resist mask is formed, the conductive film is etched, and then the resist mask is removed.

[0182] Subsequently, the insulating layer 311 is formed to cover the substrate 701 , the conductive layer 301 , the conductive layer 303 and the conductive layer 305 .

[0183] Next, the semiconductor layer 321, the semiconductor layer 323, and the semiconductor layer 325 are formed (FIG. 20A). The semiconductor layer 321, the semiconductor layer 323, and the semiconductor layer 325 can be formed by forming a semiconductor film, forming a resist mask, etching the semiconductor film, and then removing the resist mask.

[0184] Subsequently, the insulating layer 331, the conductive layer 341, the conductive layer 351, the insulating layer 333, the conductive layer 343, and the conductive layer 353 are formed. After forming an insulating film which is to be the insulating layer 331 and the insulating layer 333, a conductive film which is to be the conductive layer 341 and the conductive layer 343, and a conductive film which is to be the conductive layer 351 and the conductive layer 353, a resist mask is formed, the insulating film and the conductive film are etched, and then the resist mask is removed, whereby the insulating layer 331, the conductive layer 341, the conductive layer 351, the insulating layer 333, the conductive layer 343, and the conductive layer 353 can be formed.

[0185] Subsequently, an insulating layer 361 and an insulating layer 363 are formed (FIG. 20B).

[0186] Next, openings are formed in the insulating layer 361 and the insulating layer 363, and the conductive layer 371, the conductive layer 373a, the conductive layer 373b, the conductive layer 375, the conductive layer 377, and the wiring 760 are formed. The conductive layer 371, the conductive layer 373a, the conductive layer 373b, the conductive layer 375, the conductive layer 377, and the wiring 760 can be formed by a method similar to that for the conductive layer 301 and the like.

[0187] Through the above steps, the signal line 710, the transistor 750, the capacitor 790, and the transistor 752 can be formed (FIG. 20C). Then, an insulating layer 379 is formed. The insulating layer 379 functions as a protective film for the transistor 750 and the like.

[0188] Formation of Insulating Layer 770 Next, the insulating layer 770 is formed. By using a photosensitive material for the insulating layer 770, an opening can be formed by a photolithography method or the like. Note that the insulating layer 770 may be formed by forming an insulating film and then etching part of the insulating film using a resist mask to form the opening. It is preferable to use an organic insulating material for the insulating layer 770 because the flatness of the upper surface can be improved.

[0189] Alternatively, an inorganic insulating film may be used as the insulating layer 770. A single layer or a stack of inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, or aluminum nitride oxide can be used as the insulating layer 770. Thus, the insulating layer 770 can function as a protective layer for the transistor 750 and the like.

[0190] The insulating layer 770 may have a stacked structure of an inorganic insulating film and an organic insulating film.

[0191] Next, a portion of the insulating layer 379 on the wiring 760 of the FPC terminal portion 708 is removed to expose the wiring 760.

[0192] <Formation of Conductive Layer 772 and Conductive Layer 774> Next, a conductive layer 772 and a conductive layer 774 are formed over the insulating layer 770 (FIG. 21A). The conductive layer 772 is electrically connected to the transistor 750 through an opening in the insulating layer 770. The conductive layer 772 and the conductive layer 774 can be formed by a method similar to that for the conductive layer 301 and the like. The conductive layer 772 and the conductive layer 774 are preferably formed using a material that is light reflective. For example, the conductive layer 772 and the conductive layer 774 can be formed using a material containing silver, an alloy of palladium and copper (also referred to as APC), aluminum, titanium, copper, or the like.

[0193] Subsequently, conductive bumps 791 and 793 are formed on the conductive layers 772 and 774, respectively (FIG. 21B). The bumps 791 and 793 can be made of a metal such as gold, silver, or tin, an alloy containing these metals, an anisotropic conductive film such as a conductive resin, or a conductive paste. For example, gold can be suitably used for the bumps 791 and 793. The bumps 791 and 793 can be formed by a printing method, a transfer method, a discharging method, or the like.

[0194] <Arrangement of light-emitting element 782> Next, the light emitting element 782 is placed on the bumps 791 and 793. It is preferable to use a horizontally structured, face-down type LED chip as exemplified in FIG. 14 as the light emitting element 782. When placing, the light emitting element 782 is placed so that the cathode side electrode and the anode side electrode of the light emitting element 782 are in contact with the bumps 791 and 793, respectively. The bumps 791, 793, the light emitting element 782, the conductive layers 772 and 774 are pressed together, and the light emitting element 782 is fixed on the conductive layers 772 and 774. At the same time, the conductive layers 772 and 774 are electrically connected to the light emitting element 782 (FIG. 22).

[0195] The light-emitting element 782 can be disposed by using the manufacturing method of the display device shown in the above embodiment. The light-emitting element 782 can be disposed by using a pick-and-place device that picks up the light-emitting element 782 from a predetermined position, transports it, and places it at a predetermined position. Alternatively, the light-emitting element 782 may be disposed by using a FSA (Fluidic Self Assembly) method. In the FSA method, a concave insulating layer that fits the light-emitting element 782 is formed on the conductive layer 772 and in a region overlapping with the conductive layer 774, and the light-emitting element 782 is disposed in a self-aligned manner in the concave in liquid. In one embodiment of the present invention, one type of LED chip is used as the light-emitting element 782, and therefore the light-emitting element 782 can be disposed more easily than when multiple types are used.

[0196] <Formation of light-shielding layer 795> Next, a light-shielding film that will become the light-shielding layer 795 is formed on the insulating layer 770 and the light-emitting element 782 (FIG. 22). The light-shielding film can be formed by a photolithography method or the like using a resin containing a metal material, pigment, or dye. At this time, the thickness of the light-shielding film is adjusted so that the light-shielding film is also formed on the light-emitting element 782.

[0197] Next, a part of the light-shielding film that will become the light-shielding layer 795 is removed to expose the upper surface of the light-emitting element 782 ( FIG. 23A ). The light-shielding film can be removed by dry etching or the like. In one embodiment of the present invention, one type of LED chip is used as the light-emitting element 782, and the height of the light-emitting element 782 can be made the same between subpixels. This makes it possible to easily expose the upper surface of each light-emitting element 782 uniformly, thereby reducing manufacturing costs. In other words, one embodiment of the present invention can provide a display device that has high luminance and contrast, a fast response speed, and low power consumption at low manufacturing costs.

[0198] <Formation of Colored Layer 736 and Phosphor Layer 797> Subsequently, a light-shielding layer 738 and a colored layer 736 are formed on the substrate 705 .

[0199] A metal material or a resin material can be used for the light-shielding layer 738. When a metal material is used for the light-shielding layer 738, it can be formed by forming a conductive film and then removing unnecessary portions using a photolithography method or the like. When a metal material or a photosensitive resin material containing a pigment or dye is used for the light-shielding layer 738, it can be formed by a photolithography method or the like.

[0200] For example, a photosensitive resin material is preferably used for the colored layer 736. The colored layer 736 can be formed by applying a material onto the substrate 705 and the light-shielding layer 738, exposing the material through a photomask, developing the material, and then performing heat treatment.

[0201] Subsequently, phosphor layer 797 is formed on colored layer 736 (FIG. 23B). Phosphor layer 797 can be formed by screen printing, dispensing, or the like using, for example, an organic resin layer in which phosphor is mixed.

[0202] <Bonding of substrate 701 and substrate 705> Next, an adhesive layer is formed on either or both of the substrates 701 and 705 to bond them together. The adhesive layer is formed so as to surround the area in which the pixels are arranged. The adhesive layer can be formed by, for example, a screen printing method, a dispensing method, or the like. The adhesive layer may be made of a thermosetting resin, an ultraviolet curing resin, or the like. Alternatively, a resin that is temporarily cured by ultraviolet light and then cured by applying heat may be used as the adhesive layer. Alternatively, a resin that has both ultraviolet curing properties and thermosetting properties may be used as the adhesive layer.

[0203] Subsequently, the substrate 701 and the substrate 705 are bonded together, and the adhesive layer is cured to form a sealing film 732. The bonding is preferably performed under a reduced pressure atmosphere, since this can prevent air bubbles and the like from being mixed between the substrate 701 and the substrate 705.

[0204] Subsequently, an anisotropic conductive film 780 is provided on the wiring 760. The FPC 716 is placed on the anisotropic conductive film 780 and bonded by thermocompression, whereby the wiring 760 and the FPC 716 are electrically connected to each other.

[0205] Through the above steps, the display device 700 can be formed (FIG. 18).

[0206] <Cross-section configuration example 2> A configuration example different from the display device 700 shown previously is shown in Fig. 24. Fig. 24 is a cross-sectional view taken along dashed line QR shown in Fig. 17A. Display device 700A shown in Fig. 24 differs from display device 700 shown in Fig. 18 mainly in that it has an LED package exemplified in Fig. 15 as a light-emitting element 782, and does not have a light-shielding layer 795 and a phosphor layer 797.

[0207] An example of a method for manufacturing the display device 700A shown in Fig. 24 will be described with reference to Fig. 25 and Fig. 26. Each diagram shown in Fig. 25 and Fig. 26 is a schematic cross-sectional view at each stage of the process related to the method for manufacturing the display device 700A. Since the description of the method for manufacturing the display device 700 described above can be applied up to the formation of the insulating layer 770, detailed description will be omitted.

[0208] <Formation of Conductive Layer 772 and Conductive Layer 774> Next, a conductive layer 772 and a conductive layer 774 are formed over the insulating layer 770 (FIG. 25A). The conductive layer 772 is electrically connected to the transistor 750 through an opening in the insulating layer 770. The conductive layer 772 and the conductive layer 774 can be formed by a method similar to that for the conductive layer 301 and the like.

[0209] Subsequently, conductive bumps 791 and 793 are formed on the conductive layers 772 and 774, respectively (FIG. 25B). Metals such as gold, silver, and tin, alloys containing these metals, anisotropic conductive films such as conductive resins, and conductive pastes can be used for the bumps 791 and 793. The bumps 791 and 793 can be formed by a printing method, a transfer method, a discharging method, or the like.

[0210] For example, silver paste can be used for the bumps 791 and 793, and one or more of APC, aluminum, titanium, and copper can be used for the conductive layers 772 and 774. With such a structure, the light-emitting element 782 can be electrically connected well to each of the conductive layers 772 and 774.

[0211] <Arrangement of Light Emitting Element 782> Next, the light emitting element 782 is placed on the bumps 791 and 793. It is preferable to use the surface mount type LED package illustrated in FIG. 15 as the light emitting element 782. When placing, the light emitting element 782 is placed so that the cathode side electrode and the anode side electrode of the light emitting element 782 are in contact with the bumps 791 and 793, respectively. The bumps 791, 793, the light emitting element 782, the conductive layers 772 and 774 are pressed together, and the light emitting element 782 is fixed on the conductive layers 772 and 774. At the same time, the conductive layers 772 and 774 are electrically connected to the light emitting element 782 (FIG. 26A).

[0212] A pick-and-place device can be used to arrange the light-emitting element 782. Alternatively, an FSA method can be used to arrange the light-emitting element 782. In one embodiment of the present invention, since only one type of LED chip is used as the light-emitting element 782, the arrangement of the light-emitting element 782 is easier than when multiple types of LED chips are used.

[0213] <Formation of Colored Layer> Next, a light-shielding layer 738 and a colored layer 736 are formed on the substrate 705 (FIG. 26B). The light-shielding layer 738 and the colored layer 736 can be formed by using the same method for manufacturing the display device 700 as described above, and therefore detailed description thereof will be omitted.

[0214] <Bonding of substrate 701 and substrate 705> Next, an adhesive layer for bonding the substrates 701 and 705 is formed on either one or both of the substrates 701 and 705. The bonding of the substrates 701 and 705 can be performed using the same method as described above for producing the display device 700, and therefore detailed description thereof will be omitted.

[0215] Subsequently, an anisotropic conductive film 780 is provided on the wiring 760. The FPC 716 is placed on the anisotropic conductive film 780 and bonded by thermocompression, whereby the wiring 760 and the FPC 716 are electrically connected to each other.

[0216] Through the above steps, the display device 700A can be formed (FIG. 24).

[0217] <Example of configuration in which an input device is provided on a display device> An input device may be provided in the display devices shown in Fig. 18, Fig. 19, and Fig. 24. The input device may be, for example, a touch sensor.

[0218] For example, various types of sensors can be used, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, a pressure sensitive type, etc. Alternatively, two or more of these types may be used in combination.

[0219] The touch panel may be configured as a so-called in-cell type touch panel in which an input device is formed inside a pair of substrates, a so-called on-cell type touch panel in which an input device is formed on the display device 700, or a so-called out-cell type touch panel in which an input device is attached to the display device 700.

[0220] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0221] (Embodiment 4) In this embodiment, an example of a transistor which can be used in the display device described in the above embodiment will be described.

[0222] The display device of one embodiment of the present invention can be manufactured using transistors of various types such as bottom-gate transistors and top-gate transistors, etc. Therefore, the material of the semiconductor layer and the transistor structure to be used can be easily replaced in accordance with an existing manufacturing line.

[0223] <Bottom-gate transistor> Fig. 27A1 is a cross-sectional view in the channel length direction of a channel protection transistor 1810, which is a type of bottom-gate transistor. In Fig. 27A1, the transistor 1810 is formed on a substrate 1771. The transistor 1810 also has an electrode 1746 on the substrate 1771 with an insulating layer 1772 interposed therebetween. The transistor 1810 also has a semiconductor layer 1742 on the electrode 1746 with an insulating layer 1726 interposed therebetween. The electrode 1746 can function as a gate electrode. The insulating layer 1726 can function as a gate insulating layer.

[0224] In addition, an insulating layer 1741 is provided over a channel formation region of the semiconductor layer 1742. An electrode 1744a and an electrode 1744b are provided over the insulating layer 1746 in contact with part of the semiconductor layer 1742. The electrode 1744a can function as one of a source electrode and a drain electrode. The electrode 1744b can function as the other of the source electrode and the drain electrode. Part of the electrode 1744a and part of the electrode 1744b are formed over the insulating layer 1741.

[0225] The insulating layer 1741 can function as a channel protective layer. By providing the insulating layer 1741 over the channel formation region, exposure of the semiconductor layer 1742 that occurs when the electrodes 1744a and 1744b are formed can be prevented. Thus, the channel formation region of the semiconductor layer 1742 can be prevented from being etched when the electrodes 1744a and 1744b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

[0226] The transistor 1810 further includes an insulating layer 1728 over the electrode 1744 a , the electrode 1744 b , and the insulating layer 1741 , and an insulating layer 1729 over the insulating layer 1728 .

[0227] When an oxide semiconductor is used for the semiconductor layer 1742, it is preferable to use a material capable of removing oxygen from a part of the semiconductor layer 1742 and generating oxygen vacancies for at least the portions of the electrodes 1744a and 1744b in contact with the semiconductor layer 1742. The carrier concentration increases in the region in the semiconductor layer 1742 where oxygen vacancies have occurred, and the region becomes n-type, forming an n-type region (n + Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 1742, examples of a material that can remove oxygen from the semiconductor layer 1742 and cause oxygen vacancies include tungsten, titanium, and the like.

[0228] The source and drain regions are formed in the semiconductor layer 1742, whereby the contact resistance between the electrodes 1744a and the semiconductor layer 1742 and between the electrodes 1744b and the semiconductor layer 1742 can be reduced. As a result, the electrical characteristics of the transistor, such as the field-effect mobility and the threshold voltage, can be improved.

[0229] When a semiconductor such as silicon is used for the semiconductor layer 1742, a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 1742 and the electrode 1744a and between the semiconductor layer 1742 and the electrode 1744b. The layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.

[0230] The insulating layer 1729 is preferably formed using a material that has a function of preventing or reducing diffusion of impurities from the outside into the transistor. Note that the insulating layer 1729 can be omitted as necessary.

[0231] 27A2 differs from the transistor 1810 in that the transistor 1811 includes an electrode 1723 that can function as a backgate electrode over an insulating layer 1729. The electrode 1723 can be formed using a material and method similar to those of the electrode 1746.

[0232] In general, the backgate electrode is formed of a conductive layer and is arranged so that the gate electrode and the backgate electrode sandwich the channel formation region of the semiconductor layer. Therefore, the backgate electrode can function in the same manner as the gate electrode. The potential of the backgate electrode may be the same as that of the gate electrode, or may be the ground potential (GND potential) or any other potential. In addition, the threshold voltage of the transistor can be changed by changing the potential of the backgate electrode independently of the gate electrode.

[0233] Both the electrode 1746 and the electrode 1723 can function as a gate electrode. Thus, each of the insulating layers 1726, 1741, 1728, and 1729 can function as a gate insulating layer. Note that the electrode 1723 may be provided between the insulating layers 1728 and 1729.

[0234] Note that when one of the electrode 1746 or the electrode 1723 is referred to as a "gate electrode," the other is referred to as a "back gate electrode." For example, in the transistor 1811, when the electrode 1723 is referred to as a "gate electrode," the electrode 1746 is referred to as a "back gate electrode." When the electrode 1723 is used as a "gate electrode," the transistor 1811 can be considered as a type of top-gate transistor. Furthermore, one of the electrode 1746 or the electrode 1723 may be referred to as a "first gate electrode," and the other may be referred to as a "second gate electrode."

[0235] By providing the electrode 1746 and the electrode 1723 with the semiconductor layer 1742 therebetween and further by setting the electrode 1746 and the electrode 1723 to the same potential, the region through which carriers flow in the semiconductor layer 1742 becomes larger in the film thickness direction, and the amount of carrier movement increases. As a result, the on-state current of the transistor 1811 increases and the field-effect mobility increases.

[0236] Therefore, the transistor 1811 has a large on-state current relative to the area it occupies. That is, the area occupied by the transistor 1811 can be made small relative to the required on-state current. According to one embodiment of the present invention, the area occupied by the transistor can be made small. Thus, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

[0237] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which the channel is formed (particularly, an electric field shielding function against static electricity, etc.) Note that the electric field shielding function can be improved by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.

[0238] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side, thereby preventing photodegradation of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor.

[0239] According to one embodiment of the present invention, a highly reliable transistor and a highly reliable semiconductor device can be provided.

[0240] FIG. 27B1 is a cross-sectional view in the channel length direction of a channel protection type transistor 1820 having a different configuration from that of FIG. 27A1. The transistor 1820 has a structure similar to that of the transistor 1810, but is different in that an insulating layer 1741 covers an end of a semiconductor layer 1742. In addition, the semiconductor layer 1742 and an electrode 1744a are electrically connected in an opening formed by selectively removing a part of the insulating layer 1741 that overlaps with the semiconductor layer 1742. In addition, the semiconductor layer 1742 and an electrode 1744b are electrically connected in another opening formed by selectively removing a part of the insulating layer 1741 that overlaps with the semiconductor layer 1742. The region of the insulating layer 1741 that overlaps with the channel formation region can function as a channel protection layer.

[0241] A transistor 1821 shown in FIG. 27B2 differs from the transistor 1820 in that a transistor 1821 includes an electrode 1723 over an insulating layer 1729 that can function as a backgate electrode.

[0242] The insulating layer 1729 can prevent the semiconductor layer 1742 from being exposed when the electrodes 1744a and 1744b are formed. Thus, the semiconductor layer 1742 can be prevented from being thinned when the electrodes 1744a and 1744b are formed.

[0243] In the transistors 1820 and 1821, the distance between the electrode 1744a and the electrode 1746 and the distance between the electrode 1744b and the electrode 1746 are longer than those in the transistors 1810 and 1811. Thus, parasitic capacitance generated between the electrode 1744a and the electrode 1746 can be reduced. In addition, parasitic capacitance generated between the electrode 1744b and the electrode 1746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

[0244] 27C1 is a cross-sectional view in the channel length direction of a channel-etched transistor 1825, which is one of bottom-gate transistors. In the transistor 1825, the electrodes 1744a and 1744b are formed without using the insulating layer 1741. Therefore, a part of the semiconductor layer 1742 exposed during the formation of the electrodes 1744a and 1744b may be etched. On the other hand, since the insulating layer 1741 is not provided, the productivity of the transistor can be improved.

[0245] A transistor 1826 shown in FIG. 27C2 differs from the transistor 1825 in that a transistor 1826 includes an electrode 1723 on an insulating layer 1729 that can function as a backgate electrode.

[0246] 28A1 to 28C2 show cross-sectional views in the channel width direction of transistors 1810, 1811, 1820, 1821, 1825, and 1826, respectively.

[0247] 28B2 and 28C2, the gate electrode and the back gate electrode are connected to each other, and the gate electrode and the back gate electrode have the same potential. Also, the semiconductor layer 1742 is sandwiched between the gate electrode and the back gate electrode.

[0248] The length in the channel width direction of each of the gate electrode and the back gate electrode is longer than the length in the channel width direction of the semiconductor layer 1742, and the entire channel width direction of the semiconductor layer 1742 is covered by the gate electrode or the back gate electrode with insulating layers 1726, 1741, 1728, and 1729 sandwiched therebetween.

[0249] With this structure, the semiconductor layer 1742 included in the transistor can be electrically surrounded by the electric fields of the gate electrode and the backgate electrode.

[0250] A device structure of a transistor in which the semiconductor layer 1742 in which a channel formation region is formed is electrically surrounded by the electric field of the gate electrode and the backgate electrode, like the transistor 1821 or the transistor 1826, can be called a surrounded channel (S-channel) structure.

[0251] By adopting the S-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer 1742 by one or both of the gate electrode and the back gate electrode, so that the current drive capability of the transistor is improved and high on-current characteristics can be obtained. In addition, since the on-current can be increased, the transistor can be miniaturized. In addition, by adopting the S-channel structure, the mechanical strength of the transistor can be increased.

[0252] <Top-gate transistor> 29A1 is a top-gate transistor. The transistor 1842 differs from the transistor 1810 and the transistor 1820 in that the electrodes 1744a and 1744b are formed after the insulating layer 1729 is formed. The electrodes 1744a and 1744b are electrically connected to the semiconductor layer 1742 in openings formed in the insulating layers 1728 and 1729.

[0253] Furthermore, a part of the insulating layer 1726 that does not overlap with the electrode 1746 is removed, and impurities are introduced into the semiconductor layer 1742 using the electrode 1746 and the remaining insulating layer 1726 that has been removed as a mask, whereby an impurity region can be formed in a self-aligned manner in the semiconductor layer 1742. The transistor 1842 has a region in which the insulating layer 1726 extends beyond an end of the electrode 1746. The impurity concentration in the region of the semiconductor layer 1742 into which the impurity is introduced via the insulating layer 1726 is lower than that in the region into which the impurity is introduced without via the insulating layer 1726. In the semiconductor layer 1742, an LDD (Lightly Doped Drain) region is formed in a region that does not overlap with the electrode 1746.

[0254] 29A2 differs from the transistor 1842 in that it has an electrode 1723. The transistor 1843 has the electrode 1723 formed over a substrate 1771. The electrode 1723 has a region overlapping with the semiconductor layer 1742 with an insulating layer 1772 interposed therebetween. The electrode 1723 can function as a backgate electrode.

[0255] 29B1 and 29B2, the insulating layer 1726 may be entirely removed from the region that does not overlap with the electrode 1746. Alternatively, the insulating layer 1726 may be left as in the transistor 1846 shown in FIG. 29C1 and the transistor 1847 shown in FIG. 29C2.

[0256] In the transistors 1843 to 1847, after the electrode 1746 is formed, impurities are introduced into the semiconductor layer 1742 using the electrode 1746 as a mask, so that an impurity region can be formed in a self-aligned manner in the semiconductor layer 1742. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. According to another embodiment of the present invention, a semiconductor device with high integration density can be realized.

[0257] 30A1 to 30C2 show cross-sectional views in the channel width direction of transistors 1842, 1843, 1844, 1845, 1846, and 1847, respectively.

[0258] The transistors 1843, 1845, and 1847 each have the S-channel structure described above. However, this is not limiting, and the transistors 1843, 1845, and 1847 do not necessarily have to have the S-channel structure.

[0259] A metal oxide that can be suitably used for a channel formation region of a transistor will be described below.

[0260] As a semiconductor material for a transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A representative example is a metal oxide containing indium, such as CAC-OS described later.

[0261] A transistor using a metal oxide which has a wider band gap and a lower carrier concentration than silicon can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time owing to its low off-state current.

[0262] The semiconductor layer may be, for example, a film represented by an In-M-Zn system oxide containing indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0263] When the metal oxide constituting the semiconductor layer is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M and Zn≧M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. are preferable. The atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0264] In particular, hydrogen contained in metal oxide reacts with oxygen that bonds to metal atoms to form water, which may cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region in the metal oxide, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that bonds to metal atoms to generate electrons that serve as carriers. Therefore, transistors using metal oxides that contain a large amount of hydrogen tend to have normally-on characteristics.

[0265] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for a metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in a metal oxide, the carrier concentration may be used instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide, instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration".

[0266] It is also preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0267] The carrier concentration of the metal oxide that functions as the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the region functioning as the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0268] The above metal oxide is called a high-purity intrinsic or substantially high-purity intrinsic metal oxide. The metal oxide has a low density of defect states and has stable properties.

[0269] Note that the present invention is not limited to these, and a metal oxide having an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of a transistor. In order to obtain the required semiconductor characteristics of a transistor, it is preferable to appropriately set the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0270] When silicon or carbon, which is one of the group 14 elements, is contained in the metal oxide constituting the semiconductor layer, oxygen vacancies increase in the semiconductor layer, causing it to become n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0271] In addition, when an alkali metal or an alkaline earth metal is bonded to a metal oxide, carriers may be generated, which may increase the off-state current of a transistor. For this reason, the concentration of an alkali metal or an alkaline earth metal in a semiconductor layer obtained by secondary ion mass spectrometry is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0272] In addition, if the metal oxide that constitutes the semiconductor layer contains nitrogen, electrons that act as carriers are generated, the carrier concentration increases, and the transistor tends to become n-type. As a result, transistors that use metal oxides that contain nitrogen tend to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer obtained by secondary ion mass spectrometry is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0273] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, which include c-axis-aligned crystalline oxide semiconductors (CAAC-OS), polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0274] Further, a semiconductor layer of the transistor disclosed in one embodiment of the present invention may be formed using a cloud-aligned composite oxide semiconductor (CAC-OS).

[0275] Note that the semiconductor layer of the transistor disclosed in one embodiment of the present invention can preferably be formed using the above-described non-single-crystal oxide semiconductor or a CAC-OS. As the non-single-crystal oxide semiconductor, an nc-OS or a CAAC-OS can preferably be used.

[0276] Note that in one embodiment of the present invention, a CAC-OS is preferably used for a semiconductor layer of a transistor, which can impart excellent electrical characteristics or high reliability to the transistor.

[0277] The semiconductor layer may be a mixed film having two or more of a CAAC-OS region, a polycrystalline oxide semiconductor region, an nc-OS region, a pseudo-amorphous oxide semiconductor region, and an amorphous oxide semiconductor region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0278] The structure of a CAC-OS that can be used for a transistor disclosed in one embodiment of the present invention is described below.

[0279] CAC-OS is a material in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0280] The metal oxide preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0281] For example, the CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be specifically referred to as CAC-IGZO) is an indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic shape, and the mosaic shape of InO X1 , or In X2 Zinc Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

[0282] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In the present specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0283] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0284] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

[0285] On the other hand, CAC-OS is a material composition of metal oxide. CAC-OS is a material composition containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0286] Note that the CAC-OS does not include a laminated structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0287] In addition, GaO X3 The region where In is the main component and X2Zinc Y2 O Z2 , or InO X1 In some cases, it may be difficult to observe a clear boundary between the region in which the main component is the

[0288] In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are contained instead of gallium, the CAC-OS has a configuration in which some regions observed to be in the form of nanoparticles mainly composed of the metal element and some regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0289] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as a deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, and for example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0290] CAC-OS has the characteristic that no clear peaks are observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, the X-ray diffraction measurement shows that there is no orientation in the ab plane direction or the c axis direction in the measurement area.

[0291] In addition, in the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that has no orientation in the planar and cross-sectional directions.

[0292] For example, in the case of CAC-OS of In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) revealed that GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 It can be seen that the region in which the main component is the crystalline silicon is unevenly distributed and mixed.

[0293] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The main components are In X2 Zinc Y2 O Z2 , or InO X1 The structure is such that the regions having each element as the main component are separated from each other in a mosaic pattern.

[0294] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the metal oxide is expressed. X2Zinc Y2 O Z2 , or InO X1 A high field-effect mobility (μ) can be achieved by distributing the regions in which the main component is a cloud-like structure in the metal oxide.

[0295] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 By distributing regions in which the main components are such as those mentioned above in the metal oxide, leakage current can be suppressed and good switching operation can be achieved.

[0296] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the MOSFET and the MOSFET's resistance to the MOSFET's resistance work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ).

[0297] In addition, semiconductor elements using CAC-OS have high reliability, making CAC-OS ideal for a variety of semiconductor devices including displays.

[0298] In addition, since a transistor having a CAC-OS semiconductor layer has high field-effect mobility and high driving capability, a display device with a narrow frame width (also called a narrow frame) can be provided by using the transistor in a driver circuit, typically a scan line driver circuit that generates a gate signal. In addition, a display device with a small number of wirings connected to the display device can be provided by using the transistor in a signal line driver circuit (particularly, a demultiplexer connected to an output terminal of a shift register in the signal line driver circuit).

[0299] Moreover, unlike transistors using low-temperature polysilicon, transistors having CAC-OS in the semiconductor layer do not require a laser crystallization process. Therefore, even in display devices using large-area substrates, it is possible to reduce manufacturing costs. Furthermore, in large-sized display devices with high resolution such as ultra-high vision ("4K resolution", "4K2K", "4K") and super-high vision ("8K resolution", "8K4K", "8K"), by using transistors having CAC-OS in the semiconductor layer in the driving circuit and display section, writing can be performed in a short time and display defects can be reduced, which is preferable.

[0300] Alternatively, silicon may be used for the semiconductor in which the channel of the transistor is formed. Although amorphous silicon may be used as the silicon, it is preferable to use silicon having crystallinity. For example, it is preferable to use microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.

[0301] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0302] (Embodiment 5) In this embodiment, a display device which is one embodiment of the present invention will be described.

[0303] 31A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0304] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention can also be applied to the protection circuit 506.

[0305] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).

[0306] The driver circuit unit 504 includes driver circuits such as a gate driver 504a that outputs scan signals to the scan lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may include at least a shift register. The source driver 504b may include, for example, a plurality of analog switches. The source driver 504b may also include a shift register.

[0307] The terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0308] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 31A is connected to various wirings such as the scanning lines GL_1 to GL_X that are wirings between the gate driver 504a and the pixel circuit 501, or the data lines DL_1 to DL_Y that are wirings between the source driver 504b and the pixel circuit 501.

[0309] In addition, the gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel portion 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (e.g., a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0310] Furthermore, the pixel circuits 501 shown in Fig. 31A can have, for example, the configuration shown in Fig. 31B. The pixel circuit 501 shown in Fig. 31B has a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is connected to a data line DL_n, a scanning line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0311] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. A current flowing through the light emitting element 572 is controlled in accordance with a potential applied to the gate of the transistor 554, thereby controlling the light emission luminance of the light emitting element 572.

[0312] FIG 32A shows an example in which an n-channel transistor is used as the transistor 554 in the pixel circuit 501 shown in FIG 31B. The pixel circuit 501 shown in FIG 32A includes a transistor 552, a transistor 554a, a capacitor 562, and a light-emitting element 572a. The transistor 552 is an n-channel transistor, and the transistor 554a is an n-channel transistor. For example, the transistor having an oxide semiconductor in a channel formation region described in the above embodiment can be used as the transistor 552, and the transistor having silicon in a channel formation region can be used as the transistor 554a.

[0313] For example, the transistors including an oxide semiconductor in a channel formation region described in the above embodiment can be used as the transistors 552 and 554a. With such a structure, the area occupied by the transistor in a pixel can be reduced, and an extremely high-resolution image can be displayed.

[0314] In the pixel circuit 501 shown in FIG. 32A, one of the source and the drain of the transistor 552 is electrically connected to the data line DL_n. The other of the source and the drain of the transistor 552 is electrically connected to one electrode of the capacitor 562 and the gate of the transistor 554a. The other electrode of the capacitor 562 is electrically connected to the potential supply line VL_a. The gate of the transistor 552 is electrically connected to the scanning line GL_m. One of the source and the drain of the transistor 554a is electrically connected to the potential supply line VL_a. The other of the source and the drain of the transistor 554a is electrically connected to one electrode of the light-emitting element 572a. The other electrode of the light-emitting element 572a is electrically connected to the potential supply line VL_b. A low power supply potential VSS is applied to the potential supply line VL_a, and a high power supply potential VDD is applied to the potential supply line VL_b.

[0315] FIG. 32B shows a configuration different from that of the pixel circuit 501 shown in FIG. 32A. In the pixel circuit 501 shown in FIG. 32B, one of the source and the drain of the transistor 552 is electrically connected to the data line DL_n. The other of the source and the drain of the transistor 552 is electrically connected to one electrode of the capacitor 562 and the gate of the transistor 554a. The gate of the transistor 552 is electrically connected to the scanning line GL_m. One of the source and the drain of the transistor 554a is electrically connected to the potential supply line VL_a. The other of the source and the drain of the transistor 554a is electrically connected to the other electrode of the capacitor 562 and one electrode of the light-emitting element 572a. The other electrode of the light-emitting element 572a is electrically connected to the potential supply line VL_b. A high power supply potential VDD is applied to the potential supply line VL_a, and a low power supply potential VSS is applied to the potential supply line VL_b.

[0316] FIG 32C shows an example in which a p-channel transistor is used as the transistor 554 in the pixel circuit 501 shown in FIG 31B. The pixel circuit 501 shown in FIG 32C includes a transistor 552, a transistor 554b, a capacitor 562, and a light-emitting element 572a. The transistor 552 is an n-channel transistor, and the transistor 554b is a p-channel transistor. For example, the transistor having an oxide semiconductor in a channel formation region described in the above embodiment can be used as the transistor 552, and the transistor having silicon in a channel formation region can be used as the transistor 554b.

[0317] In the pixel circuit 501 shown in FIG. 32C, one of the source and the drain of the transistor 552 is electrically connected to the data line DL_n. The other of the source and the drain of the transistor 552 is electrically connected to one electrode of the capacitor 562 and the gate of the transistor 554b. The other electrode of the capacitor 562 is electrically connected to the potential supply line VL_a. The gate of the transistor 552 is electrically connected to the scanning line GL_m. One of the source and the drain of the transistor 554b is electrically connected to the potential supply line VL_a. The other of the source and the drain of the transistor 554a is electrically connected to one electrode of the light-emitting element 572a. The other electrode of the light-emitting element 572a is electrically connected to the potential supply line VL_b. A high power supply potential VDD is applied to the potential supply line VL_a, and a low power supply potential VSS is applied to the potential supply line VL_b.

[0318] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0319] (Embodiment 6) A pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described. The transistors described in the above embodiments can be applied to transistors used in the pixel circuits described below.

[0320] <Circuit configuration> 33A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0321] The gate of the transistor M1 is connected to the wiring G1, one of the source and drain is connected to the wiring S1, and the other of the source and drain is connected to one electrode of the capacitor C1. The gate of the transistor M2 is connected to the wiring G2, one of the source and drain is connected to the wiring S2, and the other of the source and drain is connected to the other electrode of the capacitor C1 and the circuit 401.

[0322] The circuit 401 includes at least one display element, which may be an LED element.

[0323] The node connecting the transistor M1 and the capacitor C1 is defined as N1, and the node connecting the transistor M2 and the circuit 401 is defined as N2.

[0324] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. Also, the potential of the node N2 can be maintained by turning off the transistor M2. Also, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed according to the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0325] Here, the transistor using an oxide semiconductor as exemplified in the above embodiment can be used as one or both of the transistor M1 and the transistor M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period for holding the potentials of the nodes is short (specifically, when the frame frequency is 30 Hz or more), a transistor using a semiconductor such as silicon may be used.

[0326] <Driving method example> Next, an example of an operation method of pixel circuit 400 will be described with reference to Fig. 33B. Fig. 33B is a timing chart relating to the operation of pixel circuit 400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, threshold voltages of transistors, and the like will not be taken into consideration here.

[0327] 33B, one frame period is divided into a period T1 and a period T2. The period T1 is a period in which a potential is written to the node N2, and the period T2 is a period in which a potential is written to the node N1.

[0328] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supplies.

[0329] The node N1 is connected to a potential V ref A first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0330] [Period T2] In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.

[0331] A second data potential V data At this time, the second data potential V dataIn response to the change in potential, the potential of the node N2 changes by a potential dV. That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401. Note that although dV is shown to have a positive value in FIG. 33B, it may be a negative value. That is, the potential V data is the potential V ref It may be lower.

[0332] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential becomes close to

[0333] In this manner, the pixel circuit 400 can combine two types of data signals to generate a potential to be supplied to the circuit 401 including a display element, and therefore, gray scale correction can be performed within the pixel circuit 400.

[0334] In addition, the pixel circuit 400 can generate a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. When a light-emitting element is used, high dynamic range (HDR) display and the like can be performed.

[0335] The pixel circuit 400EL shown in Fig. 33C includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0336] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and a drain connected to the potential V L The other electrode of the capacitor C2 is connected to a wiring to which a potential V com The other electrode of the light-emitting element EL is connected to a wiring that is supplied with a potential V H Connect with the wiring given.

[0337] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if not required.

[0338] In this example, the cathode side of the light-emitting element EL is connected to the transistor M3, but the transistor M3 may be connected to the anode side as shown in FIG. H and potential V L You can change the value as appropriate.

[0339] In the pixel circuit 400EL, a large current can be passed through the light-emitting element EL by applying a high potential to the gate of the transistor M3, thereby realizing, for example, HDR display, etc. In addition, by supplying a correction signal to the wiring S1 or wiring S2, it is also possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0340] It should be noted that the circuits are not limited to those illustrated in FIGS. 33C and 33D, and may be configured to include additional transistors, capacitors, and the like.

[0341] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0342] (Embodiment 7) In this embodiment, a configuration of a data processing device of one embodiment of the present invention will be described with reference to FIGS. 34 and 35. FIG.

[0343] 34 and 35 are diagrams illustrating a configuration of an information processing device of one embodiment of the present invention. Fig. 34A is a block diagram of the information processing device, and Figs. 34B to 34E are perspective views illustrating the configuration of the information processing device. Figs. 35A to 35E are perspective views illustrating the configuration of the information processing device.

[0344] <Information processing device> An information processing device 5200B described in this embodiment includes an arithmetic device 5210 and an input / output device 5220 (see FIG. 34A).

[0345] The arithmetic unit 5210 has a function of receiving operation information and a function of supplying image information based on the operation information.

[0346] The input / output device 5220 includes a display unit 5230, an input unit 5240, a detection unit 5250, and a communication unit 5290, a function of supplying operation information, and a function of being supplied with image information. The input / output device 5220 also includes a function of supplying detection information, a function of supplying communication information, and a function of being supplied with communication information.

[0347] The input unit 5240 has a function of supplying operation information. For example, the input unit 5240 supplies operation information based on an operation by a user of the information processing device 5200B.

[0348] Specifically, the input unit 5240 can use a keyboard, a hardware button, a pointing device, a touch sensor, an illuminance sensor, an imaging device, a voice input device, an eye-gaze input device, a posture detection device, or the like.

[0349] The display portion 5230 has a function of displaying a display panel and displaying image information. For example, the display device described in the above embodiment can be used for the display portion 5230.

[0350] The detection unit 5250 has a function of supplying detection information, for example, a function of detecting the surrounding environment in which the information processing device is used and supplying the detected information.

[0351] Specifically, the detection unit 5250 can include an illuminance sensor, an imaging device, a posture detection device, a pressure sensor, a human sensor, or the like.

[0352] The communication unit 5290 has a function of receiving and supplying communication information. For example, it has a function of connecting to other electronic devices or communication networks by wireless communication or wired communication. Specifically, it has functions such as wireless local area communication, telephone communication, and short-distance wireless communication.

[0353] <Configuration example 1 of information processing device> For example, an outer shape conforming to a cylindrical pillar or the like can be applied to the display unit 5230 (see FIG. 34B). The information processing device 5200B has a function of changing the display method according to the illuminance of the usage environment. The information processing device 5200B also has a function of detecting the presence of a person and changing the display content. This allows the information processing device 5200B to be installed on, for example, a pillar of a building. Alternatively, advertisements, guidance, or the like can be displayed. Alternatively, the information processing device 5200B can be used for digital signage or the like.

[0354] <Configuration example 2 of information processing device> The information processing device 5200B has a function of generating image information based on, for example, the trajectory of a pointer used by a user (see FIG. 34C). Specifically, a display panel with a diagonal length of 20 inches or more, preferably 40 inches or more, and more preferably 55 inches or more can be used. Alternatively, multiple display panels can be arranged to be used in one display area. Alternatively, multiple display panels can be arranged to be used in a multi-screen. This allows the information processing device 5200B to be used in, for example, an electronic blackboard, an electronic bulletin board, an electronic signboard, etc.

[0355] <Configuration example 3 of information processing device> The information processing device 5200B has a function of changing the display method according to the illuminance of the usage environment (see FIG. 34D). This makes it possible to reduce the power consumption of the smartwatch (registered trademark), for example. Or, for example, it is possible to display an image on the smartwatch (registered trademark) so that it can be used suitably even in an environment with strong external light, such as outdoors on a sunny day.

[0356] <Configuration example 4 of information processing device> The information processing device 5200B has a display unit 5230 and the like. The display unit 5230 has, for example, a curved surface that curves gently along the side of the housing (see FIG. 34E). Alternatively, the display unit 5230 has a display panel, and the display panel has a function of displaying on, for example, the front, side, and top. This makes it possible to display image information not only on the front of the mobile phone, but also on the side and top.

[0357] <Configuration example 5 of information processing device> The information processing device 5200B has a function of changing the display method according to the illuminance of the usage environment (see FIG. 35A). This can reduce the power consumption of the smartphone. Alternatively, for example, images can be displayed on the smartphone so that it can be used suitably even in an environment with strong external light, such as outdoors on a sunny day.

[0358] <Configuration Example 6 of Information Processing Device> The information processing device 5200B has a function of changing the display method according to the illuminance of the usage environment (see FIG. 35B). This allows the video to be displayed on the television system so that it can be used appropriately even when strong external light shines indoors on a sunny day.

[0359] <Configuration Example 7 of Information Processing Device> The information processing device 5200B has a function of changing the display method according to the illuminance of the usage environment (see FIG. 35C). This allows images to be displayed on the tablet computer so that it can be used suitably even in an environment with strong external light, such as outdoors on a sunny day.

[0360] <Configuration Example 8 of Information Processing Device> The information processing device 5200B has a function of changing the display method according to the illuminance of the usage environment (see FIG. 35D). This allows the subject to be displayed on the digital camera so that it can be viewed appropriately even in an environment with strong external light, such as outdoors on a sunny day.

[0361] <Configuration Example 9 of Information Processing Device> The information processing device 5200B has a function of changing the display method according to the illuminance of the usage environment (see FIG. 35E). This allows images to be displayed on a personal computer so that the image can be used suitably even in an environment with strong external light, such as outdoors on a sunny day.

[0362] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification. [Explanation of symbols]

[0363] C1: capacitance, C2: capacitance, CFB: colored layer, CFG: colored layer, CFR: colored layer, DL_n: data line, DL_Y: data line, DL_1: data line, EL: light-emitting element, G1: wiring, G2: wiring, GL_m: scanning line, GL_X: scanning line, GL_1: scanning line, M1: transistor, M2: transistor, M3: transistor, N1: node, N2: node, P1: area, P2: area, S1: wiring, S2: wiring, T1: period, T2: period, 10: display device, 10A: display device, 10B: display device, 10C: display device, 10D: display device, 10E: display device, 10F : display device, 10G: display device, 10H: display device, 11: substrate, 13: substrate, 15: functional layer, 17: light emitting element, 20B: blue light, 20G: green light, 20R: red light, 20W: white light, 21: electrode, 23: electrode, 25: insulating layer, 27: adhesive layer, 31: light shielding layer, 33: light shielding layer, 35: phosphor layer, 50: LED package, 51: LED chip, 51A: LED chip section, 51B: LED chip, 52: substrate, 53: reflector, 55: electrode, 57: electrode, 59: wire, 61: wire, 63: resin layer, 65: phosphor, 67: adhesive layer, 71: substrate, 71A : substrate, 75: n-type semiconductor layer, 75a: n-type contact layer, 75b: n-type cladding layer, 77: light emitting layer, 77a: barrier layer, 77b: well layer, 79: p-type semiconductor layer, 79a: p-type cladding layer, 79b: p-type contact layer, 81: semiconductor layer, 83: electrode, 85: electrode, 87: electrode, 89: insulating layer, 90: bump, 301: conductive layer, 303: conductive layer, 305: conductive layer, 311: insulating layer, 321: semiconductor layer, 323: semiconductor layer, 325: semiconductor layer, 331: insulating layer, 333: insulating layer, 341: conductive layer, 343: conductive layer, 351: conductive layer, 353: conductive layer, 361: insulating layer Edge layer, 363: insulating layer, 371: conductive layer, 373a: conductive layer, 373b: conductive layer, 375: conductive layer, 377: conductive layer, 379: insulating layer, 400: pixel circuit, 400EL: pixel circuit, 401: circuit, 401EL: circuit, 501: pixel circuit, 502: pixel section, 504: drive circuit section, 504a: gate driver, 504b: source driver, 506: protection circuit, 507: terminal section, 552: transistor, 554: transistor, 554a: transistor, 554b: transistor, 562: capacitance element, 572: light emitting element, 572a: light emitting element, 700: display device,700A: display device, 700B: display device, 701: substrate, 702: pixel section, 704: source driver circuit section, 705: substrate, 706: gate driver circuit section, 708: FPC terminal section, 710: signal line, 711: wiring section, 712: sealant, 716: FPC, 717: IC, 721: source driver IC, 722: gate driver circuit section, 723: FPC, 724: printed circuit board, 732: sealing film, 736: colored layer, 738: light-shielding layer, 740: protective layer, 742: adhesive layer, 743: resin layer, 744: insulating layer , 745: supporting substrate, 746: resin layer, 750: transistor, 752: transistor, 760: wiring, 770: insulating layer, 772: conductive layer, 774: conductive layer, 780: anisotropic conductive film, 782: light emitting element, 790: capacitance element, 791: bump, 793: bump, 795: light shielding layer, 797: phosphor layer, 800: substrate, 900: LED chip substrate, 901: film, 903: plate, 905: table, 907: grindstone, 909: grindstone wheel, 911: scribe line, 913: stand, 914: opening, 9 15: blade, 919: film, 921: fixture, 923: sheet, 924: plate, 925: fixture, 927: film, 929: extrusion mechanism, 950: device, 951: stage, 953: single-axis robot, 955: single-axis robot, 957: camera, 959: gripping mechanism, 961: control device, 963: unit, 1723: electrode, 1726: insulating layer, 1728: insulating layer, 1729: insulating layer, 1741: insulating layer, 1742: semiconductor layer, 1744a: electrode, 1744b: electrode, 1746: electrode, 1771: Substrate, 1772: insulating layer, 1810: transistor, 1811: transistor, 1820: transistor, 1821: transistor, 1825: transistor, 1826: transistor, 1842: transistor, 1843: transistor, 1844: transistor, 1845: transistor, 1846: transistor, 1847: transistor, 5200B: information processing device, 5210: arithmetic unit, 5220: input / output device, 5230: display unit, 5240: input unit, 5250: detection unit, 5290: communication unit,

Claims

[Claim 1] A first conductive film is formed; forming a first conductive layer functioning as a first gate electrode by processing the first conductive film using a first resist mask; removing the first resist mask; forming a first insulating layer on the first conductive layer, the first insulating layer functioning as a first gate insulating layer; forming a first semiconductor film on the first insulating layer; forming a first semiconductor layer by processing the first semiconductor film using a second resist mask; removing the second resist mask; forming a second insulating film on the first semiconductor layer; forming a second conductive film on the second insulating film; forming a second conductive layer functioning as a second gate electrode and a second insulating layer functioning as a second gate insulating layer by processing the second conductive film and the second insulating film using a third resist mask; removing the third resist mask; forming a third insulating layer over the second conductive layer and over the first semiconductor layer; forming a fourth insulating layer on the third insulating layer; forming a first opening and a second opening in the third insulating layer and the fourth insulating layer, the first opening and the second opening reaching the first semiconductor layer; forming a third conductive layer on the fourth insulating layer, the third conductive layer being in contact with the first semiconductor layer through the first opening and functioning as one of a source electrode or a drain electrode, and forming a fourth conductive layer on the fourth insulating layer, the fourth conductive layer being in contact with the first semiconductor layer through the second opening and functioning as the other of the source electrode or the drain electrode; forming a fifth insulating layer functioning as a protective film on the third conductive layer and on the fourth conductive layer; forming a sixth insulating layer having a flat upper surface on the fifth insulating layer; forming a third opening in the sixth insulating layer and the fifth insulating layer, the third opening reaching the third conductive layer; forming a fifth conductive layer on the sixth insulating layer, the fifth conductive layer being in contact with the third conductive layer and having reflectivity, and forming a sixth conductive layer on the sixth insulating layer; forming a conductive first bump on the fifth conductive layer and a conductive second bump on the sixth conductive layer; providing a first substrate; An LED chip substrate having a first electrode and a second electrode on a surface thereof is provided; The LED chip substrate is thinned by polishing the substrate side of the LED chip substrate; providing a first film on the first electrode side and the second electrode side of the LED chip substrate; forming a scribe line along an LED chip section of the LED chip substrate; Separating the LED chip substrate into individual LED chips by driving a blade along the scribe lines; Pulling the first film to increase the distance between the LED chips; a second film is provided on the substrate side of each of the widely spaced LED chips; forming a plurality of LED chips, each having the first electrode and the second electrode on a surface thereof, in a matrix on the second film by separating the first film from each of the LED chips; The first bump and the first electrode of the LED chip are opposed to each other, and the second bump and the second electrode of the LED chip are opposed to each other; an extrusion mechanism is extruded from the second film side to the first substrate side, thereby bringing the first bumps into contact with the first electrodes to electrically connect the first bumps to the first electrodes, and bringing the second bumps into contact with the second electrodes to electrically connect the second bumps to the second electrodes; forming a first light-shielding layer on the sixth insulating layer and on the LED chip; removing a portion of the first light-shielding layer to expose an upper surface of the LED chip; forming a second light-shielding layer and a colored layer on a second substrate; forming a phosphor layer on the color layer; The method for manufacturing a display device further comprises: placing the phosphor layer and an upper surface of the LED chip opposite each other; and then bonding the first substrate and the second substrate together using an adhesive layer.

Images