Semiconductor device and method for manufacturing the same

Abstract

The purpose of the present invention is to provide a feature capable of reducing voids in a semiconductor device. The semiconductor device comprises a plating film, a semiconductor element, and a spacer. The semiconductor element is provided over the plating film. The spacer includes a first wire bump. The spacer provides a gap between the plating film and the semiconductor element. The lower surface of the first wire bump is not in contact with the plating film, or a portion of the lower surface of the first wire bump positioned on the outside of the outer peripheral portion of the plating film is not in contact with the plating film.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Various techniques have been proposed for power semiconductor devices, which are one type of semiconductor device, as shown in Patent Document 1. For example, a technique has been proposed in which a wire bump is provided between a semiconductor element and a plating film to provide a gap between the semiconductor element and the plating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-110317 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when a wire bump is formed on a plating film by wedge bonding or the like, the wire bump and a cutter used to form the wire bump apply stress to the plating film, which can cause cracks in the plating film that are difficult to detect by visual inspection, etc. As a result, when a joining member such as a solder layer is formed, gas present in the plating film and gas present at the interface between the plating film and the base are released from around the wire bump, which can cause voids to form in the joining member.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique capable of reducing voids in a semiconductor device. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a plating film, a semiconductor element provided above the plating film, and a spacer that includes a first wire bump and provides a gap between the plating film and the semiconductor element. a conductive member provided below the plating film; and a lower surface of the first wire bump that is not in contact with the plating film; and contacts the conductive member via a through hole provided in the plating film. do. Effect of the Invention

[0007] According to the present disclosure, the lower surface of the first wire bump is not in contact with the plating film, or a part of the lower surface of the first wire bump located outside the outer periphery of the plating film is not in contact with the plating film. With this configuration, it is possible to reduce voids in the semiconductor device.

[0008] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 1 is a cross-sectional view showing a configuration of a related semiconductor device. [Figure 4] 11 is a cross-sectional view for explaining a problem that occurs during the manufacture of a related semiconductor device. [Diagram 5] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. [Figure 7] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a third embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to a fifth embodiment. [Figure 11] FIG. 13 is a plan view showing a configuration of a semiconductor device according to a fifth embodiment. [Figure 12] FIG. 13 is a plan view showing a configuration of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are given the same or similar reference numerals, and different components are mainly described. In addition, in the following description, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" do not necessarily correspond to positions and directions in actual implementation.

[0011] <Embodiment 1> Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment, and Fig. 2 is a plan view showing the configuration. The semiconductor device of the present disclosure is applied to a power semiconductor device or the like.

[0012] The semiconductor device in FIG. 1 includes a cooling mechanism 1, an insulating member 2, a conductive member 3, a plating film 4, a semiconductor element 5, a spacer 6, and a solder layer .

[0013] The cooling mechanism 1 cools the semiconductor element 5 via the insulating member 2, the conductive member 3, etc. The cooling mechanism 1 may be provided with cooling fins (not shown) or the like.

[0014] The insulating member 2 is provided on the cooling mechanism 1. The material of the insulating member 2 includes, for example, ceramic.

[0015] The conductive member 3 is provided on the insulating member 2. The material of the conductive member 3 may be a material that is difficult to solder, such as pure aluminum (Al) or an aluminum alloy, or may be copper (Cu).

[0016] The plating film 4 is provided on the conductive member 3. In other words, the conductive member 3 is provided below the plating film 4. The plating film 4 is provided with a through hole 4a that partially exposes the conductive member 3. In the present embodiment 1, the plating film 4 is an electroless plating film containing nickel and phosphorus, and the phosphorus concentration is 5 wt % or more. However, the plating film 4 is not limited to this. The phosphorus concentration can be measured by, for example, an X-ray fluorescence analyzer.

[0017] The semiconductor element 5 is provided above the plating film 4. The semiconductor element 5 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a RC-IGBT (Reverse Conducting - IGBT), an SBD (Schottky Barrier Diode), or a PND (PN junction diode). The material of the semiconductor element 5 may be ordinary silicon (Si), or may be a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. When the material of the semiconductor element 5 is a wide band gap semiconductor, stable operation under high temperature and high voltage and high switching speed can be achieved.

[0018] The spacers 6 provide a certain gap between the plating film 4 and the semiconductor element 5. For example, as shown in Fig. 2, the spacers 6 are provided to correspond to the four vertices of the plating film 4 that is rectangular in plan view. With this configuration, it is possible to suppress variation in the gap between the plating film 4 and the semiconductor element 5.

[0019] The spacer 6 includes a first wire bump 6a. In the first embodiment, the spacer 6 includes only the first wire bump 6a, but as described below, the spacer 6 may further include components other than the first wire bump 6a.

[0020] The material of the first wire bump 6a includes, for example, aluminum (Al) or copper (Cu). In the present embodiment 1, as shown in Fig. 1, the first wire bump 6a is provided inside the outer periphery of the plating film 4. The lower surface of the first wire bump 6a is not in contact with the plating film 4 and is in contact with the conductive member 3 via the through hole 4a of the plating film 4.

[0021] The solder layer 7 is a joining member that joins the plating film 4 and the semiconductor element 5, and is provided in a gap between the plating film 4 and the semiconductor element 5. The joining member is not limited to the solder layer 7.

[0022] Next, a semiconductor device related to the semiconductor device according to the first embodiment (hereinafter, referred to as a related semiconductor device) will be described. Fig. 3 is a cross-sectional view showing the configuration of the related semiconductor device. In the related semiconductor device, the entire lower surface of the first wire bump 6a, which is the spacer 6, is in contact with the plating film 4.

[0023] FIG. 4 is a cross-sectional view for explaining problems that occur during the manufacture of a related semiconductor device. As shown in FIG. 4(a), when the first wire bump 6a is formed in contact with the plating film 4 by wedge bonding or the like, stress is applied to the plating film 4 when the first wire bump 6a comes into contact with the plating film 4 and when the first wire bump 6a is cut by a cutter. This stress may cause cracks that are difficult to detect visually to occur in the plating film 4 around the first wire bump 6a. In this state, when a solder layer 7 or the like is formed on the plating film 4, gas present in the plating film 4 and gas present at the interface between the plating film 4 and the conductive member 3 are released from around the first wire bump 6a, as shown in FIG. 4(b). As a result, voids may be formed in the solder layer 7, as shown in FIG. 4(c).

[0024] In contrast, in the present embodiment 1, the lower surface of the first wire bump 6a is not in contact with the plating film 4, but is in contact with the conductive member 3 via the through hole 4a of the plating film 4. With this configuration, cracks in the plating film 4 are suppressed, and gas emission from the plating film 4 around the first wire bump 6a is suppressed, so that voids in the solder layer 7 can be reduced. As a result, the mechanical strength of the semiconductor device can be increased. Furthermore, with the configuration in which the cooling mechanism 1 is provided as in FIG. 1, the thermal conductivity between the cooling mechanism 1 and the semiconductor element 5 can be increased, so that the heat dissipation of the semiconductor element 5 can be improved.

[0025] Note that, if the lower surface of first wire bump 6a is not in contact with plating film 4, the side portion of first wire bump 6a may be in contact with plating film 4. However, it is preferable that the side portion of first wire bump 6a is not in contact with plating film 4 as shown in FIG. 1 so that the lower surface of first wire bump 6a is not in contact with plating film 4 even if manufacturing variations occur.

[0026] Moreover, in the first embodiment, a solder layer 7 is further provided in the gap between the plating film 4 and the semiconductor element 5, and the material of the conductive member 3 includes aluminum or an aluminum alloy. With this configuration, the plating film 4 can increase the adhesive strength between the solder layer 7 and the conductive member 3, so that the conductive member 3 can be made of a material that is difficult to solder, such as pure aluminum (Al) or an aluminum alloy.

[0027] In the first embodiment, the plating film 4 is an electroless plating film containing nickel (Ni) and phosphorus (P) with a phosphorus concentration of 5 wt% or more. With this configuration, the Ni plating has an amorphous structure, and the plating film 4 can release gas at a temperature lower than the solder melting temperature. As a result, the gas can be released at the start of the formation of the solder layer 7, so that the gas that was released at the start of the formation of the solder layer 7 can be discharged from the solder layer 7 by the time the formation of the solder layer 7 is completed. As a result, the voids in the solder layer 7 can be reduced.

[0028] <Embodiment 2> FIG. 5 is a plan view showing a configuration of a semiconductor device according to the second embodiment.

[0029] 5, in the second embodiment, the through holes 4a in the plating film 4 are connected to the outer periphery of the plating film 4. With this configuration, even if gas is released from the plating film 4 around the first wire bump 6a, the gas can be easily discharged from the solder layer 7 to the outer periphery of the plating film 4, so that voids in the solder layer 7 can be reduced.

[0030] <Embodiment 3> FIG. 6 is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment, and FIG. 7 is a plan view showing the configuration.

[0031] In the third embodiment, unlike the first embodiment, substantially no through holes 4a are provided in the plating film 4. On the other hand, in the semiconductor device according to the third embodiment, a multilayer plating film 8 is additionally provided on the plating film 4. The lower surface of the first wire bump 6a is not in contact with the plating film 4 and is in contact with the multilayer plating film 8.

[0032] Since the multilayer plating film 8 has a higher hardness than the plating film 4, the configuration according to the present embodiment 3 described above can reduce voids in the solder layer 7, as in the embodiment 1. Furthermore, since there is no need to provide through holes 4a in the plating film 4, the manufacturing process can be simplified. Furthermore, when a material with good heat dissipation properties is used for the material of the multilayer plating film 8, the heat dissipation properties of the semiconductor device can be improved.

[0033] <Fourth embodiment> FIG. 8 is a cross-sectional view showing the configuration of a semiconductor device according to the fourth embodiment, and FIG. 9 is a plan view showing the configuration.

[0034] In the fourth embodiment, unlike the first embodiment, substantially no through holes 4a are provided in the plating film 4. On the other hand, in the semiconductor device according to the fourth embodiment, an oxide film 9, which is an insulating film provided on the plating film 4, is added. The lower surface of the first wire bump 6a is not in contact with the plating film 4, but is in contact with the oxide film 9. The oxide film 9 may be formed by oxidizing the plating film 4.

[0035] Since the oxide film 9 has a higher hardness than the plating film 4, the configuration according to the present embodiment 4 described above can reduce voids in the solder layer 7, similarly to the embodiment 1. Furthermore, since there is no need to provide through holes 4a in the plating film 4, the manufacturing process can be simplified.

[0036] <Fifth Preferred Embodiment> FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to the fifth embodiment, and FIG. 11 is a plan view showing the configuration.

[0037] In the fifth embodiment, unlike the first embodiment, substantially no through holes 4a are provided in the plating film 4. On the other hand, as shown in Fig. 10, a part of the lower surface of the first wire bump 6a that is located outside the outer periphery of the plating film 4 is not in contact with the plating film 4. The remaining part of the lower surface of the first wire bump 6a is in contact with the plating film 4. In other words, in a plan view, the first wire bump 6a is provided straddling the outer contour of the plating film 4.

[0038] According to the configuration of the present embodiment 4, a portion of the underside of the first wire bump 6a is not in contact with the plating film 4, so that it is possible to reduce voids in the solder layer 7 more than in a configuration (configuration of FIG. 3) in which the entire underside of the first wire bump 6a is in contact with the plating film 4. Furthermore, even if gas is released from the plating film 4 around the first wire bump 6a, the gas can be easily discharged from the solder layer 7 to the outer periphery of the plating film 4, so that it is possible to reduce voids in the solder layer 7. Furthermore, since there is no need to provide through holes 4a in the plating film 4, the manufacturing process can be simplified.

[0039] <Sixth embodiment> FIG. 12 is a plan view showing the configuration of a semiconductor device according to the sixth preferred embodiment.

[0040] In the sixth embodiment, unlike the first embodiment, the plating film 4 is not substantially provided with a through hole 4a. On the other hand, in the semiconductor device according to the sixth embodiment, the spacer 6 includes a first wire bump 6a, a second wire bump 6b, and a wire 6c, and the second wire bump 6b is connected via the wire 6c. The lower surface of the first wire bump 6a is located outside the outer periphery of the plating film 4 and is not in contact with the plating film 4, and the lower surface of the second wire bump 6b is in contact with the plating film 4. In other words, in a plan view, the wire 6c connecting the first wire bump 6a and the second wire bump 6b is provided across the outer contour of the plating film 4.

[0041] According to the configuration of the sixth embodiment, since the lower surface of the first wire bump 6a is not in contact with the plating film 4, it is possible to reduce voids in the solder layer 7 compared to a configuration in which the entire lower surface of the first wire bump 6a is in contact with the plating film 4. Furthermore, since the range of the spacer 6 in a plan view can be widened, even if the semiconductor element 5 is slightly misaligned in a plan view, the semiconductor element 5 can be in contact with the spacer 6, and it is possible to suppress variations in the gap between the plating film 4 and the semiconductor element 5. Furthermore, since it is not necessary to provide a through hole 4a in the plating film 4, it is possible to simplify the manufacturing process.

[0042] It is preferable that the first wire bump 6a is formed after the second wire bump 6b is formed. In this configuration, after the first wire bump 6a located outside the outer periphery of the plating film 4 is formed, cutting can be performed with a cutter outside the outer periphery of the plating film 4. This suppresses cracking of the plating film 4, thereby reducing voids in the solder layer 7.

[0043] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0044] The above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned. [Explanation of symbols]

[0045] 3 conductive member, 4 plating film, 4a through hole, 5 semiconductor element, 6 spacer, 6a first wire bump, 6b second wire bump, 6c wire, 7 solder layer, 8 multilayer plating film, 9 oxide film.

Claims

1. A plating film, a semiconductor element provided above the plating film; a spacer including a first wire bump and providing a gap between the plating film and the semiconductor element; A conductive member provided under the plating film; Equipped with a lower surface of the first wire bump is not in contact with the plating film and is in contact with the conductive member via a through hole provided in the plating film.

2. 2. The semiconductor device according to claim 1, a solder layer provided in the gap between the plating film and the semiconductor element; A semiconductor device, wherein the material of the conductive member includes aluminum or an aluminum alloy.

3. 2. The semiconductor device according to claim 1, The through hole of the plating film is in communication with an outer periphery of the plating film.

4. A plating film, a semiconductor element provided above the plating film; a spacer including a first wire bump and providing a gap between the plating film and the semiconductor element; Equipped with a portion of a lower surface of the first wire bump that is located outside an outer periphery of the plating film is not in contact with the plating film; A semiconductor device, wherein a remainder of the lower surface of the first wire bump is in contact with the plating film.

5. A plating film, a semiconductor element provided above the plating film; a spacer including a first wire bump and providing a gap between the plating film and the semiconductor element; Equipped with The spacer is The semiconductor device further includes a second wire bump connected to the first wire bump via a wire, a lower surface of the first wire bump is located outside an outer periphery of the plating film and is not in contact with the plating film; A semiconductor device, wherein a lower surface of the second wire bump is in contact with the plating film.

6. 6. The semiconductor device according to claim 1, The semiconductor device, wherein the plating film is an electroless plating film containing nickel and phosphorus, and the concentration of the phosphorus is 5 wt % or more.

7. 6. The method for manufacturing a semiconductor device according to claim 5, The method for manufacturing a semiconductor device further comprises forming the first wire bump after forming the second wire bump.

8. A plating film, a semiconductor element provided above the plating film; a spacer including a first wire bump and providing a gap between the plating film and the semiconductor element; a high-hardness film provided on the plating film and having a higher hardness than the plating film; Equipped with A semiconductor device, wherein a lower surface of the first wire bump is not in contact with the plating film and is in contact with the high-hardness film.

9. The semiconductor device according to claim 8, The semiconductor device, wherein the high-hardness film includes a multi-layer plating film.

10. The semiconductor device according to claim 8, The high-hardness film includes an insulating film.

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