Semiconductor Device

Abstract

To provide a semiconductor device capable of improving connectivity of a semiconductor chip.SOLUTION: A semiconductor device comprises: a die pad that includes a first region and a second region surrounding the first region and being thinner than the first region; a semiconductor chip that includes an upper electrode, a lower electrode, and a silicon carbide layer between the upper and lower electrodes, being provided in an inner area from the second region on a surface of the die pad; and a connection layer for connecting the lower electrode onto the surface.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device in which a semiconductor chip is fixed onto a die pad using a connection layer such as solder, high reliability is required for the connection using the connection layer. For example, if the semiconductor chip peels off at the connection due to temperature changes that the semiconductor device experiences during use, the device characteristics of the semiconductor device will change, causing problems. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-47061 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of improving the connectivity of a semiconductor chip. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a die pad including a first region and a second region surrounding the first region and having a thickness smaller than that of the first region, an upper electrode, a lower electrode, and a silicon carbide layer between the upper electrode and the lower electrode, the semiconductor chip being provided on a surface of the die pad inside the second region, and a connection layer connecting the lower electrode to the surface. a lead portion provided in a first direction of the die pad, a plurality of bonding wires connecting the upper electrode and the lead portion, and a resin layer surrounding the semiconductor chip and the plurality of bonding wires; Equipped with an angle between an extension direction of the plurality of bonding wires and the first direction is 5 degrees or less; the plurality of bonding wires include a plurality of first bonding wires and a plurality of second bonding wires, the first bonding wires and the second bonding wires are alternately arranged in a second direction perpendicular to the first direction; the first bonding wires are connected to the upper electrode at a first position, the first bonding wires are connected to the lead portion at a second position, the second bonding wires are connected to the upper electrode at a third position, and the second bonding wires are connected to the lead portion at a fourth position; and in the first direction, the first position, the third position, the second position, and the fourth position are arranged in this order. . [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Diagram 2]1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 4] FIG. 2 is a schematic bottom view of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 2 is a schematic top view of a semiconductor device according to a first comparative example of the first embodiment. [Figure 6] FIG. 4 is a schematic top view of a semiconductor device according to a second comparative example of the first embodiment. [Figure 7] FIG. 5 is a schematic top view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 13 is a schematic top view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described may be omitted as appropriate.

[0008] (First embodiment) The semiconductor device of the first embodiment comprises a die pad including a first region and a second region surrounding the first region and having a thickness thinner than the first region, an upper electrode, a lower electrode, and a silicon carbide layer between the upper electrode and the lower electrode, a semiconductor chip provided inside the second region on a surface of the die pad, and a connection layer connecting the lower electrode to the surface.

[0009] The semiconductor device of the first embodiment is a semiconductor device 100 in which a diode chip including a silicon carbide layer is packaged with resin.

[0010] FIG. 1 is a schematic top view of the semiconductor device of the first embodiment. FIG. 1 is a top view excluding a resin layer. FIG. 2 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 2 is a cross-sectional view taken along line AA' in FIG. 1. FIG. 3 is a schematic top view of the semiconductor device of the first embodiment. FIG. 4 is a schematic bottom view of the semiconductor device of the first embodiment.

[0011] The semiconductor device 100 includes a diode chip 10 (semiconductor chip), a die pad 12, a lead portion 14, a connection layer 16, a plurality of bonding wires 18, and a resin layer 20.

[0012] The diode chip 10 includes an anode electrode 10a (upper electrode), a cathode electrode 10b (lower electrode), and a silicon carbide layer 10c. The die pad 12 includes a central region 12a (first region) and a peripheral region 12b (second region).

[0013] The diode chip 10 is an example of a semiconductor chip. The anode electrode 10a is an example of an upper electrode. The cathode electrode 10b is an example of a lower electrode. The central region 12a is an example of a first region. The peripheral region 12b is an example of a second region.

[0014] The die pad 12 has, for example, a rectangular shape. The die pad 12 includes a central region 12a and a peripheral region 12b. The peripheral region 12b surrounds the central region 12a.

[0015] 2, the thickness of the peripheral region 12b is thinner than the thickness of the central region 12a. The thickness of the central region 12a is, for example, 0.1 mm or more and 1 mm or less. The thickness of the peripheral region 12b is, for example, half or less of the thickness of the central region 12a.

[0016] The thin peripheral region 12b is provided to improve the support characteristics of the resin layer 20 for the die pad 12.

[0017] The die pad 12 is made of a metal, for example, copper or a copper alloy.

[0018] 1, a direction parallel to one side of the die pad 12 is defined as a first direction, and a direction parallel to the other side of the die pad 12 is defined as a second direction. The first direction is, for example, a direction parallel to a short side of the die pad 12, and the second direction is a direction parallel to a long side of the die pad 12.

[0019] For convenience of explanation, the direction of the die pad 12 on which the diode chip 10 is provided will be referred to as "upper" and the opposite direction as "lower."

[0020] The diode chip 10 includes an anode electrode 10a, a cathode electrode 10b, and a silicon carbide layer 10c. The silicon carbide layer 10c is provided between the anode electrode 10a and the cathode electrode 10b.

[0021] The diode chip 10 is provided on the die pad 12. The diode chip 10 is provided on the surface of the die pad 12. The diode chip 10 is provided on the surface of the die pad 12, inside the peripheral region 12b.

[0022] The diode chip 10 has a chip size of, for example, 1 mm×1 mm. The silicon carbide layer 10c has a thickness of, for example, 50 μm or more and 150 μm or less.

[0023] A first distance (d1 in FIG. 1) in a first direction between the diode chip 10 and the peripheral region 12b is, for example, equal to or greater than the thickness of the silicon carbide layer 10c. The first distance d1 is, for example, equal to or greater than 50 μm.

[0024] The second distance (d2 in FIG. 1) in the first direction between the diode chip 10 and the end of the die pad 12 is, for example, shorter than the third distance (d3 in FIG. 1) in the direction opposite to the first direction between the diode chip 10 and the end of the die pad 12. The difference between the third distance d3 and the second distance d2 is, for example, equal to or greater than the width of the diode chip 10 in the first direction. The difference between the third distance d3 and the second distance d2 is, for example, equal to or greater than three times the width of the diode chip 10 in the first direction. The difference between the third distance d3 and the second distance d2 is, for example, equal to or greater than 1 mm.

[0025] The connection layer 16 is provided between the die pad 12 and the diode chip 10. The connection layer 16 connects the die pad 12 and the diode chip 10. The connection layer 16 connects the cathode electrode 10b of the diode chip 10 to the surface of the die pad 12.

[0026] The connection layer 16 is a conductor. The connection layer 16 includes, for example, a solder. The connection layer 16 is, for example, a solder layer.

[0027] The thickness of the connection layer 16 is, for example, not less than 2 μm and not more than 10 μm.

[0028] The lead portions 14 are provided in a first direction of the die pad 12. The lead portions 14 are not provided, for example, in a direction opposite to the first direction of the die pad 12. The lead portions 14 are not provided, for example, in a second direction of the die pad 12 and in a direction opposite to the second direction.

[0029] The leads 14 are provided for establishing electrical connection between the diode chip 10 and the outside of the semiconductor device 100 .

[0030] The lead portion 14 is made of a metal, for example, copper or a copper alloy, and is formed of, for example, the same material as the die pad 12.

[0031] The bonding wire 18 connects the anode electrode 10a of the diode chip 10 to the lead portion 14. The bonding wire 18 electrically connects the anode electrode 10a to the lead portion 14.

[0032] The bonding wire 18 is a metal wire. The bonding wire 18 includes, for example, copper (Cu) or aluminum (Al). The bonding wire 18 is, for example, a copper wire or an aluminum wire.

[0033] The resin layer 20 surrounds the diode chip 10 and the bonding wires 18. The resin layer 20 has a function of protecting the diode chip 10 and the bonding wires 18.

[0034] The resin layer 20 contains a resin, for example, an epoxy resin.

[0035] 3, for example, only the resin layer 20 exists on the upper surface of the semiconductor device 100. Also, as shown in Fig. 4, for example, a part of the die pad 12 and a part of the lead portion 14 are exposed on the lower surface of the semiconductor device 100.

[0036] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0037] In a semiconductor device in which a semiconductor chip is fixed onto a die pad using a connection layer such as solder, high reliability is required for the connection using the connection layer. For example, if peeling of the semiconductor chip occurs at the connection due to temperature changes that the semiconductor device experiences during use, the device characteristics of the semiconductor device change, causing a problem. For example, if the semiconductor device is a diode, peeling at the connection increases the on-resistance of the diode, causing a problem.

[0038] The peeling of the semiconductor chip is caused by stress generated by the difference in thermal expansion coefficient between members formed of different materials, such as the semiconductor chip, die pad, resin layer, solder layer, and bonding wire. When the semiconductor chip includes a silicon carbide layer, the peeling of the semiconductor chip is accelerated, as compared to when the semiconductor chip includes a silicon layer. The reason why the peeling of the semiconductor chip is accelerated when the semiconductor chip includes a silicon carbide layer is considered to be related to the fact that the silicon carbide layer has a higher Young's modulus than the silicon layer. In addition, it is also considered to be related to the fact that the semiconductor chip using the silicon carbide layer has a larger current amount per chip unit area and generates a larger amount of heat, as compared to a semiconductor chip using a silicon layer.

[0039] Fig. 5 is a schematic top view of a semiconductor device of a first comparative example of the first embodiment, which corresponds to Fig. 1 of the first embodiment.

[0040] The semiconductor device of the first comparative example is a semiconductor device 901. In the semiconductor device 901, a diode chip including a silicon carbide layer is resin-packaged, similarly to the semiconductor device 100 of the first embodiment.

[0041] The semiconductor device 901 of the first comparative example differs from the semiconductor device 100 of the first embodiment in that a part of the diode chip 10 is provided in the peripheral region 12b of the die pad 12.

[0042] In the semiconductor device 901, peeling of the diode chip 10 is likely to occur at the connection using the connection layer 16. This is believed to be because high stress occurs at the boundary between the central region 12a and the peripheral region 12b, which have different thicknesses. Therefore, it is believed that the stress applied to the connection between the die pad 12 and the diode chip 10 becomes high, making the diode chip 10 more likely to peel off.

[0043] In the semiconductor device 100 of the first embodiment, the diode chip 10 is provided on the surface of the die pad 12, inside the peripheral region 12b. Therefore, the stress applied to the connection between the die pad 12 and the diode chip 10 is smaller than that in the semiconductor device 901 of the first comparative example. Therefore, peeling of the diode chip 10 is suppressed, and the reliability of the semiconductor device 100 is improved.

[0044] From the viewpoint of reducing stress applied to the connection portion between the die pad 12 and the diode chip 10, the first distance (d1 in FIG. 1) in the first direction between the diode chip 10 and the peripheral region 12b is preferably equal to or greater than the thickness of the silicon carbide layer 10c. Moreover, from the viewpoint of reducing stress applied to the connection portion between the die pad 12 and the diode chip 10, the first distance d1 is preferably equal to or greater than 50 μm, and more preferably equal to or greater than 100 μm.

[0045] Fig. 6 is a schematic top view of a semiconductor device of a second comparative example of the first embodiment, which corresponds to Fig. 1 of the first embodiment.

[0046] The semiconductor device of the second comparative example is a semiconductor device 902. In the semiconductor device 902, a diode chip including a silicon carbide layer is resin-packaged, similarly to the semiconductor device 100 of the first embodiment.

[0047] The semiconductor device 902 of the second comparative example differs from the semiconductor device 100 of the first embodiment in that the second distance (d2 in FIG. 6) in the first direction between the diode chip 10 and the end of the die pad 12 is longer than the third distance (d3 in FIG. 6) in the direction opposite to the first direction between the diode chip 10 and the end of the die pad 12.

[0048] The stress applied to the connection portion between the die pad 12 and the diode chip 10 changes due to the contraction or expansion of the bonding wire 18 and the resin layer 20 surrounding the bonding wire 18. It is considered that the stress applied to the connection portion between the die pad 12 and the diode chip 10 increases as the length of the bonding wire 18 increases.

[0049] In the MOSFET 100, a second distance (d2 in FIG. 1) in a first direction between the diode chip 10 and the end of the die pad 12 is shorter than a third distance (d3 in FIG. 1) in a direction opposite to the first direction between the diode chip 10 and the end of the die pad 12.

[0050] By making the second distance d2 shorter than the third distance d3, the distance between the diode chip 10 and the lead portion 14 is shorter than that of the semiconductor device 902 of the second comparative example. By shortening the distance between the diode chip 10 and the lead portion 14, the length of the bonding wire 18 can be shortened. Therefore, compared to the semiconductor device 902 of the second comparative example, the stress applied to the connection portion between the die pad 12 and the diode chip 10 due to the bonding wire 18 and the resin layer 20 surrounding the bonding wire 18 is smaller. Therefore, peeling of the diode chip 10 is suppressed, and the reliability of the semiconductor device 100 is improved.

[0051] From the viewpoint of reducing stress applied to the connection portion between the die pad 12 and the diode chip 10, the difference between the third distance d3 and the second distance d2 is preferably equal to or greater than the width of the diode chip 10 in the first direction. From the viewpoint of reducing stress applied to the connection portion between the die pad 12 and the diode chip 10, the difference between the third distance d3 and the second distance d2 is preferably equal to or greater than 1 mm, and more preferably equal to or greater than 2 mm.

[0052] In the MOSFET 100, the thickness of the connection layer 16 is preferably 10 μm or less. By making the thickness of the connection layer 16 10 μm or less, the resistance of the connection layer 16 is reduced, and the amount of heat generated in the connection layer 16 is suppressed. Therefore, the stress applied to the connection portion between the die pad 12 and the diode chip 10 is reduced. Therefore, peeling of the diode chip 10 is suppressed, and the reliability of the semiconductor device 100 is improved.

[0053] As described above, according to the first embodiment, a semiconductor device in which peeling of the semiconductor chip is suppressed and reliability is improved can be realized.

[0054] Second Embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the angle between the extending direction of the bonding wires and the first direction is 5 degrees or less. In the following, some of the contents that overlap with the first embodiment may be omitted.

[0055] Fig. 7 is a schematic top view of a semiconductor device according to a second embodiment, which corresponds to Fig. 1 of the first embodiment.

[0056] The semiconductor device of the second embodiment is a semiconductor device 200. In the semiconductor device 200, a diode chip including a silicon carbide layer is resin-packaged, similarly to the semiconductor device 100 of the first embodiment.

[0057] In the semiconductor device 200, the angle between the extension directions of all of the bonding wires 18 and the first direction is 5 degrees or less. Fig. 7 illustrates a case where the angle between the extension directions of the bonding wires 18 and the first direction is 0 degrees, that is, the extension directions of the bonding wires 18 and the first direction are parallel to each other.

[0058] As a result of the inventor's study, it was confirmed that peeling of the diode chip 10 is suppressed by making the angle between the extension direction of the bonding wires 18 and the first direction 5 degrees or less. Although the reason is not necessarily clear, it is considered to be due to the effect of limiting the direction of the stress applied to the diode chip 10 to the first direction by the multiple bonding wires 18.

[0059] In order to prevent the diode chip 10 from peeling off, the angle between the extension direction of all of the bonding wires 18 and the first direction is preferably 3 degrees or less, more preferably 1 degree or less, and further preferably 0 degrees.

[0060] As described above, according to the second embodiment, a semiconductor device in which peeling of the semiconductor chip is suppressed and reliability is improved can be realized.

[0061] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that the bonding wires include a first bonding wire and a second bonding wire, and the position where the first bonding wire is connected to the upper electrode and the position where the second bonding wire is connected to the upper electrode are shifted in a first direction. Hereinafter, some of the contents that overlap with the first and second embodiments may be omitted.

[0062] Fig. 8 is a schematic top view of a semiconductor device according to a third embodiment, which corresponds to Fig. 1 of the first embodiment and Fig. 7 of the second embodiment.

[0063] The semiconductor device of the third embodiment is a semiconductor device 300. In the semiconductor device 300, a diode chip including a silicon carbide layer is resin-packaged, similarly to the semiconductor device 100 of the first embodiment.

[0064] The semiconductor device 300 includes a first bonding wire 18a and a second bonding wire 18b. The first bonding wire 18a and the second bonding wire 18b are adjacent to each other in the second direction. The angle between the first direction and the extension direction of the first bonding wire 18a and the second bonding wire 18b is 5 degrees or less.

[0065] The position where the first bonding wire 18a is connected to the anode electrode 10a and the position where the second bonding wire 18b is connected to the anode electrode 10a are offset in a first direction. Also, the position where the first bonding wire 18a is connected to the lead portion 14 and the position where the second bonding wire 18b is connected to the lead portion 14 are offset in the first direction.

[0066] Due to the above-described configuration, the semiconductor device 300 can shorten the interval between adjacent bonding wires compared to the semiconductor device 200. Therefore, it is possible to increase the number of bonding wires connecting the anode electrode 10a and the lead portion 14.

[0067] In the semiconductor device 300, peeling of the diode chip 10 is suppressed by shortening the interval between adjacent bonding wires and increasing the number of bonding wires. By shortening the interval between the adjacent first bonding wire 18a and second bonding wire 18b, the amount of the resin layer 20 between the adjacent bonding wires is reduced. It is believed that the reduction in the amount of the resin layer 20 between the adjacent bonding wires reduces the stress applied to the diode chip 10 by the bonding wires.

[0068] As described above, according to the third embodiment, a semiconductor device in which peeling of the semiconductor chip is suppressed and reliability is improved can be realized.

[0069] In the first to third embodiments, a diode is used as an example of the semiconductor chip, but the semiconductor chip is not limited to a diode. For example, the semiconductor chip may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT).

[0070] In the first to third embodiments, the number of bonding wires is three or five, but the number of bonding wires may be any number.

[0071] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0072] 10 Diode chip (semiconductor chip) 10a Anode electrode (upper electrode) 10b Cathode electrode (lower electrode) 10c silicon carbide layer 12 Die pad 12a Central Area (First Area) 12b Peripheral area (second area) 14 Lead section 16 Connection Layer 18 Bonding Wire 18a First bonding wire 18b Second Bonding Wire 20 Resin layer 100 Semiconductor devices (semiconductor equipment) d1 First distance d2 Second distance d3 The third distance

Claims

1. a die pad including a first region and a second region surrounding the first region and having a thickness smaller than that of the first region; a semiconductor chip including an upper electrode, a lower electrode, and a silicon carbide layer between the upper electrode and the lower electrode, the semiconductor chip being provided on a surface of the die pad on an inner side than the second region; a connection layer connecting the bottom electrode to the surface; a lead portion provided in a first direction of the die pad; a plurality of bonding wires connecting the upper electrode and the lead portion; a resin layer surrounding the semiconductor chip and the plurality of bonding wires; Equipped with an angle between an extending direction of the bonding wires and the first direction is 5 degrees or less; the plurality of bonding wires includes a plurality of first bonding wires and a plurality of second bonding wires; the first bonding wires and the second bonding wires are alternately arranged in a second direction perpendicular to the first direction; the first bonding wire is connected to the upper electrode at a first position, and the first bonding wire is connected to the lead portion at a second position; the second bonding wire is connected to the upper electrode at a third position, and the second bonding wire is connected to the lead portion at a fourth position; The semiconductor device, wherein the first position, the third position, the second position, and the fourth position are arranged in this order in the first direction.

2. The semiconductor device according to claim 1 , wherein a first distance between the semiconductor chip and the second region is equal to or greater than a thickness of the silicon carbide layer.

3. 2. The semiconductor device according to claim 1, wherein a second distance in the first direction between the semiconductor chip and the end of the die pad is shorter than a third distance in a direction opposite to the first direction between the semiconductor chip and the end of the die pad.

4. 4. The semiconductor device according to claim 3, wherein the difference between the third distance and the second distance is equal to or greater than the width of the semiconductor chip in the first direction.

5. 2. The semiconductor device according to claim 1, wherein the thickness of the connection layer is 10 [mu]m or less.

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