Semiconductor Devices

Abstract

To present a semiconductor device that includes a plurality of two capacitor structures formed spaced apart from each other on a semiconductor substrate.SOLUTION: A first capacitor structure CAP1 includes: a first trench T1 formed in a semiconductor substrate; first to third electrode layers E1 to E3 disposed in the first trench; and first to third dielectric layers D1 to D6 disposed in an interlace structure with the semiconductor substrate and the first to third electrodes. The second capacitor structure CAP2 includes: a second trench T2 formed in the semiconductor substrate; fourth to sixth electrode layers E4 to E6 disposed in the second trench; and fourth to sixth dielectric layers D4 to D6 disposed in the interlace structure with the semiconductor substrate and the fourth to sixth electrode layers. A connection blocking region CBA is formed between the first and second capacitor structures to block a connection between each element constituting the first capacitor structure and each element constituting the second capacitor structure.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices having trench capacitors. [Background technology]

[0002] The integration of large-capacity capacitors used as bypass capacitors or decoupling capacitors into ICs is an important issue, and as the demand for MLCCs (Multi-Layer Ceramic Capacitors) and SLCs (Single Layer Capacitors) is increasing as part of the realization of large-capacity capacitors, research and development of trench capacitors, which have superior storage performance and reliability compared to MLCCs and SLCs and can be integrated, is being continuously conducted.

[0003] A trench capacitor has an advantage in that it can secure sufficient capacitance without the step problem compared to a stack capacitor in that the capacitor is implemented through a trench formed on a semiconductor substrate. Therefore, trench capacitors that can secure sufficient capacitance without the step problem are now widely used.

[0004] The background art of the present invention is disclosed in Korean Patent Publication No. 10-2005-0054637 (published on June 10, 2005). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Republic of Korea Patent Publication No. 10-2005-0054637 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one aspect of the present invention is to provide a semiconductor device that can expand the utility of trench capacitors in a semiconductor device (e.g., an integrated circuit (IC)) having a plurality of trench capacitors and eliminate sticking problems, warpage problems, and substrate crack problems caused by stress applied to a semiconductor substrate during a trench capacitor process. [Means for solving the problem]

[0007] The present invention provides a semiconductor device including first and second capacitor structures formed spaced apart from each other on a semiconductor substrate, the first capacitor structure including a first trench formed in the semiconductor substrate, first to third electrode layers disposed in the first trench, and first to third dielectric layers disposed in an interlace structure with the semiconductor substrate and the first to third electrode layers, the second capacitor structure including a second trench formed in the semiconductor substrate, fourth to sixth electrode layers disposed in the second trench, and fourth to sixth dielectric layers disposed in an interlace structure with the semiconductor substrate and the fourth to sixth electrode layers, and a connection interruption region is formed between the first and second capacitor structures to interrupt connections between elements constituting the first capacitor structure and elements constituting the second capacitor structure.

[0008] In the present invention, each element constituting the first capacitor structure and each element constituting the second capacitor structure that correspond to each other are formed through the same semiconductor process.

[0009] In the present invention, the semiconductor substrate, the first dielectric layer, and the first electrode layer constitute a first sub-capacitor structure of the first capacitor structure, the first electrode layer, the second dielectric layer, and the second electrode layer constitute a second sub-capacitor structure of the first capacitor structure, the second electrode layer, the third dielectric layer, and the third electrode layer constitute a third sub-capacitor structure of the first capacitor structure, the semiconductor substrate, the fourth dielectric layer, and the fourth electrode layer constitute a fourth sub-capacitor structure of the second capacitor structure, the fourth electrode layer, the fifth dielectric layer, and the fifth electrode layer constitute a fifth sub-capacitor structure of the second capacitor structure, and the fifth electrode layer, the sixth dielectric layer, and the sixth electrode layer constitute a sixth sub-capacitor structure of the second capacitor structure, and the semiconductor device further includes a connecting structure connected to the semiconductor substrate and the first to sixth electrode layers to provide a parallel connection of a plurality of sub-capacitor structures selected from the first to sixth sub-capacitor structures or to allow each sub-capacitor structure to function as a single capacitor.

[0010] In the present invention, the connection structure includes a contact-metal structure for providing a parallel connection of the first and fourth sub-capacitor structures, a parallel connection of the second and fifth sub-capacitor structures, and a parallel connection of the third and sixth sub-capacitor structures.

[0011] In the present invention, the connection structure includes a contact-metal structure for providing parallel connection of N sub-capacitor structures selected from the first to sixth sub-capacitor structures and allowing the remaining M sub-capacitor structures to function as a single capacitor.

[0012] In the present invention, each of the first to sixth dielectric layers has a thickness profile corresponding to a voltage profile predefined by voltages applied to the first to sixth sub-capacitor structures, so that a plurality of voltages having different voltage values ​​can be applied to the first and second capacitor structures.

[0013] In the present invention, the semiconductor substrate itself is highly doped to form a common ground electrode for the first and second capacitor structures.

[0014] In the present invention, the first trench has a first length and the second trench has a second length greater than the first length, based on a first direction on the semiconductor substrate.

[0015] In the present invention, the first and second trenches are alternately arranged in at least a portion of the semiconductor substrate with respect to the first direction or the second direction, and the arrangement structure of the first and second trenches on the semiconductor substrate has irregularity.

[0016] In the present invention, the semiconductor device includes a first trench module, and the first trench module includes the second trench and the first trenches arranged on both sides of the second trench based on a second direction perpendicular to the first direction.

[0017] In the present invention, the semiconductor device includes a second trench module, the second trench module including the first trench and the second trenches disposed on both sides of the first trench based on the second direction.

[0018] In the present invention, the first trench module and the second trench module are arranged adjacent to each other based on the second direction, and when the adjacently arranged first trench module and the second trench module are defined as a composite trench module, the first trench module is additionally arranged on one side of the composite trench module based on the first direction or the second direction, and the additionally arranged first trench module has the second direction as its length direction.

[0019] The present invention provides a semiconductor device including first and second mesh structures defined by a trench formed in a semiconductor substrate, the trench having a plurality of electrode layers and one or more dielectric layers arranged in an interlaced structure with the semiconductor substrate and the plurality of electrode layers, the first and second mesh structures each including, at least in part, a tapered portion whose width narrows toward the bottom of the first and second mesh structures, respectively.

[0020] In the present invention, a void for stress relief is formed inside the trench in which the plurality of electrode layers and the one or more dielectric layers are stacked, the void having a width profile corresponding to the tapered portion.

[0021] In the present invention, the void is a free space that is enclosed by only an outermost electrode layer among a plurality of electrode layers disposed in the trench.

[0022] In the present invention, the outermost electrode layer is disposed along a bottom surface, a first sidewall and a second sidewall of the trench, and the outermost electrode layer disposed along the first sidewall and the outermost electrode layer disposed along the second sidewall are brought into contact with each other above the tapered portion by the tapered portion, thereby closing an upper opening of the trench and forming the void.

[0023] In the present invention, the void is formed independently of an inter-layer dielectric (ILD) applied to the semiconductor device by contacting the outermost electrode layer on the upper side of the tapered portion. Effect of the Invention

[0024] According to the present invention, in a semiconductor device (e.g., an integrated circuit (IC)) having multiple trench capacitors, the utility of the trench capacitors can be expanded, and sticking problems, warpage problems, and substrate crack problems caused by stress applied to a semiconductor substrate during the trench capacitor process can be eliminated. [Brief description of the drawings]

[0025] [Figure 1] 1 is a cross-sectional view showing a capacitor structure in a semiconductor device according to an embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view showing first and second capacitor structures in a semiconductor device according to an embodiment of the present invention. FIG. [Figure 3A] 1 is a circuit diagram showing a method of connecting sub-capacitor structures according to a method of implementing a connecting structure in a semiconductor device according to an embodiment of the present invention; [Figure 3B] 1 is a circuit diagram showing a method of connecting sub-capacitor structures according to a method of implementing a connecting structure in a semiconductor device according to an embodiment of the present invention; [Figure 3C] 1 is a circuit diagram showing a method of connecting sub-capacitor structures according to a method of implementing a connecting structure in a semiconductor device according to an embodiment of the present invention; [Figure 3D] 1 is a circuit diagram showing a method of connecting sub-capacitor structures according to a method of implementing a connecting structure in a semiconductor device according to an embodiment of the present invention; [Figure 3E] 1 is a circuit diagram showing a method of connecting sub-capacitor structures according to a method of implementing a connecting structure in a semiconductor device according to an embodiment of the present invention; [Figure 3F]1 is a circuit diagram showing a method of connecting sub-capacitor structures according to a method of implementing a connecting structure in a semiconductor device according to an embodiment of the present invention; [Figure 4A] 1 is an exemplary diagram showing a trench arrangement in a semiconductor device according to an embodiment of the present invention; [Figure 4B] 1 is an exemplary diagram showing a trench arrangement in a semiconductor device according to an embodiment of the present invention; [Figure 5A] 1 is a cross-sectional view showing a tapered portion and a void of a mesh structure in a semiconductor device according to an embodiment of the present invention. [Figure 5B] 1 is a cross-sectional view showing a tapered portion and a void of a mesh structure in a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, a semiconductor device according to the present invention will be described with reference to the accompanying drawings. In the process, the thickness of lines and the size of components shown in the drawings may be exaggerated for clarity and convenience of the description. In addition, the terms described below are defined in consideration of the functions of the present invention, and may vary depending on the intention or practice of a user or operator. Therefore, the definitions of such terms should be based on the entire contents of this specification.

[0027] When a layer, film, region, plate, or other part described in this specification is described as being "on" or "above" another part, this includes not only the case where the part is "directly on" the other part, but also the case where there is another part in between. Conversely, when a part is described as being "directly on" another part, it means that there is no other part in between. In addition, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" the side opposite to gravity.

[0028] In addition, throughout the specification, when a part "comprises" a certain element, this does not mean to exclude other elements, but means that it may further include other elements, unless specifically stated to the contrary.

[0029] Also, throughout the specification, "on a plane" means when the part is viewed from above, and "on a cross section" means when the part is cut vertically and viewed from the side.

[0030] Furthermore, throughout the specification, when the term "connected" is used, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected through other components, that are not only physically connected but also electrically connected, or that are designated by different names depending on their position or function but are a single entity.

[0031] In addition, although terms such as "first" or "second" are used to describe various components, such components are not limited by such terms. Such terms may be used merely to distinguish one component from another component. Thus, a first component referred to below may be a second component within the technical spirit of the present invention.

[0032] FIG. 1 is a cross-sectional view showing a capacitor structure in a semiconductor device according to this embodiment, FIG. 2 is a cross-sectional view showing first and second capacitor structures in a semiconductor device according to this embodiment, FIG. 3 is a circuit diagram showing a method of connecting sub-capacitor structures according to a method of implementing a connecting structure in a semiconductor device according to this embodiment, FIG. 4 is an example diagram showing a trench arrangement in a semiconductor device according to this embodiment, and FIG. 5 is a cross-sectional view showing a tapered portion and voids of a mesh structure in a semiconductor device according to this embodiment.

[0033] 1. Capacitor structure

[0034] Referring to FIG. 1, a capacitor structure CAP1 of this embodiment can be defined as a structure including a trench T1 formed in a semiconductor substrate S, a plurality of electrode layers E1-E3 disposed in the trench T1, and one or more dielectric layers D1-D3 arranged in an interlace structure with the semiconductor substrate S and the plurality of electrode layers E1-E3.

[0035] The semiconductor substrate S may be an N-type silicon substrate, and may be highly doped with an N-type dopant (N++ highly doped), so that the semiconductor substrate S itself may be configured as a ground electrode for the capacitor structure CAP1. The trench T1 formed in the semiconductor substrate S may correspond to a deep trench, and may be formed with a high aspect ratio having a depth of 10 μm or 100 μm or more. Each of the electrode layers E1-E3 may be formed of, but is not limited to, N-type doped polysilicon, and may be formed of a metallic material (such as copper or aluminum). Each of the dielectric layers D1-D3 may be formed of a high-density dielectric and a high-K dielectric material, such as SiN, BaTiO3, PZT, Al2O3, Ta2O3, and HfO2.

[0036] The capacitor structure CAP1 may be formed by stacking a plurality of electrode layers E1-E3 and one or more dielectric layers D1-D3 in an interlaced structure, so that the capacitor structure CAP1 may include a plurality of sub-capacitor structures SCAP1-SCAP3. Fig. 1 shows an example in which the capacitor structure CAP1 is formed by stacking three electrode layers E1-E3 and three dielectric layers D1-D3 in an interlaced structure, that is, the capacitor structure CAP1 in Fig. 1 has a structure in which a semiconductor substrate S, a first dielectric layer D1, a first electrode layer E1, a second dielectric layer D2, a second electrode layer E2, a third dielectric layer D3, and a third electrode layer E3 are stacked in this order. The semiconductor substrate S and the first electrode layer E1 are insulated by the first dielectric layer D1, the first electrode layer E1 and the second electrode layer E2 are insulated by the second dielectric layer D2, and the second electrode layer E2 and the third electrode layer E3 are insulated by the third dielectric layer D3. For ease of understanding of the embodiment, the capacitor structure CAP1 will be described in this embodiment as including three electrode layers E1-E3 and three dielectric layers D1-D3.

[0037] The semiconductor substrate S, the first dielectric layer D1, and the first electrode layer E1 constitute the first sub-capacitor structure SCAP1 of the capacitor structure CAP1, the first electrode layer E1, the second dielectric layer D2, and the second electrode layer E2 constitute the second sub-capacitor structure SCAP2 of the capacitor structure CAP1, and the second electrode layer E2, the third dielectric layer D3, and the third electrode layer E3 constitute the third sub-capacitor structure SCAP3 of the capacitor structure CAP1. The semiconductor substrate S is grounded, and a voltage is applied to the first to third electrode layers E1-E3 through an interconnection structure (Interconnection Structure) described later, so that the first to third sub-capacitor structures SCAP1-SCAP3 can each operate as a capacitor. For convenience of explanation, the positions of the first to third sub-capacitor structures SCAP1-SCAP3 on the stacked structure are denoted as Level 1 to Level 3 (LV1-LV3) below.

[0038] 2. Connection Blocking Regions and Connection Structures

[0039] The semiconductor device of this embodiment is configured to include a plurality of capacitor structures formed on a semiconductor substrate S at a distance from each other. As shown in FIG. 2, two adjacent capacitor structures among the plurality of capacitor structures are defined as first and second capacitor structures CAP1 and CAP2, and the first and second capacitor structures CAP1 and CAP2 are configured to have the same stack structure and material. In the examples of FIG. 1 and FIG. 2, the capacitor structures CAP1 and CAP2 are described as including three electrode layers (E1-E3 / E4-E6) and three dielectric layers (D1-D3 / D4-D6). For the sake of clear distinction of terms, the terms first trench T1, first to third dielectric layers D1-D3, and first to third electrode layers E1-E3 are used for the first capacitor structure CAP1, and the terms second trench T2, fourth to sixth dielectric layers D4-D6, and fourth to sixth electrode layers E4-E6 are used for the second capacitor structure CAP2. A protruding portion of the semiconductor substrate S located between the first trench T1 of the first capacitor structure CAP1 and the second trench T2 of the second capacitor structure CAP2 (i.e., a protruding portion of the semiconductor substrate S partitioning the first and second trenches T1, T2) is defined as a mesh structure (a tapered portion of the mesh structure, which will be described later, is not shown in FIG. 2 to facilitate understanding of the embodiment). Meanwhile, the first and second capacitor structures CAP1 and CAP2 share the semiconductor substrate S with a common ground electrode.

[0040] Accordingly, the semiconductor substrate S, the first dielectric layer D1 and the first electrode layer E1 constitute a first sub-capacitor structure SCAP1 of the first capacitor structure CAP1, the first electrode layer E1, the second dielectric layer D2 and the second electrode layer E2 constitute a second sub-capacitor structure SCAP2 of the first capacitor structure CAP1, and the second electrode layer E2, the third dielectric layer D3 and the third electrode layer E3 constitute a third sub-capacitor structure SCAP3 of the first capacitor structure CAP1.

[0041] Similarly, the semiconductor substrate S, the fourth dielectric layer D4 and the fourth electrode layer E4 constitute a fourth sub-capacitor structure SCAP4 of the second capacitor structure CAP2, the fourth electrode layer E4, the fifth dielectric layer D5 and the fifth electrode layer E5 constitute a fifth sub-capacitor structure SCAP5 of the second capacitor structure CAP2, and the fifth electrode layer E5, the sixth dielectric layer D6 and the sixth electrode layer E6 constitute a sixth sub-capacitor structure SCAP6 of the second capacitor structure CAP2.

[0042] As shown in FIG. 2, a connection blocking area (CBA) is formed between the first and second capacitor structures CAP1 and CAP2, in which connections between each element constituting the first capacitor structure CAP1 (i.e., the first to third dielectric layers D1-D3 and the first to third electrode layers E1-E3) and each element constituting the second capacitor structure CAP2 (i.e., the fourth to sixth dielectric layers D4-D6 and the fourth to sixth electrode layers E4-E6) are blocked.

[0043] The connection blocking region CBA functions as a base structure for connecting a plurality of sub-capacitor structures selected from the first to sixth sub-capacitor structures SCAP1-SCAP6 in parallel or for operating each sub-capacitor structure as a single capacitor. Based on an integrated circuit (IC) in which the semiconductor device of this embodiment is integrated, the capacitance required for each integrated circuit may be different, and even the same integrated circuit may require multiple capacitances for the operation of the corresponding integrated circuit depending on the application to which the integrated circuit is applied, and an integrated circuit to which multiple operating voltages are applied may also require multiple capacitances for the operation of the corresponding integrated circuit.

[0044] In order to expand the application to such integrated circuits, this embodiment employs a structure in which the elements of the first capacitor structure CAP1 and the elements of the second capacitor structure CAP2 are disconnected from each other, rather than a structure in which the elements of the first and second capacitor structures CAP1 and CAP2 are connected to each other. That is, the connection between the first and fourth electrode layers E1, E4, between the second and fifth electrode layers E2, E5, between the third and sixth electrode layers E3, E6, between the first and fourth dielectric layers D1, D4, between the second and fifth dielectric layers D2, D5, and between the third and sixth dielectric layers D3, D6 is interrupted by the connection interruption region CBA.

[0045] In relation to the processes of the first and second capacitor structures CAP1 and CAP2, the elements constituting the first capacitor structure CAP1 and the elements constituting the second capacitor structure CAP2 that correspond to each other may be formed through the same semiconductor process. That is, in a state in which the connection blocking region CBA is masked, the first and second trenches T1 and T2 are sequentially subjected to the following processes: "Process 1 (simultaneous formation of first and fourth dielectric layers D1, D4 by dielectric layer deposition)", "Process 2 (simultaneous formation of first and fourth electrode layers E1, E4 by electrode layer deposition)", "Process 3 (simultaneous formation of second and fifth dielectric layers D2, D5 by dielectric layer deposition)", "Process 4 (simultaneous formation of second and fifth electrode layers E2, E5 by electrode layer deposition)", "Process 5 (simultaneous formation of third and sixth dielectric layers D3, D6 by dielectric layer deposition)", and "Process 6 (simultaneous formation of third and sixth electrode layers E3, E6 by electrode layer deposition)" to form the connection blocking region CBA and the elements of the capacitor structures CAP1 and CAP2. In addition, the first and fourth dielectric layers D1, D4 are simultaneously formed through the first process, so that the first and fourth dielectric layers D1, D4 have the same first thickness, the second and fifth dielectric layers D2, D5 are simultaneously formed through the third process, so that the second and fifth dielectric layers D2, D5 have the same second thickness, and the third and sixth dielectric layers D3, D6 are simultaneously formed through the fifth process, so that the third and sixth dielectric layers D3, D6 have the same third thickness. The first to third thicknesses constitute a thickness profile of the semiconductor device, and such a thickness profile (i.e., the values ​​of the first to third thicknesses) may be predefined by the voltages applied to the first to sixth sub-capacitor structures SCAP1-SCAP6. Each of the dielectric layers D1-D6 having the thickness profile is configured so that a plurality of voltages having different voltage values ​​can be applied to the first and second capacitor structures.

[0046] The connection structure is configured to be connected to the semiconductor substrate S and the first to sixth electrode layers E1-E6 to provide a parallel connection of a plurality of sub-capacitor structures selected from the first to sixth sub-capacitor structures SCAP1-SCAP6 or to allow each sub-capacitor structure to function as a single capacitor. For this purpose, the connection structure may include contacts CS, C1-C6 respectively connected to the semiconductor substrate S and the first to sixth electrode layers E1-E6, and metal interconnects (MI) for forming a parallel connection of the plurality of sub-capacitor structures (the metal interconnects are omitted in the drawings for clear illustration of the configuration, and physical metal interconnects may be realized according to the wiring method of the electrode layers according to FIG. 3) (when each sub-capacitor structure is made to function as a single capacitor, a structure may be applied in which each contact (and a contact pad (not shown) connected to the contact) is directly connected to a PCB integrated into an integrated circuit, and therefore the metal interconnects may be omitted).

[0047] The connection method of each sub-capacitor structure by the connection structure may be i) a method of using each sub-capacitor structure as a single capacitor (hereinafter, a single method), ii) a method of providing a sub-capacitor structure with a plurality of parallel connection structures (hereinafter, a multiple parallel connection method), or iii) a method of combining parallel connection and single use of the sub-capacitor structures (hereinafter, a mixed method). Each case will be described in detail.

[0048] (1) Single method

[0049] As described above, in the case of the stand-alone method, a structure may be applied in which each contact (and contact pads connected to the contacts) are directly connected to a PCB integrated into an integrated circuit, so that metal wiring may be omitted, and accordingly, the connecting structure may be composed of contacts CS, C1-C6 connected to the semiconductor substrate S and the first to sixth electrode layers E1-E6, respectively, and contact pads connected to the contacts CS, C1-C6.

[0050] Meanwhile, the first to sixth sub-capacitor structures SCAP1-SCAP6 may be configured to receive the same voltage V1 (FIG. 3A), in which case the first to sixth dielectric layers D1-D6 may all be configured to have the same thickness.

[0051] The first to sixth sub-capacitor structures SCAP1-SCAP6 may be configured to receive different voltages V1-V3 (FIG. 3B). For example, the first and fourth sub-capacitor structures SCAP1 and SCAP4 may be configured to receive a first voltage V1 (e.g., 1.2V), the second and fifth capacitor structures SCAP2 and SCAP5 may be configured to receive a second voltage V2 (e.g., 1.8V) different from the first voltage V1, and the third and sixth capacitor structures SCAP3 and SCAP6 may be configured to receive a third voltage V3 (e.g., 3.3V) different from the first and second voltages V1 and V2. Accordingly, the first and fourth dielectric layers D1, D4 may be configured to have a first thickness having a voltage resistance to a first voltage V1, the second and fifth dielectric layers D2, D5 may be configured to have a second thickness (>first thickness) having a voltage resistance to a second voltage V2, and the third and sixth dielectric layers D3, D6 may be configured to have a third thickness (>second thickness) having a voltage resistance to a third voltage V3. Such thickness profiles of the dielectric layers according to the voltage profiles are commonly applied to the capacitor structures described herein.

[0052] (2) Multiple parallel connection method

[0053] The connection structure may include a contact-metal structure for providing a parallel connection of the first and fourth sub-capacitor structures SCAP1 and SCAP4, a parallel connection of the second and fifth sub-capacitor structures SCAP2 and SCAP5, and a parallel connection of the third and sixth sub-capacitor structures SCAP3 and SCAP6. This may be realized through a contact-metal connection of the first and fourth electrode layers E1 and E4, a contact-metal connection of the second and fifth electrode layers E2 and E5, and a contact-metal connection of the third and sixth electrode layers E3 and E6. As in the case of the single type, the first to sixth sub-capacitor structures SCAP1-SCAP6 may be configured to receive the same voltage V1 (FIG. 3C) or different voltages V1-V3 (FIG. 3D). In the case of a multiple parallel connection method, the capacitance at each level of levels 1 to 3 (LV1-LV3) may be increased compared to the case of the single type.

[0054] Meanwhile, when the same voltage V1 is applied to the first to sixth sub-capacitor structures SCAP1-SCAP6, a contact-metal connection structure may be adopted to connect the first and fourth electrode layers E1, E4 and the third and sixth electrode layers E3, E6 as shown in Fig. 3E. In this case, a structure is provided in which a capacitor formed by the parallel connection of the second and fifth sub-capacitor structures SCAP2, SCAP5 and a capacitor formed by the parallel connection of the third and sixth sub-capacitor structures SCAP3, SCAP6 are again connected in parallel, so that the capacitance at levels 2 and 3 (LV2, LV3) may be further increased.

[0055] (3)Mixing method

[0056] The connection structure may include a contact-metal structure for providing parallel connection of N sub-capacitor structures selected from the first to sixth sub-capacitor structures SCAP1-SCAP6 and allowing the remaining M sub-capacitor structures to function as a single capacitor (where N and M are natural numbers, N≧2, N+M=6). FIG. 3F shows an example in which the second and third sub-capacitor structures SCAP2 and SCAP3 are connected in parallel, the fifth and sixth sub-capacitor structures SCAP5 and SCAP6 are connected in parallel, and the first and fourth sub-capacitor structures SCAP1 and SCAP4 function as a single capacitor (i.e., N=4, M=2).

[0057] By employing the above-described coupling blocking region CBA and coupling structure, it is possible to ensure the scalability of application to integrated circuits in a semiconductor device having a plurality of capacitor structures.

[0058] 3. Trench array

[0059] As described above, the trench in this embodiment may be embodied as a dip trench, and as stress is applied to the semiconductor substrate S due to the high step of the dip trench, after etching the trench on the semiconductor substrate S, a sticking problem may occur in which the sidewall of the semiconductor substrate S forming the trench collapses, and warpage of the semiconductor substrate S due to the dip trench structure and resulting substrate crack problems may occur.

[0060] In order to solve the above problems, the present embodiment employs a trench arrangement as shown in FIG. 4 (for ease of understanding the embodiment, FIG. 4 omits the dielectric layer and electrode layer and only illustrates the trenches).

[0061] As shown in FIG. 4A, based on a first direction DIR1 on the semiconductor substrate S, a first trench T1 may have a first length, and a second trench T2 may have a second length greater than the first length (the first trench T1 may correspond to a trench constituting a first capacitor structure CAP1, and the second trench T2 may correspond to a trench constituting a second capacitor structure CAP2, and thus the space between the first and second trenches T1, T2 may correspond to the aforementioned connection blocking region CBA).

[0062] At this time, the first and second trenches T1, T2 are alternately arranged in at least a portion of the semiconductor substrate S based on the first direction DIR1 or the second direction DIR2, and the arrangement structure of the first and second trenches T1, T2 on the semiconductor substrate S may have irregularity. The alternate arrangement of the first and second trenches T1, T2 in the first direction DIR1 may be, for example, an arrangement structure such as "TM1_A" or "TM1_B" in FIG. 4A, and the alternate arrangement of the first and second trenches T1, T2 in the second direction DIR2 may be, for example, an arrangement structure such as "TM1" or "TM2" in FIG. Such an arrangement structure of the first and second trenches T1, T2 ensures the irregularity of the entire or part of the trench structure on the semiconductor substrate S.

[0063] Based on such first and second trenches T1, T2, first and second trench modules TM1, TM2 can be provided in this embodiment.

[0064] The first trench module TM1 may include a second trench T2 and first trenches T1 disposed on both sides of the second trench T2 with respect to a second direction DIR2 perpendicular to the first direction DIR1. As shown in Fig. 4A, in the first trench module TM1, two first trenches T1 may be disposed on both sides of one second trench T2 in the first direction DIR1, and are configured to be edge-aligned with respect to the first direction DIR1. That is, the stress applied to the semiconductor substrate S is relieved by irregularly disposing trenches having different lengths with respect to the second direction DIR2.

[0065] The second trench module TM2 may include a first trench T1 and second trenches T2 disposed on both sides of the first trench T1 with respect to a second direction DIR2. As shown in Fig. 4A, in the second trench module TM2, one second trench T2 may be disposed on both sides of the two first trenches T1 disposed in the first direction DIR1, and configured to be edge-aligned with respect to the first direction DIR1. That is, the stress applied to the semiconductor substrate S is relieved by irregularly disposing trenches having different lengths with respect to the second direction DIR2.

[0066] The first trench module TM1 and the second trench module TM2 may be arranged adjacent to each other based on the second direction DIR2, and when the adjacently arranged first trench module TM1 and second trench module TM2 are defined as a complex trench module (CTM) CTM1, a first trench module may be additionally arranged on one side of the complex trench module CTM1 based on the first direction DIR1 or the second direction DIR2 (in FIG. 4A, the first trench module additionally arranged on one side (upper side) of the complex trench module CTM1 based on the first direction DIR1 is denoted as "TM1_A", and the first trench module additionally arranged on one side (right side) of the complex trench module CTM1 based on the second direction DIR2 is denoted as "TM1_B").

[0067] In this case, the additionally arranged first trench modules TM1_A and TM1_B may be configured to have the second direction DIR2 in the length direction. Accordingly, the length direction (first direction DIR1 in FIG. 4A) of each trench constituting the composite trench module CTM1 and the length direction (second direction DIR2 in FIG. 4A) of the additionally arranged first trench modules TM1_A and TM1_B are formed perpendicular to each other, so that the stresses applied to the semiconductor substrate S by each trench may be offset.

[0068] Furthermore, as described above, the first and second trenches T1, T2 are alternately arranged on at least a portion of the semiconductor substrate S with respect to the first direction DIR1 or the second direction DIR2, and the arrangement structure of the first and second trenches T1, T2 on the semiconductor substrate S may have irregularity. The "irregularity" of the trench structure may mean asymmetry (left-right asymmetry or up-down asymmetry, and rotational asymmetry) of the trench structure at the level of the "composite trench modules" CTM1, CTM2. With reference to FIG. 4A, the composite trench module CTM1 has asymmetry with respect to the second direction (for example, even if the composite trench module CTM1 is flipped in the second direction with the first direction as the rotation axis, the composite trench module CTM1 "before flipping" and the composite trench module CTM1 "after flipping" do not match each other). 4A, the composite trench module CTM1 has rotational asymmetry (e.g., even if the composite trench module CTM1 is rotated, the composite trench module CTM1 "before rotation" and the composite trench module CTM1 "after rotation" do not match each other). Such irregularity and asymmetry of the composite trench module CTM1 may alleviate stress applied to the semiconductor substrate S, and the irregularity and asymmetry of the composite trench module CTM1 also causes the entire trench structure formed on the semiconductor substrate S to have irregularity and asymmetry.

[0069] In order for the overall trench array to be rectangular and patterned, it may be composed of two composite trench modules CTM1, CTM2 and two additional first trench modules TM1_A, TM1_B as shown in FIG. 4A, and in addition to the trench array of FIG. 4A, an additional number of trenches (T_ADD) may be provided as shown in FIG. 4B so that the overall trench array may be patterned into a square shape.

[0070] 4. Tapered section of mesh structure

[0071] In the above, the present embodiment has been described focusing on a structure in which the first and second capacitor structures CAP1 and CAP2 are defined based on one mesh structure, and in the following, in order to specifically explain the "tapered portion" adopted in the present embodiment, the present embodiment will be described focusing on a structure in which two mesh structures (represented as the first and second mesh structures M1 and M2) are defined based on one trench. It goes without saying that the configuration described below can be applied to both of the configurations of the present embodiment described above.

[0072] In the case of a trench capacitor, the difference between the thermal expansion coefficient of the semiconductor substrate S and the thermal expansion coefficients of the dielectric layer and electrode layer disposed in the trench causes stress due to tensile and compressive stress to be applied to the semiconductor substrate S, resulting in a crack problem that breaks the semiconductor substrate S. For this reason, in this embodiment, a void V corresponding to a free space is formed inside the trench to form a space that dissipates tensile and compressive stress generated by the difference in thermal expansion coefficient between the semiconductor substrate S and the dielectric layer and electrode layer inside the trench (i.e., the void V functions as a component for stress relief).

[0073] Specifically, as shown in Fig. 5A, the first and second mesh structures M1 and M2 of this embodiment may at least partially include a tapered portion TP that narrows toward the bottom of the first and second mesh structures M1 and M2, and as shown in Fig. 5B, the void V formed inside the trench may be configured to have a width profile corresponding to the tapered portion TP. That is, the first and second mesh structures M1 and M2 are formed with a first width W1 at their upper ends and a second width W2 smaller than the first width W1 at their lower ends based on the tapered portion TP. Accordingly, the trench disposed between the first and second mesh structures M1 and M2 is formed with a smaller width at its upper end than its lower end based on the tapered portion TP, as shown in Fig. 5B.

[0074] 5B, when the first dielectric layer D1, the first electrode layer E1, the second dielectric layer D2, the second electrode layer E2, the third dielectric layer D3, and the third electrode layer E3 are sequentially deposited in the trench, the upper opening of the trench is closed by the contact of the third electrode layer E3 due to the large width (i.e., the first width W1) of the upper ends of the first and second mesh structures M1 and M2. Accordingly, the void V has a constant width at the lower end of the tapered portion TP, and the width of the void V at the tapered portion TP decreases according to the inclination of the tapered portion TP, and the void V is closed at the contact point of the third electrode layer E3. Accordingly, the void V is composed of a free space that is closed only by the third electrode layer E3 (i.e., the outermost electrode layer) among the multiple electrode layers E1-E3 arranged in the trench.

[0075] 5B, the void V is formed in a structure that is closed by the contact of the outermost electrode layer E3 on the upper side of the tapered portion TP, and therefore can be formed independently of an inter-layer dielectric (ILD) (i.e., an insulating film at a contact level below the metal wiring MI) applied to the semiconductor device. That is, a space (i.e., void V) for relieving stress applied to the semiconductor substrate S is formed, and the problem of cracking the semiconductor substrate S can be solved. In addition, the void V can be naturally formed by the tapered portion TP only through the deposition process of the dielectric layer and the electrode layer that is inevitably involved in the manufacturing process of the semiconductor device, without an additional process of depositing the inter-layer dielectric ILD inside the trench to form the void V, and therefore simplification and convenience of the manufacturing process can be ensured.

[0076] In this manner, by following the present invention, in a semiconductor device (e.g., an integrated circuit (IC)) having multiple trench capacitors, the utility of the trench capacitors can be expanded, and problems such as sticking, warpage, and substrate cracking caused by stress applied to a semiconductor substrate during the trench capacitor process can be eliminated.

[0077] Although the present invention has been described with reference to the embodiments shown in the drawings, these are merely illustrative, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of the present invention should be determined by the following claims. [Explanation of symbols]

[0078] CAP1, CAP2: first and second capacitor structures SCAP1-SCAP6: 1st to 6th sub-capacitor structures S: Semiconductor substrate T1, T2: First and second trenches D1-D6: 1st to 6th dielectric layers E1-E6: 1st to 6th electrode layer CBA: Connection Blocking Area CS, C1-C6: Contact MI: Metal wiring TM1, TM1_A, TM1_B: First trench module TM2: Second trench module CTM, CTM1, CTM2: Composite Trench Module T_ADD:Additional multiple trenches M1, M2: 1st and 2nd mesh structures TP: Tapered section V: Void ILD: Interlayer Dielectric

Claims

1. 1. A semiconductor device comprising first and second capacitor structures formed spaced apart from one another on a semiconductor substrate, the first capacitor structure includes a first trench formed in the semiconductor substrate, first to third electrode layers disposed in the first trench, and first to third dielectric layers disposed in an interlaced structure with the semiconductor substrate and the first to third electrode layers; the second capacitor structure includes a second trench formed in the semiconductor substrate, fourth to sixth electrode layers disposed in the second trench, and fourth to sixth dielectric layers disposed in an interlaced structure with the semiconductor substrate and the fourth to sixth electrode layers; a connection interruption region is formed between the first and second capacitor structures, where a connection between each element constituting the first capacitor structure and each element constituting the second capacitor structure is interrupted; A semiconductor device, comprising: a first trench having a first length and a second trench having a second length greater than the first length, the first trench being spaced apart from the first length in a first direction on the semiconductor substrate.

2. the semiconductor substrate, the first dielectric layer and the first electrode layer form a first sub-capacitor structure of the first capacitor structure, the first electrode layer, the second dielectric layer and the second electrode layer form a second sub-capacitor structure of the first capacitor structure, and the second electrode layer, the third dielectric layer and the third electrode layer form a third sub-capacitor structure of the first capacitor structure; the semiconductor substrate, the fourth dielectric layer and the fourth electrode layer constitute a fourth sub-capacitor structure of the second capacitor structure, the fourth electrode layer, the fifth dielectric layer and the fifth electrode layer constitute a fifth sub-capacitor structure of the second capacitor structure, and the fifth electrode layer, the sixth dielectric layer and the sixth electrode layer constitute a sixth sub-capacitor structure of the second capacitor structure; 2. The semiconductor device of claim 1, further comprising a connecting structure connected to the semiconductor substrate and the first to sixth electrode layers to provide a parallel connection of a plurality of sub-capacitor structures selected from the first to sixth sub-capacitor structures or to allow each sub-capacitor structure to function as a single capacitor.

3. 3. The semiconductor device of claim 2, wherein the connection structure includes a contact-metal structure for providing a parallel connection of the first and fourth sub-capacitor structures, a parallel connection of the second and fifth sub-capacitor structures, and a parallel connection of the third and sixth sub-capacitor structures.

4. 3. The semiconductor device of claim 2, wherein the connection structure includes a contact-metal structure for providing parallel connection of N sub-capacitor structures selected from the first to sixth sub-capacitor structures and allowing the remaining M sub-capacitor structures to function as a single capacitor, wherein N and M are natural numbers, N≧2, and N+M=6.

5. 3. The semiconductor device of claim 2, wherein each of the first to sixth dielectric layers has a thickness profile corresponding to a predefined voltage profile based on voltages applied to the first to sixth sub-capacitor structures, such that a plurality of voltages having different voltage values ​​can be applied to the first and second capacitor structures.

6. 2. The semiconductor device of claim 1, wherein the semiconductor substrate itself is highly doped to form a common ground electrode for the first and second capacitor structures.

7. 2. The semiconductor device according to claim 1, wherein the first and second trenches are alternately arranged in at least a portion of the semiconductor substrate with respect to the first direction or a second direction perpendicular to the first direction, and the arrangement structure of the first and second trenches on the semiconductor substrate has irregularity.

8. 2. The semiconductor device of claim 1, wherein the semiconductor device includes a first trench module, the first trench module including the second trench and the first trenches disposed on both sides of the second trench with respect to a second direction perpendicular to the first direction.

9. 9. The semiconductor device of claim 8, wherein the semiconductor device includes a second trench module, the second trench module including the first trench and the second trenches disposed on both sides of the first trench relative to the second direction.

10. 10. The semiconductor device of claim 9, wherein the first trench module and the second trench module are adjacently arranged based on the second direction, and when the adjacently arranged first trench module and the second trench module are defined as a composite trench module, the first trench module is additionally arranged on one side of the composite trench module based on the first direction or the second direction, and the additionally arranged first trench module has the second direction as a length direction.

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