Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of obtaining excellent heat dissipation efficiency without forming a thick diamond layer, and to provide a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device includes a substrate that has a first surface and a second surface opposite to the first surface, and in which an opening is formed from the first surface to the second surface, a semiconductor device layer having a third surface facing the second surface, and a heat transfer member provided in the opening and transferring heat generated in the semiconductor device layer to the first surface, and the heat transfer member includes a diamond layer covering the bottom surface and the inner wall surface of the opening, and a metal layer provided on the diamond layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Nitride semiconductors such as GaN and AlN have characteristics such as high saturation electron velocity and wide band gap. Therefore, various studies have been conducted on the application of nitride semiconductors to semiconductor devices with high breakdown voltage and high output by utilizing these characteristics. As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). Semiconductor devices using nitride semiconductors are expected to be applied to, for example, millimeter wave radar systems, wireless communication base station systems, server systems, and the like.

[0003] Generally, the higher the output of a semiconductor device, the more heat it generates. Therefore, a heat dissipation structure including a diamond layer has been proposed to improve heat dissipation efficiency. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-027912 A [Patent Document 2] JP 2008-135532 A [Patent Document 3] Special Publication No. 2016-528744 [Patent Document 4] JP 2018-041785 A [Non-patent literature]

[0005] [Non-Patent Document 1] B. Poust et al., "Selective Growth of Diamond in Thermal Vias for GaN HEMTs", 2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) [Non-Patent Document 2] JD Blevins et al., "Prospects for Gallium Nitride-on-Diamond Transistors", 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Summary of the Invention [Problem to be solved by the invention]

[0006] Although it is possible to improve the heat dissipation efficiency by using a diamond layer, it takes a lot of time to form a diamond layer thick enough to obtain sufficient heat dissipation efficiency. This significantly increases the time required to manufacture a semiconductor device. For example, when forming a diamond layer by chemical vapor deposition (CVD) method, the film formation speed is about 0.5 μm per hour when the substrate temperature is 700° C. Therefore, it takes about 40 hours to form a diamond layer with a thickness of 20 μm.

[0007] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can obtain excellent heat dissipation efficiency without forming a thick diamond layer. [Means for solving the problem]

[0008] According to one embodiment of the present disclosure, there is provided a substrate having a first surface and a second surface opposite to the first surface, with an opening formed from the first surface toward the second surface, and a third surface facing the second surface. and a fourth surface opposite to the third surface.a heat transfer member provided in the opening and configured to transfer heat generated in the semiconductor device layer to the first surface side; a source electrode provided on the fourth surface; The heat transfer member has a diamond layer covering a bottom surface and an inner wall surface of the opening, and a metal layer provided on the diamond layer. a conductive via that penetrates the semiconductor device layer and the diamond layer and electrically connects the source electrode and the metal layer, the metal layer and the conductive via having a common Cu plating layer. A semiconductor device is provided. Effect of the Invention

[0009] According to the present disclosure, excellent heat dissipation efficiency can be obtained without forming a thick diamond layer. [Brief description of the drawings]

[0010] [Figure 1] 1 is a top view showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment. [Diagram 3] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing an example of a usage mode of the semiconductor device according to the first embodiment. [Diagram 5] 1A to 1C are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 4A to 4C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment; [Figure 9] 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 6 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 7 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12]8 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 9 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. [Figure 14] FIG. 11 is a top view showing a semiconductor device according to a second embodiment. [Figure 15] FIG. 11 is a bottom view showing the semiconductor device according to the second embodiment. [Figure 16] FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 17] 10 is a cross-sectional view showing an example of a usage mode of the semiconductor device according to the second embodiment. FIG. [Figure 18] 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 19] 11A to 11C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 20] 11A to 11C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 21] 11A to 11C are cross-sectional views (part 4) illustrating the method for manufacturing a semiconductor device according to the second embodiment. [Figure 22] 5 is a cross-sectional view (part 5) illustrating the method for manufacturing a semiconductor device according to the second embodiment. [Figure 23] FIG. 13 is a diagram showing the results of a simulation regarding heat dissipation efficiency. [Figure 24] FIG. 13 is a top view showing a semiconductor device according to a third embodiment. [Diagram 25] FIG. 13 is a bottom view showing the semiconductor device according to the third embodiment. [Figure 26] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 27] FIG. 11 is a cross-sectional view showing an example of a usage mode of the semiconductor device according to the third embodiment. [Figure 28] 11A to 11C are cross-sectional views (part 1) illustrating the method for manufacturing a semiconductor device according to a third embodiment. [Figure 29] 13A to 13C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Diagram 30] 13A to 13C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Diagram 31] 13A to 13C are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Diagram 32] FIG. 13 is a top view showing a semiconductor device according to a fourth embodiment. [Diagram 33] FIG. 13 is a bottom view showing a semiconductor device according to a fourth embodiment. [Diagram 34] FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Diagram 35] FIG. 11 is a cross-sectional view showing an example of a usage mode of the semiconductor device according to the fourth embodiment. [Diagram 36] 11A to 11C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 37] 13A to 13C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. [Figure 38] 13A to 13C are cross-sectional views (part 3) illustrating the method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 39] 13A to 13C are cross-sectional views (part 4) illustrating the method for manufacturing a semiconductor device according to the fourth embodiment. [Diagram 40] FIG. 13 is a diagram showing a discrete package according to a fifth embodiment. [Diagram 41] FIG. 13 is a wiring diagram showing a PFC circuit according to a sixth embodiment. [Diagram 42] FIG. 13 is a wiring diagram showing a power supply device according to a seventh embodiment. [Diagram 43] FIG. 13 is a wiring diagram showing an amplifier according to an eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are denoted by the same reference numerals, and redundant description may be omitted.

[0012] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT). FIG. 1 is a top view showing the semiconductor device according to the first embodiment. FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIGS. 1 and 2.

[0013] The semiconductor device 100 according to the first embodiment includes a substrate 10, a semiconductor device layer 20, a plurality of gate electrodes 31, a plurality of source electrodes 32, and a plurality of drain electrodes 33, as shown in FIGS.

[0014] The substrate 10 has a lower surface 10A and an upper surface 10B. The substrate 10 is, for example, an AlN substrate, a SiC substrate, a GaN substrate, or a Si substrate. The thickness of the substrate 10 is, for example, 20 μm to 100 μm. The lower surface 10A is an example of a first surface, and the upper surface 10B is an example of a second surface.

[0015] The semiconductor device layer 20 has a lower surface 20A and an upper surface 20B. The semiconductor device layer 20 is, for example, an epitaxial layer. The lower surface 20A of the semiconductor device layer 20 faces the upper surface 10B of the substrate 10. The lower surface 20A may be in direct contact with the upper surface 10B. The semiconductor device layer 20 includes a plurality of compound semiconductor layers constituting a HEMT. The semiconductor device layer 20 includes, for example, a channel layer (electron transport layer) such as GaN and a barrier layer (electron supply layer) such as AlGaN. The semiconductor device layer 20 may further include a buffer layer, a spacer layer, a cap layer, and the like. The lower surface 20A is an example of a third surface, and the upper surface 20B is an example of a fourth surface.

[0016] The gate electrode 31, the source electrode 32, and the drain electrode 33 are provided on the upper surface 20B of the semiconductor device layer 20. The upper surface 20B is further provided with a gate wiring 41, a gate pad 51, a source wiring 42, a source pad 52, a drain wiring 43, and a drain pad 53. The gate wiring 41 electrically connects the multiple gate electrodes 31 and the gate pad 51. The source wiring 42 electrically connects the multiple source electrodes 32 and the source pad 52. The drain wiring 43 electrically connects the multiple drain electrodes 33 and the drain pad 53. In a plan view, the multiple gate electrodes 31 and the gate wiring 41 may be arranged in a comb-teeth shape, the multiple source electrodes 32 and the source wiring 42 may be arranged in a comb-teeth shape, and the multiple drain electrodes 33 and the drain wiring 43 may be arranged in a comb-teeth shape.

[0017] An opening 11 is formed in the substrate 10 from the lower surface 10A toward the upper surface 10B. The opening 11 may reach the upper surface 10B. In other words, the opening 11 may penetrate the substrate 10. The opening 11 is formed, for example, in a rectangular shape in a plan view. In the semiconductor device layer 20, heat is likely to be generated particularly in a portion located between the adjacent gate electrode 31 and drain electrode 33 in a plan view. The opening 11 is preferably formed so as to surround the portion located between the adjacent gate electrode 31 and drain electrode 33 in a plan view.

[0018] The semiconductor device 100 has a thermal via 60 provided in the opening 11 to transfer heat generated in the semiconductor device layer 20 to the lower surface 10A of the substrate 10. The thermal via 60 has a diamond layer 61 and a metal layer 62. The diamond layer 61 covers the bottom surface and the inner wall surface of the opening 11. The diamond layer 61 may be in direct contact with the lower surface 20A of the semiconductor device layer 20. The diamond layer 61 has a thickness of, for example, 5 μm to 10 μm. The metal layer 62 contains, for example, Cu. The metal layer 62 may contain Ag or the like. The inner part of the diamond layer 61 in the opening 11 may be filled with the metal layer 62. The thermal via 60 is an example of a heat transfer member.

[0019] The semiconductor device 100 is used by being mounted on, for example, a heat sink. FIG. 4 is a cross-sectional view showing an example of a usage mode of the semiconductor device 100 according to the first embodiment. As shown in FIG. 4, the semiconductor device 100 is mounted on a heat sink 71 by using solder 72. The material of the heat sink 71 is, for example, a CuMo alloy or a CuW alloy. The material of the solder 72 is, for example, an AuSn alloy. The solder 72 is in direct contact with the metal layer 62. The solder 72 may also be in direct contact with the diamond layer 61. The heat sink 71 and the thermal via 60 are thermally connected by the solder 72. The solder 72 is an example of a connecting member.

[0020] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 5 to 13 are cross-sectional views showing the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0021] First, as shown in FIG. 5, a substrate 10 is prepared, and a semiconductor device layer 20 is formed on an upper surface 10B of the substrate 10. The semiconductor device layer 20 can be formed by a crystal growth method such as metal organic chemical vapor deposition (MOCVD). That is, the semiconductor device layer 20 can be formed by epitaxial growth. Next, a gate electrode 31, a source electrode 32, and a drain electrode 33 are formed on an upper surface 20B of the semiconductor device layer 20. Although not shown in FIG. 5, a gate wiring 41, a gate pad 51, a source wiring 42, a source pad 52, a drain wiring 43, and a drain pad 53 are also formed.

[0022] 6, an adhesive 91 is provided on the upper surface 20B of the semiconductor device layer 20, and the semiconductor device layer 20 is attached to a support substrate 92. The adhesive 91 can be provided by, for example, coating. Then, the substrate 10 is ground from the lower surface 10A. The thickness of the substrate 10 after grinding is, for example, 20 μm to 100 μm.

[0023] 7, a metal mask 93 is formed on the lower surface 10A. The metal mask 93 has openings 94 that expose areas where the openings 11 are to be formed. The metal mask 93 has, for example, a Ni layer.

[0024] 8, a portion of the substrate 10 exposed from the opening 94 is dry etched to form an opening 11 in the substrate 10. The opening 11 is formed so as to expose, for example, the lower surface 20A of the semiconductor device layer 20. The opening 11 may be formed so as to extend into the semiconductor device layer 20. Alternatively, the opening 11 may be formed so as to leave a portion of the substrate 10 in the thickness direction.

[0025] 9, the adhesive 91 is removed, and the substrate 10 and the semiconductor device layer 20 are peeled off from the support substrate 92. Next, nanodiamond grains 95 are attached to the inner wall surface of the opening 11, the lower surface 20A of the semiconductor device layer 20, and the lower surface of the metal mask 93.

[0026] 10, the metal mask 93 is removed. The metal mask 93 can be removed using, for example, dilute nitric acid. When the metal mask 93 is removed, the nanodiamond grains 95 formed on the lower surface of the metal mask 93 are also removed.

[0027] 11, the nanodiamond grains 95 are used as growth nuclei to form a diamond layer 61 on the inner wall surface of the opening 11 and on the lower surface 20A of the semiconductor device layer 20. The nanodiamond grains 95 are incorporated into the diamond layer 61. The diamond layer 61 can be formed by, for example, a CVD method. The thickness of the diamond layer 61 is, for example, 5 μm to 10 μm. The growth rate of the diamond layer 61 is about 0.5 μm per hour when the temperature of the substrate 10 is 700° C.

[0028] 12, an adhesive 96 is provided on the upper surface 20B of the semiconductor device layer 20, and the semiconductor device layer 20 is attached to a support substrate 97. The adhesive 96 can be provided by, for example, coating. Thereafter, a metal layer 62 is formed on the lower surface of the diamond layer 61 and on the lower surface 10A of the substrate 10. In forming the metal layer 62, for example, a seed layer (not shown) is formed by sputtering, and a Cu plating layer is formed on the seed layer by electrolytic plating. The metal layer 62 is formed, for example, so as to fill the inner portion of the diamond layer 61 in the opening 11.

[0029] 13, the metal layer 62 is polished by a chemical mechanical polishing (CMP) method. Polishing of the metal layer 62 may be performed until the lower surface 10A of the substrate 10 is exposed, or may be stopped before the lower surface 10A is exposed so that a portion of the metal layer 62 remains in the thickness direction. Next, the adhesive 96 is removed, and the substrate 10 and the semiconductor device layer 20 are peeled off from the support substrate 97 (see FIG. 3).

[0030] In this manner, the semiconductor device 100 according to the first embodiment can be manufactured.

[0031] In the semiconductor device 100 according to the first embodiment, the semiconductor device layer 20 generates heat in accordance with the operation of the HEMT including the channel layer (electron transit layer) and the barrier layer (electron supply layer). As described above, heat is likely to be generated in the semiconductor device layer 20, particularly in a portion located between the adjacent gate electrode 31 and drain electrode 33 in plan view.

[0032] In the semiconductor device 100, the thermal via 60 includes the diamond layer 61 and the metal layer 62, and the heat generated in the semiconductor device layer 20 is transferred to the heat sink 71 on the lower surface 10A side through not only the diamond layer 61 but also the metal layer 62. The heat transferred to the heat sink 71 is then released from the heat sink 71 to the outside. Therefore, according to this embodiment, even if the diamond layer 61 is not thick, excellent heat dissipation efficiency can be obtained. For example, as shown in the results of a simulation described later (see FIG. 23), compared with the reference example in which the metal layer 62 is not formed, a higher heat dissipation efficiency can be obtained using the diamond layer 61 with a thickness of 5 μm than when the diamond layer in the reference example is 20 μm thick. This means that the deposition time of the diamond layer can be reduced to 1 / 4 while obtaining a better heat dissipation efficiency than the reference example. If the deposition rate of the diamond layer is about 0.5 μm per hour, a reduction of as much as 30 hours can be achieved. Therefore, even if the increase in time required for forming the metal layer 62 is taken into account, the time required for the entire process can be significantly reduced.

[0033] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the thermal vias 60. Fig. 14 is a top view showing the semiconductor device according to the second embodiment. Fig. 15 is a bottom view showing the semiconductor device according to the second embodiment. Fig. 16 is a cross-sectional view showing the semiconductor device according to the second embodiment. Fig. 16 corresponds to a cross-sectional view taken along line XVI-XVI in Figs. 14 and 15.

[0034] 14 to 16, in the semiconductor device 200 according to the second embodiment, a diamond layer 61 included in a thermal via 60 covers the bottom surface and inner wall surface of the opening 11 and also covers the lower surface 10A of the substrate 10. The lower surface of the metal layer 62 is flush with the lower surface of the portion of the diamond layer 61 covering the lower surface 10A of the substrate 10.

[0035] The other configuration is similar to that of the first embodiment.

[0036] The semiconductor device 200 is also mounted on, for example, a heat sink when used. Fig. 17 is a cross-sectional view showing an example of a usage mode of the semiconductor device 200 according to the second embodiment. As shown in Fig. 17, the semiconductor device 200 is mounted on a heat sink 71 using solder 72. The solder 72 is in direct contact with the diamond layer 61 and the metal layer 62. The heat sink 71 and the thermal via 60 are thermally connected by the solder 72.

[0037] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figures 18 to 22 are cross-sectional views showing the method for manufacturing the semiconductor device 200 according to the second embodiment.

[0038] First, similarly to the first embodiment, the processes up to the formation of the openings 11 are performed (see FIG. 8). Next, as shown in FIG. 18, the metal mask 93 is removed. The metal mask 93 can be removed using, for example, diluted nitric acid.

[0039] Thereafter, as shown in FIG. 19, nanodiamond grains 95 are attached onto the inner wall surface of the opening 11, onto the lower surface 20A of the semiconductor device layer 20, and onto the lower surface 10A of the substrate 10.

[0040] 20, the nanodiamond grains 95 are used as growth nuclei to form a diamond layer 61 on the inner wall surface of the opening 11, on the lower surface 20A of the semiconductor device layer 20, and on the lower surface 10A of the substrate 10. The nanodiamond grains 95 are incorporated into the diamond layer 61.

[0041] 21, an adhesive 96 is applied to the upper surface 20B of the semiconductor device layer 20, and the semiconductor device layer 20 is attached to a support substrate 97. Thereafter, a metal layer 62 is formed on the lower surface of the diamond layer 61.

[0042] 22, the metal layer 62 is polished by the CMP method. The polishing of the metal layer 62 may be performed until the lower surface of the diamond layer 61 is exposed, or may be stopped before the lower surface of the diamond layer 61 is exposed so that a part of the metal layer 62 remains in the thickness direction. Next, the adhesive 96 is removed, and the substrate 10 and the semiconductor device layer 20 are peeled off from the support substrate 97 (see FIG. 16).

[0043] In this manner, the semiconductor device 200 according to the second embodiment can be manufactured.

[0044] According to the second embodiment, since the diamond layer 61 covers the lower surface 10A of the substrate 10, a better heat dissipation efficiency can be obtained. For example, as shown in the results of a simulation described later (see FIG. 23), compared with the reference example in which the metal layer 62 is not formed, a higher heat dissipation efficiency can be obtained by using the diamond layer 61 having a thickness of 10 μm than when the diamond layer in the reference example has a thickness of 50 μm. This means that a better heat dissipation efficiency than that of the reference example can be obtained while reducing the deposition time of the diamond layer to 1 / 5. If the deposition rate of the diamond layer is about 0.5 μm per hour, a reduction of as much as 80 hours can be achieved. Therefore, even if the increase in time required for forming the metal layer 62 is taken into account, the time required for the entire process can be significantly reduced.

[0045] Here, a simulation of the heat dissipation efficiency of the first and second embodiments performed by the inventors of the present application will be described. In this simulation, the difference between the channel temperature during operation of the HEMT in the first and second embodiments and the channel temperature during operation of the HEMT in the first reference example in which the opening 11 is not formed in the substrate 10 and the thermal via 60 is not provided was calculated. In addition, the difference between the channel temperature during operation of the HEMT in the second reference example in which the diamond layer 61 is provided but the metal layer 62 is not provided and the channel temperature during operation of the HEMT in the first reference example was also calculated.

[0046] In all of the first reference example, the second reference example, the first embodiment, and the second embodiment, the substrate 10 was an AlN substrate with a thickness of 50 μm. In the second reference example, the thickness of the diamond layer 61 was 10 μm (condition A), 15 μm (condition B), 20 μm (condition C), 30 μm (condition D), and 50 μm (condition E). Condition E is a condition in which the opening is filled with the diamond layer 61. In the first embodiment, the thickness of the diamond layer 61 was 5 μm (condition F) and 10 μm (condition G). In the second embodiment, the thickness of the diamond layer 61 was 5 μm (condition H) and 10 μm (condition I). The other conditions are common between the first reference example, the second reference example, the first embodiment, and the second embodiment.

[0047] The results of the simulation are shown in Fig. 23. The vertical axis of the graph in Fig. 23 is the difference in channel temperature in the second reference example, the first embodiment, and the second embodiment with the channel temperature in the first reference example as the reference. A positive difference indicates that the channel temperature is higher than in the first reference example, and a negative difference indicates that the channel temperature is lower than in the first reference example.

[0048] As shown in FIG. 23, under condition F of the first embodiment, even if the diamond layer 61 is 5 μm thick, the channel temperature is lower than under condition C of the second reference example in which the diamond layer 61 is 20 μm thick. Under condition G of the first embodiment, the channel temperature is lower still. Moreover, under condition H of the second embodiment, even if the diamond layer 61 is 5 μm thick, the channel temperature is lower than under condition G of the first embodiment in which the diamond layer 61 is 10 μm thick. Under condition I of the second embodiment, the channel temperature is lower still, and is lower than under condition E of the second reference example in which the diamond layer 61 is 50 μm thick.

[0049] Third embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in that the source electrode and the metal layer are electrically connected. FIG. 24 is a top view showing the semiconductor device according to the third embodiment. FIG. 25 is a bottom view showing the semiconductor device according to the third embodiment. FIG. 26 is a cross-sectional view showing the semiconductor device according to the third embodiment. FIG. 26 corresponds to a cross-sectional view taken along the line XXVI-XXVI in FIGS. 24 and 25.

[0050] In the semiconductor device 300 according to the third embodiment, as shown in FIGS. 24 to 26, a through hole 81 is formed in the semiconductor device layer 20 and the diamond layer 61. The through hole 81 is formed between the source electrode 32 and the metal layer 62. The semiconductor device 300 has a conductive via 82 provided in the through hole 81 and electrically connecting the source electrode 32 and the metal layer 62. The conductive via 82 penetrates the semiconductor device layer 20 and the diamond layer 61. The conductive via 82 contains, for example, Cu. The conductive via 82 may contain Ag. The semiconductor device 300 does not need to include the source wiring 42 and the source pad 52.

[0051] The other configuration is similar to that of the first embodiment.

[0052] The semiconductor device 300 is also used, for example, mounted on a heat sink. Fig. 27 is a cross-sectional view showing an example of a usage mode of the semiconductor device 300 according to the third embodiment. As shown in Fig. 27, the semiconductor device 300 is mounted on a heat sink 71 using solder 72. The solder 72 is in direct contact with the metal layer 62. The solder 72 may also be in direct contact with the diamond layer 61. The heat sink 71 and the thermal via 60 are thermally connected by the solder 72.

[0053] Next, a method for manufacturing the semiconductor device 300 according to the third embodiment will be described. Figures 28 to 31 are cross-sectional views showing the method for manufacturing the semiconductor device 300 according to the third embodiment.

[0054] First, similarly to the first embodiment, the process up to the formation of the diamond layer 61 is performed (see FIG. 11). Next, as shown in FIG. 28, an adhesive 96 is provided on the upper surface 20B of the semiconductor device layer 20, and the semiconductor device layer 20 is attached to a support substrate 97. After that, a metal mask 98 is formed on the lower surface 10A of the substrate 10 and on the lower surface of the diamond layer 61. The metal mask 98 has an opening 99 exposing an area where the through hole 81 is to be formed. The metal mask 98 has, for example, a Ni layer. In forming the metal mask 98, for example, a seed layer (not shown) is formed by a sputtering method, the area where the through hole 81 of the seed layer is to be formed is covered with a photoresist or the like, and a Ni plating layer is formed on the seed layer by an electrolytic plating method. After forming the Ni plating layer, the photoresist is removed, and the part of the seed layer exposed from the Ni plating layer is removed.

[0055] After the metal mask 98 is formed, as shown in FIG. 29, the portion of the diamond layer 61 exposed from the opening 99 is dry etched, and the portion of the semiconductor device layer 20 exposed from the opening 99 is dry etched to form through holes 81 in the diamond layer 61 and the semiconductor device layer 20. For example, the diamond layer 61 can be dry etched using oxygen, and the semiconductor device layer 20 can be dry etched using chlorine. Next, the metal mask 98 is removed. The metal mask 98 can be removed using, for example, diluted nitric acid.

[0056] 30, a metal layer 62 is formed on the lower surface of the diamond layer 61 and on the lower surface 10A of the substrate 10, and a conductive via 82 is formed inside the through hole 81. In forming the metal layer 62 and the conductive via 82, for example, a seed layer (not shown) is formed by a sputtering method, and a Cu plating layer is formed on the seed layer by an electrolytic plating method.

[0057] Subsequently, the metal layer 62 is polished by the CMP method as shown in Fig. 31. Next, the adhesive 96 is removed, and the substrate 10 and the semiconductor device layer 20 are peeled off from the support substrate 97 (see Fig. 26).

[0058] In this manner, the semiconductor device 300 according to the third embodiment can be manufactured.

[0059] The third embodiment also provides the same effects as the first embodiment. In addition, the source electrode 32 is electrically connected to the metal layer 62 through the conductive via 82. Therefore, by grounding the metal layer 62, the source inductance can be reduced.

[0060] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the third embodiment mainly in the configuration of the thermal vias 60. Fig. 32 is a top view showing the semiconductor device according to the fourth embodiment. Fig. 33 is a bottom view showing the semiconductor device according to the fourth embodiment. Fig. 34 is a cross-sectional view showing the semiconductor device according to the fourth embodiment. Fig. 34 corresponds to a cross-sectional view taken along line XXXIV-XXXIV in Figs. 32 and 33.

[0061] 32 to 34, in the semiconductor device 200 according to the fourth embodiment, similarly to the second embodiment, the diamond layer 61 included in the thermal via 60 covers the bottom and inner wall surfaces of the opening 11 and also covers the lower surface 10A of the substrate 10. The lower surface of the metal layer 62 is flush with the lower surface of the portion of the diamond layer 61 covering the lower surface 10A of the substrate 10.

[0062] The other configuration is similar to that of the third embodiment.

[0063] The semiconductor device 400 is also used, for example, mounted on a heat sink. Fig. 35 is a cross-sectional view showing an example of a usage mode of the semiconductor device 400 according to the fourth embodiment. As shown in Fig. 35, the semiconductor device 400 is mounted on a heat sink 71 using solder 72. The solder 72 is in direct contact with the diamond layer 61 and the metal layer 62. The heat sink 71 and the thermal via 60 are thermally connected by the solder 72.

[0064] Next, a method for manufacturing the semiconductor device 400 according to the fourth embodiment will be described. Figures 36 to 39 are cross-sectional views showing the method for manufacturing the semiconductor device 400 according to the fourth embodiment.

[0065] First, similarly to the second embodiment, processing up to the formation of the diamond layer 61 is performed (see FIG. 20). Next, as shown in FIG. 36, an adhesive 96 is provided on the upper surface 20B of the semiconductor device layer 20, and the semiconductor device layer 20 is attached to a support substrate 97. Thereafter, a metal mask 98 is formed on the lower surface 10A of the substrate 10 and on the lower surface of the diamond layer 61. The metal mask 98 has openings 99 that expose areas where the through holes 81 are to be formed.

[0066] 37, after the metal mask 98 is formed, the portions of the diamond layer 61 exposed from the openings 99 are dry etched, and the portions of the semiconductor device layer 20 exposed from the openings 99 are dry etched to form through-holes 81 in the diamond layer 61 and the semiconductor device layer 20. Then, the metal mask 98 is removed.

[0067] Thereafter, as shown in FIG. 38, a metal layer 62 is formed on the lower surface of the diamond layer 61, and a conductive via 82 is formed inside the through hole 81.

[0068] 39, the metal layer 62 is polished by CMP. Next, the adhesive 96 is removed, and the substrate 10 and the semiconductor device layer 20 are peeled off from the support substrate 97.

[0069] In this manner, the semiconductor device 400 according to the fourth embodiment can be manufactured.

[0070] The fourth embodiment also provides the same effects as the second embodiment. In addition, the source electrode 32 is electrically connected to the metal layer 62 through the conductive via 82. Therefore, by grounding the metal layer 62, the source inductance can be reduced.

[0071] In the third and fourth embodiments, the source wiring 42 and the source pad 52 may be provided, and a conductive via may be provided to connect the source pad 52 and the metal layer 62. In this case, too, the source inductance can be reduced by grounding the metal layer 62.

[0072] The thickness of the substrate 10 is not particularly limited, but is, for example, 20 μm to 100 μm. If the substrate 10 is excessively thin, the parasitic capacitance between the semiconductor elements formed in the semiconductor device layer 20 and the heat sink 71, etc. may become large. If the substrate 10 is excessively thick, the heat dissipation efficiency may decrease, and it may take a long time to form the openings 11. For example, in the first and third embodiments, the thickness of the substrate 10 may be 30 μm to 100 μm, and in the second and fourth embodiments, the thickness of the substrate 10 may be 20 μm to 70 μm.

[0073] Fifth embodiment Next, a fifth embodiment will be described. The fifth embodiment relates to a discrete package of a HEMT. Fig. 40 is a diagram showing the discrete package according to the fifth embodiment.

[0074] In the fifth embodiment, as shown in FIG. 40, the back surface of a semiconductor device 1210 having a structure similar to any one of the first to fourth embodiments is fixed to a land (die pad) 1233 using a die attaching agent 1234 such as solder. A wire 1235d such as an Al wire is connected to a drain pad 1226d (drain pad 53) to which a drain electrode 33 is connected, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to a source pad 1226s (source pad 52) connected to a source electrode 32, and the other end of the wire 1235s is connected to a source lead 1232s independent from the land 1233. When the semiconductor device 1210 has a structure similar to the third or fourth embodiment, the metal layer 62 may be grounded. A wire 1235g such as an Al wire is connected to a gate pad 1226g (gate pad 51) connected to the gate electrode 31, and the other end of the wire 1235g is connected to a gate lead 1232g independent from the land 1233. The land 1233, the semiconductor device 1210, etc. are packaged by mold resin 1231 such that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

[0075] Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attaching agent 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. After that, sealing is performed using the molding resin 1231 by the transfer molding method. Then, the lead frame is separated.

[0076] Sixth embodiment Next, a sixth embodiment will be described. The sixth embodiment relates to a PFC (Power Factor Correction) circuit equipped with a HEMT. Fig. 41 is a wiring diagram showing a PFC circuit according to the sixth embodiment.

[0077] The PFC circuit 1250 includes a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switch element 1251. The AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. A direct current power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, a semiconductor device having the same structure as any one of the first to fourth embodiments is used for the switch element 1251.

[0078] When manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252 and the choke coil 1253, etc., using, for example, solder or the like.

[0079] Seventh embodiment Next, a seventh embodiment will be described. The seventh embodiment relates to a power supply device equipped with a HEMT, suitable for a server power supply. Fig. 42 is a wiring diagram showing the power supply device according to the seventh embodiment.

[0080] The power supply device is provided with a high-voltage primary circuit 1261 , a low-voltage secondary circuit 1262 , and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262 .

[0081] The primary side circuit 1261 is provided with a PFC circuit 1250 according to the sixth embodiment, and an inverter circuit, for example, a full-bridge inverter circuit 1260, connected between both terminals of a capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 is provided with a plurality of (four in this case) switch elements 1264a, 1264b, 1264c, and 1264d.

[0082] The secondary side circuit 1262 is provided with a plurality of (three in this case) switch elements 1265a, 1265b, and 1265c.

[0083] In this embodiment, a semiconductor device having a structure similar to that of any one of the first to fourth embodiments is used for the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261, and the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260. On the other hand, normal MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262.

[0084] Eighth embodiment Next, an eighth embodiment will be described. The eighth embodiment relates to an amplifier including a HEMT. Fig. 43 is a wiring diagram showing the amplifier according to the eighth embodiment.

[0085] The amplifier includes a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

[0086] The digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the input signal, the nonlinear distortion of which has been compensated for, with an AC signal. The power amplifier 1273 includes a semiconductor device having a structure similar to that of any one of the first to fourth embodiments, and amplifies the input signal mixed with the AC signal. In this embodiment, for example, by switching a switch, the output side signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-output amplifier. The high-frequency amplifier can be used, for example, in a transmitting / receiving device for a mobile phone base station, a radar device, and a microwave generating device.

[0087] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0088] Various aspects of the present disclosure are summarized below as appendices.

[0089] (Appendix 1) a substrate having a first surface and a second surface opposite to the first surface, the substrate having an opening formed from the first surface toward the second surface; a semiconductor device layer having a third surface opposite the second surface; a heat transfer member provided in the opening and configured to transfer heat generated in the semiconductor device layer to the first surface side; having The heat transfer member is a diamond layer covering a bottom surface and an inner wall surface of the opening; a metal layer disposed on the diamond layer; A semiconductor device comprising: (Appendix 2) The opening reaches the second surface, 2. The semiconductor device of claim 1, wherein the diamond layer is in direct contact with the third surface. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the diamond layer further covers the first surface. (Appendix 4) A heat sink; a connection member that thermally connects the heat sink and the heat transfer member; 4. The semiconductor device according to claim 1, further comprising: (Appendix 5) 5. The semiconductor device according to claim 1, wherein an inner portion of the opening in the diamond layer is filled with the metal layer. (Appendix 6) the semiconductor device layer has a fourth surface opposite the third surface; a source electrode provided on the fourth surface; a conductive via passing through the semiconductor device layer and the diamond layer and electrically connecting the source electrode and the metal layer; 6. The semiconductor device according to claim 1, further comprising: (Appendix 7) 7. The semiconductor device according to claim 1, wherein the diamond layer has a thickness of 5 μm to 10 μm. (Appendix 8) 8. The semiconductor device according to claim 1, wherein the substrate has a thickness of 20 μm to 100 μm. (Appendix 9) 9. The semiconductor device according to claim 1, wherein the substrate is an AlN substrate, a SiC substrate, a GaN substrate, or a Si substrate. (Appendix 10) 10. The semiconductor device according to claim 1, wherein the metal layer contains Cu or Ag. (Appendix 11) 11. An amplifier comprising the semiconductor device according to any one of claims 1 to 10. (Appendix 12) A power supply device comprising the semiconductor device according to any one of claims 1 to 10. (Appendix 13) forming a semiconductor device layer on a substrate having a first surface and a second surface opposite the first surface, the semiconductor device layer having a third surface opposite the second surface; forming an opening in the substrate from the first surface to the second surface; forming a heat transfer member in the opening for transferring heat generated in the semiconductor device layer to the first surface side; having The step of forming the heat transfer member includes: forming a diamond layer covering a bottom surface and an inner wall surface of the opening; forming a metal layer over the diamond layer; 1. A method for manufacturing a semiconductor device comprising the steps of: [Explanation of symbols]

[0090] 100, 200, 300, 400: Semiconductor device 10: Substrate 10A: Bottom side 10B:Top surface 11: Opening 20: Semiconductor device layer 20A: Bottom surface 20B:Top surface 31: Gate electrode 32: Source electrode 33: Drain electrode 60: Thermal via 61: Diamond Layer 62: Metal layer 71: Heat sink 72: Solder 81:Through hole 82: Conductive via

Claims

1. a substrate having a first surface and a second surface opposite to the first surface, the substrate having an opening formed from the first surface toward the second surface; a semiconductor device layer having a third surface opposite the second surface and a fourth surface opposite the third surface; a heat transfer member provided in the opening and configured to transfer heat generated in the semiconductor device layer to the first surface side; A source electrode provided on the fourth surface; having The heat transfer member is a diamond layer covering a bottom surface and an inner wall surface of the opening; a metal layer disposed on the diamond layer; having a conductive via extending through the semiconductor device layer and the diamond layer and electrically connecting the source electrode and the metal layer; The semiconductor device according to claim 1, wherein the metal layer and the conductive via have a common Cu plating layer.

2. The opening reaches the second surface, 2. The semiconductor device according to claim 1, wherein the diamond layer is in direct contact with the third surface.

3. 3. The semiconductor device according to claim 1, wherein the diamond layer further covers the first surface.

4. A heat sink; a connection member that thermally connects the heat sink and the heat transfer member; 4. The semiconductor device according to claim 1, further comprising:

5. 5. The semiconductor device according to claim 1, wherein an inner portion of said opening in said diamond layer is filled with said metal layer.

6. 6. The semiconductor device according to claim 1, wherein the diamond layer has a thickness of 5 μm to 10 μm.

7. forming a semiconductor device layer on a substrate having a first surface and a second surface opposite the first surface, the semiconductor device layer having a third surface opposite the second surface and a fourth surface opposite the third surface; forming a source electrode on the fourth surface; forming an opening in the substrate from the first surface to the second surface; forming a heat transfer member in the opening for transferring heat generated in the semiconductor device layer to the first surface side; having The step of forming the heat transfer member includes: forming a diamond layer covering a bottom surface and an inner wall surface of the opening; forming a through hole through the semiconductor device layer and the diamond layer; forming a metal layer on the diamond layer and forming a conductive via within the through hole; having 2. A method for manufacturing a semiconductor device, comprising the steps of: forming a metal layer and forming a conductive via; forming a Cu plating layer on the diamond layer and inside the through hole.

Images