Information processing device, information processing system, and information processing method

Abstract

A processing load relating to inner product computation is further reduced, and also quantization granularity of weight coefficients is ensured. An information processing device according to an embodiment comprises a product-sum computation circuit (200) that executes product-sum computation on the basis of a plurality of input values quantized by exponential expressions, and a plurality of weight coefficients quantized by exponential expressions respectively corresponding to the input values, wherein indices of the respective input values are each expressed by fractions having a divisor determined in advance as the denominator, indices of the respective weight coefficients are each expressed by fractions having the divisor as the denominator, the product-sum computation circuit executes the product-sum computation by using a plurality of added multiplicators based on remainders of divisions in which values obtained by adding numerators relating to the respective indices of the input values and numerators relating to the indices of the respective weight coefficients are dividends, and the added multiplicators are each floating point numbers of which the base of the exponential part is 2.

Description

[Technical field]

[0001] The present disclosure relates to an information processing device, an information processing system, and an information processing method. [Background technology]

[0002] In recent years, neural networks, which are mathematical models that mimic the mechanism of the brain and nervous system, have been attracting attention. Also, various methods have been proposed to reduce the processing load of calculations in neural networks. For example, Non-Patent Document 1 describes a method of reducing the processing load by binarizing weight coefficients. Also, Non-Patent Document 2 describes a method of converting multiplication to addition by converting an input signal into the log domain. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Matthieu Courbariaux and 2 others, "BinaryConnect: Training Deep Neural Networks with binary weights during propagations", [online], November 2, 2015, arXiv, [Retrieved March 22, 2017], Internet〈URL: https: / / arxiv.org / pdf / 1511.00363.pdf〉 [Non-Patent Document 2] Daisuke Miyashita and 2 others, “Convolutional Neural Networks using Logarithmic Data Representation”, [online], March 3, 2016, arXiv, [Retrieved March 22, 2017], Internet〈URL: https: / / arxiv.org / pdf / 1603.01025.pdf〉 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the method described in Non-Patent Document 1, binarization is performed using +1 or -1, so it is expected that the granularity of quantization will become coarser as the number of dimensions of the weighting coefficient increases. Also, while the method described in Non-Patent Document 2 has a certain effect in avoiding multiplication, it is expected that there is still room for further reduction in the processing load.

[0005] Therefore, the present disclosure proposes a new and improved information processing device, information processing system, and information processing method that can further reduce the processing load associated with inner product calculations and ensure the quantization granularity of weighting coefficients. [Means for solving the problem]

[0006] In order to solve the above problem, an information processing device according to one embodiment of the present disclosure includes a multiply-and-accumulate circuit that performs a multiply-and-accumulate operation based on a plurality of input values ​​quantized by a power representation and a plurality of weighting coefficients quantized by a power representation corresponding to the input values, wherein an exponent of each of the input values ​​is expressed by a fraction having a predetermined divisor in its denominator, and an exponent of each of the weighting coefficients is expressed by a fraction having the divisor in its denominator, and the multiply-and-accumulate circuit performs the multiply-and-accumulate operation using a plurality of addition multipliers based on a remainder obtained when a dividend is obtained by adding a numerator related to the exponent of each of the input values ​​to a numerator related to the exponent of each of the weighting coefficients, and each of the addition multipliers is a floating-point number whose exponent part has a base of 2. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a conceptual diagram for explaining an overview of basic operations in a neural network according to a related technique of the present disclosure. [Diagram 2] 1 is a schematic diagram for explaining an inner product calculation between an input vector and a weight vector according to a related technique of the present disclosure. FIG. [Diagram 3] 11 is a diagram for explaining a weight vector that is binary quantized in a two-dimensional space according to a related technique of the present disclosure. FIG. [Figure 4] 11 is a diagram for explaining a weight vector that is four-value quantized in a two-dimensional space according to a related technique of the present disclosure. FIG. [Diagram 5] 11 is a diagram for explaining the variation in granularity of weight vectors in a three-dimensional space according to a related technique of the present disclosure. FIG. [Figure 6] 11 is a diagram for explaining the variation in granularity of weight vectors in an N-dimensional space according to a related technique of the present disclosure. FIG. [Figure 7] FIG. 2 is an example of a functional block diagram of an information processing device according to a base technique. [Figure 8] 1 is an example of a circuit block diagram of a product-sum calculation circuit included in an information processing device according to a base technique; [Figure 9] 13 is an example of offset notation related to address information held in an address table related to the base technology. [Figure 10] FIG. 1 is a diagram showing a processing image of an information processing method according to a base technology. [Figure 11] FIG. 13 is a diagram for explaining a quantization granularity Δθ ​​according to the base technology. [Figure 12] 13 is a graph showing the maximum value of the quantization granularity Δθ ​​according to α according to the base technology. [Figure 13] FIG. 13 is a diagram for explaining the maximum power number according to the base technology. [Figure 14] FIG. 13 is a diagram showing an example of the number of multiplications with respect to the number of inputs N according to the base technique. [Figure 15] FIG. 13 is a diagram showing an example of the number of multiplications with respect to the number of inputs N according to the base technique. [Figure 16] 13 is a diagram showing an example of a product-sum calculation circuit in the case where a weight vector according to an advanced example of the base technology is quantized. [Figure 17] 13 is a diagram showing an example of a product-sum calculation circuit in a case where both a weight vector and an input vector are quantized, according to an advanced example of the base technology. [Figure 18] 13 is a diagram showing an example of a product-sum calculation circuit in a case where both a weight vector and an input vector are quantized, according to an advanced example of the base technology. [Figure 19] FIG. 1 is a diagram showing the network structure of ResNet used in a comparative experiment relating to an advanced example of the base technology. [Figure 20] FIG. 1 is a diagram showing a ResNet network configuration that does not include a Max Pooling layer according to an example of an extension of the base technology. [Figure 21] FIG. 1 is a diagram showing a ResNet network configuration including a Max Pooling layer according to an example of an extension of the base technology. [Figure 22] FIG. 13 is a diagram showing a comparison result of image recognition rates according to an advanced example of the base technology. [Diagram 23] 13 is a diagram showing an example of a product-sum calculation circuit in a case where both a weight vector and an input vector are quantized, according to an advanced example of the base technology. [Figure 24] FIG. 4 is a diagram illustrating a relationship between indexes and table values ​​according to the first embodiment. [Diagram 25] 13 is a diagram showing another relationship between indexes and table values ​​according to the first embodiment. FIG. [Figure 26] FIG. 2 is a diagram in which table values ​​in a power-of-two representation and table values ​​in a linear representation according to the first embodiment are plotted on the same graph. [Figure 27] 1 is a circuit diagram showing a schematic configuration example of a product-sum calculation circuit according to a first specific example of the first embodiment. FIG. [Figure 28] 10 is a circuit diagram showing a schematic configuration example of a product-sum calculation circuit according to a second specific example of the first embodiment. FIG. [Figure 29] FIG. 11 is a diagram illustrating an example of rounding of a quantizer according to the second embodiment. [Diagram 30] FIG. 1 is a block diagram showing a schematic configuration example of a neural network circuit as a comparative example. [Diagram 31] FIG. 13 is a block diagram showing a schematic configuration example of a neural network circuit as another comparative example. [Diagram 32] FIG. 13 is a block diagram showing a schematic configuration example of a neural network circuit as yet another comparative example. [Diagram 33] FIG. 11 is a block diagram showing a schematic configuration example of a neural network circuit according to a second embodiment. [Diagram 34] FIG. 13 is a circuit diagram showing a schematic configuration example of a product-sum calculation circuit according to a third embodiment. [Diagram 35] FIG. 13 is a circuit diagram illustrating a schematic configuration example of a quantization circuit according to a third embodiment. [Diagram 36] This is a schematic diagram for explaining the operation of general DNN and CNN. [Figure 37] FIG. 37 is a diagram showing a coefficient w1 input to the first convolutional layer in FIG. 36. [Figure 38] FIG. 37 is a diagram showing a coefficient w2 input to the second convolutional layer in FIG. 36. [Figure 39] FIG. 37 is a diagram showing a coefficient w3 input to the first convolutional layer in FIG. 36. [Diagram 40] FIG. 37 is a diagram showing the input (variable) x0 of the convolutional neural network in FIG. 36. [Diagram 41] FIG. 37 is a diagram showing the output (variable) x1 from the first layer in FIG. 36. [Diagram 42] FIG. 37 is a diagram showing the output (variable) x2 from the second layer in FIG. 36. [Diagram 43] FIG. 37 is a diagram showing the output (variable) x3 from the third layer in FIG. 36. [Diagram 44] FIG. 13 is a diagram showing an example of a table of powers of two according to the fourth embodiment; [Diagram 45] FIG. 13 is a diagram showing the relationship between the sem format, the sBQ format, numeric format information, and a container (Numeric Data Container) according to the fourth embodiment. [Diagram 46] FIG. 13 is a diagram illustrating an example of a packet structure having a basic structure according to the fourth embodiment. [Figure 47] FIG. 13 is a diagram illustrating an example of a packet structure of a continue structure according to the fourth embodiment. [Figure 48] FIG. 13 is a diagram illustrating an example of a packet structure of an extended structure according to the fourth embodiment. [Figure 49] FIG. 13 is a diagram illustrating an example of the structure of a packet aligned as only the payload according to the fourth embodiment. [Figure 50] FIG. 13 is a diagram illustrating an example of a header of a custom extension structure (Custom Structure) according to the fourth embodiment. [Figure 51] FIG. 13 is a diagram showing an example of a payload of a custom extension structure (Custom Structure) according to the fourth embodiment. [Figure 52] FIG. 13 is a diagram showing an example of packet implementation of a basic structure according to the fourth embodiment. [Figure 53] FIG. 13 is a diagram illustrating an example of packet implementation of a continue structure according to the fourth embodiment. [Figure 54] FIG. 13 is a diagram illustrating an example of packet implementation of an extended structure according to the fourth embodiment. [Figure 55] FIG. 13 is a diagram showing an implementation example of a packet having only a continuing payload area (Payload) according to the fourth embodiment. [Figure 56] FIG. 13 is a diagram illustrating an example of an implementation of a packet of a custom structure according to the fourth embodiment. [Figure 57] FIG. 13 is a diagram showing an implementation example of a packet having only a continuing payload area (Payload) according to the fourth embodiment. [Figure 58] FIG. 13 is a block diagram showing a schematic configuration example of a system for processing a byte stream according to a fourth embodiment. [Figure 59] 11 is a diagram showing a simulation result of frequency characteristics (gain characteristics) when the quantization method according to the present disclosure is applied to a bandpass filter. FIG. [Figure 60] 13A and 13B are diagrams illustrating simulation results of phase characteristics when the quantization method according to the present disclosure is applied to a bandpass filter. [Figure 61] FIG. 1 is a block diagram used for BER evaluation according to the present disclosure. [Figure 62]FIG. 13 is a diagram showing a BER evaluation result when BPSK according to the present disclosure is used as a modulation scheme. [Figure 63] FIG. 63 is an enlarged view of the data in FIG. 62 where SNR is 7 to 9 dB. [Figure 64] FIG. 13 is a diagram showing a BER evaluation result when QPSK according to the present disclosure is used as the modulation scheme. [Figure 65] This is an enlarged view of the data in FIG. 64 where SNR is 10 to 12 dB. [Figure 66] FIG. 11 is a diagram showing a BER evaluation result when 16QAM according to the present disclosure is used as a modulation scheme. [Figure 67] This is an enlarged view of the data in FIG. 66 where SNR is 16 to 18 dB. [Figure 68] FIG. 2 is a diagram illustrating an example of a hardware configuration according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0009] The present disclosure will be described in the following order. 1. Base Technology 1.1 Background 1.2 Example of Functional Configuration of Information Processing Device 10 1.3 Quantization of weight vectors 1.4 Example of a multiply-and-accumulate circuit 1.5 Quantization during training 1.6 Effect of base technology 2. Examples of developments in base technologies 2.1 Overview 2.2 Quantization of weight vectors 2.3 Quantization of both weight vectors and input vectors 2.4 Effects of development examples 3. Summary 4. First embodiment 4.1 Issues with the Base Technology 4.2 Value Table Example 4.3 Examples of multiply-and-accumulate circuits 4.3.1 First concrete example 4.3.2 Second Example 4.4 Actions and Effects 5. Second embodiment 5.1 Issues with the Base Technology 5.2 Examples of quantization circuits 5.3 Actions and Effects 6. Third embodiment 6.1 Issues with the Base Technology 6.2 Examples of multiply-accumulate circuits 6.3 Expansion to quantization methods 6.4 Examples of quantization circuits 6.5 Actions and Effects 6.6 Variations 6.6.1 First variant 6.6.2 Second variant 6.6.3 Third variant 6.6.4 Fourth variant 6.6.5 Fifth Variation 6.6.6 Sixth Variation 7. Fourth embodiment 7.1 Issues with the Base Technology 7.2 Examples of Number Format Information 7.2.1 sem format 7.2.2 sBQ Format 7.3 Management of Actual Data: Relationship between Containers and Numeric Format Information 7.4 Byte Streams 7.4.1 Byte Stream with Basic Structure and Continuation Structure Packets 7.4.2 Byte Stream in Extended Structure Packets 7.4.3 Payload variable length stream with custom extended packet header (Custom Structure) 7.5 Example of a byte stream implementation 7.5.1 Example of a byte stream implementation of Basic Structure and Continuation Structure 7.5.2 Example of an Extended Structure Byte Stream Implementation 7.5.3 Example of a Custom Structure Byte Stream Implementation 7.6 Example of a byte stream processing system 7.7 Actions and Effects 8. Application examples to communication technology 9. Hardware configuration example

[0010] 1. Base Technology First, a technology on which the present disclosure is based (hereinafter, referred to as the base technology) will be described in detail with reference to the drawings.

[0011] 1.1 Background In recent years, learning methods using neural networks, such as deep learning, have been widely studied. While learning methods using neural networks have high accuracy, they impose a large processing load on the calculations, and therefore a calculation method that can effectively reduce the processing load is required.

[0012] For this reason, in recent years, calculation methods aimed at reducing the amount of calculation and the amount of information, such as Binary weight network and XNOR net, have been proposed.

[0013] Here, an overview of basic operations in a general neural network will be described. Fig. 1 is a conceptual diagram for explaining the overview of basic operations in a neural network. Fig. 1 shows two layers constituting a neural network and cells c11 to c11 belonging to the two layers, respectively. N and cell c21 are shown.

[0014] At this time, the input signal (hereinafter also referred to as an input vector) input to the cell c21 is input to the cells c11 to c1 NIn more detail, the input vector input to the cell c21 is determined based on the input vector and weighting coefficients (hereinafter, also referred to as weight vectors) of the cells c11 to c1. N The value is obtained by adding a bias b to the inner product of the input vector and weight vector related to the vector and further processing it with the activation function h.

[0015] That is, cells c11 to c1 N The input vector and weight vector for x = (x1, x2, x3, ... x N ), w=(w1,w2,w3,...w N ), the input vector z input to cell c21 is defined by the following formula (1).

[0016]

number

[0017] In this case, assuming a hyperplane h with the weight vector w as its normal, the inner product of the input vector x and the weight vector w expressed in N dimensions can be expressed by a value obtained by multiplying the projection distance d of the input vector x projected onto the weight vector w based on the hyperplane h by ||w||, as shown in Fig. 2. Here, ||w|| is the norm of the vector w. Fig. 2 is an overview diagram for explaining the inner product calculation of the input vector x and the weight vector w.

[0018] Here, when the input vector x and the weight vector w are two-dimensional, if the weight vector w is quantized with two values ​​of +1 or -1 as in Non-Patent Document 1, the weight vector w can be expressed as shown in Fig. 3. Fig. 3 is a diagram for explaining the weight vector w that has been binary quantized in a two-dimensional space. In this case, the granularity of the weight vector w can be expressed by a rotation angle θ on a plane, and the granularity is 90 degrees as shown in Fig. 3.

[0019] Next, consider the case where the weight vector w is quantized with four values ​​of {0, 1 / 4, 1 / 2, 1}. Figure 4 is a diagram for explaining the weight vector w quantized with four values ​​in a two-dimensional space. In this case, the granularity of the weight vector w, that is, the rotation angle θ, is about 15 degrees, which makes it possible to guarantee finer granularity compared to the case of binary quantization.

[0020] On the other hand, it is expected that the granularity of the weight vector w will vary more as the number of dimensions increases. Fig. 5 is a diagram for explaining the variation in the granularity of the weight vector w in a three-dimensional space. For example, as shown in Fig. 5, when considering the quantization of the weight vector w on a plane defined by (1,1,0) and (0,0,1), the length of the side in the (1,1,0) direction is √2 times the length of the side in the (0,0,1) direction, and therefore it can be seen that the variation in the granularity during quantization will be large.

[0021] Moreover, the above-mentioned variation in granularity, i.e., non-uniformity, becomes more prominent as the number of dimensions increases. FIG. 6 is a diagram for explaining the variation in granularity of the weight vector w in an N-dimensional space. FIG. 6 shows a surface defined by (1,1,...,1,0) and (0,0,...,0,1) in an N-dimensional space. In this case, the length of the side in the (1,1,...,1,0) direction can be expressed as √(N-1) times the length of the side in the (0,0,...,0,1) direction. For example, when N=100, the length of the side in the (1,1,...,1,0) direction is √99 times (≒10 times) the length of the side in the (0,0,...,0,1) direction.

[0022] Since the non-uniformity of the granularity of the weight vector w as described above may cause the performance of the neural network to decrease, a more accurate quantization method has been desired. The technical idea according to the present disclosure has been conceived by focusing on the above points, and makes it possible to effectively reduce the processing load while maintaining a high approximation accuracy of the weight vector in the N-dimensional space. For this reason, one of the features of the information processing device and information processing method according to the base technology of the present disclosure is to perform an inner product operation using a weight vector quantized based on the granularity of the vector direction in the N-dimensional hypersphere plane. The information processing device and information processing method according to the base technology of the present disclosure can achieve both high approximation accuracy and reduction in the processing load by quantizing the weight vector at a granularity that is neither too fine nor too coarse. More specifically, the information processing device and information processing method according to the base technology of the present disclosure may perform an inner product operation using a weight vector expressed by power. The above features of the information processing device and information processing method according to the base technology of the present disclosure will be described in detail below.

[0023] 1.2 Example of Functional Configuration of Information Processing Device 10 Next, a functional configuration example of the information processing device 10 that realizes the information processing method according to the base technology will be described. Fig. 7 is an example of a functional block diagram of the information processing device 10 according to the base technology. Referring to Fig. 7, the information processing device 10 according to the base technology includes an input unit 110, a calculation unit 120, a storage unit 130, and an output unit 140. The above configuration will be described below, focusing on the functions of the configuration.

[0024] (Input unit 110) The input unit 110 has a function of detecting various input operations by an operator. For this purpose, the input unit 110 may include various devices for detecting the input operations by the operator. The input unit 110 may be realized by, for example, various buttons, a keyboard, a touch panel, a mouse, a switch, or the like.

[0025] (Computation unit 120) The calculation unit 120 has a function of performing an inner product calculation based on a plurality of input values ​​and a plurality of weighting coefficients respectively corresponding to the input values ​​to calculate an output value. The calculation unit 120 performs an inner product calculation related to forward propagation of a neural network in particular. At this time, one of the characteristics of the calculation unit 120 is that it calculates an output value based on weighting coefficients quantized based on the granularity of the vector direction on the surface of an N-dimensional hypersphere. More specifically, the calculation unit 120 may calculate an output value based on weighting coefficients expressed by powers. The characteristics of the inner product calculation will be described in detail separately.

[0026] (Storage unit 130) The storage unit 130 has a function of storing programs, data, and the like used in each component of the information processing device 10. The storage unit 130 stores, for example, various parameters used in a neural network.

[0027] (Output unit 140) The output unit 140 has a function of outputting various information to an operator. For this purpose, the output unit 140 may be configured to include a display device that outputs visual information. Here, the above-mentioned display device may be realized by, for example, a CRT (Cathode Ray Tube) display device, a Liquid Crystal Display (LCD) device, an OLED (Organic Light Emitting Diode) device, or the like.

[0028] An example of the functional configuration of the information processing device 10 according to the base technology has been described above. Note that the above-described example of the functional configuration is merely an example, and the functional configuration example is not limited to the above example. The information processing device 10 may further include a configuration other than that shown in FIG. 1. The information processing device 10 may further include, for example, a communication unit that performs information communication with other information processing terminals. In other words, the functional configuration of the information processing device 10 according to the base technology can be flexibly changed in design.

[0029] 1.3 Quantization of weight vectors Next, the quantization of the weight vector according to the base technology will be described in detail. As described above, the information processing device 10 according to the base technology can maintain high uniformity of granularity by performing quantization using the weight vector w expressed by powers. At this time, the calculation unit 120 quantizes a plurality of weight vector components w i In addition, the weight vector components w i The largest weighting coefficient w i One of the features is that the weight vector is normalized by w j Then, the weight vector w j is expressed by the following formulas (2) to (4).

[0030]

number

[0031] In this case, α in the above formula (2) is 0<α<1, and s j s j ∈{-1,1}, n j is n j ∈{0, 1, 2, ...}. That is, the calculation unit 120 calculates n j is treated as an integer and quantized. In this case, the inner product calculation performed by the calculation unit 120 is expressed by the following formula (5). Note that K in the following formula (5) represents a normalization constant. Furthermore, even if the value of α is appropriately modified from the following formula (5), it is sufficient that it is ultimately determined to be within the above range in the inner product calculation. The formulas shown in this disclosure are merely examples and can be flexibly modified.

[0032]

number

[0033] For this reason, it is expected that the inner product calculation by the calculation unit 120 can be processed with N addition operations and a number of multiplications on the order of −1 / 2log(N−1) / logα.

[0034] In this way, one of the features of the information processing method according to the base technology is that the weight vector w is approximated by a power expression of α, and the weight vector w is rearranged in ascending order of value. In this case, the information processing method according to the base technology quantizes the weight vector w by converting the exponent of α into a t-value according to N.

[0035] For example, when N=100, the information processing method according to the base technology may adopt t=4 (2 bits), 8 (3 bits), 16 (4 bits), etc. By setting t as above, n in the above formula (5) 1- n2,n 2- n3,n 3- Many of n4... are quantized to the same value and become 0, so the number of multiplications can be significantly reduced. To give a more specific example, when N=100 and t=4, n j-1 -n j can take a value other than 0 only four times. Therefore, in this example, the number of multiplications required for the inner product calculation is only four, and the rest are all additions, which effectively reduces the processing load.

[0036] 1.4 Example of a multiply-and-accumulate circuit Next, we will explain the product-sum operation circuit that realizes the operation method related to the base technology. As described above, when the weight vector w is quantized by the power expression and rearranged, it is also necessary to rearrange the input vector x corresponding to the weight vector w.

[0037] For this reason, the information processing device 10 may include a product-sum calculation circuit having a table that holds address information of a plurality of weight vectors w sorted in ascending order of value and the corresponding input vectors x.

[0038] Fig. 8 is an example of a circuit block diagram of a product-sum calculation circuit 200 included in the information processing device 10 according to the base technology. As shown in Fig. 8, the product-sum calculation circuit according to the base technology includes a storage circuit that holds a table WT that holds address information of an input vector x corresponding to a weight vector w, a RAM 210, an adder circuit 220, an accumulator 230, a first multiplier circuit 240 that performs multiplication related to α, and a second multiplier circuit 250 that performs multiplication related to a normalization constant.

[0039] (Address table WT) The address table WT according to the base technology holds address information, sign information, and multiplication instruction information for a plurality of weight vectors w sorted in ascending order of value and corresponding input vectors x. The address information may include a null pointer, as shown in FIG. 8. In this case, 0 is added to the accumulator 230, and the value of the accumulator 230 can be simply multiplied by α. The sign information is expressed by S in the above-mentioned formula (5). j This is information indicating the value corresponding to.

[0040] The multiplication instruction information is information that instructs the processing content by the first multiplication circuit 240. The multiplication instruction information related to the base technology may include, for example, information that specifies whether or not multiplication is required. Fig. 8 shows an example in which, when the multiplication instruction information is 0, the first multiplication circuit 240 does not perform multiplication, and, when the multiplication instruction information is 1, the first multiplication circuit 240 multiplies by α.

[0041] The multiplication instruction information related to the base technique is not limited to the above example, and may include information specifying various processing contents. For example, the multiplication instruction information related to the base technique may include information specifying the number of multiplications or shift operations.

[0042] (RAM210) The RAM 210 calculates the weight vector components w based on the address information input from the address table WT. j The input vector component x corresponding to jis output to the adder circuit 220.

[0043] (Addition circuit 220) The adder circuit 220 adds the input vector component x j and the value output from the first multiplication circuit 240. At this time, the addition circuit 220 performs the above addition based on the sign information held in the address table WT.

[0044] (Accumulator 230) The accumulator 230 accumulates the calculation results output from the addition circuit 220. The accumulator 230 outputs the accumulated value to the first multiplication circuit 240 and the second multiplication circuit 250. In addition, a reset signal for resetting the accumulated value to 0 is appropriately input to the accumulator 230.

[0045] (First multiplication circuit 240) The first multiplication circuit 240 multiplies the value accumulated by the accumulator 230 by α. At this time, the first multiplication circuit 240 performs the above multiplication based on the multiplication instruction information held in the address table WT, as described above. The first multiplication circuit 240 outputs the calculation result to the addition circuit 220.

[0046] (Second multiplication circuit 250) The second multiplication circuit 250 multiplies the value output from the accumulator 230 by a normalization constant K.

[0047] The above describes an example of the configuration of the product-sum calculation circuit 200 according to the base technology. The product-sum calculation circuit 200 according to the base technology makes it possible to effectively reduce the number of multiplications in an inner product calculation, thereby reducing the processing load.

[0048] On the other hand, since the address table WT has a large capacity due to holding the address information of the input vector x, it is expected that the power consumption will increase. For this reason, the address table WT may include an offset indicating the relative position between addresses, as shown in Fig. 9. Fig. 9 is an example of offset notation related to the address information held in the address table WT according to the base technology.

[0049] As shown in FIG. 9, the address table WT is j-1 -n j The addresses in a section where the value of is consecutively 0, i.e., a section where multiplication is not performed, may be sorted in address order, and the offset between the addresses may be held as address information. According to the above address table WT related to the base technology, it is possible to significantly reduce the amount of information related to the address information, and effectively reduce power consumption.

[0050] The address table WT may take various forms other than those shown in Figures 8 and 9. For example, the address table WT does not need to hold the sign information and the multiplication instruction information clearly separated, and an address compression method other than the above may be adopted. The address table WT may be flexibly modified according to the configuration of the neural network, the performance of the information processing device 10, and the like.

[0051] 1.5 Quantization during training Next, the quantization of the weight vector w during learning according to the base technology will be described. i The update can be calculated using the following formula (6).

[0052]

number

[0053] However, in the above formula (6), w max , w iIn addition, the integer int may be rounded up or down, whichever is closer. In the information processing method according to the base technology, n i By rearranging the addresses, the above-mentioned address table WT can be generated.

[0054] In addition, when α is set close to 1, the calculation is performed using a learning algorithm based on a DNN (Deep Neural Network) using normal floating-point arithmetic, and w after learning is completed. i It is also possible to adopt a method of quantizing the weight vector w. In other words, when the quantization granularity of the weight vector w is small, it is expected that the recognition accuracy will not decrease even if the network structure is not modified.

[0055] 1.6 Effect of base technology Next, the effect of quantizing the weight vector according to the base technology will be described in detail. As described above, in the information processing method according to the base technology, the weight vector quantized by the power expression is i By sorting and normalizing the values ​​in ascending order, j In this case, the rearranged basis vectors are defined as q j Then, the weight vector w is expressed by the following equation (7).

[0056]

number

[0057] That is, the information processing method according to the base technology is as shown in FIG. j-1 The weight vector projected onto the space spanned by and q j A vector is created on the plane formed by and the vector is expressed as α nj-nj+1 10 is a diagram showing a process image of the information processing method according to the base technology.

[0058] For this reason, in the information processing method according to the base technology, the weight vector is q1, q2, ... q j-1 Axes and q projected into space j In a plane spanned by and, the quantization granularity Δθ ​​of the weight vector can be expressed by the following formulas (8) and (9) in the counterclockwise and clockwise directions, respectively, as shown in Fig. 11. However, in this case, l in formulas (8) and (9) is defined by formula (10). Fig. 11 is a diagram for explaining the quantization granularity Δθ ​​according to the base technology. Note that Fig. 11 shows a weight vector projected onto the first quadrant.

[0059]

number

[0060] Furthermore, when the quantization granularities Δθ1 and Δθ2 are differentiated with respect to 1 and set to 0, the maximum values ​​of each are defined by the following formula (11).

[0061]

number

[0062] 12 is a graph showing the maximum value of the quantization granularity Δθ ​​according to α according to the base technology. In this way, according to the information processing method according to the base technology, the quantization granularity is guaranteed in all orthogonal rotation directions in an N-dimensional space.

[0063] If the power calculation is stopped midway, the quantization granularity Δθ ​​remains as shown in FIG. 13. FIG. 13 is a diagram for explaining the maximum power number according to the base technology. Note that FIG. 13 shows a weight vector projected onto the first quadrant. In this case, the maximum power number that guarantees the quantization granularity Δθ ​​can be obtained by adding the following formula (13) to the minimum m that satisfies the following formula (12). Therefore, the number of multiplications performed by the information processing device 10 can be calculated by the following formula (14).

[0064]

number

[0065] For example, when α=3 / 4, the number of multiplications for the number of inputs N is determined as shown in the graph in Fig. 14. Also, when α=7 / 8, the number of multiplications for the number of inputs N is determined as shown in the graph in Fig. 15. That is, in the inner product calculation by the calculation unit 120, the number of multiplications is determined based on the base value of the weight vector. Figs. 14 and 15 are diagrams showing examples of the number of multiplications for the number of inputs N according to the base technology.

[0066] As described above, according to the information processing device that realizes the information processing method based on the base technology, it is possible to significantly reduce the number of multiplications in the inner product calculation related to the forward propagation of the neural network, and effectively reduce the power consumption by the product-sum calculation circuit 200. Furthermore, according to the information processing device that realizes the information processing method based on the base technology, it is possible to improve the quantization accuracy of the weight vector, and it is expected to have the effect of improving the recognition accuracy and approximation accuracy by the neural network compared to the conventional quantization method using the same number of bits.

[0067] 2. Examples of developments in base technologies 2.1 Overview Next, an example of the development of the base technology will be described. In the base technology, the weight vector components w j α n We have described a method to achieve high approximation accuracy and reduce the number of multiplications in the inner product calculation by the order of logarithm by expressing it as

[0068] However, while the method exemplified in the base technology is effective when the number of dimensions of the inner product space is relatively large, it is expected that the effect of reducing the processing load may not be sufficient for inner product calculations with a relatively small number of dimensions, such as in a Convolutional Neural Network (CNN).

[0069] Therefore, in an advanced example of the base technology (hereinafter simply referred to as the advanced example), an arithmetic circuit is proposed that can effectively reduce the processing load of inner product operations even when the number of dimensions of the inner product space is relatively small.

[0070] Specifically, the weight vector components w i or the input vector component x i α -n / p In this case, if α = 2, then α -n / p The possible values ​​for can be expressed as shown in Table 1 below.

[0071] [Table 1]

[0072] Table 1 above shows that the larger the value of p, the smaller the granularity of quantization. For this reason, in the developed example, the weight vector component w i or the input vector component x i α -n / p By quantizing the data by the above formula, it is possible to reduce the quantization error compared to the base technology. In addition, according to the calculation method in the developed example, it is possible to perform processing equivalent to the inner product calculation described in the base technology by only shift calculations and additions, and it is possible to effectively reduce the processing load in the inner product calculation.

[0073] 2.2 Quantization of weight vectors First, we set only the weight vector w as α -n / p Here, a case will be described in which α=2, p∈{1, 2, 3, ...} is a natural number, and an inner product operation is performed using the following formula (15). Note that p corresponds to the divisor in this disclosure. In addition, w i is expressed by the following formula (16). i and n i are respectively, s i ∈{-1,1}, n i Let ∈{0,1,2,...}.

[0074]

number

[0075] In this case, w is all w i For |w i If normalization is performed so that |≦1, and if necessary, y is later multiplied by a normalization multiplier, the above formula (15) can be expressed as the following formula (17). r is defined by the following formula (18).

[0076]

number

[0077] where r∈{0,1,...,p-1}, δ i,j =1 if i=j, otherwise 0, then y r can be expressed in the usual fixed-point notation, which expresses negative numbers in two's complement.

number

number

[0078]

number

[0079] In this case, the inner product calculation shown in the above formula (19) can be realized, for example, by a product-sum calculation circuit 300 shown in Fig. 16. Fig. 16 shows an example of a product-sum calculation circuit when the weight vector according to the developed example is quantized.

[0080] 16, the product-sum calculation circuit 300 includes a shift calculation unit 310, a remainder calculation unit 320, selectors 330 and 340, an accumulator group 350, an adder-subtracter 360, a multiplier group 370, and an adder 380.

[0081] (Shift calculator 310) The shift calculator 310 shifts the input vector component x i、 and n i Specifically, the shift calculator 310 performs a shift operation based on the input vector component x i , int(n i / p) bit shift to the right.

[0082] (Remainder calculator 320) The remainder calculator 320 calculates the n i Based on n i A mod p operation is performed, and the remainder value is input to the selectors 330 and 340 .

[0083] (Selectors 330 and 340) The selectors 330 and 340 select an accumulator to connect to the circuit from among the multiple accumulators included in the accumulator group 350 based on the calculation result by the remainder calculator 320. At this time, the selectors 330 and 340 operate to connect the circuit to an accumulator that corresponds to the value of the remainder. For example, when the remainder is 0, the selectors 330 and 340 operate to connect the accumulator y0 to the circuit, and when the remainder is 1, the selectors 330 and 340 operate to connect the accumulator y1 to the circuit.

[0084] (Accumulator group 350) The accumulator group 350 includes n iThe accumulator group 350 includes a plurality of accumulators each corresponding to a value of the remainder of mod p. That is, the accumulator group 350 stores y r Hold.

[0085] (Adder / Subtractor 360) The adder / subtractor 360 receives the input s i , the shift operation result, and y r In this case, the adder / subtractor 360 performs addition and subtraction based on the value of n i y held by the accumulator selected based on the value of the remainder mod p r Based on the result of the calculation by the adder / subtractor 360, the value of y r will be updated.

[0086] (Multiplier group 370) The multiplier group 370 multiplies y r For this purpose, the multiplier group 370 multiplies n i For example, the multiplier group 370 multiplies y0 input from the accumulator group 350 by 1, and multiplies y1 by 2. -1 / p Multiply by.

[0087] (Adder 380) The adder 380 multiplies the y r The value of is added and the final calculation result y is output.

[0088] The above describes the sum-of-products calculation circuit 300. As described above, the sum-of-products calculation circuit 300 calculates n i For each remainder mod p, store y in the corresponding accumulator. r By accumulating each of these and then multiplying them together at the end, it is possible to minimize the number of multiplications. In the example shown in FIG. 16, the calculation is performed sequentially for i and y r However, it is possible to perform some or all of the above calculations in parallel.

[0089] 2.3 Quantization of both weight vectors and input vectors Next, we set both the weight vector w and the input vector x to α -n / p Here, we will explain the case where α=2, p∈{1,2,3,...} is a natural number, and an inner product operation is performed. Here, the input vector component x i and the weight vector components w i are expressed by the following formulas (20) and (21), respectively. In the following formulas (20) and (21), s xi ,s wi ∈{-1,1}, n i ,m i Let ∈{0,1,2,...}.

[0090]

number

[0091] Here, the input vector x and the weight vector w are respectively defined as |x i |≦1, |w i If y is normalized so that |≦1, and then multiplied by a normalization multiplier as necessary, the inner product operation can be expressed by the following formula (22). r is defined by the following formula (23).

[0092]

number

[0093] In this case, if r∈{0,1,...,p-1}, then y r can be expressed in the usual fixed-point notation, which expresses negative numbers in two's complement. In the above, it was stated that p may be a natural number, but p may also be expressed in a power notation. For example, p=2 q , q∈{0,1,2,...}, then int((m i +n i ) / p) and (m i +ni ) The calculation of mod p can be performed by extracting bits, and division is not required, which has the effect of simplifying the calculation.

[0094] In this case, the inner product calculation can be realized by, for example, a product-sum calculation circuit 400 shown in Fig. 17. Fig. 17 shows an example of a product-sum calculation circuit in the case where both the weight vector and the input vector according to the developed example are quantized.

[0095] 17, the product-sum operation circuit 400 includes a first adder 410, a shift operation unit 420, a selector 430, an XOR circuit 440, an accumulator group 450, a multiplier group 460, and a second adder 470.

[0096] (First adder 410) The first adder 410 receives m i and i In this case, m i and n i As shown in the figure, the sum of [b k-1 ,...,b q ,b q-1 It can be represented as a bit array [b0,...b1,...b2].

[0097] (Shift calculator 420) The shift calculator 420 calculates 1 expressed in fixed point notation by adding int((m i +n i ) / p) to the right. i +n i The value of [b k-1 ,...,b q Therefore, the shift calculator 420 may perform a shift operation using the value of the upper bits.

[0098] (Selector 430) The selector 430 selects (m i +ni ) mod p, an adder / subtractor to be used for addition / subtraction is selected from among the multiple accumulators and adders / subtractors included in the accumulator group 450, and an Enable signal = 1 is input. At this time, the value of the remainder is input to the [b q-1 ,...,b0], it is possible to simplify the calculation as above.

[0099] (XOR circuit 440) The XOR circuit 440 receives the S xi and S wi Based on this, the XOR circuit 440 inputs 1 or 0 to each accumulator of the accumulator group 450. wi S xi =-1, then 1, S wi S xi If the result is +1, input 0 into each accumulator.

[0100] (Accumulator group 450) The accumulator group 450 includes (m i +n i ) mod p. Accumulator group 450 includes a plurality of accumulators each corresponding to a remainder value of p. Accumulator group 450 includes a plurality of adder-subtractors (1-bit up-down counters) corresponding to the accumulators.

[0101] Here, as shown in the lower right of the figure, each of the adder-subtractors determines whether or not addition or subtraction is necessary based on the Enable signal input from the selector 430. Specifically, only when the input Enable signal is 1, each adder-subtractor adds or subtracts only one bit to the value O held by the corresponding accumulator, according to the U / D value input from the XOR circuit 440. According to the accumulator group 450 of the developed example, addition or subtraction of one bit to the most significant bit results in y r Since the value of can be updated, a normal adder / subtractor is not required, making it possible to reduce the circuit scale.

[0102] (Multiplier group 460) The multiplier group 460 multiplies y r To this end, the multiplier group 460 multiplies (m i +n i For example, the multiplier group 460 multiplies y0 input from the accumulator group 450 by 1, and multiplies y1 by 2. -1 / p Multiply by.

[0103] (Second adder 470) The second adder 470 multiplies the y r The value of is added and the final calculation result y is output.

[0104] The above describes the sum-of-products circuit 400. As described above, according to the sum-of-products circuit 400 according to the developed example, (m i +n i ) mod p, the corresponding accumulator is filled with y r By accumulating each of these and multiplying them together at the end, it is possible to minimize the number of multiplications. In the example shown in FIG. 17, the calculation is performed sequentially for i and y r However, it is possible to perform some or all of the above calculations in parallel.

[0105] In addition, in the product-sum arithmetic circuit 400 shown in Fig. 17, an example has been described in which a plurality of adders / subtractors (1-bit up / down counters) corresponding to accumulators are implemented in parallel, but instead of the above configuration, the product-sum arithmetic circuit 400 according to the developed example may include a selector and a single adder / subtractor as in the product-sum arithmetic circuit 300 shown in Fig. 16. Similarly, it is also possible to implement a plurality of adders / subtractors in parallel in the product-sum arithmetic circuit 300. The configuration of the product-sum arithmetic circuit according to the developed example can be appropriately designed so that the circuit scale becomes smaller according to the value of p.

[0106] In addition, in the product-sum calculation circuit 400 shown in FIG. i +ni In the above, the adder / subtractor and the accumulator are selected based on the lowest q bits of the arithmetic unit (22). On the other hand, the above equation (22) can be transformed into the following equation (24).

[0107]

number

[0108] Therefore, the inner product calculation can be realized by a single adder / subtractor, as in the case of a product-sum calculation circuit 500 shown in Fig. 18. Fig. 18 shows an example of a product-sum calculation circuit in the case where both the weight vector and the input vector according to the developed example are quantized.

[0109] 18, the product-sum calculation circuit 500 includes an adder 510, a selector 520, a memory circuit group 530, a shift calculation unit 540, an XOR circuit 550, an adder-subtractor 560, and an accumulator 570.

[0110] (Adder 510) The adder 510 receives the m i and i The adder 510 may perform the same operation as the first adder 410 shown in FIG.

[0111] (Selector 520) The selector 520 selects the [b q-1 , . . . , b0], a storage circuit to which the circuit is to be connected is selected from among the multiple storage circuits included in the storage circuit group 530.

[0112] (Memory circuit group 530) The memory circuit group 530 includes (m i +n i) mod p. Each storage circuit stores an addition multiplier corresponding to each remainder. Each storage circuit in the storage circuit group 530 may be a read-only circuit that holds the addition multiplier as a constant, or may be a rewritable register. Storing the addition multiplier as a constant in a read-only circuit has the advantage of simplifying the circuit configuration and reducing power consumption.

[0113] (Shift calculator 540) The shift calculator 540 converts the added multiplier stored in the connected storage circuit into [b k-1 ,...,b q ] and then a right shift operation is performed by the value of the upper bit corresponding to .

[0114] (XOR circuit 550) The XOR circuit 550 receives the input S xi and S wi 17. The XOR circuit 550 may perform the same operation as the XOR circuit 440 shown in FIG.

[0115] (Adder / Subtractor 560) The adder / subtractor 560 repeatedly performs addition or subtraction on y held in the accumulator 570 based on the operation result from the shift calculator 540 and the input from the XOR circuit 550 .

[0116] (Accumulator 570) Accumulator 570 holds the result y of the dot product operation.

[0117] As described above, according to the product-sum calculation circuit 500 of the developed example, the inner product calculation can be realized by a single adder-subtractor 560 and a single accumulator 570, making it possible to further reduce the circuit scale.

[0118] In the above description, a common p is used for the input vector x and the weight vector w, but in the information processing method according to the developed example, it is also possible to use a different p for the input vector x and the weight vector w. In this case, the input vector x and the weight vector w can be expressed by the following formulas (25) and (26), respectively.

[0119]

number

[0120] In this case, p m and p n Let p0 be the least common multiple of ap m = p0, and bp n = p0, then the input vector component x i and the weight vector components w i are expressed by the following formulas (27) and (28), respectively.

[0121]

number

[0122] Therefore, m i +n i The calculation of am i +bn i By replacing p with p0, the calculation can be performed in the same manner as described above, even if p is different. m and p n If we use the power expression, am i and bn i can be calculated by a shift operation.

[0123] Next, a method for quantizing an input vector x according to a developed example will be described in detail. When quantizing both the input vector x and the weight vector w, the quantization of the weight vector w can be calculated in advance, but the quantization of the input vector x needs to be performed at run time. For this reason, a method is required for realizing the quantization of the input vector x using a small-scale arithmetic circuit.

[0124] where |x i |≦1, c=[c k-1 ,...,c0], where c is the bit sequence k-1 is the fixed-point notation corresponding to 1.

[0125] In this case, the number of consecutive 0 bits from the most significant bit (msb) of c is L. Also, c = [c k-1 ,...,c0] is shifted left by L bits to create a bit array called d, and the bit array is treated as a fixed-point number with its msb set to 0.5.

[0126] Next, let r be the minimum r that satisfies the following formula (29). min Here, r∈{0,...,p-1}, but if the smallest r cannot be found, r min = p, where m i If we define |x i | can be approximated, that is, quantized, as the following equation (31).

[0127]

number

[0128] The above-mentioned calculation can be realized by including a configuration for counting the number of consecutive 0 bits L from the msb of c, and a configuration for comparing with a fixed value p times.

[0129] 2.4 Effects of development examples Next, the effect of quantizing the weight vector w and the input vector x according to the developed example will be described in detail. Here, the weight vector components w i and the input vector component x i ±2 -n / p When quantization is performed as above, the recognition rates are compared for p=1, i.e., when the quantization method described in the base technology is used, and for p=2, i.e., when the quantization method in the advanced example is used.

[0130] Specifically, we conducted experiments to compare the image recognition rate when learning the weight vector w and input vector x using floats, then quantizing the obtained coefficients to the nearest quantization point using the respective p values, and performing inference without re-learning.

[0131] The dataset used was the CIFAR-10 image set (10-class classification, training data = 50,000 images, test data = 10,000 images).

[0132] In addition, an 11-layer ResNet based on ResNet23 was used for the network. FIG. 19 is a diagram showing the network structure of ResNet used in the comparative experiment according to the developed example. In FIG. 19, the input size input to each layer is shown on the right side of the figure, and the kernel size is shown on the left side of the figure. As shown in FIG. 19, the created network includes both a ResBlock that does not include a Max Pooling layer and a ResBlock that includes a Max Pooling layer. FIG. 20 and FIG. 21 are diagrams showing the network configurations of a ResBlock that does not include a Max Pooling layer and a ResBlock that includes a Max Pooling layer, respectively.

[0133] Next, the quantization method of the weight vector w and the input vector x used in the experiment will be described in detail.

[0134] First, the data when quantization is performed with p=1 will be described. Here, 32 values ​​(16 values ​​× 2±) of n=-3 to 12 are used in quantization of the weight vector w. In this case, the quantized weight vector component w i =±(2 -n ) can take on values ​​as shown in Table 2 below.

[0135] [Table 2]

[0136] In addition, before inputting the input vector x to the Relu block, three different quantizations were performed: 16 values ​​(8 values ​​x 2 ±) for n = -4 to 3, 32 values ​​(16 values ​​x 2 ±) for n = -4 to 11, and 64 values ​​(32 values ​​x 2 ±) for n = -4 to 27. At this time, the quantized input vector components x i =±(2 -n ) can take the values ​​shown in Tables 3 to 5 below.

[0137] [Table 3]

[0138] [Table 4]

[0139] [Table 5]

[0140] Next, we will explain data when p=2, that is, when quantization is performed using the method according to the developed example. Here, 32 values ​​(16 values ​​x 2±) from n=-6 to 9 are used in quantization of the weight vector w. In this case, the quantized weight vector component w i =±(2 -n / 2 ) can take on values ​​as shown in Table 6 below.

[0141] [Table 6]

[0142] In addition, before inputting the input vector x to the Relu block, three different quantizations were performed: 16 values ​​(8 values ​​x 2 ±) from n = -8 to -1, 32 values ​​(16 values ​​x 2 ±) from n = -8 to 7, and 64 values ​​(32 values ​​x 2 ±) from n = -8 to 23. At this time, the quantized input vector component x i =±(2 -n / 2 ) can take the values ​​shown in Tables 7 to 9 below.

[0143] [Table 7]

[0144] [Table 8]

[0145] [Table 9]

[0146] Fig. 22 shows a comparison result of image recognition rates when inference is performed without re-learning using the quantization described above. In Fig. 22, the vertical axis shows recognition accuracy, and the horizontal axis shows the quantization number (N value) of the input vector x. Also in Fig. 22, the recognition accuracy before quantization is shown by line segment C, the recognition accuracy when quantization is performed with p=1 is shown by line segment P1, and the recognition accuracy when quantization is performed with p=2 is shown by line segment P2.

[0147] Comparing line segments P1 and P2, it can be seen that when the quantization number of the input vector x is set to 32 or 64, quantization at p=2 improves the recognition accuracy significantly more than quantization at p=1. Also, comparing line segments P2 and C, it can be seen that no significant deterioration in recognition accuracy is observed. This shows that when the quantization number of the input vector x is sufficient, by adopting the quantization method according to the developed example, it is possible to maintain high recognition accuracy even without re-learning.

[0148] In this way, the quantization method according to the developed example makes it possible to effectively reduce the processing load in the inner product calculation while maintaining high performance of the learning device.

[0149] 3. Summary As described above, the information processing device according to the base technology and its developed example includes a product-sum operation circuit that performs a product-sum operation based on a plurality of input values ​​and a plurality of weighting coefficients quantized by power expressions, each corresponding to the input values. The exponents of the quantized weighting coefficients are expressed by fractions having a predetermined divisor p as a denominator. The product-sum operation circuit also performs a product-sum operation using different addition multipliers based on a remainder determined from the divisor p. This configuration makes it possible to further reduce the processing load related to the inner product operation and to guarantee the quantization granularity of the weighting coefficients.

[0150] 4. First embodiment Next, a first embodiment of the present disclosure will be described in detail below with reference to the drawings. In the following description, the base technology and its developed example will be referred to simply as the base technology.

[0151] 4.1 Issues with the Base Technology An example of a product-sum operation circuit in the case where both the weight vector and the input vector according to the base technology are quantized (corresponding to FIG. 18) is shown again in FIG. 23. As shown in FIG. 23, the base technology illustrates a method of implementing the product-sum operation by table lookup. Specifically, it is provided with a table (storage circuit group 530) in which the number of entries and the value are determined by p indicating the granularity of quantization, and the product-sum operation oriented to the inference processing of DNN / CNN is performed using this table.

[0152] Therefore, in the following embodiment, by illustrating a configuration for switching between multiple tables while illustrating a table other than a value table formed from a power of the p-th root of 2, the advantage of the memory circuit group 530 being a rewritable register is more clearly shown.

[0153] 4.2 Value Table Example As mentioned above, the base technology proposes a new quantization method with the aim of reducing the amount of product-sum calculations in deep neural networks (DNNs) and convolutional neural networks (CNNs). Generally, quantization in information theory refers to the approximation of analog quantities with discrete values, but quantization here is defined as expressing the precision of the original value with fewer bits. For example, quantization refers to truncating a value originally expressed as a 32-bit floating-point number to a 10-bit or 8-bit floating-point number or fixed-point number, or more extremely, to 2 bits or 1 bit.

[0154] In the base technology, the coefficients and variables during DNN / CNN inference are quantized to shorten the word length of the values ​​that represent the coefficients and variables. This makes it possible to reduce the memory capacity required to store parameters, as well as the amount of calculations and energy required for product-sum calculations.

[0155] Therefore, in the base technique, quantization is performed as shown in the following equation (32) (corresponding to the above-mentioned equations (20) and (21)) with a variable x and a constant w.

number

[0156] where x i is the i-th element of the input vector x, and w i is the i-th element of the coefficient vector w, s is the positive or negative sign of the element, m is the index (symbol) when the i-th element of the input vector x is quantized, n is the index (symbol) when the i-th element of the coefficient vector w is quantized, and p is the quantization granularity.

[0157] In the base technology, as shown in Fig. 23, a product-sum operation oriented to DNN / CNN inference processing is performed using a table (storage circuit group 530) in which the number of entries and values ​​are determined by p, which indicates the granularity of quantization, as a parameter. Specifically, p values ​​according to the function space of powers of 2 (more precisely, the power of the p-th root of 2) are stored as table values, and the product-sum operation by the power of 2 method is realized by accumulating while scaling according to the positive / negative signs and dynamic ranges of the variables and coefficients. Note that in the base technology, the following formula (33) is exemplified as the table value.

number

[0158] When the table values ​​of equation (33) are plotted on a graph, the relationship between the index and the table values ​​is as shown in FIG.

[0159] Here, consider another table value. For example, apply a value along a linear function space instead of a value along a power of 2 function space. In that case, quantization is performed as shown in the following formula (34).

number

[0160] In formula (34), each symbol is x, just like the power of 2 representation in formula (32). i is the i-th element of the input vector x, and wi is the i-th element of the coefficient vector w, s is the positive or negative sign of the element, m is the index (symbol) when the i-th element of the input vector x is quantized, n is the index (symbol) when the i-th element of the coefficient vector w is quantized, and p is the quantization granularity.

[0161] In this embodiment, the table in the power-of-two representation of the base technology is combined with the domain and range, and p values ​​along a linear function space are set as table values. Using these values, scaling according to the positive / negative signs and dynamic ranges of the variables and coefficients is performed while accumulating, thereby making it possible to realize a product-sum operation using a linear method. The circuit configuration in this case may be the same as the product-sum operation circuit illustrated in FIG. 23. However, the table values ​​in the memory circuit group 530 are values ​​expressed by the following formula (35).

number

[0162] Incidentally, equation (35) can be simplified and expressed as equation (36) below.

number

[0163] When the table values ​​shown in equation (35) or equation (36) are plotted on a graph, the relationship between the index and the table values ​​becomes as shown in FIG.

[0164] Up to this point, we have been expressing numbers in the form of linear representations, but by adopting the notation method exemplified in the third embodiment described below, this can also be applied to floating-point number representations having a sign part, an exponent, and a mantissa.

[0165] Fig. 26 is a diagram in which table values ​​in a power of 2 representation and table values ​​in a linear representation are plotted on the same graph. As shown in Fig. 26, compared to the linear representation, the table values ​​in the power of 2 representation have a downward convex shape.

[0166] By changing the table values ​​in this way, a product-sum calculation circuit with different characteristics can be easily realized.

[0167] Yet another example of a table is one in which a power-of-two representation is converted into an upward convex representation with the linear representation value as the axis.

[0168] In addition, by changing the underlying function space, it is possible to create various tables suitable for CNN / DNN tasks. However, due to the characteristics of the multiply-and-accumulate circuit, it is required that the function be monotonically decreasing in this domain interval.

[0169] As explained in the base technology, each storage circuit included in the storage circuit group 530 may be a read-only circuit that holds the addition multiplier as a constant, or may be a rewritable register.

[0170] 4.3 Examples of multiply-and-accumulate circuits Next, some specific examples of the product-sum calculation circuit according to the first embodiment will be described.

[0171] 4.3.1 First concrete example Fig. 27 is a circuit diagram showing a schematic configuration example of a product-sum operation circuit according to a first specific example. As shown in Fig. 27, the product-sum operation circuit according to the first specific example includes an integer adder (also simply called an adder) 510, a selector 520, a memory circuit group 530, a shift operation unit 540, an XOR circuit 550, an adder-subtractor 560, and an accumulator 570, similar to the product-sum operation circuit shown in Fig. 23.

[0172] (Integer adder 510) The integer adder 510 receives m i and i In this case, m i and n i As shown in the figure, the sum of [b k-1 ,...,b q ,b q-1,...,b0].

[0173] (Selector 520) The selector 520 selects the [b q-1 , . . . , b0], a storage circuit to which the circuit is to be connected is selected from among the multiple storage circuits included in the storage circuit group 530.

[0174] (Memory circuit group 530) The memory circuit group 530 includes (m i +n i ) mod p. The multipliers corresponding to the remainders are stored in each of the memory circuits as normalized floating-point numbers with an exponent part with a base of 2. The multipliers stored in the memory circuit group 530 are in the range of 0.5 to 1.0, and can be expressed in normalized numbers by having a word length of 1 bit or more as the exponent part. Each of the memory circuits in the memory circuit group 530 may be a read-only circuit that holds the multipliers as constants, or may be a rewritable register. Storing the multipliers as constants in the read-only circuit has the advantage of simplifying the circuit configuration and reducing power consumption.

[0175] (Shift calculator 540) The shift calculator 540 according to the present embodiment calculates the sum of the multipliers stored in the connected storage circuit by [b k-1 ,...,b q ] and then a right shift operation is performed by the value of the upper bit corresponding to .

[0176] (XOR circuit 550) The XOR circuit 550 receives the input S xi and S wi Based on this, it outputs 1 or 0.

[0177] (Adder / Subtractor 560) The adder-subtractor 560 repeatedly adds or subtracts the input from the shift calculator 540 to y held in the accumulator 570 based on the input from the XOR circuit 550. If the input from the XOR circuit 550 is 0, addition is performed, and if it is 1, subtraction is performed.

[0178] (Accumulator 570) The accumulator 570 holds the result y of the multiply-and-accumulate operation.

[0179] In addition to the above configuration, the product-sum calculation circuit according to the first specific example further includes a memory 1530 that holds a plurality of different tables, and a selector 1531 that selectively writes the table values ​​in the memory 1530 to each memory circuit (register or memory) of the memory circuit group 530.

[0180] (Memory 1530) The memory 1530 holds, for example, the above-mentioned table 1530a of power-of-two expressions and table 1530b of linear expressions.

[0181] (Selector 1531) The selector 1531 reads out the table 1530 a or 1530 b from the memory 1530 in accordance with a write table control value input from a higher-level control unit or the like, and writes the read out table 1530 a / 1530 b into each memory circuit of the memory circuit group 530 .

[0182] With the above configuration, it becomes possible to switch the underlying function space, making it possible to perform multiply-and-accumulate operations using an appropriate table depending on the CNN / DNN task.

[0183] 4.3.2 Second Example Fig. 28 is a circuit diagram showing a schematic configuration example of a product-sum calculation circuit according to a second specific example. As shown in Fig. 28, the product-sum calculation circuit according to the second specific example has a configuration similar to that of the product-sum calculation circuit shown in Fig. 23, in which the memory circuit group 530 is replaced with a plurality of (two in this example) memory circuit groups 530A and 530B each holding a plurality of different tables, and further includes a selector 1532 that selectively switches the connection between the memory circuit group 530A or 530B and the selector 520.

[0184] The memory circuit group 530A is composed of a plurality of memory circuits that store the table values ​​of the power of 2 expressions described above, for example, as in Fig. 23. On the other hand, the memory circuit group 530B is composed of a plurality of memory circuits that store the table values ​​of the linear expressions described above, for example.

[0185] The selector 1532 switches the connection between the memory circuit groups 530A / 530B and the selector 520 in accordance with a table switching signal input from a higher-level control unit or the like.

[0186] With the above configuration, as in the first concrete example, it becomes possible to switch the underlying function space, making it possible to perform product-sum operations using an appropriate table depending on the CNN / DNN task.

[0187] 4.4 Actions and Effects As described above, according to this embodiment, by selecting an appropriate additive constant for the table (storage circuit group 530), it is possible to select, without changing the configuration of the arithmetic circuit portion in the product-sum calculation circuit 2100, a floating-point number that is not a power of two expression, for example, a linear floating-point number.

[0188] This makes it possible to select table values ​​according to the processing task of the DNN / CNN, without being limited to power-of-two expressions or linear expressions.

[0189] In general, when implementing an arithmetic circuit system for DNN / CNN, a large number of processor elements equipped with multiple sum-of-product circuits are arranged, including sum-of-product circuits using powers of two expressions of the base technology, such as float32, float16, and short word length float, in order to handle various processing tasks. In contrast, according to this embodiment, the exact same circuit can be used for sum-of-product circuits using powers of two expressions and short word length floats simply by switching tables, making it possible to achieve a significant reduction in the overall circuitry.

[0190] The other configurations, operations, and effects may be similar to those of the base technology described above, so detailed explanations will be omitted here.

[0191] 5. Second embodiment Next, the second embodiment will be described in detail with reference to the drawings.

[0192] 5.1 Issues with the Base Technology In the base technology, it is necessary to find the minimum r that satisfies formula (29), but in the implementation, it is necessary to prepare a value obtained by multiplying the power of the p-th root of 2 by the 2p-th root of 2 for value comparison when searching for the optimal r. Therefore, when using an existing table (storage circuit group 530) for value search, it is necessary to perform an operation of multiplying by the 2p-th root of 2 each time, which significantly increases the calculation cost. Alternatively, when using a table that has been multiplied by the 2p-th root of 2 in advance, it is necessary to implement two tables, a table for multiplication and accumulation operations and a table for quantization rounding, in the system that realizes the base technology, which poses a problem that management is likely to become complicated.

[0193] In this embodiment, a quantization circuit and method that can reduce calculation costs while suppressing complication in management will be described by way of example.

[0194] 5.2 Examples of quantization circuits In the base technology, the input vector or the product-sum operation results in each layer (or feature map) had to be quantized to a power-of-two representation at runtime and sent to subsequent processing or stored in memory. Since the values ​​of the coefficients of DNNs and CNNs do not change during processing, they can be converted to a power-of-two representation in advance for use, but it becomes necessary to convert numerical values ​​that appear in inference calculations to a power-of-two representation. This process is generally called runtime quantization. In this embodiment, a more advanced form of this quantizer rounding will be described.

[0195] The rounding of the quantizer is aimed at reducing the amount of information, so the output has less information than the input to the quantizer. Specifically, an input numerical value having a certain range is represented by one value. In other words, numerical values ​​in a certain range are rounded to one representative value. FIG. 29 is a diagram showing an example of rounding of the quantizer. As shown in FIG. 29, when a value included in a certain range RA is input to the quantizer, the value is rounded to A and the symbol m-1 is assigned. On the other hand, when a value included in a certain range RB is input, the value is rounded to B and the symbol m is assigned.

[0196] In the runtime quantization of the input vector x in the base technology, it is necessary to find the minimum r that satisfies the above-mentioned formula (29), but in the implementation, in order to search for the optimal r, it is necessary to prepare a value obtained by multiplying the p-th root of 2 by the 2p-th root of 2. This corresponds to the part surrounded by the solid line in formula (37) (the same as formula (29)).

number

[0197] This means 0.5 rounding according to the expression function of the power of 2 expression, and calculates the value of the midpoint B in Fig. 29. If the items in the above formula (37) except for those enclosed by a solid line are arranged according to the value of r, it will be the same as the value table for the product-sum operation exemplified in the first embodiment (see formula (33)).

[0198] This means that the table (storage circuit group 530) described in the base technology can be used for value search during runtime quantization, as shown in Fig. 30. Note that Fig. 30 is a block diagram showing a schematic configuration example of a neural network circuit as a comparative example.

[0199] 30, the neural network circuit as the comparative example includes a power expression converter 2001, a multiplier 2002, a variable buffer 2003, a coefficient memory 2004, an operation result buffer 2005, and a product-sum operation circuit 2100. The product-sum operation circuit 2100 includes a product-sum operation unit 2101, a power expression converter 2102, a power expression table 2103, and a multiplier 2104.

[0200] (Multiplication unit 2002) The multiplication unit 2002 performs 0.5 rounding according to the expression function of the power of 2 expression by multiplying the table value read from the power expression table 2103 as shown in the following equation (38), and inputs the obtained value to the power expression conversion unit 2001.

number

[0201] (Power Expression Converter 2001) The power expression converter 2001 converts an input value into a power of 2 expression using a value input from the multiplier 2002. The value obtained by the conversion is stored in the variable buffer 2003. Therefore, the variable buffer 2003 stores variables in a power of 2 expression.

[0202] (Product-sum calculation unit 2101) The product-sum operation unit 2101 executes a product-sum operation using variables of power expressions stored in a variable buffer 2003 and coefficients of power expressions stored in a coefficient memory 2004. At this time, the product-sum operation unit 2101 executes the product-sum operation using table values ​​stored in a power expression table 2103. The table stored in the power expression table 2103 is the value table shown in equation (33) above.

[0203] (Multiplication unit 2104) The multiplication unit 2104 performs multiplication as shown in the above equation (38) on the table value read from the power expression table 2103, thereby performing 0.5 rounding in accordance with the expression function of the power expression of 2, and inputs the obtained value to the power expression conversion unit 2001.

[0204] (Power expression converter 2102) The power representation converter 2102 converts the value input from the product-sum calculator 2101 into a power-of-two representation by using the value input from the multiplier 2104. The value obtained by the conversion is stored in the operation result buffer 2005. Therefore, the operation result buffer 2005 stores variables in a power-of-two representation.

[0205] In this way, by multiplying the power of 2 expression table 2103 (parameter p) present in the product-sum calculation circuit 2100 by the 2p-th root of 2, it is possible to realize the power expression conversion units 2001 and 2102 as run-time quantizers.

[0206] However, in the above configuration, since multiplication occurs every time runtime quantization is performed, the calculation cost is extremely high. Therefore, as shown in Fig. 31, it is also possible to prepare in advance tables (power expression conversion tables 2202 and 2204) in which the table values ​​in the power expression table 2103 are multiplied by the constant shown in equation (38).

[0207] In addition, runtime quantization is performed by quantizing input data from the outside for DNN / CNN, and quantizing including rounding after multiplication and accumulation. These are the same processes. Therefore, as shown in FIG. 32, the power expression conversion units 2001 and 2102 share the power expression conversion table 2204 and use it in a time-division manner, thereby reducing the amount of table storage in the entire system.

[0208] Incidentally, the power expression conversion tables 2202 and 2204 are obtained by multiplying a power expression table of 2, which is the parameter p that determines the granularity of quantization, by the 2p-th root of 2. That is, when conversion equation (38) for deriving the power expression conversion tables 2202 and 2204 from the power expression table 2103 is transformed, it becomes the following equation (39).

number

[0209] This means an odd-numbered subset of the power expression table of 2, which is the parameter 2p. Therefore, by combining this with the table of the even-numbered subset expressed by the following formula (40), that is, by combining the power expression table 2103 and the power expression conversion table 2202 / 2204, it is possible to treat them as one table.

number

[0210] Fig. 33 is a diagram showing a case where the even number portion subset and the odd number portion subset are combined into one table. As shown in Fig. 33, the power expression table 2203 including the even number portion subset and the odd number portion subset is shared by the product-sum operation unit 2101 and the power expression conversion units 2001 and 2102. The table values ​​input to the product-sum operation unit 2101 and the power expression conversion units 2001 and 2102 can be distributed according to, for example, whether the address of the symbol index is even or odd.

[0211] In this way, by combining the two tables into a single table, for example when storing the constants in a read-only circuit, it is possible to greatly simplify the circuit configuration through logic compression, and it is also possible to obtain the advantage of reducing power consumption.

[0212] 5.3 Actions and Effects As described above, according to this embodiment, when runtime quantization is performed, a power-of-two representation table for multiply-and-accumulate operations can be used to generate values ​​for comparison in runtime quantization.

[0213] In this case, in the base technology, multiplications occur frequently, but by using a pre-prepared table, it is possible to eliminate each multiplication and significantly reduce the calculation cost during runtime quantization.

[0214] Furthermore, by integrating the power-of-two representation table and the comparison value table, it is possible to consolidate the tables to be managed into one, which makes it possible to reduce the circuit scale and power consumption.

[0215] The other configurations, operations, and effects may be similar to those of the base technology or embodiments described above, and therefore detailed description thereof will be omitted here.

[0216] 6. Third embodiment Next, the third embodiment will be described in detail below with reference to the drawings.

[0217] 6.1 Issues with the Base Technology The above-mentioned base technology proposes a new and improved information processing device and information processing method that can further reduce the processing load associated with inner product calculations and ensure the quantization granularity of weighting coefficients.

[0218] However, the base technology requires the use of fixed-point representation as an internal numerical representation, which requires a long word length, resulting in an increase in scale and power consumption.

[0219] For example, if a numeric representation other than fixed-point representation is used, the shift operation is a power of 2 multiplication operation, so generally it would be y=x*2^n. This requires a power calculator and a multiplier, leading to an increase in scale. Here, * is the multiplication operator, and ^ is the power operator.

[0220] Furthermore, in the base technology, as for quantization of an input vector, only quantization from a fixed-point representation is shown, and no means for performing quantization at low cost from other numerical representations is shown.

[0221] When the base technique is used, the required word length of the fixed-point representation is, for example, as follows: i and the weight vector components w i are expressed by the above-mentioned formula (32). In formula (32), s xi ,s wi ∈{-1,1}, n i ,m i ∈{0,1,2,...}.

[0222] Also, the numerator related to the exponent of the quantized input value is m i Let p be the predetermined divisor of the denominator, and n be the numerator related to the exponent of the quantized weighting coefficient. i ,Let the predetermined divisor of the denominator be p.

[0223] The multiplication and accumulation circuit according to the base technique described above with reference to FIG. 23 realizes inner product calculations on a smaller circuit scale by using a single adder-subtractor 560 and a single accumulator 570. i and n i is 8 bits, the maximum shift amount of the shift calculator 540 is 32 bits. For example, if the significant digits are 6, the word length of the addition, subtraction, and multiplication numbers stored in the memory circuit group 530 is 20 bits, so the output word length of the shift calculator 540 is 52 bits. Since the word length of the accumulator 570 depends on how many additions are performed, for example, if the maximum number of additions is 255, the word length of the shift calculator 540 is 60 bits, which is 8 bits longer than the output word length of the shift calculator 540.

[0224] On the other hand, the IEEE754 standard is known as a method of expressing numbers using floating-point. According to this standard, finite numbers with base 2 or 10 are expressed by three integers: the sign, the mantissa, and the exponent. A feature of this standard is that in the binary floating-point format with base 2, the most significant bit of the normalized mantissa is always 1, so this bit is omitted in the expression. In addition, the exponent is expressed as 0 for 0 or a denormalized number, and as a biased expression in which a predetermined fixed value is added to the exponent for a normalized number. These expression methods can be easily extended to exponent and mantissa parts of any word length. Hereinafter, floating-point notation that omits the most significant bit of the normalized number in the mantissa, as in the IEEE754 standard, and adopts 0 for the exponent for 0 or a denormalized number, and as a biased expression for the exponent for a normalized number, is referred to as IEEE754-compliant.

[0225] In this embodiment, a multiply-and-accumulate circuit and a method thereof that enable a reduction in circuit size and power consumption will be described by way of example. According to the embodiment, it is possible to achieve the same effect as the base technology with a shorter word length, in other words, with a smaller circuit size and power consumption.

[0226] 6.2 Examples of multiply-accumulate circuits Fig. 34 is a circuit diagram showing a schematic configuration example of a product-sum operation circuit according to the third embodiment. As shown in Fig. 34, the product-sum operation circuit according to the third embodiment includes an integer adder 510, a selector 520, a memory circuit group 530, a power-of-two multiplication unit 3540, an XOR circuit 550, a floating-point adder-subtracter 3560, and an accumulator 570.

[0227] In the configuration shown in FIG. 34, the integer adder 510, the selector 520, the memory circuit group 530, the XOR circuit 550, and the accumulator 570 may be similar to the configuration described with reference to FIG. 27 in the first embodiment.

[0228] (Power of 2 multiplication calculator 3540) The power-of-two multiplication unit 3540 corresponds to the shift calculation unit 540 in Fig. 27. Therefore, the calculation executed by the power-of-two multiplication unit 3540 corresponds to a shift calculation in fixed-point representation.

[0229] The power-of-two multiplication unit 3540 calculates the addition multiplier stored in the connected storage circuit as [b k-1 ,...,b q ], a power-of-two multiplication operation is performed on the value S of the upper bits corresponding to [0..1], using -S as the exponent, that is, D*2^-S. Here, p=2^q, and in the power-of-two multiplication operation unit 3540, the word length of the exponent part of the floating-point representation of the input D is expanded to a size that can express the exponent of the minimum value of -S, in addition to the word length of the exponent part in the storage circuit, that is, -(1+2^(bw(m i )-q)+2^(bw(n i If the exponent of bw(m)-q) is expanded to a representable size, this operation can be implemented using only an integer subtractor for the exponent part of the floating-point representation, and the operation result will not be a denormalized number. i ), bw(n i ) are m i , n i Let the value represent the word length of

[0230] (Floating point adder / subtractor 3560) Similar to the adder-subtractor 560, the floating-point adder-subtractor 3560 repeatedly adds or subtracts the input from the power-of-two multiplication unit 3540 to y held in the accumulator 570 based on the input from the XOR circuit 550. If the input from the XOR circuit 550 is 0, addition is performed, and if it is 1, subtraction is performed.

[0231] For example, if the values ​​stored in the memory circuit group 530, the power-of-two multiplication unit 3540, the floating-point adder / subtracter 3560, and the accumulator 570 are expressed in floating-point notation conforming to IEEE 754, then p=16, m i , n iAssuming that the word length of each of these is 8 bits, the maximum value of S is 32 bits, and the exponent part of the floating-point in the power-of-two multiplication unit 3540 only needs to be 7 bits (since the bias is 63, the range of 2^63 to 2^-62 can be expressed in normalized numbers), and the word length of the addition / subtraction multiplier stored in the memory circuit group 530 can be, for example, 19 bits for the mantissa and 1 bit for the exponent, assuming 6 significant digits, and the word length of the floating-point adder / subtractor 3560 and accumulator 570 is, for example, 19 bits for the mantissa and 7 bits for the exponent, without further extension from the word length of the exponent part determined from the maximum value of S, assuming a maximum number of additions of 255.

[0232] 6.3 Expansion to quantization methods As described above, according to this embodiment, since a value in floating-point representation is output as a result of the multiply-and-accumulate operation, it is also desirable to be able to requantize this value at low cost. Quantization from a radix-2 floating-point representation can be performed as follows.

[0233] First, the floating-point representation x i is normalized so that its absolute value is equal to or less than 1.0. This normalization may be the same as in the base technique.

[0234] Next, the numerator of the exponent of the quantized value is m i , the predetermined divisor of the denominator is p, and m i Let bw(m i ), p=2^q, then input |x i At least 2^(-2^(bw(m as a floating point number with |<=1 i A floating-point representation with an exponent word length that allows the normalized number q)-q) to be expressed as a normalized number. This allows quantization to be performed as follows:

[0235] x i ≠0 and exponent is -2^(bw(m i )-q) above conditions are met L=-exponent (base 2 exponent) d = mantissa (treated as fixed-point notation with the MSB being 0.5 digits) As in the base technique, r is the smallest r that satisfies d≧2^-((r+1 / 2) / p). min Find m i =p(L-1)+r min Quantization is performed as follows. Inputs that meet this condition are limited to floating-point numbers of normalized numbers, so if a radix-2 floating-point representation is used, it is possible to omit the "configuration of counting the number of consecutive 0 bits L from the msb of c," which was necessary in the base technology.

[0236] On the other hand, if the above condition is not satisfied, that is, x i =0 or exponent is -2^(bw(m i If the exponent is less than -2^(bw(m )-q) (including denormalized numbers), it is replaced with a quantization code that represents 0. i A value less than q−q) can be treated as 0 because it is less than the minimum value that can be expressed by the quantized value.

[0237] For example, after quantization, m i If the word length is 8 bits and q=4, the input floating point only needs to be able to express exponents up to -2^(8-4)=-16 as normalized numbers, so if a floating point representation conforming to IEEE754 is used, the exponent part only needs to be 6 bits. In other words, the bias needs to be 31 and the range 2^31 to 2^-30 needs to be able to be expressed as normalized numbers.

[0238] Also, for example, if the input is expressed as a floating-point number conforming to IEEE754, in other words, the exponent part exp is expressed in biased form and the mantissa part frac is expressed in a form in which the MSB 1 is omitted, then x i ≠0 and exponent is -2^(bw(m i )-q) or more x i can be calculated as follows: L-1=(Ebias-1)-exp (where Ebias is the exponent bias value) d={1,frac} (where {,} is the bitwise concatenation operator)

[0239] 6.4 Examples of quantization circuits Next, a quantization circuit for implementing the above-mentioned quantization method will be described. Fig. 35 is a circuit diagram showing a schematic configuration example of a quantization circuit according to the third embodiment.

[0240] As shown in FIG. 35, the quantization circuit according to this embodiment includes an integer subtractor 3210, a shift calculator 3220, a memory circuit group 3230, a comparator group 3240, a priority encoder 3250, an integer adder 3260, a comparator 3270, and a selector 3280.

[0241] (Integer Subtractor 3210) The integer subtractor 3210 performs the calculation (L-1)=(Ebias-1)-exp using the exponent part exp of the input floating-point representation conforming to IEEE754.

[0242] (Shift calculator 3220) The shift calculator 3220 calculates p(L-1) by multiplying the value of (L-1) calculated by the integer subtractor 3210 by p. Here, since p=2^q, this multiplication can be realized by a q-bit left shift operation.

[0243] (Memory circuit group 3230) The memory circuit group 3230 includes p memory circuits corresponding to 2^-((r+1 / 2) / p), r∈{0,...,p-1}.

[0244] Each memory circuit included in the memory circuit group 3230 may be a read-only circuit that holds a value as a constant, or may be a rewritable register. When storing a value as a constant in a read-only circuit, the circuit configuration is simplified together with the comparator group 3240 and the priority encoder 3250 described later, and power consumption can be reduced.

[0245] (Comparator group 3240) The comparator group 3240 compares the p values ​​output from the memory circuit group with d={1,frac} generated from the mantissa of the input floating-point representation, and outputs 1 if d is equal or greater, and 0 if not.

[0246] (Priority Encoder 3250) Priority encoder 3250 outputs a value in the range of 0 to p-1 according to the position where a 1 is input among p inputs. If there are multiple inputs of 1, the position with the lower number is given priority. If all inputs are 0, p is output. Table 10 shows the operation of priority encoder 3250 in the form of a truth table. [Table 10]

[0247] The output of this priority encoder is min Then, the memory circuit group 3230, the comparator group 3240, and the priority encoder 3250 select r, which is the smallest r such that d≧2^-((r+1 / 2) / p). min If the minimum r is not found, r min =p.

[0248] (Integer adder 3260) The integer adder 3260 receives the p(L-1) value input from the shift calculator 3220 and the r min Add p(L-1)+r min get.

[0249] (Comparator 3270) The comparator 3270 compares the exponent part exp of the input IEEE754-compliant floating-point representation with Ebias-2^(bw(m i )-q), and compare exp with Ebias-2^(bw(m i )-q) is equal to or greater than exp, output 1, otherwise output 0. This makes x i ≠0 and exponent is -2^(bw(m i By using IEEE754-compliant floating-point representation for the input, it is possible to make judgments, including whether the input is 0, simply by comparing the exponent part exp.

[0250] (Selector 3280) The selector 3280 selects p(L−1)+r output from the integer adder 3260 based on the output of the comparator 3270. min , or the code representing 0 is m i The output is as follows:

[0251] 6.5 Actions and Effects As described above, according to this embodiment, it is possible to obtain the same effect as the base technology with a shorter word length, in other words, with a smaller circuit scale and power consumption.

[0252] Furthermore, when multiple arithmetic units according to this embodiment are installed, more arithmetic units can be installed with the same resources (circuit size, power), and it is also possible to improve the computing performance per resource.

[0253] The other configurations, operations, and effects may be similar to those of the base technology or embodiments described above, and therefore detailed description thereof will be omitted here.

[0254] 6.6 Variations The configuration according to the above-described third embodiment can also be modified as follows.

[0255] 6.6.1 First variant Since the range of values ​​stored in the memory circuit group 3230 of the multiply-accumulate circuit is limited to a range greater than 0.5 and less than or equal to 1.0, the exponent of D*2^-S is 0 or a negative value. Therefore, when an exponent bias conforming to IEEE754 is adopted, the MSB of the exponent is fixed to a value of 0 and can be omitted. For example, when p=16 (q=4), m i , n i If the word length is 8 bits, the exponent range of D*2^-S is 2^0 to 2^-33, so only the lower 6 bits of the 7-bit exponent (bias is 63) are used. In other words, the range of 2^0 to 2^-62 can be expressed. In this case, the omitted MSB can be extended and passed to the downstream floating-point adder / subtractor 3560.

[0256] 6.6.2 Second variant Furthermore, since the range of values ​​stored in the memory circuit group 3230 of the multiply-and-accumulate circuit is limited to a range greater than 0.5 and less than or equal to 1.0, the maximum positive value of the exponent range is determined by the number of additions made by the accumulator 570, and the maximum negative value is determined by the maximum value of S. Since these may not be symmetrical, the exponent bias in the integer adder 510 and accumulator 570 can be set to a value shifted from 2^(word length of exponent-1)-1 to reduce the bits of the exponent. For example, when p=16 (q=4), m i , n i If the word length is 8 bits, the number of significant digits is 6, and the number of accumulator additions is a maximum of 255, the range of the exponent is 2^-33 to 2^7, so if the bias is set to 42, for example, the exponent part can be 6 bits. In this example, 2^-41 to 2^20 can be expressed.

[0257] 6.6.3 Third variant Furthermore, the maximum negative value of the exponent part of the multiply-and-accumulate circuit may be made smaller than the maximum value of S. In that case, when the exponent part exceeds the representable range as a result of subtraction, it is possible to handle denormalized numbers by shifting the mantissa part to the right. With this configuration, although it becomes necessary to add a comparator or shift circuit, it is possible to reduce the bit length of the exponent part.

[0258] 6.6.4 Fourth variant Furthermore, when the maximum negative value of the exponent part of the multiply-and-accumulate circuit is made smaller than the maximum value of S, if the exponent part exceeds the representable range as a result of subtraction, the exponent part may be set to zero. If the loss of precision due to this is negligible, it is possible to reduce the bit length of the exponent part.

[0259] 6.6.5 Fifth Variation Furthermore, the calculation of D*2^-S in the multiply-and-accumulate circuit may be realized by a floating-point calculator (a multiplier and an exponentiator).

[0260] 6.6.6 Sixth Variation Furthermore, the circuit configuration (the product-sum calculation circuit and / or the quantization circuit) according to the above-mentioned third embodiment may be implemented in part or in whole by a program.

[0261] 7. Fourth embodiment Next, the fourth embodiment will be described in detail below with reference to the drawings.

[0262] 7.1 Issues with the Base Technology As mentioned above, in the base technology, a new quantization method has been proposed with the aim of reducing the amount of product-sum calculations in deep neural networks (DNNs) and convolutional neural networks (CNNs).

[0263] Fig. 36 is a schematic diagram for explaining the operation of a general DNN or CNN. Note that Fig. 36 shows a three-layer convolutional neural network.

[0264] As shown in Figure 36, in the operation of a typical DNN or CNN, processes such as convolution by multiplication and accumulation, pooling, and activation are sequentially performed for each layer. In this case, there are situations where the value range and distribution of coefficients used in the calculations of each layer and variables appearing in the output of the layer differ from layer to layer. In addition, such characteristics are not limited to each layer, and may appear as a characteristic in which the distribution differs for each feature map.

[0265] Examples of input / output variables of each layer and coefficients used in convolution are shown in Figs. 37 to 43. Fig. 37 shows a coefficient w1 input to the first convolution layer in Fig. 36, Fig. 38 shows a coefficient w2 input to the second convolution layer in Fig. 36, and Fig. 39 shows a coefficient w3 input to the first convolution layer in Fig. 36. In addition, Fig. 40 shows an input (variable) x0 of the convolution neural network in Fig. 36, Fig. 41 shows an output (variable) x1 from the first layer in Fig. 36, Fig. 42 shows an output (variable) x2 from the second layer in Fig. 36, and Fig. 43 shows an output (variable) x3 from the third layer in Fig. 36.

[0266] As can be seen from Figures 37 to 43, the value ranges of both coefficients and variables differ for each layer. Specifically, for coefficients, as shown in Figures 37 to 39, w1 has a value range of approximately -5 to 4, w2 has a value range of approximately -0.15 to 0.15, and w3 has a value range of approximately -0.4 to 0.5. On the other hand, for variables, as shown in Figures 40 to 43, x0 has a value range of approximately -1 to 1, x1 has a value range of approximately 0 to 90, x2 has a value range of approximately 0 to 120, and x3 has a value range of approximately 0 to 20.

[0267] For the reasons mentioned above, rather than unnecessarily reducing the number of representation bits, it is better to set the necessary and sufficient quantization (=bit reduction) for each layer (or each feature map) so as not to affect the results of the DNN / CNN inference task. In that case, the base technology is considered to have the following issues:

[0268] -No consideration is given to the management of numerical formats and actual data. -The expression regarding the distinction of quantization settings (precision settings, dynamic range settings) is not taken into consideration. Therefore, it is not possible to set different quantization settings for each layer (or each feature map). -Numeric expressions with positive and negative signs and numeric expressions without positive and negative signs are not distinguished. All values ​​are expressed with positive and negative signs, and when trying to specify variables for a specific layer (or feature map) (for example, x1, x2, and x3 in Figures 41 to 43), the signs used are unnecessary. The representation of the value 0 (zero) is not taken into consideration. For this reason, the number 0 (zero) that appears in Figures 41 to 43 cannot be represented.

[0269] Therefore, in this embodiment, in order to solve the above problems, we propose numeric format information and a container that can express numeric values ​​using a power of 2 representation. Furthermore, this embodiment also proposes a byte stream format that can hold and separate multiple quantization settings.

[0270] 7.2 Examples of Number Format Information First, the numeric value format information will be described with a concrete example.

[0271] 7.2.1 sem format It is necessary to encode numeric data in a power-of-two representation with a flexible word length into a positive / negative floating-point representation. To distinguish between numeric representations with and without positive / negative signs, it is necessary to be able to specify settings for the presence or absence of a positive / negative sign. In addition, to distinguish between quantization settings, it is necessary to be able to specify settings related to precision and settings related to dynamic range independently.

[0272] Therefore, in this embodiment, a set of the following three elements is defined as the sem format.

[0273] Sign Information The 's' in the sem format indicates the number of bits allocated for the presence or absence of a positive or negative sign.

[0274] Exponent Bit Width The 'e' in the sem format indicates the number of allocated bits for the dynamic range.

[0275] ·Mantissa Bit Width The 'm' in sem format indicates the allocated number of bits of precision.

[0276] An example of a power of 2 to which (sem)=(1.4.3) (i.e., 1 bit sign, 4 bits dynamic range, 3 bits precision) is assigned is shown in the table in Figure 44. m The value corresponds to the p-value of the base technology.

[0277] Furthermore, it is necessary to consider the representation of the value 0 (zero) so that zero can be handled as a numerical representation. Therefore, in this embodiment, the value 0 is defined as when all bits of e and m are 1. By defining this location as the value 0, it is possible to ensure monotonically decreasing (when the value of the index consisting of the bit string formed by combining {e, m} increases within the same positive and negative sign, the represented numerical value decreases).

[0278] Note that the maximum value (maximum absolute value) of this numerical representation is 1.0, and all bits of e and m at that time are 0.

[0279] In the sem format, the sum of the respective bit allocation numbers s+e+m indicates the data word length (Numeric Data Bit Width).

[0280] 7.2.2 sBQ Format In the above-mentioned sem format, the sem values ​​must be added together to confirm the word length of the numerical value and take it out of the area, so calculations are required every time the format is switched in the arithmetic unit. Therefore, in this embodiment, in addition to the sem format, the sBQ format is defined, which is an extension of the sem format, by incorporating word length information into the numerical value format information itself so that it can be separated without additional calculations. Note that the handling of numerical values ​​indicated by the sBQ format is completely equivalent to that of the sem format. The elements of the sBQ format are shown below.

[0281] Sign Information The 's' in the sBQ format indicates the number of bits allocated for the presence or absence of a positive or negative sign. This is synonymous with s (Sign Information) in the sem format.

[0282] Numeric Data Bit Width The 'B' in the sBQ format indicates the word length of the Numeric Data. The exponent bit width (e) in the sem format can be derived as e = Numeric Data Bit Width - sQ.

[0283] Q The 'Q' in the sBQ format indicates the allocated number of bits of precision. This is the same as m (Mantissa Bit Width) in the sem format.

[0284] 7.3 Management of Actual Data: Relationship between Containers and Numeric Format Information In this embodiment, the sem format and the sBQ format are referred to as Numeric Format Information. A container (Numeric Data Container) that stores actual data is expressed as shown in FIG.

[0285] 7.4 Byte Streams To use multiple values ​​shown in sem or sBQ format, the numeric format information corresponding to each value must be clear. If there is only one type, the word length does not change even if the values ​​are consecutive, and they can be extracted, but if there are multiple types, the change point must be identified, the numeric format information for each type must be confirmed, and the word length must be determined before it can be extracted. If numeric format information is added to all values, it is possible to determine the word length each time, but the data compressed by quantization becomes bloated.

[0286] Therefore, in this embodiment, we propose the following three types of byte streams that can be expressed in a state that can be separated at a certain cost without having to assign consecutive numeric format information and numeric value correspondences to all of them. Note that the byte stream structures illustrated below are merely examples and can be modified in various ways. -Byte stream with packets of basic and continuation structures -Byte stream with extended structure packets - Payload variable length stream with custom extended packet header structure

[0287] 7.4.1 Byte Stream with Basic Structure and Continuation Structure Packets A byte stream always starts with a basic structure aligned to a fixed byte size. This fixed size of data is called a packet. The header of a packet (hereafter called the packet header) contains the following elements:

[0288] ·Continue decision identifier (Continue) The continuation determination identifier (Continue) is an identifier indicating whether or not to reuse the previously specified numeric value format information.

[0289] Numeric Format Information The numeric format information is information indicating whether the numeric format information is in the sem format or the sBQ format.

[0290] Number of numerical data items (Number) The number of pieces of numeric data (Number) indicates the number of pieces of numeric data stored in the Payload.

[0291] Payload area The payload area indicates the area in which numerical data is stored. This payload area may not exist within the aligned byte size depending on other identifiers.

[0292] Numeric Data Numeric data is the body of the numeric value specified in the sem format or sBQ format. This numeric data is stored inside the payload, and the unused area is filled with padding. Note that the area filled with padding is not limited to the area immediately after the packet header. For example, the numeric data may be placed immediately after the packet header, and the remaining area may be filled with padding. This is also true for the byte stream that will be described later.

[0293] · Header skip identifier (Skip Header) The header skip identifier (Skip Header) is an identifier for determining whether or not the next aligned data is to be treated as a payload without a header.

[0294] Custom Identifier (Custom) The custom identifier (Custom) is an identifier that indicates whether the packet header is treated as a custom format. When the custom identifier (Custom) is confirmed as a valid value, the interpretation method of the packet is switched according to the value.

[0295] Figures 46 and 47 are diagrams showing two basic structure examples that can be realized by the Basic Structure. Specifically, Figure 46 shows a Basic Structure in which the continuation judgment identifier is set to "not continue", and Figure 47 shows a Continue Structure in which the continuation judgment identifier is set to "continue".

[0296] As shown in Fig. 46, in the Basic Structure, if the continuation judgment identifier is set to "do not continue" and the header skip identifier is set to "do not skip," the numerical value specified by the numerical format information is stored in the remaining payload area (Payload) for the amount indicated by the number of numerical data. Although the number of numerical data that can be stored in this packet itself is small, the packet header of the continuation structure is useful for maintaining the same format as subsequent consecutive numerical values.

[0297] As shown in Figure 47, in the packet header of a continue structure where the continuation judgment identifier is set to "continue", it is possible to continue storing numerical data in the payload until the subsequent alignment by simply entering the number of numerical data items.

[0298] When switching formats, it is possible to switch to a different format by specifying the continuation judgment identifier as "do not continue" and inserting a packet with a basic structure. This makes it possible to separate numerical data by processing it in units of a fixed byte size.

[0299] With the above structure, correspondence is possible without parsing a complex byte stream, without allocating a temporary storage area larger than the alignment size, and without adding numeric format information to all numeric values.

[0300] 7.4.2 Byte Stream in Extended Structure Packets In a byte stream of packets of an Extended Structure, if the continuation judgment identifier in the packet header of the basic structure is set to "do not continue" and the header skip identifier is set to "skip", the following two elements are treated as extended information, and the entire packet up to the byte size of the next alignment unit is treated as the payload area.

[0301] ·Payload Recursive Number Payload Recursive Number indicates how many times the payload of the alignment unit is repeated when the next alignment unit is used as the payload. Since a packet including the packet header is written again after the byte size of the alignment unit of the number specified here, the format can be switched at this point.

[0302] ·Reserved area (Reserved) The Reserved area (Reserved) is a spare area.

[0303] The structures of such an extended structure packet and a packet aligned with only the payload are shown in Figures 48 and 49. Figure 48 shows the structure of an extended structure packet, and Figure 49 shows the structure of a packet aligned with only the payload. A packet with only the payload and no header, as shown in Figure 49, is useful in cases where the byte size of the entire payload is divisible by the word length of the numeric data, or where a continuation structure would leave a lot of surplus space.

[0304] By using the above structure, as with the Basic Structure, it is possible to store numeric data without having to parse a complex byte stream, without having to allocate a temporary storage area larger than the alignment size, and without having to assign numeric format information to all numeric values.

[0305] 7.4.3 Payload variable length stream with custom extended packet header (Custom Structure) In a payload variable-length stream with a packet header of a custom extended structure, similarly to a packet header of an extended structure, if the continuation judgment identifier is specified as "do not continue", the header skip identifier is specified as "skip", and the custom identifier is specified as "valid", it is permitted to reinterpret part of the packet header defined in the basic structure, and only the positions and meanings of the following three types are treated equivalently to the packet header of the basic structure.

[0306] ·Continue decision identifier (Continue) · Header skip identifier (Skip Header) Custom Identifier (Custom)

[0307] In addition to the above, the following information is added to the Custom Structure:

[0308] Version number The version number is a number that indicates the type of custom extension structure. The number 0 holds the following four elements of information as a payload size extension.

[0309] Payload Size Payload size indicates the size of the payload following the packet header. In the case of a custom extension structure, it is permitted that the size is not the same as the byte size of the packet header indicated in the previous structure.

[0310] Numeric Format Information The numeric format information may be the same as the numeric format information in the basic structure.

[0311] Number of numerical data items (Number) The number of pieces of numerical data (Number) may be equal to the number of pieces of numerical data (Number) in the basic structure (Basic Structure).

[0312] Payload Recursive Number The payload recursive number may be the same as the payload recursive number in the extended structure.

[0313] Examples of the header and payload of this custom extension structure are shown in Figures 50 and 51. Figure 50 shows an example of the header of the custom extension structure, and Figure 51 shows an example of the payload of the custom extension structure.

[0314] In the Custom Structure, unlike the Basic Structure and Extended Structure described above, the parsing process of the byte stream is more complex and the temporary storage area required before the payload is separated must be increased to the size indicated by the payload size, but it is possible to store more numerical values ​​in the payload than with the Extended Structure.

[0315] As an advanced example, this custom extension structure (Custom Structure) leaves room for storing information other than numbers in the payload section by changing the version number, making it possible to embed additional information such as numerical calculation methods in the byte stream.

[0316] 7.5 Example of a byte stream implementation Next, specific implementation examples of the three types of byte streams exemplified above will be described in detail below with reference to the drawings. Note that in the following description, an implementation example in the sBQ format will be shown.

[0317] 7.5.1 Example of a byte stream implementation of Basic Structure and Continuation Structure Figures 52 and 53 are diagrams showing an example of a byte stream implementation of the Basic Structure. Figure 52 shows a packet of the Basic Structure, and Figure 53 shows a packet of the Continue Structure.

[0318] As shown in Figure 52, a packet of the Basic Structure is composed of, for example, from the MSB (Most Significant Bit) on the left, a 1-bit continuation decision identifier (labeled as 'Continue' in the figure), a 2-bit number of numerical data items (labeled as 'Number' in the figure), a 1-bit header skip identifier (labeled as 'SkipHeader' in the figure), a 1-bit custom identifier (labeled as 'Custom' in the figure), a 1-bit s (Sign Information) (labeled as 'sign' in the figure), a 4-bit B (Numeric Data Bit Width) (labeled as 'B' in the figure), a 3-bit Q (labeled as 'Q' in the figure), and a 19-bit payload area (labeled as 'Payload' in the figure).

[0319] The 1-bit continuation judgment identifier (Continue) indicates, for example, that the packet contains a new format header when its value is '1', and indicates that the format header of the previous packet is to be used when its value is '0'.

[0320] For example, when the 2-bit numeric data number (Number) has a value of '01', it indicates that one numeric data is stored in the payload area (Payload) of the packet, when it is '10' it indicates that two numeric data are stored, when it is '11' it indicates that three numeric data are stored, and when it is '00' it indicates that no numeric data is stored in the packet.

[0321] The 1-bit header skip identifier (Skip Header) indicates, for example, that when its value is '1', the next aligned data is treated as a payload area (Payload) without a header, and when its value is '0', it indicates that the next aligned data is treated as a new packet that does not continue.

[0322] The 1-bit custom identifier (Custom) indicates that the packet is to be treated as a normal format packet when its value is '0', and indicates that the packet is to be treated as a custom format packet when its value is '1'. In other words, when the custom identifier (Custom) is '1', the interpretation method of the packet is switched.

[0323] On the other hand, as shown in Figure 53, a packet of a continue structure consists of, starting from the MSB on the left, a 1-bit continuation judgment identifier (represented as 'Continue' in the figure), a 2-bit number of numerical data items (represented as 'Number' in the figure), and a 29-bit payload area (represented as 'Payload' in the figure).

[0324] The continuation judgment identifier (Continue), the number of pieces of numerical data (Number), and the payload area (Payload) may be the same as those described with reference to FIG.

[0325] 7.5.2 Example of an Extended Structure Byte Stream Implementation Figures 54 and 55 are diagrams showing an example of byte stream implementation of an Extended Structure. Figure 54 shows a packet of an Extended Structure, and Figure 55 shows a packet with only a continuing payload area.

[0326] As shown in Fig. 54, an Extended Structure packet has a structure similar to that of a Basic Structure packet shown in Fig. 52, in which a 19-bit payload area is replaced with an 11-bit Reserved area (represented as 'Reserved' in the figure) and an 8-bit Payload recursive number (represented as 'Payload Recursive Number' in the figure). If the Reserved area is not used, it may be filled with, for example, zero padding.

[0327] On the other hand, as shown in FIG. 55, a packet with only a payload area (Payload) is composed of, for example, a 32-bit payload area (denoted as 'Payload' in the figure).

[0328] 7.5.3 Example of a Custom Structure Byte Stream Implementation Figures 56 and 57 are diagrams showing an example of a byte stream implementation of a custom structure. Figure 56 shows a packet of a custom structure, and (a) to (c) of Figure 57 show a packet with only a continuing payload area.

[0329] As shown in Fig. 56, a packet of a custom structure (Custom Structure) has a structure similar to that of a packet of a basic structure (Basic Structure) shown in Fig. 52, except that the number of pieces of numerical data (indicated as 'Number' in the figure) is moved next to the sBQ format section, and instead, a version number (indicated as 'Version' in the figure) is placed between the continuation judgment identifier (Continue) and the header skip identifier (SkipHeader), and further, a payload size (indicated as 'PayloadSize' in the figure) is added between the custom identifier (Custom) and the sBQ format section. Also, the 19-bit payload area (Payload) is replaced with the above-mentioned 6-bit number of pieces of numerical data ('Number') and 8-bit number of Payload recursives (indicated as 'Payload Recursive Number' in the figure).

[0330] On the other hand, for a packet with a custom structure, a packet with only the payload area continues for the size specified by the payload size as shown in Fig. 57. This forms a payload variable-length stream with a packet header with a custom extension structure.

[0331] The other configurations, operations, and effects may be similar to those of the base technology or embodiments described above, and therefore detailed description thereof will be omitted here.

[0332] 7.6 Example of a byte stream processing system Fig. 58 is a block diagram showing an example of a schematic configuration of a system for processing a byte stream according to this embodiment. In the drawing, solid arrows indicate data flows and control command flows in a basic structure, a continuation structure, an extended structure, and a custom structure, and dashed arrows indicate data flows and control command flows in an extended example that can be handled by extending the custom structure. Also, dashed and dotted arrows indicate instructions and commands from outside the system, and dashed and dotted arrows indicate instructions and commands from outside the system in an extended example that can be handled by extending the custom structure.

[0333] As shown in FIG. 58, the processing system 4000 includes a power representation conversion unit 4003, a storage and conversion unit 4004, an input feature map memory 4005, a coefficient memory 4006, an analysis unit 4007, an extraction unit 4008, a power representation conversion unit 4009, a calculation control unit 4010, a calculator array 4011, a power representation conversion unit 4013, a storage and conversion unit 4014, and an output feature map memory 4015.

[0334] (Power expression converter 4003) The power expression converter 4003 has a configuration corresponding to, for example, the power expression converters 2001 and 2102 in the above-described embodiment, and converts a value input via the sensor I / F 4001 into a power expression of 2 using a coefficient 4002 input from the multiplier 2002 / 2104, etc. Note that the sensor I / F 4001 may be applied with various sensors that obtain measurement values ​​that can be converted into numerical data, such as an image sensor, a ToF (Time of Flight) sensor, a microphone, and various sensors that measure weather information such as air pressure, temperature, humidity, and wind speed.

[0335] (Storage and conversion unit 4004) The storage / conversion unit 4004 is configured to store values ​​in containers and convert them into byte streams. The storage / conversion unit 4004 constructs a byte stream that stores the numerical expression and the arithmetic control command input from the sensor I / F 4001 and the power expression conversion unit 4003 in accordance with the arithmetic control command input from the upper device and the instruction of the storage / conversion method. The byte stream to be constructed includes the above-mentioned basic structure, continuation structure, extended structure, and custom structure byte streams. The arithmetic control command may also include, for example, a specification of a value table to be used by the multiplication / accumulation circuit 4012 of the arithmetic unit array 4011 described later.

[0336] (Input feature map memory 4005) The input feature map memory 4005 has a configuration corresponding to the variable buffer 2003 in the above-described embodiment, and stores the byte stream constructed by the storage / conversion unit 4004. Therefore, the input feature map memory 4005 stores variables expressed as powers of two.

[0337] (Coefficient memory 4006) The coefficient memory 4006 corresponds to the coefficient memory 2004 in the above-described embodiment, and stores the coefficients of the power-of-two representation input from the storage / conversion unit 4004 .

[0338] (Analysis Department 4007) The analysis unit 4007 parses (analyzes) the byte stream read from the input feature map memory 4005, and separates the payload area from other information.

[0339] (Extraction part 4008) The extraction unit 4008 extracts a combination of actual data in a container. Specifically, it extracts numerical format information such as sem format or sBQ format from the container, and numerical expression (Numeric Data) inside the container.

[0340] Furthermore, when a predetermined version number (Version) is specified in the byte stream of the custom structure (Custom Structure), the extraction unit 4008 extracts numerical values ​​and control commands other than the power expressions from the byte stream. For example, the extraction unit 4008 extracts a numerical calculation method (calculation control command), a type of numerical value (such as a floating point type), actual data of the numerical value, etc.

[0341] (Power expression converter 4009) The power expression converter 4009 corresponds to the power expression converters 2001 and 2102 in the above-described embodiments, and converts the numerical value of the other numerical expression input from the extraction unit 4008 into a numerical value of the power expression.

[0342] (Arithmetic and control unit 4010) The arithmetic control unit 4010 outputs a control command to the arithmetic unit array 4011 based on an arithmetic control command embedded in a byte stream of a custom structure of a predetermined version number.

[0343] (Computer array 4011) The arithmetic unit array 4011 includes, for example, the product-sum calculation circuit 4012 in the above-described embodiment, and executes a predetermined calculation process on input numerical values ​​of power expressions and numerical values ​​of other numerical expressions.

[0344] (Power expression converter 4013) The power expression converter 4013 has a configuration corresponding to the power expression converters 2001 and 2102 in the above-described embodiments, and converts the numerical value of the power expression input from the arithmetic unit array 4011 .

[0345] (Storage and conversion unit 4014) The storage / conversion unit 4014, like the storage / conversion unit 4004, is configured to store values ​​into containers and convert byte streams, and constructs a byte stream storing a numerical expression and an arithmetic control command input from the power expression conversion unit 4013 or the arithmetic unit array 4011 in accordance with an arithmetic control command and a storage / conversion method instruction input from a higher-level device. The byte streams constructed include byte streams of the above-mentioned basic structure, continuation structure, extended structure, and custom structure.

[0346] (Output feature map memory 4015) The output feature map memory 4015 has a configuration corresponding to the calculation result buffer 2005 in the above-described embodiment, and stores the byte stream constructed by the storage / conversion unit 4014. The output feature map stored in the output feature map memory 4015 can be re-input into the analysis unit 4007 as an input feature map.

[0347] It should be noted that each unit shown in Fig. 58 can be realized in part or in whole by hardware or software. In addition, in the configuration shown in Fig. 58, the output of each unit may be buffered as appropriate.

[0348] 7.7 Actions and Effects As described above, according to this embodiment, the container and numeric format information make it possible to adopt different numeric representation settings for each layer and / or each map in application to CNN / DNN.

[0349] For example, it will be possible to adopt a numerical representation that allows independent setting of the positive / negative sign, precision, dynamic range, etc. for power-of-two representations oriented toward DNN / CNN.

[0350] It is also possible to adopt a combination of containers and numeric value format information for different units of numeric value expression settings (layers, maps, etc.).

[0351] Furthermore, by incorporating word length information into the format of the numerical representation, it is possible to omit calculations for obtaining word lengths, thereby reducing computation costs.

[0352] Furthermore, the use of byte stream formats makes it possible to adopt different numerical representation settings at finer units than per layer and / or map of a DNN, for example, by implementing byte stream formats that efficiently switch numerical representation settings at finer units such as per line or pixel.

[0353] The other configurations, operations, and effects may be similar to those of the base technology or embodiments described above, and therefore detailed description thereof will be omitted here.

[0354] 8. Application examples to communication technology Next, the application of the quantization method according to the present disclosure to other fields will be described. In the above description, the quantization method according to the present disclosure is applied to the inner product calculation related to the forward propagation of a neural network. However, the quantization method according to the present disclosure is not limited to the above example, and can be applied to various technologies that perform inner product calculations.

[0355] For example, the quantization method according to the present disclosure may be applied to a convolution operation in a bandpass filter used in the field of communication technology. Simulation results when the quantization method according to the present disclosure is applied to a bandpass filter will be described below.

[0356] 59 is a diagram showing a simulation result of frequency characteristics (gain characteristics) when the quantization method according to the present disclosure is applied to a bandpass filter. Here, quantization was performed on coefficients (63 taps, rolloff 0.5) in an RRC (Root-Raised Cosine) filter.

[0357] For quantization, 32 values ​​(0 to 31) were used for p = 2, 3, and 4. In the figure, this is shown as DNN(p,32). For comparison, the simulation results when using floating point (Float) and integer (Linear) are also shown.

[0358] Here, referring to FIG. 59, it can be seen that even when the quantization method according to the present disclosure is applied, the flatness characteristic in the bandpass is not deteriorated. On the other hand, when focusing on the sideband, even in the case of DNN(2,32), it can be seen that attenuation of about -25 dB is possible, and the larger p is made, the greater the attenuation effect becomes. It is expected that the effect of quantization will be further reduced by combining it with, for example, an LPF (Low Pass Filter).

[0359] Also, Fig. 60 is a diagram showing a simulation result of the phase characteristic when the quantization method according to the present disclosure is applied to a bandpass filter. Referring to Fig. 60, it can be seen that even when the quantization method according to the present disclosure is applied, the phase rotation in the passband, that is, the deterioration of the phase characteristic is not confirmed. In this way, the quantization method according to the present disclosure does not significantly deteriorate the frequency characteristic of the bandpass filter, and therefore can be said to be fully applicable in the field of communication technology.

[0360] In addition, in order to further investigate the effect of the quantization technique according to the present disclosure, an evaluation was performed using BER (Bit Error Rate). Fig. 61 is a block diagram used in the BER evaluation according to the present disclosure.

[0361] As shown in Figure 61, in this evaluation, floating point, integer, and DNN (p, 32) were applied to the ADC (Analog to Digital Converter) and RRC filter before demodulation, and the BER was measured. In addition, BPSK, QPSK, and 16QAM were used as the modulation and demodulation methods, respectively.

[0362] Fig. 62 is a diagram showing the BER evaluation results when BPSK is used as the modulation method. Fig. 63 is a diagram showing an enlarged view of the data of SNR 7 to 9 dB in Fig. 62. With reference to Fig. 62 and Fig. 63, when BPSK is used as the modulation method, no degradation of the BER is observed at all when p=4, and even when p=2 or 3, it is found that there is no significant impact on the BER.

[0363] Fig. 64 is a diagram showing the BER evaluation results when QPSK is used as the modulation method. Fig. 65 is a diagram showing an enlarged view of the data of SNR 10 to 12 dB in Fig. 64. With reference to Fig. 64 and Fig. 65, it can be seen that, similar to the case of using BPSK as the modulation method, quantization with p=2 or 3 does not have a large effect on the BER.

[0364] Fig. 66 is a diagram showing BER evaluation results when 16QAM is used as the modulation method. Fig. 67 is a diagram showing an enlarged view of the data of SNR 16 to 18 dB in Fig. 66. It can be seen from Fig. 66 and Fig. 67 that, when 16QAM is used as the modulation method, an increase in BER is observed with quantization by p=2 or 3, but no deterioration in BER is observed with quantization by p=4.

[0365] As described above, when BPSK or QPSK is used as the modulation scheme, the quantization method according to the present disclosure is effective regardless of the value of p. Also, when 16QAM is used as the modulation scheme, it is considered that there is no effect on the BER if p≧4.

[0366] In this way, the quantization technique according to the present disclosure is also effective in the field of communications technology, and can achieve both maintaining performance and reducing processing load.

[0367] 9. Hardware configuration example Next, a hardware configuration example of the information processing device 10 according to an embodiment of the present disclosure will be described. FIG. 68 is a block diagram showing a hardware configuration example of the information processing device 10 according to an embodiment of the present disclosure. Referring to FIG. 68, the information processing device 10 has, for example, a CPU 871, a ROM 872, a RAM 873, a host bus 874, a bridge 875, an external bus 876, an interface 877, an input device 878, an output device 879, a storage 880, a drive 881, a connection port 882, and a communication device 883. Note that the hardware configuration shown here is an example, and some of the components may be omitted. In addition, the information processing device 10 may further include components other than those shown here.

[0368] (CPU871) The CPU 871 functions, for example, as an arithmetic processing device or control device, and controls all or part of the operation of each component based on various programs recorded in the ROM 872, the RAM 873, the storage 880, or the removable recording medium 901.

[0369] (ROM 872, RAM 873) The ROM 872 is a means for storing programs to be read into the CPU 871, data to be used for calculations, etc. The RAM 873 temporarily or permanently stores, for example, the programs to be read into the CPU 871, and various parameters that change appropriately when the programs are executed.

[0370] (host bus 874, bridge 875, external bus 876, interface 877) The CPU 871, ROM 872, and RAM 873 are connected to one another via, for example, a host bus 874 capable of high-speed data transmission. On the other hand, the host bus 874 is connected to an external bus 876 having a relatively low data transmission speed via, for example, a bridge 875. In addition, the external bus 876 is connected to various components via an interface 877.

[0371] (Input Device 878) The input device 878 may be, for example, a mouse, a keyboard, a touch panel, a button, a switch, a lever, etc. Furthermore, a remote controller capable of transmitting a control signal using infrared rays or other radio waves may be used as the input device 878. The input device 878 may also include an audio input device such as a microphone.

[0372] (Output Device 879) The output device 879 is a device capable of visually or audibly notifying the user of acquired information, such as a display device such as a CRT (Cathode Ray Tube), LCD, or organic EL, an audio output device such as a speaker or a headphone, a printer, a mobile phone, a facsimile, etc. The output device 879 according to the present disclosure also includes various vibration devices capable of outputting tactile stimuli.

[0373] (Storage 880) The storage 880 is a device for storing various types of data. For example, a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, or a magneto-optical storage device may be used as the storage 880.

[0374] (Drive 881) The drive 881 is a device that reads information recorded on a removable recording medium 901 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, or writes information to the removable recording medium 901.

[0375] (Removable recording media 901) The removable recording medium 901 is, for example, a DVD medium, a Blu-ray (registered trademark) medium, an HD DVD medium, various semiconductor storage media, etc. Of course, the removable recording medium 901 may be, for example, an IC card equipped with a non-contact type IC chip, an electronic device, etc.

[0376] (Connection port 882) The connection port 882 is a port for connecting an external device 902, such as a Universal Serial Bus (USB) port, an IEEE 1394 port, a Small Computer System Interface (SCSI), an RS-232C port, or an optical audio terminal.

[0377] (External connection device 902) The external connection device 902 is, for example, a printer, a portable music player, a digital camera, a digital video camera, or an IC recorder.

[0378] (Communication Device 883) The communication device 883 is a communication device for connecting to a network, such as a communication card for wired or wireless LAN, Bluetooth (registered trademark), or WUSB (Wireless USB), a router for optical communications, a router for ADSL (Asymmetric Digital Subscriber Line), or a modem for various types of communications.

[0379] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present disclosure. In addition, components of different embodiments and modifications may be appropriately combined.

[0380] Furthermore, the effects of each embodiment described in this specification are merely examples and are not limiting, and other effects may also be provided.

[0381] The present technology can also be configured as follows. (1) a multiply-and-accumulate circuit for performing a multiply-and-accumulate operation based on a plurality of input values ​​quantized by a power expression and a plurality of weighting coefficients quantized by a power expression corresponding to the input values, the exponent of each of said input values ​​is expressed as a fraction having a predetermined divisor as its denominator; the exponent of each of the weighting coefficients is expressed as a fraction having the divisor as a denominator; the product-sum operation circuit executes the product-sum operation using a plurality of addition multipliers based on a remainder when a dividend is obtained by dividing a value obtained by adding a numerator related to the exponent of each of the input values ​​and a numerator related to the exponent of each of the weighting coefficients, Each of the additive multipliers is a floating-point number whose exponent is base 2. Information processing device. (2) The information processing device according to (1), further comprising a storage unit for storing the plurality of addition multipliers. (3) The information processing device according to (2), further comprising an arithmetic unit that performs a power-of-two multiplication operation on the addition multiplier stored in the memory unit based on an integer value of a quotient obtained by the division. (4) The information processing device described in (3), wherein the word length of the exponent part of the floating-point number in the arithmetic unit is determined based on the word length of the numerator associated with the exponent of each of the input values, the word length of the numerator associated with the exponent of each of the weighting coefficients, and the predetermined divisor. (5) The information processing device according to (3) or (4), wherein the arithmetic unit performs addition and subtraction on an exponent part of a floating-point number having a base of 2. (6) The storage unit is a memory circuit group including a plurality of rewritable memory circuits; a memory for holding a plurality of first sum multipliers and a plurality of second sum multipliers different from the plurality of first sum multipliers; a selector that selectively writes one of the plurality of first sum multipliers and the plurality of second sum multipliers held in the memory into the group of memory circuits. The information processing device according to (2). (7) The storage unit is a first memory circuit group that holds a plurality of first addition multipliers; a second memory circuit group that stores a plurality of second sum multipliers different from the plurality of first sum multipliers; a selector that switches a storage circuit group connected to the multiply-and-accumulate circuit between the first storage circuit group and the second storage circuit group; Equipped The information processing device according to (2). (8) the first sum multipliers are values ​​expressed as powers of two; The plurality of second additive multipliers are linearly expressed values. The information processing device according to (6) or (7). (9) The information processing device according to (2), wherein the storage unit holds the plurality of addition multipliers and values ​​of the plurality of addition multipliers rounded to 0.5 according to a representation function of a power of two representation. (10) a parser for parsing the byte stream; an arithmetic unit array including a multiply-and-accumulate circuit that executes a multiply-and-accumulate operation based on a plurality of input values ​​quantized by a power expression and a plurality of weighting coefficients quantized by a power expression corresponding to the input values; an arithmetic control unit that controls the arithmetic unit array based on an analysis result by the analysis unit; Equipped with the arithmetic unit array further comprises a storage unit for storing a plurality of addition multipliers; The storage unit is a first memory circuit group that holds a plurality of first addition multipliers; a second memory circuit group that stores a plurality of second sum multipliers different from the plurality of first sum multipliers; a selector that switches a storage circuit group connected to the multiply-and-accumulate circuit between the first storage circuit group and the second storage circuit group; Equipped with the byte stream includes a designation of a memory circuit group to be used in the multiply-and-accumulate operation; The arithmetic control unit controls the selector based on the designation, the exponent of each of said input values ​​is expressed as a fraction having a predetermined divisor as its denominator; the exponent of each of the weighting coefficients is expressed as a fraction having the divisor as a denominator; the product-sum operation circuit executes the product-sum operation using a plurality of addition multipliers based on a remainder when a dividend is obtained by dividing a value obtained by adding a numerator related to the exponent of each of the input values ​​and a numerator related to the exponent of each of the weighting coefficients, Each of the additive multipliers is a floating-point number whose exponent is base 2. Information processing system. (11) an information processing method executed by an information processing system comprising: an analysis unit that analyzes a byte stream; an arithmetic unit array including a product-sum operation circuit that performs a product-sum operation based on a plurality of input values ​​quantized by a power expression and a plurality of weighting coefficients quantized by a power expression corresponding to the input values; and an operation control unit that controls the arithmetic unit array based on an analysis result by the analysis unit, the arithmetic unit array further comprising a memory unit that holds a plurality of addition multipliers, the memory unit comprising a first memory circuit group that holds a plurality of first addition multipliers, a second memory circuit group that holds a plurality of second addition multipliers different from the plurality of first addition multipliers, and a selector that switches the memory circuit group connected to the product-sum operation circuit between the first memory circuit group and the second memory circuit group, the product-sum operation circuit performing the product-sum operation using a plurality of addition multipliers based on a remainder when a dividend is used as a value obtained by adding a numerator related to an exponent of each of the input values ​​and a numerator related to the exponent of each of the weighting coefficients, the analysis unit identifies, from the byte stream, a designation of a memory circuit group to be used in the multiply-and-accumulate operation; the arithmetic control unit controls the selector based on the designation; The multiply-and-accumulate circuit executes the multiply-and-accumulate operation using the plurality of multipliers stored in a memory circuit group connected via the selector. Including, the exponent of each of said input values ​​is expressed as a fraction having a predetermined divisor as its denominator; the exponent of each of the weighting coefficients is expressed as a fraction having the divisor as a denominator; Each of the additive multipliers is a floating-point number whose exponent is base 2. Information processing methods. [Explanation of symbols]

[0382] 10. Information processing device 110 Input section 120 Arithmetic section 130 Storage section 140 Output section 200, 300, 400, 500 Multiply-and-accumulate circuits 530, 530A, 530B memory circuit group 1530 Memory Tables 1530a and 1530b 1531, 1532 selector 2001, 2102 Power expression converter 2002, 2104 Multiplication section 2003 Variable Buffer 2004 Coefficient Memory 2005 Calculation result buffer 2100 Multiply-and-accumulate circuit 2101 Multiply-and-accumulate section 2103 Power Expression Table 2202, 2204 Power expression conversion table 2203 Power Expression Table 3210 Integer Subtractor 3220 Shift calculator 3230 Memory circuit group 3240 Comparator group 3250 Priority Encoder 3260 Integer Adder 3270 Comparator 3280 Selector 3540 Power of 2 multiplication calculator 3560 floating point adder / subtractor 4001 Sensor I / F 4002 coefficient 4003, 4009, 4013 Power expression converter 4004, 4014 Storage and conversion unit 4005 Input feature map memory 4006 Coefficient Memory 4007 Analysis Department 4008 Extraction part 4010 Calculation control unit 4011 Arithmetic Unit Array 4015 Output feature map memory

Claims

1. An analysis unit that analyzes a byte stream; an arithmetic unit array including a multiply-and-accumulate circuit that executes a multiply-and-accumulate operation based on a plurality of input values ​​quantized by a power expression and a plurality of weighting coefficients quantized by a power expression corresponding to the input values; an arithmetic control unit that controls the arithmetic unit array based on an analysis result by the analysis unit; Equipped with the arithmetic unit array further comprises a storage unit for storing a plurality of addition multipliers; The storage unit is a first memory circuit group that stores a plurality of first sum multipliers; a second memory circuit group that stores a plurality of second sum multipliers different from the plurality of first sum multipliers; a selector that switches a storage circuit group connected to the multiply-and-accumulate circuit between the first storage circuit group and the second storage circuit group; Equipped with the byte stream includes a designation of a memory circuit group to be used in the multiply-and-accumulate operation; The arithmetic control unit controls the selector based on the designation, the exponent of each of said input values ​​is expressed as a fraction having a predetermined divisor as its denominator; the exponent of each of the weighting coefficients is expressed as a fraction having the divisor as a denominator; the product-sum operation circuit executes the product-sum operation using a plurality of addition multipliers based on a remainder when a dividend is obtained by dividing a value obtained by adding a numerator related to the exponent of each of the input values ​​and a numerator related to the exponent of each of the weighting coefficients, Each of the additive multipliers is a floating-point number whose exponent is base 2. Information processing device.

2. a parser for parsing the byte stream; an arithmetic unit array including a multiply-and-accumulate circuit that executes a multiply-and-accumulate operation based on a plurality of input values ​​quantized by a power expression and a plurality of weighting coefficients quantized by a power expression corresponding to the input values; an arithmetic control unit that controls the arithmetic unit array based on an analysis result by the analysis unit; Equipped with the arithmetic unit array further comprises a storage unit for storing a plurality of addition multipliers; The storage unit is a first memory circuit group that stores a plurality of first sum multipliers; a second memory circuit group that stores a plurality of second sum multipliers different from the plurality of first sum multipliers; a selector that switches a storage circuit group connected to the multiply-and-accumulate circuit between the first storage circuit group and the second storage circuit group; Equipped with the byte stream includes a designation of a memory circuit group to be used in the multiply-and-accumulate operation; The arithmetic control unit controls the selector based on the designation, the exponent of each of said input values ​​is expressed as a fraction having a predetermined divisor as its denominator; the exponent of each of the weighting coefficients is expressed as a fraction having the divisor as a denominator; the product-sum operation circuit executes the product-sum operation using a plurality of addition multipliers based on a remainder when a dividend is obtained by dividing a value obtained by adding a numerator related to the exponent of each of the input values ​​and a numerator related to the exponent of each of the weighting coefficients, Each of the additive multipliers is a floating-point number whose exponent is base 2. Information processing system.

3. an information processing method executed by an information processing system comprising: an analysis unit that analyzes a byte stream; an arithmetic unit array including a product-sum operation circuit that performs a product-sum operation based on a plurality of input values ​​quantized by a power expression and a plurality of weighting coefficients quantized by a power expression corresponding to the input values; and an operation control unit that controls the arithmetic unit array based on an analysis result by the analysis unit, the arithmetic unit array further comprising a memory unit that holds a plurality of addition multipliers, the memory unit comprising a first memory circuit group that holds a plurality of first addition multipliers, a second memory circuit group that holds a plurality of second addition multipliers different from the plurality of first addition multipliers, and a selector that switches the memory circuit group connected to the product-sum operation circuit between the first memory circuit group and the second memory circuit group, the analysis unit identifies, from the byte stream, a designation of a memory circuit group to be used in the multiply-and-accumulate operation; the arithmetic control unit controls the selector based on the designation; The multiply-and-accumulate circuit executes the multiply-and-accumulate operation using the plurality of multipliers stored in a memory circuit group connected via the selector. Including, the exponent of each of said input values ​​is expressed as a fraction having a predetermined divisor as its denominator; the exponent of each of the weighting coefficients is expressed as a fraction having the divisor as a denominator; Each of the additive multipliers is a floating-point number whose exponent is base 2. Information processing methods.

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