Semiconductor device manufacturing method and exposure mask

Abstract

An etching-resistant material (20) is disposed on one surface (11) of a substrate (10), and the etching-resistant material is dry-etched and patterned using a photoresist (40). When patterning the photoresist (40), the sidewalls of the photoresist are given a tapered shape using a gray-tone mask (50) having a gray-tone portion (53). Then, by dry etching the etching-resistant material using the photoresist having the sidewall made into a tapered shape, the etching-resistant material becomes a tapered shape in which the sidewalls (21a–23a) are inclined relative to one surface. The taper angle θ1 can be made to be 0.2-60 degrees inclusive, with no fence remaining.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2022-048698 filed on March 24, 2022, the contents of which are incorporated herein by reference. [Technical field]

[0002] The present disclosure relates to a semiconductor device having a patterned difficult-to-etch material. Place Manufacturing method and exposure mask This is regarding. [Background technology]

[0003] When forming a semiconductor device using a material that is difficult to etch, such as nickel iron (NiFe), the material is patterned into a desired shape by dry etching. Specifically, a photoresist is placed on the material that is difficult to etch as a mask, and the photoresist is exposed and developed to form a pattern, and then anisotropic etching is performed using the photoresist as a mask to pattern the material.

[0004] A difficult-to-etch material is one that produces a reaction product with the process gas used in the etching process with a low vapor pressure, in other words, one that produces a reaction product with a high boiling point and is difficult to etch. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 09-118018 Summary of the Invention

[0006] However, if the sidewalls of the patterned photoresist are approximately perpendicular to the surface of the underlying material that is difficult to etch, a reaction product of etching called a fence remains on the sidewall of the photoresist after dry etching. Since corrosive gases such as chlorine (Cl) are used in dry etching of the material that is difficult to etch, if the fence remains after dry etching, it can cause corrosion. In addition, if the fence remains after removing the photoresist, it will protrude from the surface of the material that is difficult to etch, and the fence will break through the protective film formed thereon, affecting the coverage of the protective film. This poses a problem that high-quality semiconductor devices cannot be obtained. In order to prevent this, it is conceivable to make the sidewalls of the photoresist inclined with respect to the surface of the difficult-to-etch material, so that the surface side of the photoresist is narrower than the difficult-to-etch material side, forming a tapered shape. As a method for forming the sidewalls of the photoresist into a tapered shape, a thermal flow method can be used in which the photoresist is baked at a high temperature to form a tapered shape.

[0007] However, with the thermal flow method, it is difficult to control the taper shape with high precision, and the taper angle, i.e., the angle between the surface of the base and the sidewall of the photoresist, varies depending on the pattern density. Also, the taper angle becomes almost vertical at the corners of the layout, which raises the concern that fences may be generated in these parts. In particular, the thicker the difficult-to-etch material to be etched is, the more likely it is that fences will remain. The present disclosure relates to a semiconductor device in which a difficult-to-etch material is patterned with high quality while suppressing the formation of fences. Place Manufacturing method and an exposure mask applied thereto The purpose is to provide.

[0010] The present disclosure 1 The method for manufacturing a semiconductor device according to the present invention comprises the steps of: Preparing a substrate; Depositing a film of a difficult-to-etch material on one surface of a substrate; depositing a photoresist on the difficult-to-etch material; patterning the photoresist by exposure and development; After patterning the photoresist, dry etching the difficult-to-etch material using the photoresist as a mask to pattern the difficult-to-etch material; In the patterning of the photoresist, exposure is performed using a graytone mask having a solid pattern that blocks the exposure light, a non-patterned portion that transmits the exposure light without blocking it, and a graytone portion that transmits an intermediate amount of exposure light between the solid pattern and the non-patterned portion, and the graytone portion is used to expose a portion of the photoresist that corresponds to the sidewall of the difficult-to-etch material, thereby forming the sidewall of the photoresist into a tapered shape; In patterning the difficult-to-etch material, the difficult-to-etch material is dry-etched using a photoresist having a tapered sidewall, so that the sidewall of the difficult-to-etch material has a tapered angle of 0.20 degrees or more and 60 degrees or less with respect to the one surface. Furthermore, the substrate is prepared by preparing a semiconductor wafer (100) having an effective area (101) that is a semiconductor chip pattern area (321, 521) to be extracted as a semiconductor chip, and an invalid area (102) that is an area not used as a semiconductor chip at the outer edge of the effective area; In patterning the photoresist, an exposure mask is used in which the boundary between the effective area and the ineffective area is made a gray-tone portion (330), and the sidewalls of the photoresist placed in the ineffective area at the boundary are made tapered.

[0011] In this way, the difficult-to-etch material is patterned by dry etching using a gray-tone mask. Therefore, unlike the thermal flow method, the sidewalls of the photoresist can be precisely tapered, and the sidewalls of the difficult-to-etch material can be precisely tapered. This makes it possible to precisely prevent the fence from remaining.

[0012] The present disclosure 2 The aspect of the present invention is an exposure mask for patterning a photoresist (40) formed on a film of a difficult-to-etch material (20) formed on one surface (11) of a substrate (10) by exposure and development, The graytone mask (50) includes a solid pattern (51) that blocks exposure light, a non-patterned portion (52) that transmits the exposure light without blocking it, and a graytone portion (53) that transmits an amount of exposure light intermediate between that of the solid pattern and the non-patterned portion, In the gray tone portion, when the portion of the photoresist corresponding to the side wall (21a to 23a, 24) of the difficult-to-etch material is exposed, the side wall (41) of the photoresist becomes tapered, When a photoresist having a tapered sidewall is used to dry etch a material that is difficult to etch, the sidewall of the material that is difficult to etch forms a tapered angle of 0.20 degrees or more and 60 degrees or less with respect to one surface. When applied as a reticle (300) in a stepper, which is a reduced projection exposure apparatus, the outer edge of the reticle is a light-shielding area (310) consisting of a solid pattern, the inside of the light-shielding area corresponds to the position where a semiconductor chip pattern region (321) that will become the semiconductor chip on the semiconductor wafer is formed, and is a non-light-shielding area (320) where exposure light can be irradiated onto the photoresist, and the area between the light-shielding area and the non-light-shielding area is a graytone portion (330). In addition, when the mask is applied as a one-to-one mask (500) for exposing the entire effective area at once to a semiconductor wafer having an effective area (101) that is extracted as a chip and an invalid area (102) that is not extracted as a chip, the invalid area is a shaded area (510) consisting of a solid pattern, the effective area is a non-shaded area (520) where a semiconductor chip pattern area (521) that will become the semiconductor chip on the semiconductor wafer is formed and where exposure light can be irradiated onto the photoresist, and the area between the shaded area and the non-shaded area is a graytone portion (530).

[0013] In this way, the exposure mask includes a gray-tone mask. By performing dry etching using this exposure mask to pattern the difficult-to-etch material, the sidewalls of the photoresist can be precisely tapered, unlike the thermal flow method, and the sidewalls of the difficult-to-etch material can be precisely tapered. This makes it possible to precisely prevent the fence from remaining.

[0014] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a top view of the layout of a difficult-to-etch material provided in the semiconductor device shown in FIG. 1. [Diagram 3] FIG. 13 is a diagram showing the relationship between the film thickness of a material that is difficult to etch and the offset voltage Voff. [Figure 4] 3 is an enlarged perspective view of a region of the resistant-to-etch material surrounded by a two-dot chain line in FIG. 2. FIG. [Figure 5A] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 5B] 5B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 5A. [Figure 6]FIG. 2 is a top view layout diagram of a gray-tone mask. [Figure 7] 1 is a diagram showing the relationship between the top surface layout of a gray-tone mask and the shape of a photoresist after patterning. [Figure 8] 11A and 11B are cross-sectional views showing the state after photolithography, during etching, and after resist peeling in the cases where the sidewall shape of the photoresist is made vertical and tapered, respectively. [Figure 9] 13 is a diagram showing a top surface layout of a gray-tone mask near a folded portion, and an optical simulation bird's-eye view and cross-sectional view of a photoresist patterned with the gray-tone mask; [Figure 10] FIG. 11 is a top view layout diagram of a difficult-to-etch material provided in a semiconductor device according to a second embodiment. [Figure 11] 13 is a diagram showing a top surface layout of a gray-tone mask near a folded portion, and an optical simulation bird's-eye view and cross-sectional view of a photoresist patterned with the gray-tone mask; [Figure 12] 13 is a top view of a semiconductor wafer in which portions where fences are likely to be formed are indicated by hatching, as described in a third embodiment. FIG. [Figure 13] FIG. 13 is a top view of a reticle used when exposing a photoresist, which will be described as a comparative example of the third embodiment. [Figure 14] FIG. 11 is a top view of a reticle used when exposing a photoresist according to a third embodiment. [Figure 15] FIG. 15 is a top view showing a state in which a masking blade is placed over the reticle shown in FIG. 14. [Figure 16A] FIG. 1 is a top view showing overlapping exposures using a reticle in successive shots. [Figure 16B] FIG. 16B is an enlarged view of an area XVIB surrounded by a dashed line in FIG. 16A. [Figure 17] FIG. 13 is a top view of a reticle used when exposing a photoresist, which will be described as a comparative example of the fourth embodiment. [Figure 18]FIG. 13 is a top view of a reticle used when exposing a photoresist according to a fourth embodiment. [Figure 19] FIG. 13 is a top view of a 1:1 mask used when exposing a photoresist according to a fifth embodiment. [Figure 20] FIG. 11 is a top view layout diagram of a gray-tone mask according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0017] (First embodiment) A first embodiment will be described below. In this embodiment, a magnetic sensor will be described as an example of a semiconductor device using a difficult-to-etch material, but the present invention is not limited to a magnetic sensor and may be a semiconductor device having other elements.

[0018] As shown in FIG. 1, the semiconductor device of this embodiment is configured by patterning a difficult-to-etch material 20 on a substrate 10, and further forming a protective film 30 thereon.

[0019] The substrate 10 is made of, for example, a semiconductor substrate such as silicon, an insulating substrate, etc. A difficult-to-etch material 20 is disposed on one surface 11 of the substrate 10.

[0020] The etching-resistant material 20 is made of a material that is difficult to etch, such as NiFe, platinum (Pt), scandium aluminum nitride (ScAlN), nickel cobalt (NiCo), cobalt iron (CoFe), etc. The etching-resistant material 20 is patterned into a desired shape, and constitutes, for example, a resistance element in a magnetic sensor.

[0021] When the etch-resistant material 20 is used as a resistive element in a magnetic sensor, it is shaped as shown in FIG. 2, for example. That is, the etch-resistant material 20 is extended in one direction, then folded back in the opposite direction, and then folded back again in one direction to form an S-shape, and this S-shape is regularly repeated to form a serpentine shape. Specifically, the etch-resistant material 20 has a first portion 21 extending in one direction as a longitudinal direction, and a second portion 22 arranged adjacent to the first portion 21 and extending in one direction as a longitudinal direction. Furthermore, the etch-resistant material 20 is configured to have a folded portion 23 extending in a direction intersecting the longitudinal direction of the first portion 21 and the second portion 22. The first portion 21 and the folded portion 23 are connected, and the folded portion 23 and the second portion 22 are connected to each other, so that the etch-resistant material 20 is laid out in a serpentine shape.

[0022] Note that the connection points between first portion 21 and folded portion 23 and the connection points between folded portion 23 and second portion 22 become corners of the layout. In the present embodiment, the outer and inner corners of first portion 21 and folded portion 23 are not vertical but are inclined chamfered portions, but may be vertical.

[0023] Moreover, the film thickness of the difficult-to-etch material 20 is set to 30 nm or more. This thickness is arbitrary and may be smaller than 30 nm. However, when the thickness is set to a large thickness of 30 nm or more, a fence is likely to remain when the difficult-to-etch material 20 is etched. In addition, for a magnetic sensor that utilizes the magnetoresistance effect in which the electrical resistance of a solid changes with a magnetic field, it has been confirmed by simulation that there is a correlation between the thickness of the difficult-to-etch material 20 and the variation in the offset voltage Voff. Specifically, the relationship is as shown in FIG. 3, and the variation in the offset voltage Voff can be reduced by making the thickness of the difficult-to-etch material 20 30 nm or more. Therefore, when the difficult-to-etch material 20 is used to form a resistance element, it is preferable to make the film thickness of the difficult-to-etch material 20 30 nm or more as in this embodiment.

[0024] The etching-resistant material 20 is in a patterned state. As shown in FIG. 4, the first and second parts 21 and 22 of the etching-resistant material 20, which are arranged in parallel and adjacent to each other, and the side walls 21a to 23a of the folded part 23 are tapered with respect to the surface 11 of the substrate 10. The taper angle θ1, which is the angle that each of the side walls 21a to 23a makes with respect to the surface 11 of the substrate 10, is 0.20 degrees or more and 60 degrees or less. The side walls 21a and 22a refer to the end faces on both sides of the width direction of the first and second parts 21 and 22, respectively, with the direction perpendicular to the longitudinal direction of the first and second parts 21 and 22 being the width direction of the folded part 23. The side walls 23a refer to the end faces on both sides of the width direction of the folded part 23, respectively, with the longitudinal direction of the first and second parts 21 and 22 being the width direction of the folded part 23.

[0025] Furthermore, in this embodiment, the folded portion 23 is linear and perpendicular to the first portion 21 and the second portion 22, which are also linear. Therefore, as shown in FIG. 4, at the boundary between the first portion 21 and the folded portion 23 and the boundary between the folded portion 23 and the second portion 22, boundary surfaces 24 that become part of the side walls are also formed between the side walls 21a and 23a and between the side walls 23a and 22a. The boundary surfaces 24 are also tapered surfaces inclined with respect to the surface 11 of the substrate 10, and the taper angle θ2 is also 0.20 degrees or more and 60 degrees or less. The taper angle θ2 is likely to be an angle equal to or greater than the taper angle θ1, and a fence is likely to remain in this portion, but in this embodiment, the taper angle θ2 is also in the range of 0.20 degrees or more and 60 degrees or less. That is, in the entire area of ​​the etch-resistant material 20 including the boundary surface 24, the taper angles θ1 and θ2 of the side walls 21a to 23a and the boundary surface 24 are 0.20 degrees or more and 60 degrees or less. Therefore, no fence remains.

[0026] The taper angle θ1 is the angle that each of the side walls 21a to 23a makes with respect to the surface 11 in a cross section when the first portion 21, the second portion 22, and the folded-back portion 23 are cut along the width direction of each of them, as shown in (1) of Fig. 4. The taper angle θ2 is the angle that the boundary surface 24 makes with respect to the surface 11 in a cross section when the boundary surface 24 is cut perpendicularly to an inclined line 25 formed at the connecting point between the first portion 21 or the second portion 22 and the folded-back portion 23, as shown in (2) of Fig. 4.

[0027] The protective film 30 is a passivation film, and is formed so as to cover the upper surface of the etch-resistant material 20, the side walls 21a to 23a shown in FIG.

[0028] Although not shown here, when the semiconductor device is used as a magnetic sensor, the difficult-to-etch material 20 is used as a resistive element, both ends of which are connected to lead-out wiring or the like and connected to pads, allowing electrical connection to the outside. Alternatively, both ends of the difficult-to-etch material 20 constituting the resistive element are connected to a control circuit (not shown) mounted on the substrate 10, and an output signal corresponding to the electrical resistance that changes based on magnetic changes is input to the control circuit, thereby detecting the surrounding magnetic field.

[0029] The semiconductor device according to this embodiment is constructed as described above. Next, a method for manufacturing the semiconductor device according to this embodiment will be described.

[0030] 5A, a substrate 10 is prepared, and then a film of a difficult-to-etch material 20 is formed on one surface 11 of the substrate 10. The method for forming the difficult-to-etch material 20 may be any method such as sputtering or vapor deposition. Furthermore, a photoresist 40 is formed on the difficult-to-etch material 20.

[0031] Then, as shown in FIG. 5B, the photoresist 40 is exposed and developed to be patterned. At this time, the photoresist 40 is exposed using a graytone mask method so that the sidewalls 41 of the photoresist 40 have a tapered shape. The graytone mask method uses a graytone mask with slits formed therein that are equal to or smaller than the resolution of the exposure machine, and blocks part of the exposure light in the graytone portion where the slits are formed, thereby achieving intermediate exposure. In other words, in addition to the portion that is exposed without being covered by the mask and the portion that is covered by the mask and blocks the exposure light, a graytone portion is provided in which an intermediate amount of exposure light passes through the slit portion for exposure.

[0032] For example, when a positive resist is used as the photoresist 40, a graytone mask 50 shown in FIG. 6 is used as a reticle that serves as an exposure mask. The graytone mask 50 is a pattern having a solid pattern 51 that blocks the entire exposure light, a non-patterned portion 52 that does not block the exposure light and transmits the light, and a graytone portion 53 in which a slit 53a is formed. The slit 53a is a portion that adjusts the area of ​​the mask portion per unit area, and in this embodiment, it is a linear shape with a predetermined width to adjust the width of the mask portion. Specifically, a plurality of slits 53a are formed, and the width is increased from the solid pattern 51 toward the non-patterned portion 52. For this reason, the width of the mask portion is gradually narrowed, in other words, the width of the portion that is opened by the slit 53a and does not become the mask portion is gradually increased.

[0033] Therefore, by exposing the photoresist 40 so that the gray-tone portion 53 is disposed at a position corresponding to the sidewalls 21a to 23a and the boundary surface 24, the amount of exposure can be gradually changed at the position of the gray-tone portion 53. Specifically, the amount of exposure can be gradually increased from the solid pattern 51 toward the non-patterned portion 52. As a result, when the photoresist 40 is developed, as shown in FIG. 7, the photoresist 40 remains thick at the portion corresponding to the solid pattern 51, and the photoresist 40 is completely removed at the non-patterned portion 52. Then, at the position of the gray-tone portion 53, the thickness of the photoresist 40 gradually becomes thinner from the solid pattern 51 toward the non-patterned portion 52. Therefore, the sidewall of the photoresist 40 can be tapered.

[0034] The taper angle θ3 that the sidewall of the photoresist 40 makes with respect to the surface of the etch-resistant material 20 can be appropriately set according to the reduction rate of the length and width of the slit 53a, and is set to be in the range of 0.20 degrees or more and 60 degrees or less. In Fig. 7, the taper angle θ3 is shown as 45 degrees as an example, but is not limited to this.

[0035] Thereafter, the etching-resistant material 20 is dry-etched using the photoresist 40 with the tapered sidewalls as an etching mask, thereby patterning the etching-resistant material 20. At this time, the etching-resistant material 20 is also etched according to the thickness of the photoresist 40, so that the sidewalls 21a-23a and the interface 24 of the etching-resistant material 20 can be tapered like the sidewalls of the photoresist 40. The taper angle θ1 of the sidewalls 21a-23a and the taper angle θ2 of the interface 24 are approximately equal to the taper angle θ3 of the sidewalls of the photoresist 40, and therefore fall within the range of 0.20 degrees or more and 60 degrees or less.

[0036] In this way, the etching-resistant material 20 is patterned into a desired shape, and then the photoresist 40 is removed by washing. At this time, since the etching-resistant material 20 is patterned with a tapered sidewall of the photoresist 40, no fence remains. This will be described with reference to FIG. 8, which shows the state in which the sidewall of the photoresist 40 is tapered as in this embodiment and the state in which the sidewall of the photoresist 40 is not tapered as in a comparative example.

[0037] First, a comparative example shown in the upper diagram of FIG. 8 will be described. In this comparative example, the sidewall 41 of the photoresist 40 is made perpendicular to the surface of the etch-resistant material 20 by photolithography. In this case, during dry etching of the etch-resistant material 20, an etchant is supplied perpendicular to one surface 11 of the substrate 10 as shown by the arrow in the figure, and then the reaction product 60 bounces back. At this time, if the sidewall 41 of the photoresist 40 is vertical to the surface of the etch-resistant material 20, the reaction product 60 is likely to collide with the sidewall, and the reaction product 60 is likely to adhere to the sidewall of the photoresist 40 or the etch-resistant material 20. For this reason, the reaction product 60 remains attached to the sidewall of the photoresist 40 or the etch-resistant material 20 even after etching, and the fence 61 is generated by the reaction product 60 remaining after the photoresist 40 is removed.

[0038] Since corrosive gas such as Cl is used to etch the difficult-to-etch material 20, if the fence 61 remains after the dry etching process, it will cause corrosion. In addition, if the fence 61 remains after removing the photoresist 40, the fence 61 will protrude from the surface of the difficult-to-etch material 20, and the fence 61 will break through the protective film 30 formed thereon, affecting the coverage of the protective film 30. This makes it impossible to obtain a high-quality semiconductor device.

[0039] Next, the present embodiment shown in the lower diagram of FIG. 8 will be described. In this embodiment, the sidewall 41 of the photoresist 40 is tapered with respect to the surface of the difficult-to-etch material 20 by photolithography. The taper angle θ3 at this time is set to the same angle as the taper angles θ1 and θ2 at the position of the photoresist 40 corresponding to the difficult-to-etch material 20. Therefore, the rebounded reaction product 60 is unlikely to collide with the sidewalls of the photoresist 40 or the difficult-to-etch material 20, and the reaction product 60 is unlikely to adhere to the sidewalls of the photoresist 40 or the difficult-to-etch material 20. Therefore, the fence 61 is not generated after etching or after the photoresist 40 is removed.

[0040] Therefore, in this embodiment, the cause of corrosion can be eliminated, and the fence 61 does not protrude from the surface of the difficult-to-etch material 20. Therefore, the protective film 30 formed thereon can be formed well, and the coverage of the protective film 30 can be improved. This makes it possible to obtain a high-quality semiconductor device.

[0041] After the etching-resistant material 20 has been patterned in this manner, a protective film 30 is then formed so as to cover the etching-resistant material 20. This completes the semiconductor device shown in FIG.

[0042] As described above, in the semiconductor device of this embodiment, the side walls 21a to 23a and the boundary surface 24 of the difficult-to-etch material 20 are tapered. This makes it possible to obtain a semiconductor device in which no fence 61 remains, and thus to obtain a high-quality semiconductor device with good device characteristics.

[0043] In addition, the taper angles θ1 and θ2 of the side walls 21a to 23a and the boundary surface 24 are set in the range of 0.20 degrees or more and 60 degrees or less. If the taper angles θ1 and θ2 are large, the fence 61 will adhere. According to an experiment, if the taper angles θ1 and θ2 are larger than 60 degrees, the fence 61 may remain. For this reason, by setting the taper angles θ1 and θ2 to 60 degrees or less, a high-quality semiconductor device with almost no fence 61 remaining can be obtained. Furthermore, as for the taper angles θ1 and θ2, if they are 60 degrees or less, the fence 61 can be prevented from remaining, but the smaller the taper angles θ1 and θ2 are, the larger the area occupied by the side walls 21a to 23a and the boundary surface 24 becomes. In this embodiment, the etch-resistant material 20 is laid out in a meandering shape, but in order to realize finer design, it is necessary to set the pitch at which the etch-resistant material 20 is folded back, that is, the pitch at which the first portion 21 and the second portion 22 are arranged, to a desired pitch. For this reason, if the taper angles θ1 and θ2 are small, there is a concern that the gap between the first portion 21 and the second portion 22 will become too short, resulting in a short circuit. In consideration of this, the taper angles θ1 and θ2 are set to 0.20 degrees or more, and by setting such angles, it is possible to prevent the first portion 21 and the second portion 22 from shorting out while realizing miniaturization.

[0044] Furthermore, in this embodiment, the following effects can be obtained.

[0045] (i) In the manufacturing method of the semiconductor device of this embodiment, the etching-resistant material 20 is patterned by dry etching using a gray-tone mask 50. Therefore, unlike the thermal flow method, the sidewall 41 of the photoresist 40 can be precisely tapered, and the sidewalls 21a to 23a and the boundary surface 24 of the etching-resistant material 20 can be precisely tapered. In addition, the variation in the taper angle θ3 of the sidewall 41 of the photoresist 40 due to the pattern density dependency can be suppressed. Furthermore, the taper angle θ2 of the boundary surface 24 formed at the corner of the layout of the etching-resistant material 20 can be set to 60 degrees or less, and the fence 61 can be precisely prevented from remaining. An experiment was conducted to realize the taper shape by the thermal flow method. As a result, the taper angle θ3 of the sidewall 41 of the photoresist 40 was 38 degrees at the sidewalls 21a to 23a of the etching-resistant material 20, that is, at the position corresponding to the position where the taper angle θ1 is obtained. However, at the interface 24 in the etch-resistant material 20, that is, at the position corresponding to the position of the taper angle θ2, the taper angle θ3 of the side wall 41 of the photoresist 40 was 78 degrees. When the etch-resistant material 20 was patterned using this photoresist 40, the fence 61 remained at the interface 24.

[0046] Therefore, even at positions corresponding to the boundary surfaces 24 formed at the corners of the layout in the etch-resistant material 20, the taper angle θ3 of the side walls 41 of the photoresist 40 can be set to 60 degrees or less, so that the fences 61 are precisely prevented from remaining.

[0047] Here, referring to Fig. 9, it will be described how the taper angle θ2 of the interface 24 can also be set to 60 degrees or less. Note that the layout diagram of the gray-tone mask 50 near the turn-back portion in Fig. 9 shows an enlarged view of only the inner portion of the turn-back portion 23, etc. The optical simulation bird's-eye view shows the shape of the photoresist 40, but in order to make it easier to understand the corresponding relationship with each part of the etching-resistant material 20, the reference characters of the corresponding parts of the etching-resistant material 20 are indicated by dashed lines. The optical simulation cross-sectional views (1) and (2) show the cross-sectional shapes of the two-dot chain lines (1) and (2) in the bird's-eye view, respectively.

[0048] 9, slits 53a are provided extending along the longitudinal direction of each portion in the portions corresponding to first portion 21, second portion 22, and folded portion 23. In these portions, the longitudinal lengths of each slit 53a at the respective locations of first portion 21, second portion 22, and folded portion 23 are made equal, so that graytone portion 53 in which slits 53a are formed has a rectangular shape.

[0049] On the other hand, in the portion corresponding to the boundary surface 24, the slit 53a is connected to the slit 53a in the portion corresponding to the first portion 21, the second portion 22, and the folded portion 23. In this portion, the length of the slit 53a in the longitudinal direction is shortened from the solid pattern 51 toward the non-pattern portion 52, so that the gray-tone portion in which the slit 53a is formed has a triangular shape. Therefore, in the portion corresponding to the boundary surface 24, the width of the slit 53a connected to each other and the width of the pattern portion are narrower than those in the portion corresponding to the first portion 21, the second portion 22, and the folded portion 23. Therefore, the taper angle θ2 of the sidewall of the photoresist 40 in the portion corresponding to the boundary surface 24 is likely to be large, and the taper angle θ1 of the sidewalls 21a to 23a and the taper angle θ2 of the boundary surface 24 become non-uniform.

[0050] Specifically, in the vicinity of the folded portion 23, the photoresist 40 has a shape shown in the bird's-eye view by optical simulation in Fig. 9. The photoresist 40 has a cross-sectional shape of a cut surface (1) along the width direction of a portion corresponding to the first portion 21 in the figure, and a cut surface (2) along a direction perpendicular to the inclined line 25 of the corner of the layout at the connecting portion between the first portion 21 and the folded portion 23. That is, the taper angle θ3 of the sidewall 41 of the photoresist 40 is larger at the portion at the boundary surface 24 where the taper angle θ2 is larger than the portion at the sidewalls 21a to 23a of the etch-resistant material 20 where the taper angle θ1 is larger.

[0051] However, because the gray-tone mask 50 is used, the variation due to pattern density dependency is small, and the portion of the taper angle θ3 that becomes the taper angle θ2 can be formed at the desired angle. This makes it possible to accurately set the taper angle θ3 of the sidewall 41 of the photoresist 40, and further the taper angle θ2 of the boundary surface 24 of the difficult-to-etch material 20 that is patterned using the photoresist 40 as a mask, to 60 degrees or less.

[0052] When using graytone mask 50, a graytone design is necessary because an existing mask other than graytone mask 50 cannot be used. However, with just graytone design, sidewall 41 of photoresist 40 can be tapered by a normal exposure process, and variation in taper angle θ3 of sidewall 41 of photoresist 40 due to pattern density dependency can also be reduced.

[0053] (ii) According to the manufacturing method of the semiconductor device of the present embodiment, the tapered shape of the sidewall 41 of the photoresist 40 can be appropriately adjusted based on the layout of the slits 53a in the gray-tone mask 50. Therefore, the tapered shapes of the sidewalls 21a to 23a and the boundary surface 24 of the etch-resistant material 20 after dry etching processing using the photoresist 40 as a mask can also be appropriately adjusted.

[0054] For example, when the slit 53a is formed in a straight line as in this embodiment, the taper shape of the sidewall 41 of the photoresist 40 can be adjusted by setting the width of the slit 53a. That is, the wider the width of the slit 53a, the greater the amount of exposure, and the deeper the photoresist 40 is exposed. For this reason, when the sidewall 41 of the photoresist 40 is to be flattened, the expansion ratio when expanding the width of the slit 53a from the solid pattern 51 toward the non-patterned portion 52 may be made constant. When the sidewall 41 is to be recessed from the flat surface, the expansion ratio may be made larger on the solid pattern 51 side and smaller on the non-patterned portion 52 side, compared to when the sidewall 41 is to be flat. Conversely, when the sidewall 41 is to be protruding from the flat surface, the expansion ratio may be made smaller on the solid pattern 51 side and larger on the non-patterned portion 52 side, compared to when the sidewall 41 is to be flat. Furthermore, the length of the range of the portion forming the graytone portion 53, that is, the distance from the solid pattern 51 to the non-pattern portion 52, can determine the range of the side walls 21a to 23a and the boundary surface 24 of the etch-resistant material 20 that are to be tapered.

[0055] Second embodiment The second embodiment will be described. This embodiment is similar to the first embodiment except that the shape of the folded portion 23 is changed, and therefore only the differences from the first embodiment will be described.

[0056] 10, in this embodiment, the folded portion 23 is not linear along the width direction of the first portion 21 and the second portion 22, but is semicircular connecting the first portion 21 and the second portion 22. By forming the folded portion 23 in a semicircular shape in this manner, it is possible to prevent the formation of the boundary surface 24. For this reason, the folded portion 23 can be configured with side walls 21a to 23a having a uniform taper angle θ1, including the side walls 23a on both sides in the width direction of the folded portion 23, i.e., the radial direction of the semicircular shape.

[0057] The taper angle θ1 at each part of this embodiment will be described with reference to Fig. 11. Note that the layout diagram of the gray-tone mask 50 near the turn-back part in Fig. 11 shows only the inside part of the turn-back part 23 and the like in an enlarged manner. The optical simulation bird's-eye view shows the shape of the photoresist 40, but in order to make it easier to understand the corresponding relationship with each part of the etching-resistant material 20, the reference characters of the corresponding parts of the etching-resistant material 20 are indicated by dashed lines. The optical simulation cross-sectional views (1) and (2) show the cross-sectional shapes of the two-dot chain lines (1) and (2) in the bird's-eye view, respectively.

[0058] 11, in the portions corresponding to the first portion 21 and the second portion 22, slits 53a are provided extending along the longitudinal direction of each portion. In these portions, the longitudinal lengths of slits 53a are made equal in the respective locations of first portion 21 and second portion 22, so that graytone portion 53 in which slits 53a are formed has a rectangular shape.

[0059] On the other hand, in the portion corresponding to the folded portion 23, the slits 53a are connected to the slits 53a in the portion corresponding to the first portion 21 and the second portion 22. However, this portion is formed in a semicircular shape. Therefore, even in the portion corresponding to the folded portion 23, the width of the slits 53a connected to each other and the width of the pattern portion are the same as those in the portion corresponding to the first portion 21 and the second portion 22. In other words, the regularity of the formation ratio of the portion that becomes the pattern portion and the portion that becomes the slits 53a in the gray tone portion 53 can be made uniform. Therefore, the side walls 21a to 23a can be configured with a uniform taper angle θ1 in the entire area of ​​the folded portion 23 as well as the first portion 21 and the second portion 22.

[0060] In this way, by forming the folded portion 23 in a semicircular shape, it is possible to make the side walls 21a to 23a all have a taper angle θ1, and the etch-resistant material 20 can be patterned with high accuracy.

[0061] Third embodiment A third embodiment will be described. In this embodiment, a method for manufacturing a semiconductor device is provided that can suppress the formation of a fence 61 at the boundary between an effective area from which element forming chips are extracted and an ineffective area from which element forming chips are not extracted in a wafer state before the substrate 10 is diced into chip units. The rest is the same as in the first and second embodiments.

[0062] In the above first and second embodiments, the suppression of the formation of the fence 61 in the case of forming a resistor element or the like in the effective area has been described. In addition, as shown in FIG. 12, it is preferable to suppress the formation of the fence 61 in consideration of not only the effective area 101 but also the ineffective area 102 of the semiconductor wafer 100, which is a wafer state before being diced into chip units. Therefore, in this embodiment, the side wall of the photoresist 40 is tapered by using a gray tone part even in the boundary position between the effective area 101 and the ineffective area 102, specifically, in the area shown by hatching in the figure, so that the formation of the fence 61 is suppressed. Note that, although the above embodiments have been described as the substrate 10, in reality, the substrate 10 is in the state of a wafer that constitutes the semiconductor wafer 100, and after the difficult-to-etch material 20 and the photoresist 40 are formed thereon, they are patterned.

[0063] First, in this embodiment, a case will be described in which a photoresist is patterned using a stepper which is a reduction projection exposure apparatus.

[0064] When patterning the etching-resistant material 20 formed on the semiconductor wafer 100 by etching, as explained in the first embodiment, a photoresist 40 is placed on the etching-resistant material 20, and then the photoresist 40 is patterned by a stepper. At this time, as shown in Fig. 12, one-shot exposure areas 103, each represented by a rectangular square, are arranged in a matrix, and the exposure light is scanned to expose the photoresist 40 in order of each shot.

[0065] 13 shows a reticle 200 for photoresist exposure that is generally used in a stepper. The reticle 200 is made of a light-transmitting substrate or the like, and the outer edge is covered with a solid pattern of light-shielding material to form a light-shielding area 210 that blocks exposure light. The part inside the light-shielding area 210 on the reticle 200 is a non-light-shielding area 220 where the exposure light can be irradiated onto the photoresist 40.

[0066] As shown in this figure, non-light-shielding area 220 is provided with semiconductor chip pattern region 221 which will actually be taken out as a chip to become a product, and peripheral region 211 which will become light-shielding area 210 is provided in the hatched portion around them. Semiconductor chip pattern region 221 is composed of a plurality of chip regions 222 which will ultimately be taken out as chips, and scribe regions 223 provided between each chip region 222. Note that non-light-shielding area 220 is illustrated as non-patterned portion 52 which opens up the entire light-shielding area 210, but in reality, not only non-patterned portion 52 but also light-shielding patterns corresponding to patterns of resistor elements and the like to be built into the chip are formed.

[0067] 8 is likely to be formed at the boundary between the semiconductor chip pattern region 221 and the outer edge region 211. That is, at the boundary between the semiconductor chip pattern region 221 and the outer edge region 211, the non-light-shielded area 220 changes to the light-shielded area 210 that entirely shields light. For this reason, the difficult-to-etch material 20 is etched so as to stand vertically to the surface of the semiconductor wafer 100, and the fence 61 can be formed in this portion.

[0068] For this reason, in this embodiment, when using a stepper, a reticle 300 for photoresist exposure shown in Fig. 14 is used. As shown in this figure, a semiconductor chip pattern region 321 is provided as a non-light-shielding area 320, and a peripheral area 311 surrounding the non-light-shielding area 321 is provided as a light-shielding area 310. The semiconductor chip pattern region 321 is composed of a plurality of chip regions 322 which are ultimately taken out as chips, and a scribe region 323 provided between each chip region 322. In this embodiment, a gray-tone portion 330 is provided at the boundary position between the non-light-shielding area 320 and the light-shielding area 310, that is, at the boundary position between the semiconductor chip pattern region 321 and the peripheral area 311.

[0069] Although FIG. 14 is not a cross-sectional view, the light-shielding area 310 and the gray-tone portion 330 are hatched to make the ranges of the light-shielding area 310 and the gray-tone portion 330 easier to understand. The following figures are also hatched. The non-light-shielding area 320 is illustrated as a non-patterned portion 52 in which the light-shielding area 310 and the gray-tone portion 330 are entirely open. However, in reality, a light-shielding pattern is formed that is composed of not only the non-patterned portion 52 but also a solid pattern 51 corresponding to a pattern of a resistor element or the like to be fabricated in a chip. In addition, the gray-tone portion 53 described in the first and second embodiments is disposed at the boundary position between the solid pattern 51 and the non-patterned portion 52 that constitute the light-shielding pattern. In addition, the light-shielding area 310 is also made into a solid pattern 51, and the gray-tone portion 330 has the same configuration as the gray-tone portion 53. Here, the gray-tone portion 330 has a frame shape, and although not shown in FIG. 14, it is a pattern having a plurality of slit portions that extend in the length direction of each side and have a width direction perpendicular to each side. The width of the slit portion becomes wider from the light-shielding area 310 to the light-non-shielding area 320.

[0070] When exposing using a stepper, as shown in FIG. 15, a masking blade 400 is placed on the reticle 300 to mask the light-shielded area 310 while exposing the non-light-shielded area 320. The masking blade 400 forms an opening 410 that is slightly larger than the non-light-shielded area 320. The inside of the opening 410 is an area that can be exposed, and the part outside of the opening 410 that is covered by the masking blade 400 is a completely light-shielded area. Then, the photoresist 40 is exposed to a desired pattern in the exposable area, except for the part of the reticle 300 that is the light-shielded area 310 and the part that is masked by the light-shielding pattern. Also, the part covered by the masking blade 400 is shifted from the gray-tone part 330 so as not to cover the gray-tone part 330 during exposure.

[0071] 14, the portions of the chip regions 322 and the scribe region 323 sandwiched between the chip regions 322, i.e., the portions of the scribe region 323 located other than the outer edge of the non-shielded area 320, are regions where the projection ranges of the exposure light do not overlap between adjacent shots. In this region of the scribe region 323, i.e., the region shown by the thick dashed line in the figure, alignment keys and inspection patterns (not shown) are formed, and mask alignment and characteristic inspection can be performed. Of course, when forming alignment keys and inspection patterns in the difficult-to-etch material 20, a gray-tone mask is used so that the sides are tapered.

[0072] On the other hand, the portion of the scribe region 323 located on the outer edge of the non-shielded area 320 is an area where the projection ranges of the exposure light between adjacent shots overlap, or an area that is the boundary between the effective region 101 and the invalid region 102.

[0073] That is, as shown in Fig. 12, the reticle 300 is scanned for each shot, and exposure is performed on the entire effective area 101 of the semiconductor wafer 100. Therefore, in adjacent shots, the projection ranges of the exposure light overlap in the portion of the scribe area 323 on the reticle 300 that is located on the outer edge side of the non-shielded area 320, and do not overlap in the portions located other than the outer edge. Also, at the boundary position between the effective area 101 and the invalid area 102 shown by hatching in Fig. 12, the projection ranges of the exposure light do not overlap in the portion of the scribe area 323 that is located on the outer edge of the non-shielded area 320.

[0074] As described above, by providing a graytone portion 330 between the non-shielded area 320 and the shielded area 310 of the reticle 300, the side of the etched difficult-to-etch material 20 at the boundary between the effective area 101 and the ineffective area 102 can be prevented from becoming vertically steep.

[0075] However, it is not preferable that residues of photoresist 40 are generated between adjacent shots due to the provision of gray-tone portion 330 in the portion of scribe region 323 on reticle 300 that is positioned on the outer edge of non-shielded area 320.

[0076] For this reason, the width W1 of the gray-tone portion 330 shown in FIG. 15, FIG. 16A, and FIG. 16B is set to be less than 1 / 2 of the width W2 of the scribe region 323. In other words, for the portion of the scribe region 323 located on the outer edge side of the non-light-shielding area 320, as shown in FIG. 16B, the gray-tone portion 330 is arranged only outside the scribe center line Lc, which is the center line in the width direction. The inside of the scribe center line Lc is exposed in its entirety. The width W1 means the dimension of the gray-tone portion 330 that corresponds to the shortest distance between the non-light-shielding area 320 and the light-shielding area 310. The width W2 means the dimension of the scribe region 323 in the direction perpendicular to the longitudinal direction.

[0077] As a result, even if the first shot is exposed such that the photoresist 40 remains tapered on the outer edge of the non-shielded area 320 due to the graytone portion 330, the next shot can completely expose that portion. Specifically, as shown in Figures 16A and 16B, the graytone portion 330 of the first shot represented by the dashed line becomes the non-shielded area 320 in the portion that overlaps with the next shot represented by the solid line. This makes it possible to prevent the residue of the photoresist 40 caused by providing the graytone portion 330 from being generated in the portion of the scribe region 323 located on the outer edge side of the non-shielded area 320.

[0078] In addition, in FIGS. 16A and 16B, the light-shielding area 310 of the reticle 300 is omitted in order to make the drawings easier to see.

[0079] As described above, by providing graytone portion 330 at the boundary between non-shielded area 320 and shielded area 310 in reticle 300, it is possible to prevent fence 61 from being formed at the boundary between effective area 101 and invalid area 102.

[0080] (Fourth embodiment) The fourth embodiment will be described. This embodiment is different from the third embodiment in that it includes an area other than the semiconductor chip pattern area 321, and the rest is the same as the third embodiment, so only the differences from the third embodiment will be described.

[0081] 17, a TEG (Test Element Group) pattern region 224 for testing may be provided in addition to a semiconductor chip pattern region 221 in a non-shielded area 220 of a commonly used reticle 200. In this case, an outer edge region 211 that becomes the light-shielded area 210 is provided so as to surround the periphery of each of the semiconductor chip pattern region 221 and the TEG pattern region 224.

[0082] In this case as well, if the resistant-to-etch material 20 is etched perpendicularly to the surface of the semiconductor wafer 100 at the boundary positions between the semiconductor chip pattern region 221 and the TEG pattern region 224 and the outer edge region 211, the fences 61 are likely to be formed.

[0083] Therefore, in this embodiment, when using a stepper, a reticle 300 shown in Fig. 18 is used. As shown in this figure, in addition to a semiconductor chip pattern region 321, a TEG pattern region 324 is provided as a non-light-shielded area 320, and further a peripheral region 311 surrounding the TEG pattern region 324 is provided as a light-shielded area 310. In this embodiment, a gray-tone portion 330 is provided at the boundary position between the non-light-shielded area 320 and the light-shielded area 310, that is, the boundary position between the semiconductor chip pattern region 321 and the peripheral region 311, and the boundary position between the TEG pattern region 324 and the peripheral region 311.

[0084] In this way, even when the TEG pattern region 324 is provided in addition to the semiconductor chip pattern region 321, the formation of the fence 61 at the boundary between the non-shielded area 320 and the shielded area 310 can be suppressed by providing the gray tone portion 330.

[0085] Fifth embodiment A fifth embodiment will be described. In the third and fourth embodiments, a case where one semiconductor wafer 100 is exposed multiple times using a reticle 300 as an exposure mask has been described. That is, while repeatedly exposing using the reticle 300, the sidewall of the photoresist 40 is tapered at the boundary position between the effective area 101 and the invalid area 102 by the gray tone portion 330. In this embodiment, the same thing can be done when a one-to-one mask such as an aligner, that is, a single exposure mask is used to expose the entire effective area 101 of the semiconductor wafer 100 at once.

[0086] In this embodiment, the exposure of the photoresist 40 is performed using a one-to-one mask 500 such as an aligner shown in FIG. 19. As shown in this figure, the one-to-one mask 500 is made of a light-transmitting substrate or the like, and the outer edge including the invalid area 102 is a light-shielding area 510 covered with a light-shielding material, and the effective area 101 inside the light-shielding area 510 is a non-light-shielding area 520 having an opening in the light-shielding material of the same size as the semiconductor wafer 100. Of these, the non-light-shielding area 520 becomes a semiconductor chip pattern area 521 that is actually taken out as a chip and made into a product, and although not shown, the space between each of the chip areas provided in the semiconductor chip pattern area 521 becomes a scribe area. The non-light-shielding area 520 is illustrated as a non-patterned portion 52 in which the light-shielding area 510 is entirely opened, but in reality, not only the non-patterned portion 52 but also a light-shielding pattern corresponding to a pattern such as a resistor element to be formed in the chip is formed. In addition, the gray tone portion 53 described in the first and second embodiments is disposed at the boundary position of the light blocking pattern with the non-pattern portion 52. The light blocking area 510 is a solid pattern 51.

[0087] 8 is likely to be formed at the boundary between the light-shielding area 510 and the non-light-shielding area 520. That is, at this boundary, the non-light-shielding area 520 changes to the light-shielding area 510 which entirely shields light, so that the etch-resistant material 20 is etched so as to stand vertically to the surface of the semiconductor wafer 100, and the fence 61 can be formed.

[0088] For this reason, even when the 1:1 mask 500 is used, the graytone portion 530 is provided at the boundary between the light-shielding area 510 and the non-light-shielding area 520. Although not shown in FIG. 19, the graytone portion 530 is a pattern having a plurality of slit portions extending in the length direction of each boundary line between the light-shielding area 510 and the non-light-shielding area 520 and having a width direction perpendicular to each line. The width of the slit portions is wider from the invalid area 102 toward the valid area 101. In this way, even when the photoresist 40 is exposed using the 1:1 mask 500, it is possible to prevent the fence 61 from being formed at the boundary between the valid area 101 and the invalid area 102.

[0089] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0090] For example, the pattern of the graytone portion 53 of the graytone mask 50 described in the first embodiment is merely an example, and the pattern of the graytone portion 53 is arbitrary. For example, as shown in FIG. 20, the slit 53a is shaped to extend in a direction from the solid pattern 51 toward the non-pattern portion 52. The width of the slit 53a is gradually increased from the solid pattern 51 toward the non-pattern portion 52, in other words, the width of the pattern portion sandwiched between the slits 53a is gradually decreased. The graytone portion 53 of the graytone mask 50 may be configured with such a pattern. The graytone portion 330 in the third and fourth embodiments and the graytone portion 530 in the fifth embodiment may also be formed in other shapes including the shape shown in FIG. 20. Of course, when the shape shown in FIG. 20 is used, the shape is formed on only one side of the center line in the left-right direction of FIG. 20. In the third and fourth embodiments, the width of the slit 53a is gradually increased from the light-shielding area 310 toward the non-light-shielding area 320. In the fifth embodiment, the width of the slit 53 a is gradually increased from the ineffective area 102 toward the effective area 101 .

[0091] In the above embodiment, a magnetic sensor is taken as an example of a semiconductor device, but the present disclosure can be applied to semiconductor devices in which an element is formed by patterning a difficult-to-etch material 20 other than the magnetic sensor. For example, the present disclosure can be applied to semiconductor devices such as airflow sensors and MEMS (Micro Electro Mechanical Systems) sensors. Furthermore, the present disclosure is not limited to the case where an element is formed using the difficult-to-etch material 20. In other words, the present disclosure can be applied to the case where the difficult-to-etch material 20 is patterned using a photoresist 40 as a mask.

Claims

1. A method for manufacturing a semiconductor device, comprising: Providing a substrate (10); Depositing a film of a difficult-to-etch material (20) on one surface (11) of the substrate; depositing a photoresist (40) on the difficult-to-etch material; patterning the photoresist by exposure and development; After patterning the photoresist, the photoresist is used as a mask to dry etch the difficult-to-etch material, thereby patterning the difficult-to-etch material; In patterning the photoresist, exposure is performed using a graytone mask (50) having a solid pattern (51) that blocks the exposure light, a non-patterned portion (52) that transmits the exposure light without blocking it, and a graytone portion (53) that transmits an amount of exposure light intermediate between that of the solid pattern and the non-patterned portion, and the graytone portion is exposed to the photoresist in the graytone portion, thereby forming the sidewall (41) of the photoresist into a tapered shape; In the patterning of the etch-resistant material, the etch-resistant material is dry-etched using the photoresist having a tapered sidewall, so that the sidewall of the etch-resistant material has a tapered angle of 0.20 degrees or more and 60 degrees or less with respect to the one surface; The substrate is prepared by preparing a semiconductor wafer (100) having an effective area (101) that is a semiconductor chip pattern area (321, 521) to be extracted as a semiconductor chip, and an invalid area (102) that is an area not used as a semiconductor chip at the outer edge of the effective area; A method for manufacturing a semiconductor device, wherein the photoresist is patterned using an exposure mask in which the boundary position between the effective area and the invalid area is the gray tone portion (330), and the sidewall of the photoresist located in the invalid area is tapered at the boundary position.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the photoresist is patterned using a reticle (300) as the exposure mask, the reticle having a light-shielding area (310) and an exposure area (320) inside the light-shielding area where exposure light can be irradiated onto the photoresist, the boundary position between the light-shielding area and the exposure area being the graytone portion.

3. 3. The method for manufacturing a semiconductor device according to claim 2, wherein, by patterning the photoresist, a width (W1) of the graytone portion in the reticle is set to be less than 1 / 2 of a width (W2) of a scribe region (323) located at an outer edge of the semiconductor chip pattern region.

4. An exposure mask for patterning a photoresist (40) formed on a film of a difficult-to-etch material (20) formed on one surface (11) of a substrate (10) constituting a semiconductor wafer (100) by exposure and development, comprising: The graytone mask (50) includes a solid pattern (51) that blocks exposure light, a non-patterned portion (52) that transmits the exposure light without blocking it, and a graytone portion (53) that transmits an amount of exposure light intermediate between that of the solid pattern and the non-patterned portion, In the gray tone portion, when a portion of the photoresist corresponding to a side wall (21a to 23a, 24) of the difficult-to-etch material is exposed, the side wall (41) of the photoresist becomes tapered, When the photoresist having the tapered sidewall is used to dry etch the difficult-to-etch material, the sidewall of the difficult-to-etch material has a tapered angle of 0.20 degrees or more and 60 degrees or less with respect to the one surface, Furthermore, it is applied as a reticle (300) in a stepper, which is a reduction projection exposure apparatus, The outer edge of the reticle is a light-shielding area (310) formed of the solid pattern. a non-shielded area (320) in which the exposure light can be irradiated onto the photoresist, the non-shielded area corresponding to a position where a semiconductor chip pattern area (321) to be a semiconductor chip is to be formed on the semiconductor wafer; Between the light-shielding area and the non-light-shielding area is the gray-tone portion (330); This is the exposure mask.

5. An exposure mask for patterning a photoresist (40) formed on a film of a difficult-to-etch material (20) formed on one surface (11) of a substrate (10) constituting a semiconductor wafer (100) by exposure and development, comprising: The graytone mask (50) includes a solid pattern (51) that blocks exposure light, a non-patterned portion (52) that transmits the exposure light without blocking it, and a graytone portion (53) that transmits an amount of exposure light intermediate between that of the solid pattern and the non-patterned portion, In the gray tone portion, when a portion of the photoresist corresponding to a side wall (21a to 23a, 24) of the difficult-to-etch material is exposed, the side wall (41) of the photoresist becomes tapered, When the photoresist having the tapered sidewall is used to dry etch the difficult-to-etch material, the sidewall of the difficult-to-etch material has a tapered angle of 0.20 degrees or more and 60 degrees or less with respect to the one surface, Furthermore, the mask is applied to a semiconductor wafer having an effective area (101) to be extracted as a chip and an ineffective area (102) not to be extracted as the chip, as a one-to-one mask (500) for exposing the entire effective area at once with a single mask, The invalid area is a light-shielding area (510) formed of the solid pattern. The effective area is a non-shielded area (520) in which a semiconductor chip pattern area (521) that will become a semiconductor chip on the semiconductor wafer is formed and in which the exposure light can be irradiated onto the photoresist, and the area between the light-shielded area and the non-shielded area is the graytone portion (530).

Images