Semiconductor Module

Abstract

This semiconductor module comprises: an insulating substrate; a conductive pattern; a transistor; a negative-side power supply terminal which is positioned in a first direction with respect to the transistor; and an auxiliary wire joined to the conductive pattern. The transistor includes an emitter electrode and a gate electrode which is positioned in the first direction with respect to the emitter electrode. In the conductive pattern, electric current flows from a specific point via the transistor to the negative-side power supply terminal. The emitter electrode includes a first portion and a second portion which is positioned in a second direction opposite to the first direction with respect to the first portion. The auxiliary wire includes a first end close to the specific point, and a second end close to the transistor. The second end is closer to the second portion than to the first portion.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor module. [Background technology]

[0002] 2. Description of the Related Art There is known a semiconductor module used in a power conversion device such as an inverter device, etc. The semiconductor module has semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and an FWD (Free Wheeling Diode).

[0003] The semiconductor module described in Patent Document 1 includes an insulating substrate, a plurality of conductor patterns formed on the insulating substrate, and a semiconductor element. The lower surface of the semiconductor element is a collector electrode. The lower surface is joined to one of the plurality of conductor patterns via solder. In addition, an emitter terminal and a gate terminal serving as a control terminal are provided on the upper surface of the semiconductor element.

[0004] A larger current flows through the conductor pattern electrically connected to the collector and the conductor pattern electrically connected to the emitter than through the conductor pattern electrically connected to the gate. Cited Document 1 discloses a technique for bonding a plurality of metal wires to the conductor pattern electrically connected to the collector so as to facilitate the flow of a larger current through the conductor pattern. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2010-251551 A Summary of the Invention [Problem to be solved by the invention]

[0006] Not only does the ease of current flow differ between multiple conductive patterns, but also there are positional differences in the ease of current flow within one semiconductor element. Therefore, for example, when an emitter electrode is formed on the upper surface of a semiconductor element, there are areas in the emitter electrode where the current flows easily and areas where the current does not flow easily. The areas where the current flows easily may generate heat more easily than the areas where the current does not flow easily.

[0007] Furthermore, when a control electrode such as a gate terminal is formed on the upper surface of a semiconductor element, the area of ​​the emitter electrode in the vicinity of the control electrode may be reduced compared to other portions. Furthermore, for example, when various wirings are joined to the emitter electrode, the number of wirings in the emitter electrode in the vicinity of the control electrode may be reduced compared to other portions. Therefore, if the portion of the emitter electrode in the vicinity of the control electrode is an area where current flows easily, the various wirings are more likely to generate heat. This may cause damage, etc. For this reason, it is desirable to suppress positional bias in the ease of current flow within a semiconductor element. [Means for solving the problem]

[0008] In order to solve the above problems, a semiconductor module according to a preferred embodiment of the present disclosure comprises an insulating substrate, a conductive pattern on the insulating substrate, a transistor on the conductive pattern, a connection terminal located on the insulating substrate in a first direction relative to the transistor, and an auxiliary wiring joined to the conductive pattern, wherein the transistor includes a first main electrode formed on a first surface facing the conductive pattern, a second main electrode formed on a second surface opposite to the first surface, and a control electrode located on the second surface in the first direction relative to the second main electrode, a current flows from a specific point on the conductive pattern located in the first direction relative to the transistor to the connection terminal via the transistor, the second main electrode includes a first portion arranged in the first direction and a second portion located in a second direction opposite to the first direction relative to the first portion, and the auxiliary wiring includes a first end closer to the specific point and a second end closer to the transistor, and the second end is closer to the second portion than the first portion.

[0009] Furthermore, a semiconductor module according to a preferred embodiment of the present disclosure comprises an insulating substrate, a conductive pattern on the insulating substrate, a transistor on the conductive pattern, and a connection terminal located on the insulating substrate in a first direction relative to the transistor, the transistor including a first main electrode formed on a first surface facing the conductive pattern, a second main electrode formed on a second surface opposite the first surface, and a control electrode located on the second surface in the first direction relative to the second main electrode, a current flows from a specific point on the conductive pattern located in the first direction relative to the transistor via the transistor to the connection terminal, the second main electrode including a first portion and a second portion located in a second direction opposite to the first direction relative to the first portion, and a slit is formed in the conductive pattern between the specific point and the first portion. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a semiconductor module according to a first embodiment. [Diagram 2]FIG. 1 is a circuit diagram for one phase of a three-level power conversion circuit. [Diagram 3] 3 is a plan view of the semiconductor unit shown in FIG. 2. [Figure 4] 4 is a cross-sectional view taken along the line A1-A1 shown in FIG. [Diagram 5] 5 is a diagram for explaining a current flow in the semiconductor unit of FIG. 4. [Figure 6] 1 is a diagram for explaining a current path from a specific point to a transistor. [Figure 7] FIG. 11 is a plan view of a semiconductor unit according to a second embodiment. [Figure 8] FIG. 13 is a plan view of a semiconductor unit according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, preferred embodiments of the present disclosure will be described with reference to the accompanying drawings. Note that the dimensions and scale of each part in the drawings may differ from the actual dimensions, and some parts are shown diagrammatically to facilitate understanding. In addition, the scope of the present disclosure is not limited to these forms unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0012] In the following description, for convenience, the X-axis, Y-axis, and Z-axis, which are mutually orthogonal, are appropriately used. In addition, in the following, one direction along the X-axis is the X1 direction, and the direction opposite to the X1 direction is the X2 direction. In the following, one direction along the Y-axis is the Y1 direction, and the direction opposite to the Y1 direction is the Y2 direction. In the following, one direction along the Z-axis is the Z1 direction, and the direction opposite to the Z1 direction is the Z2 direction. In addition, the plane along the X-axis and the Y-axis is the XY plane. In addition, in the following, the view from the normal direction of the XY plane is referred to as "planar view". In addition, the Z1 direction is referred to as "upward" and the Z2 direction is referred to as "downward". In addition, the X1 direction is referred to as the "first direction", and the X2 direction is referred to as the "second direction". In addition, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α, but also the case where element α and element β are separated. In addition, the “electrical connection” between elements α and β includes not only a configuration in which elements α and β are directly joined to each other to establish electrical conductivity, but also a configuration in which elements α and β are indirectly connected to each other via another conductor.

[0013] 1. Semiconductor module 1 1-1. Overview of Semiconductor Module 1 Fig. 1 is a plan view of a semiconductor module 1 according to the present embodiment. The semiconductor module 1 shown in Fig. 1 is used as a power conversion device such as a power module. The semiconductor module 1 includes a heat dissipation substrate 11, a plurality of semiconductor units 10a, and a plurality of semiconductor units 10b.

[0014] The heat dissipation substrate 11 is a flat substrate that functions as a base for the semiconductor units 10a and the semiconductor units 10b. The heat dissipation substrate 11 is made of a material with excellent thermal conductivity. Examples of materials for the heat dissipation substrate 11 include metals such as copper and aluminum, and alloys. The upper surface 111 of the heat dissipation substrate 11 may be plated with a metal or alloy such as nickel to improve corrosion resistance.

[0015] The heat dissipation substrate 11 is formed with, for example, a plurality of external terminals Ts for inputting and outputting current to and from the plurality of semiconductor units 10a and the plurality of semiconductor units 10b, and a thermistor Th. The upper surface 111 of the heat dissipation substrate 11 is parallel to the XY plane. The thickness direction of the heat dissipation substrate 11 is parallel to the normal direction of the XY plane. In the example shown in FIG. 1, the shape of the heat dissipation substrate 11 in a plan view is a quadrangle with the X1 direction as the longitudinal direction, but this is just one example and the heat dissipation substrate 11 may have any desired shape.

[0016] The semiconductor units 10a and the semiconductor units 10b are disposed on an upper surface 111 of the heat dissipation substrate 11. In the example shown in Fig. 1, the semiconductor units 10a and the semiconductor units 10b are arranged in an example in the X1 direction. Note that the number of the semiconductor units 10a and the number of the semiconductor units 10b shown in Fig. 1 are each just an example, and the number of the semiconductor units 10a and the semiconductor units 10b can be installed as necessary.

[0017] Each of the semiconductor units 10a and the semiconductor units 10b includes, for example, a switching element, a diode, etc. Examples of the switching element include an IGBT (Insulated Gate Bipolar Transistor) and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), etc. Examples of the diode include an FWD (Free Wheeling Diode), etc.

[0018] One semiconductor unit 10a and one semiconductor unit 10b can configure a circuit for one phase of a three-level power conversion circuit. A configuration of multiple semiconductor units 10a and multiple semiconductor units 10b can obtain a larger current. In this example, the semiconductor module 1 configures a circuit for one phase of a three-level power conversion circuit with multiple semiconductor units 10a and multiple semiconductor units 10b.

[0019] 1-2.3 level power conversion circuit Fig. 2 is a circuit diagram of one phase of the three-level power conversion circuit. As shown in Fig. 2, the circuit configuration of one phase is composed of four transistors T1, T2, T3, and T4, and six diodes D1, D2, D3, D4, D5, and D6. In this example, each of the transistors T1 to T4 is an IGBT. Each of the diodes D1 to D6 is an FWD.

[0020] The transistors T1 to T4 and the diodes D1 to D4 constitute an inverter. The transistors T1, T2, T3, and T4 are connected in series. The transistors T1 and T2 constitute an upper arm A of the inverter, and the transistors T3 and T4 constitute a lower arm B of the inverter. Each semiconductor unit 10a shown in FIG. 1 includes the upper arm A of the inverter. Each semiconductor unit 10b shown in FIG. 1 includes the lower arm B of the inverter.

[0021] Diode D1 is connected in anti-parallel with transistor T1. Diode D2 is connected in anti-parallel with transistor T2. Diode D3 is connected in anti-parallel with transistor T3. Diode D4 is connected in anti-parallel with transistor T4.

[0022] Each of transistors T1, T2, T3, and T4 has a collector, an emitter, and a gate. The collector of transistor T1 is connected to a positive power supply terminal P that is connected to the positive side of a DC power supply. The emitter of transistor T4 is connected to a negative power supply terminal N that is connected to the negative side of the DC power supply. The negative power supply terminal N is a "connection terminal." The junction between the emitter of transistor T2 and the collector of transistor T3 is connected to an AC output terminal U. The junction between the anode of diode D5 and the cathode of diode D6 is connected to an intermediate terminal M.

[0023] According to the semiconductor module 1 including such a three-level power conversion circuit, the mounting area of ​​the semiconductor module 1 can be reduced, and the device with excellent conversion efficiency can be made smaller. In addition, by forming the semiconductor module 1 into a single package, the internal inductance can be reduced.

[0024] 1-3. Each semiconductor unit 10b Fig. 3 is a plan view of each semiconductor unit 10b shown in Fig. 1. Fig. 4 is a cross-sectional view taken along the line A1-A1 shown in Fig. 3. As shown in Fig. 3, each semiconductor unit 10b includes an insulating substrate 21, a plurality of conductive patterns 231, 232, 233, 234, 235, 236, and 237, two transistors T3 and T4, three diodes D3, D4, and D6, an output terminal U, an intermediate terminal M, a negative power supply terminal N, and a plurality of auxiliary wirings 51.

[0025] In the illustrated example, the shape of insulating substrate 21 in a plan view is a rectangle. Insulating substrate 21 has insulating properties. Examples of materials for insulating substrate 21 include ceramics such as aluminum oxide and resins such as epoxy resin. Although not illustrated, a metal plate to be joined to heat dissipation substrate 11 shown in FIG. 1 is disposed on the lower surface of insulating substrate 21.

[0026] Each of the plurality of conductive patterns 231-237 is disposed on the upper surface of the insulating substrate 21. Each of the plurality of conductive patterns 231-237 has electrical conductivity and is formed of, for example, a metal such as copper or aluminum, or an alloy. The plurality of conductive patterns 231-237 are electrically separated from each other. The thickness of each of the plurality of conductive patterns 231-237 is not particularly limited, but is, for example, 0.1 mm or more and 2.0 mm or less. The thickness of each of the plurality of conductive patterns 231-237 is uniform.

[0027] 3, an output terminal U, a transistor T3, and a diode D3 are disposed on the conductive pattern 233. The output terminal U, the transistor T3, and the diode D3 are electrically connected to the conductive pattern 233. Furthermore, the conductive pattern 235 is electrically connected to the conductive pattern 232 via a wire 49. Furthermore, the output terminal U is provided in the X2 direction from the transistor T3.

[0028] The transistor T3 has a collector electrode (not shown), a gate electrode 311, and an emitter electrode 312. The collector electrode is an electrode formed on the lower surface of the semiconductor layer, and is connected to the conductive pattern 233 via, for example, solder or conductive paste. The gate electrode 311 and the emitter electrode 312 are electrodes formed on the upper surface of the semiconductor layer. The gate electrode 311 is disposed in the Y1 direction with respect to the emitter electrode 312. The gate electrode 311 is electrically connected to the conductive pattern 231 via a wire 411. In the illustrated example, the emitter electrode 312 is divided into three parts, and the three divided parts are aligned in the Y1 direction. In addition, a plurality of wires 412 are disposed on the upper surface of the emitter electrode 312. Each wire 412 extends in the X1 direction. Both ends of each wire 412 are joined to the emitter electrode 312. A part of the current flowing through the emitter electrode 312 flows through each wire 412. Moreover, the conductive pattern 235 is electrically connected to the emitter electrode 312 via a plurality of wires 413 .

[0029] The diode D3 has a cathode electrode (not shown) and an anode electrode 321. The cathode electrode is an electrode formed on the lower surface of the semiconductor layer, and is connected to the conductive pattern 233 via, for example, solder or conductive paste. The anode electrode 321 is an electrode formed on the upper surface of the semiconductor layer. The anode electrode 321 is electrically connected to the emitter electrode 312 via a wire 421. In addition, the anode electrode 321 is electrically connected to the conductive pattern 235 via a plurality of wires 422 of different lengths.

[0030] An intermediate terminal M and a diode D6 are disposed on the conductive pattern 234. The intermediate terminal M and the diode D6 are electrically connected to the conductive pattern 234. Furthermore, the intermediate terminal M is provided in the X1 direction from the diode D6.

[0031] The diode D6 has a cathode electrode (not shown) and an anode electrode 331. The cathode electrode is an electrode formed on the lower surface of the semiconductor layer and is connected to the conductive pattern 234 via, for example, solder or conductive paste. The anode electrode 331 is an electrode formed on the upper surface of the semiconductor layer. The anode electrode 331 is electrically connected to the conductive pattern 235 via a plurality of wires 431 of different lengths.

[0032] A transistor T4 and a diode D4 are disposed on the conductive pattern 235. The transistor T4 and the diode D4 are electrically connected to the conductive pattern 235.

[0033] As shown in FIG. 4, the transistor T4 has a collector electrode 341, a gate electrode 342, and an emitter electrode 343. The collector electrode 341 corresponds to a "first main electrode". The collector electrode 341 is formed on a first surface S1 facing the conductive pattern 235. The collector electrode 341 is connected to the conductive pattern 235 via, for example, solder or conductive paste. The gate electrode 342 corresponds to a "control electrode", and the emitter electrode 343 corresponds to a "second main electrode". The gate electrode 342 and the emitter electrode 343 are each formed on a second surface S2 opposite to the first surface S1.

[0034] 3, the gate electrode 342 is located further in the X1 direction than the emitter electrode 343. That is, the position of the gate electrode 342 on the X-axis is located further in the X1 direction than the position of the emitter electrode 343 on the X-axis. The gate electrode 342 is electrically connected to the conductive pattern 237 via a wire 441.

[0035] In the illustrated example, the emitter electrode 343 is divided into three parts, including a first part 343a, a second part 343b, and a third part 343c. The first part 343a, the third part 343c, and the second part 343b are arranged in this order in the X2 direction. Therefore, in a plan view, the third part 343c is disposed between the first part 343a and the second part 343b. In addition, the second part 343b and the third part 343c are located in the X2 direction of the "second direction" from the first part 343a. That is, the positions of the second part 343b and the third part 343c on the X axis are located in the X2 direction from the position of the first part 343a on the X axis.

[0036] The first portion 343a is provided near the gate electrode 342. The first portion 343a, the second portion 343b, and the third portion 343c have the same width and total length. The width is the length in the X1 direction. The total length is the length in the Y1 direction. A recess is formed on the long side of the first portion 343a, and the gate electrode 342 is formed in the recess. Therefore, the area of ​​the gate electrode 342, that is, the plane area of ​​the first portion 343a is smaller than each of the plane areas of the second portion 343b and the third portion 343c. The plane area of ​​the second portion 343b is approximately equal to the plane area of ​​the third portion 343c.

[0037] A plurality of wires 442 are disposed on the upper surface of the emitter electrode 343. Each wire 442 extends in the Y1 direction. Both ends of each wire 442 are joined to the emitter electrode 343. A portion of the current flowing through the emitter electrode 343 flows through each wire 442. By providing a plurality of wires 442, it is possible to allow a current to flow in a balanced manner throughout the entire area of ​​the emitter electrode 343, compared to a case in which a plurality of wires 442 is not provided.

[0038] As described above, the plane area of ​​the first portion 343a is smaller than the plane areas of the second portion 343b and the third portion 343c. Therefore, the number of wires 442 joined to the first portion 343a is smaller than the number of wires 442 joined to the second portion 343b. Similarly, the number of wires 442 joined to the first portion 343a is smaller than the number of wires 442 joined to the third portion 343c. In the example shown in FIG. 3, three wires 442 are joined to the first portion 343a, and four wires 442 are joined to each of the second portion 343b and the third portion 343c.

[0039] Moreover, the emitter electrode 343 is electrically connected to the conductive pattern 236 via a plurality of wires 443 .

[0040] As shown by the dashed line in Fig. 3 and in Fig. 4, an external connection terminal 90 is disposed on the second portion 343b of the emitter electrode 343. Although not shown in detail, the external connection terminal 90 is joined to, for example, the negative power supply terminal N or the intermediate terminal M of the adjacent semiconductor unit 10b, and is used for connection to the external terminal Ts of the adjacent semiconductor unit 10b. By disposing the external connection terminal 90 on the second portion 343b, the two adjacent semiconductor units 10b can be brought closer to each other. This allows the semiconductor module 1 to be made more compact.

[0041] As shown in FIG. 3, a plurality of auxiliary wirings 51 are arranged on the conductive pattern 235. Each auxiliary wiring 51 is joined to the conductive pattern 235. Each auxiliary wiring 51 is linear in a plan view, and is joined to the conductive pattern 235 at a first end 511 and a second end 512. The first end 511 is located in the Y1 direction from the second end 512. That is, the position of the first end 511 on the Y axis is located in the Y1 direction from the position of the second end 512 on the Y axis. A part of the current flowing through the conductive pattern 235 flows through the plurality of auxiliary wirings 51. By providing such a plurality of auxiliary wirings 51, the positional difference in the ease of current flow within the conductive pattern 235 is reduced. In the example shown in FIG. 3, the auxiliary wiring 51 is a wire, but may be, for example, a ribbon cable or a lead frame.

[0042] 3, the diode D4 is located in the X1 direction of the "first direction" relative to the transistor T4 on the insulating substrate 21. That is, the position of the diode D4 on the X axis is located further in the X1 direction than the position of the transistor T4 on the X axis.

[0043] 4, the diode D4 has a cathode electrode 351 and an anode electrode 352. The cathode electrode 351 is formed on a third surface S3 facing the conductive pattern 235. The cathode electrode 351 is connected to the conductive pattern 235 via, for example, solder or a conductive paste. The anode electrode 352 is formed on a fourth surface S4 opposite to the third surface S3.

[0044] 3, the anode electrode 352 is electrically connected to the emitter electrode 343 via a wire 450 serving as a "relay wiring." Thus, the wire 450 electrically connects the diode D4 and the transistor T4. One end of the wire 450 is joined to the first portion 343a of the emitter electrode 343, and the other end of the wire 450 is joined to the anode electrode 352. By providing the wire 450, parasitic oscillation can be suppressed compared to a case in which the wire 450 is not provided, and therefore noise can be reduced.

[0045] In addition, the anode electrode 352 is electrically connected to the conductive pattern 236 via a plurality of wires 451 .

[0046] A negative power supply terminal N is disposed on the conductive pattern 236. The negative power supply terminal N is electrically connected to the conductive pattern 236. The negative power supply terminal N is located further in the X1 direction, which is the "first direction", than the transistor T4. In other words, the position of the negative power supply terminal N on the X axis is located further in the X1 direction than the position of the transistor T4 on the X axis.

[0047] It should be noted that each of the wires 49, 411, 412, 413, 421, 422, 431, 441, 442, 443, 450 and 451 in the above description may be replaced with a ribbon cable or a lead frame.

[0048] Fig. 5 is a diagram for explaining the flow of current in the semiconductor unit 10b in Fig. 4. In the semiconductor unit 10b, current flows as shown by multiple arrows in Fig. 5. The current flows from a wire 413 provided in the transistor T3 through the transistor T4 to the negative power supply terminal N, which is the "connection terminal."

[0049] For example, a junction point between one of the wires 413 and the conductive pattern 235 is defined as a specific point P1. The specific point P1 is located in the X1 direction, which is the "first direction," from the transistor T4. That is, the position of the specific point P1 on the X axis is located in the X1 direction from the position of the transistor T4 on the X axis. A current flows from the specific point P1 on the conductive pattern 235 to the negative power supply terminal N via the transistor T4.

[0050] The current flowing from the specific point P1 to the transistor T4 flows through a portion of the conductive pattern 235 with small inductance. Therefore, the current tries to flow from the specific point P1 to the transistor T4 through a path with a short distance in the conductive pattern 235. Therefore, a positional difference occurs in the ease of current flow in the conductive pattern 235, and as a result, a positional difference occurs in the ease of current flow in the transistor T4 as well. In order to reduce this positional difference, a plurality of auxiliary wirings 51 are provided.

[0051] 6 is a diagram for explaining a path of a current from a specific point P1 to a transistor T4. As described above, the specific point P1 is located in the X1 direction from the transistor T4. Also, the first portion 343a of the transistor T4 is located in the X1 direction from the second portion 343b. Therefore, on the conductive pattern 235, the first portion 343a is located closer to the specific point P1 than the second portion 343b. Therefore, the first shortest path R1 on the conductive pattern 235 from the specific point P1 to the first portion 343a is shorter than the second shortest path R2 on the conductive pattern 235 from the specific point P1 to the second portion 343b.

[0052] The first shortest path R1 is shorter than the second shortest path R2. Therefore, when the auxiliary wirings 51 are not provided, the inductance of the first shortest path R1 is smaller than the inductance of the second shortest path R2. Therefore, the current flows easily through the first shortest path R1, which has a small inductance, and does not flow easily through the second shortest path R2, which has a large inductance. As a result, in the transistor T4, the amount of current flowing through the first portion 343a is larger than that of the second portion 343b. Furthermore, the negative power supply terminal N, which is the "connection terminal", is located in the X1 direction from the transistor T4. Therefore, the amount of current flowing through the first portion 343a is larger than that of the second portion 343b, compared to when the negative power supply terminal N is located in the X2 direction from the transistor T4.

[0053] A plurality of auxiliary wirings 51 are provided to reduce the inductance of the second shortest path R2 and alleviate the amount of current flowing through the first portion 343a. Specifically, each auxiliary wiring 51 includes a first end 511 close to the specific point P1 and a second end 512 close to the transistor T4. The second end 512 is closer to the second portion 343b than the first portion 343a.

[0054] By arranging each auxiliary wiring 51 so that the second end 512 is closer to the second portion 343b than to the first portion 343a, the auxiliary wiring 51 is arranged along the second shortest path R2. Therefore, a part of the current flowing through the second shortest path R2 flows through the auxiliary wiring 51, so that the inductance of the second shortest path R2 can be reduced. As a result, the amount of current flowing through the first portion 343a can be reduced. Therefore, the difference in the ease of current flow between the first portion 343a and the second portion 343b can be reduced. Therefore, the positional bias in the ease of current flow within the transistor T4 can be suppressed.

[0055] Since the amount of current flowing through the first portion 343a can be reduced, the risk of the wire 442 joined to the first portion 343a being damaged by heat generation is reduced. Furthermore, since a plurality of auxiliary wirings 51 are provided, positional bias in the ease of current flow within the transistor T4 can be more effectively reduced compared to the case where one auxiliary wiring 51 is provided.

[0056] In particular, in the transistor T4, the gate electrode 342 is located in the X1 direction further than the emitter electrode 343. Therefore, the first portion 343a is provided closer to the gate electrode 342 than the second portion 343b, and is heavily restricted by the gate electrode 342. Specifically, as described above, the plane area of ​​the first portion 343a is smaller than the plane area of ​​the second portion 343b, and the number of wires 442 joined to the first portion 343a is smaller than the number of wires 442 joined to the second portion 343b. Therefore, a large current is more likely to flow through each wire 442 joined to the first portion 343a than through each wire 442 joined to the second portion 343b.

[0057] In addition to the first shortest path R1 being shorter than the second shortest path R2, when the gate electrode 342 is disposed closer to the first portion 343a than to the second portion 343b, a particularly large current is likely to flow through the first portion 343a. Therefore, the effect of reducing the amount of current flowing through the first portion 343a by the multiple auxiliary wirings 51 is particularly remarkable. Therefore, damage to the wire 443 connected to the first portion 343a can be suppressed.

[0058] As described above, one end of the wire 450 electrically connecting the transistor T4 and the diode D6 is joined to the first portion 342a. The number of wires 450 is restricted by the reduction in the plane area of ​​the first portion 343a due to the gate electrode 342 being provided near the first portion 343a. For this reason, a large current is likely to flow through the wire 450. As described above, the amount of current flowing through the first portion 343a is reduced by the multiple auxiliary wirings 51, so that the amount of current flowing through the wire 450 can be reduced. For this reason, by providing the wire 450, it is possible to reduce noise and the risk of damage to the wire 450. As a result, it is possible to provide a highly reliable semiconductor module 1.

[0059] 4, an external connection terminal 90 is disposed on the second portion 343b of the emitter electrode 343. For example, by disposing the gate electrode 342 in the X2 direction from the second portion 343b, the gate electrode 342 is disposed in an area where current does not easily flow, and it is considered that damage to the wire 442 joined to the first portion 343a described above is suppressed. However, in this case, the external connection terminal 90 and the gate wire interfere with each other, increasing the current and making it more likely to be damaged. Therefore, when the external connection terminal 90 is disposed on the second portion 343b, by providing the auxiliary wiring 51 described above, it is possible to provide a highly reliable semiconductor unit 10b in which the risk of damage to the wire 442 is suppressed.

[0060] 2. Second embodiment A second embodiment of the present disclosure will be described below. In the following exemplary embodiment, for elements having the same actions and functions as those in the first embodiment, the reference numerals used in the description of the first embodiment will be used and detailed descriptions of each will be omitted as appropriate.

[0061] 7 is a plan view of a semiconductor unit 10bA according to the second embodiment. As shown in FIG. 7, this embodiment is similar to the first embodiment except that the auxiliary wiring 51 is omitted and a slit 52 is provided in the conductive pattern 235.

[0062] 7, a slit 52 is formed in the conductive pattern 235. The slit 52 penetrates the conductive pattern 235 in the thickness direction. The slit 52 has one end 251 and the other end 252, and is a straight line parallel to the X-axis in a plan view. The slit 52 is formed between a specific point P1 in the conductive pattern 235 and the first portion 343a.

[0063] 6, if the slit 52 is not provided, the first shortest path R1 is shorter than the second shortest path R2. Therefore, if the slit 52 is not provided, the inductance of the second shortest path R2 is larger than the inductance of the first shortest path R1. Therefore, it is more difficult for a current to flow through the second portion 343b than through the first portion 343a.

[0064] The provision of the slit 52 can lengthen the length of the current path from the specific point P1 to the first portion 343a. As a result, the inductance in the path from the specific point P1 to the first portion 343a increases, so the amount of current flowing through the first portion 343a can be reduced. This can reduce the difference in ease of current flow between the first portion 343a and the second portion 343b. This can suppress positional bias in ease of current flow within the transistor T4.

[0065] Furthermore, the provision of the slits 52 can reduce the amount of current flowing through the first portion 343a, which reduces the risk of the wire 442 joined to the first portion 343a being damaged by heat generation, as in the first embodiment.

[0066] Furthermore, similarly to the first embodiment, when the gate electrode 342 is provided closer to the first portion 343a than to the second portion 343b, the effect of the slits 52 in reducing the amount of current flowing through the first portion 343a is particularly pronounced.

[0067] Moreover, the slit 52 is formed so as to cross the first shortest path R1 that would exist if the slit 52 were not provided. This ensures that the length of the current path from the specific point P1 to the first portion 343a is long. This ensures that the amount of current flowing through the first portion 343a is reduced.

[0068] In the illustrated example, the position of the slit 52 on the X-axis is the same as the position of the first portion 343a on the X-axis. This ensures that the current path length from the specific point P1 to the first portion 343a is long. Furthermore, the position of the slit 52 on the X-axis is located in the X1 direction further than the position of the second portion 343b on the X-axis. This ensures that the current path length from the specific point P1 to the first portion 343a is long without increasing the current path length from the specific point P1 to the second portion 343b.

[0069] In the illustrated example, one end 521 of the slit 52 is provided on an end side in the X1 direction of the conductive pattern 235, and the other end 522 of the slit 52 is located at the boundary between the first portion 343a and the third portion 343c. However, the other end 522 of the slit 52 may be located further in the X1 direction than the boundary, or may be located at a position on the X-axis of the third portion 343c.

[0070] According to the second embodiment described above, it is also possible to suppress positional bias in the ease with which a current flows within the transistor T4.

[0071] 3. Third embodiment The third embodiment of the present disclosure will be described below. In the following exemplary embodiment, for elements whose actions and functions are similar to those of the first and second embodiments, the reference numerals used in the first and second embodiments will be used and detailed descriptions thereof will be omitted as appropriate.

[0072] Fig. 8 is a plan view of a semiconductor unit 10bB of the third embodiment. This embodiment is a combination of the first and second embodiments. Specifically, as shown in Fig. 8, this embodiment is similar to the first embodiment except that the number of auxiliary wirings 51 is smaller than that in Fig. 3 and that slits 52 are provided. This embodiment is also similar to the second embodiment except that auxiliary wirings 51 are provided.

[0073] As shown in FIG. 8, the conductive pattern 235 is provided with a plurality of auxiliary wirings 51, as in the first embodiment. Therefore, the same effect as in the first embodiment can be obtained. For example, the provision of a plurality of auxiliary wirings 51 can reduce the inductance of the second shortest path R2. In addition, the conductive pattern 235 is formed with slits 52, as in the second embodiment. The provision of the slits 52 can provide the same effect as in the second embodiment. For example, the inductance in the path from the specific point P1 to the first portion 343a can be increased. Therefore, the provision of the auxiliary wirings 51 and the slits 52 can suppress positional bias in the ease of current flow in the transistor T4.

[0074] Furthermore, by providing the slits 52, even if the number of auxiliary wirings 51 is reduced compared to the number of auxiliary wirings 51 in the first embodiment, positional bias in the ease of current flow within the transistor T4 can be suppressed.

[0075] According to the third embodiment, it is also possible to suppress positional bias in the ease of current flow within the transistor T4. Moreover, according to the third embodiment, since the auxiliary wiring 51 and the slit 52 are provided, it is possible to enjoy both the effect of providing the auxiliary wiring 51 and the effect of providing the slit 52.

[0076] 4. Variations The above-described embodiments may be modified in various ways, for example as described below. In addition, the modifications may be combined as appropriate.

[0077] In the above description, each of the transistors T1 and T4 is an IGBT, but may be, for example, a MOSFET. If a MOSFET, each of the transistors T1 and T4 includes a drain electrode instead of a collector electrode and a source electrode instead of an emitter electrode. Thus, the "first main electrode" includes a collector electrode and a drain electrode, and the "second main electrode" includes an emitter electrode and a source electrode.

[0078] In the above description, the auxiliary wiring 51 is linear in plan view, but the "auxiliary wiring" may be curved in plan view. In the above description, only both ends of the auxiliary wiring 51 are connected to the conductive pattern 235, but a plurality of portions between both ends may be joined to the conductive pattern 235 by stitches. In the above description, the slit 52 is linear in plan view, but the "slit" may be curved in plan view. In addition, the "slit" may be inclined with respect to the X-axis and Y-axis.

[0079] Although the present disclosure has been described above based on the illustrated embodiments, the present disclosure is not limited thereto. In addition, the configurations of the components of the present disclosure can be replaced with any configuration that exhibits the same functions as those of the above-described embodiments, and any configuration can be added. [Explanation of symbols]

[0080] 1...semiconductor module, 10a...semiconductor unit, 10b...semiconductor unit, 10bA...semiconductor unit, 10bB...semiconductor unit, 11...heat dissipation substrate, 21...insulating substrate, 49...wire, 51...auxiliary wiring, 52...slit, 90...external connection terminal, 111...upper surface, 231...conductive pattern, 232...conductive pattern, 233...conductive pattern, 234...conductive pattern, 235...conductive pattern, 236...conductive pattern, 237...conductive pattern, 311...gate electrode, 312...emitter electrode, 321...anode electrode, 331...anode electrode, 341...collector electrode, 342...gate electrode, 343...emitter electrode, 343a...first portion, 343b...second portion, 343c...third portion, 351...cathode electrode, 352...anode electrode, 411...wire , 412...wire, 413...wire, 421...wire, 422...wire, 431...wire, 441...wire, 442...wire, 443...wire, 450...relay wiring, 451...wire, 511...first end, 512...second end, 521...one end, 522...other end, A...upper arm, B...lower arm, D1...diode, D2...diode, D3...diode, D4...diode, D5...diode, D6...diode, M...intermediate terminal, N...negative power supply terminal, P...positive power supply terminal, P1...specific point, R1...first shortest path, R2...second shortest path, S1...first surface, S2...second surface, S3...third surface, S4...fourth surface, T1...transistor, T2...transistor, T3...transistor, T4...transistor, Ts...external terminal, U...output terminal.

Claims

1. An insulating substrate; A conductive pattern on the insulating substrate; a transistor on the conductive pattern; a connection terminal located on the insulating substrate in a first direction relative to the transistor; an auxiliary wiring connected to the conductive pattern; The transistor is a first main electrode formed on a first surface facing the conductive pattern; a second main electrode formed on a second surface opposite the first surface; a control electrode located on the second surface in the first direction relative to the second main electrode, a current flows from a specific point in the conductive pattern that is located in the first direction relative to the transistor to the connection terminal via the transistor; the second main electrode includes a first portion and a second portion located in a second direction opposite to the first direction relative to the first portion, The auxiliary wiring is A first end close to the particular point; a second end proximate the transistor; The second end is closer to the second portion than the first portion. A semiconductor module comprising:

2. a slit is formed in the conductive pattern between the specific point and the first portion; The semiconductor module according to claim 1 .

3. An insulating substrate; A conductive pattern on the insulating substrate; a transistor on the conductive pattern; a connection terminal located on the insulating substrate in a first direction relative to the transistor, The transistor is a first main electrode formed on a first surface facing the conductive pattern; a second main electrode formed on a second surface opposite the first surface; a control electrode located on the second surface in the first direction relative to the second main electrode, a current flows from a specific point in the conductive pattern that is located in the first direction relative to the transistor to the connection terminal via the transistor; the second main electrode includes a first portion and a second portion located in a second direction opposite to the first direction relative to the first portion, a slit is formed between the specific point and the first portion in the conductive pattern; A semiconductor module comprising:

4. a diode located on the insulating substrate in the first direction relative to the transistor; a relay wiring electrically connecting the transistor and the diode, The diode is a cathode electrode formed on a third surface facing the conductive pattern; an anode electrode formed on a fourth surface opposite to the third surface, One end of the relay wiring is joined to the first portion, and the other end of the relay wiring is joined to the cathode electrode. The semiconductor module according to claim 1 .

5. Further comprising an external connection terminal overlapping the second portion in a plan view. The semiconductor module according to claim 1 .

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