Semiconductor Device

Abstract

To provide a semiconductor device capable of suppressing a spacing error occurring between layouts of a potential fixed cell and another adjacent cell when laying out a potential fixed cell for outputting a reference potential to a spare cell.SOLUTION: A semiconductor device includes a logic cell, a spare cell, and a potential fixing cell VFC1 that outputs a reference potential for fixing the potential of an input wiring of the spare cell, and the potential fixing cell VFC1 includes an interconnecting wire MDa, a first wiring M0b, a second wiring M0c, and an output wiring M1a, and the second wiring M0c has a power supply potential and is wired at a cell boundary between the potential fixing cell VFC1 and another adjacent cell. The first wiring M0b is wired inside the potential fixing cell VFC1. The output wiring M1a receives the power supply potential via the second wiring M0c, an interconnection wiring MDa, and the first wiring M0b, and outputs the reference potential.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a layout of a potential fixed cell for outputting a reference potential to an input wiring of a spare cell of the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a technique for preventing a shoot-through current from flowing between the drain and source of a transistor included in a spare logic cell called a spare cell. As an example of the technique, Patent Document 1 discloses a configuration in which the gate of the transistor included in the spare cell, i.e., the input wiring of the spare cell, is electrically connected to the power supply wiring of the semiconductor device.

[0003] Furthermore, when changing the design of a semiconductor device, the cost of changing the design is cheaper if the upper wiring layer away from the semiconductor substrate is revised than if the lower wiring layer closer to the semiconductor substrate is revised. For example, Patent Document 1 discloses a technique for raising the input / output wiring of an inverter cell to an upper wiring layer in a direction away from the semiconductor substrate. In other words, if the need for a design change arises during the design process of the semiconductor device and the connection state of the input / output wiring of the inverter cell is changed, the design change can be accommodated by only changing the wiring pattern in the upper wiring layer because the input / output wiring of the inverter cell has been raised. This makes it possible to reduce the manufacturing cost associated with the design change. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-114641 A Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, the power supply wiring of the semiconductor device is arranged in a lower wiring layer close to the semiconductor substrate at the cell boundary of the logic cell, the spare cell, etc. In this case, in order to reduce the manufacturing cost related to the design change, it is preferable to provide the power supply wiring connected to the input wiring of the spare cell with an output wiring pulled up in a direction away from the semiconductor substrate. That is, when the need for the design change using the spare cell arises in the design process of the semiconductor device, it is necessary to first disconnect the input wiring of the spare cell and the power supply wiring, which is performed as a through current prevention measure. At this time, if the input wiring of the spare cell and the output wiring of the power supply wiring connected to the input wiring are pulled up in a direction away from the semiconductor substrate, the input wiring of the spare cell can be separated from the power supply wiring by only changing the wiring pattern in the upper wiring layer away from the semiconductor substrate. However, if the output wiring of the power supply wiring located at the cell boundary is simply provided at a position pulled up from the power supply wiring in the upper layer direction, there is a high possibility that a spacing error will occur between the pulled up output wiring and the wiring of another adjacent cell.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] According to one embodiment, a semiconductor device includes a logic cell, a spare cell that is combined with the logic cell to configure a new logic function when a design change is made, and a voltage-fixed cell that outputs a reference voltage for fixing a voltage of an input wiring of the spare cell. The voltage-fixed cell includes an interconnection wiring, a first wiring formed in an upper layer of the interconnection wiring and connected to the interconnection wiring, a second wiring formed in an upper layer of the interconnection wiring and connected to the interconnection wiring, and an output wiring formed in an upper layer of the first wiring and connected to the first wiring. The second wiring has a power supply potential and is wired in a lower layer of the output wiring at a cell boundary between the voltage-fixed cell and another cell adjacent thereto. The first wiring is wired inside the voltage-fixed cell with respect to the second wiring. The output wiring outputs a reference voltage by receiving a power supply potential via the second wiring, the interconnection wiring, and the first wiring. Effect of the Invention

[0008] According to one embodiment, when laying out a potential fixed cell for outputting a reference potential to a spare cell, it is possible to suppress spacing errors occurring between the potential fixed cell and the layout of other adjacent cells. [Brief description of the drawings]

[0009] [Figure 1] Fig. 1(A) is a plan view showing an example of a layout of a potential clamped cell according to embodiment 1. Fig. 1(B) is a plan view showing an example of a layout of a potential clamped cell according to embodiment 1. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of a layout of the potential clamped cell according to the first embodiment. [Diagram 3] Fig. 3(A) is a plan view showing an example of a layout in which a potential fixed cell and a logic cell according to embodiment 1 are arranged adjacent to each other. Fig. 3(B) is a plan view showing an example of a layout in which a potential fixed cell and a logic cell according to embodiment 1 are arranged adjacent to each other. [Figure 4] FIG. 4 is a cross-sectional view showing an example of a layout in which a potential fixed cell and a logic cell according to the first embodiment are arranged adjacent to each other. [Diagram 5] FIG. 5 is a cross-sectional view showing an example of a layout in which a potential fixed cell and a logic cell according to a comparative example are arranged adjacent to each other. [Figure 6] FIG. 6 is a circuit diagram showing an example of an equivalent circuit of the logic cell according to the first embodiment. [Figure 7] FIG. 7 is a plan view showing an example of the overall arrangement of cells according to the first embodiment. [Figure 8] FIG. 8 is a plan view showing an example of a layout of wiring for fixing the potential of the input wiring of the spare cell according to the first embodiment. [Figure 9] FIG. 9 is a plan view showing an example of a change in layout of wiring using spare cells when metal is revised according to the first embodiment. [Figure 10]FIG. 10 is a plan view showing another example of a change in the layout of wiring using spare cells when metal is revised according to the first embodiment. [Figure 11] Fig. 11(A) is a flowchart showing an example of design of the semiconductor device according to embodiment 1. Fig. 11(B) is a flowchart showing an example of a processing procedure at the time of metal revision of the semiconductor device according to embodiment 1. [Figure 12] FIG. 12 is a plan view showing an example of the overall arrangement of cells according to the second embodiment. [Figure 13] Fig. 13(A) is a plan view showing an example of the layout of a tap cell with a potential clamping function according to embodiment 2. Fig. 13(B) is a plan view showing an example of the layout of a tap cell with a potential clamping function according to embodiment 2. [Figure 14] FIG. 14 is a cross-sectional view showing an example of a layout of a tap cell with a potential clamping function according to the second embodiment. [Figure 15] Fig. 15(A) is a plan view showing a layout of a logic cell with a potential clamping function according to embodiment 3. Fig. 15(B) is a plan view showing a layout of a logic cell with a potential clamping function according to embodiment 3. [Figure 16] FIG. 16 is a cross-sectional view showing an example of a layout of a logic cell with a potential clamping function according to the third embodiment. [Figure 17] FIG. 17 is a plan view showing an example of the overall arrangement and wiring of the cells according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is related to the other as a partial or complete modification, detail, supplementary explanation, etc. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more than or less than the specific number, unless otherwise specified or clearly limited in principle to a specific number, etc.

[0011] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be obviously not essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] In addition, the semiconductor devices constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by known integrated circuit technology such as CMOS (complementary metal oxide semiconductor transistor). Examples of circuit elements include resistors, capacitors, coils, etc.

[0013] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In addition, in all the drawings for explaining the embodiments, the same members are generally given the same reference numerals, and the repeated explanations thereof will be omitted. Furthermore, the dimensional ratios of the drawings are exaggerated for convenience of explanation, and may differ from the actual ratios. Furthermore, the wiring layer in the plane closest to the semiconductor device, such as a transistor, formed on the semiconductor substrate of the semiconductor device is an interconnection layer that is a conductor such as metal. The wiring layer above the interconnection layer is the metal 0 layer. The wiring layer above the metal 0 layer is the metal 1 layer. The wiring layer above the metal 1 layer is the metal 2 layer. The wiring layer above the metal 2 layer is the metal 3 layer. Thus, except for the lowest interconnection layer, the upper wiring layer refers to a wiring layer with a higher metal layer number than the wiring layer to be compared. Therefore, the metal layers in the plane in the direction away from the semiconductor device have metal layer numbers that increase in order. In addition, for convenience of explanation, an XYZ orthogonal coordinate system is introduced. One direction and the other direction perpendicular to the plane parallel to the drawing, and a direction perpendicular to the drawing are expressed using the X-axis direction, the Y-axis direction, and the Z-axis direction.

[0014] (Embodiment 1) <Configuration of potential fixing cell of semiconductor device> 1(A) and 1(B) are plan views showing an example of the layout of a potential clamped cell according to embodiment 1. Fig. 1(A) shows the upper wiring portion of the potential clamped cell. Fig. 1(B) shows the lower wiring portion of the potential clamped cell. The length of the potential clamped cell VFC1 in the X-axis direction is lb, and the length of the potential clamped cell VFC1 in the Y-axis direction is la. In addition, in the XY plane, the dashed line AA in Fig. 1(A) overlaps with the dashed line BB in Fig. 1(B).

[0015] The potential fixed cell VFC1 (UPPER) in FIG. 1(A) includes a first wiring M0b, a via V0a, a second wiring M0c, a third wiring M0a, and an output wiring M1a. The first wiring M0b, the second wiring M0c, and the third wiring M0a are formed in the metal 0 layer. The output wiring M1a is formed in the metal 1 layer, which is the layer above the metal 0 layer. The via V0a is formed between the metal 0 layer and the metal 1 layer. The via V0a electrically connects the first wiring M0b and the output wiring M1a. Note that the metal 1 layer is located in the +Z-axis direction from the metal 0 layer in FIG. 1(A). The second wiring M0c is a GND wiring having a GND potential. The third wiring M0a is a VDD wiring having a VDD potential. The VDD wiring and the GND wiring are collectively called power supply wiring. Therefore, the second wiring and the third wiring are also called the first power supply wiring and the second power supply wiring. The first power supply wiring and the second power supply wiring are arranged at the cell boundary of the cells included in the semiconductor device. The first power supply wiring supplies a GND potential, i.e., a first power supply potential, to the cells included in the semiconductor device. The second power supply wiring supplies a VDD potential, i.e., a second power supply potential, to the cells included in the semiconductor device.

[0016] 1B includes an interconnection line MDa, a via VDa, and a via VDb. The interconnection line MDa is electrically connected to the vias VDa and VDb formed in the +Z-axis direction from the interconnection line MDa.

[0017] The potential-fixed cell is a cell that outputs a reference potential for suppressing a through current flowing through a transistor included in a spare cell. Specifically, the output wiring of the potential-fixed cell is connected to the input wiring (gate of the transistor) of the spare cell, and supplies a potential (reference potential) corresponding to the first power supply potential or the second power supply potential. This fixes the potential of the input wiring (gate of the transistor) of the spare cell to a predetermined potential, suppressing the through current from flowing through the spare cell. In FIG. 1, the output wiring M1a of the potential-fixed cell VFC1 outputs a potential (reference potential) corresponding to the GND potential. The output wiring M1a of the potential-fixed cell VFC1 is connected to the gate (input wiring) of a transistor included in a spare cell (not shown), and the potential of the input wiring of the spare cell is fixed by the reference potential output from the potential-fixed cell VFC1.

[0018] Fig. 2 is a cross-sectional view showing an example of the layout of the voltage clamped cell VFC1 according to embodiment 1. Fig. 2 shows a cross section taken along dashed line AA in Fig. 1(A) and dashed line BB in Fig. 1(B). Therefore, Fig. 2 includes the cross section taken along dashed line AA in Fig. 1(A) on the upper layer side and the cross section taken along dashed line BB in Fig. 1(B) on the lower layer side.

[0019] In Fig. 2, interconnection wiring MDa made of metal or the like is electrically connected to first wiring M0b in the metal 0 layer through a via VDa. The first wiring M0b in the metal 0 layer is electrically connected to output wiring M1a in the metal 1 layer through a via V0a. Also, in Fig. 2, interconnection wiring MDa is electrically connected to second wiring M0c in the metal 0 layer through a via VDb. As described above, the second wiring M0c is a GND wiring.

[0020] Therefore, as shown by the arrow in FIG. 2, the second wiring M0c of the metal 0 layer included in the potential fixed cell VFC1 of the semiconductor device according to the first embodiment is electrically connected to the output wiring M1a of the metal 1 layer. That is, the second wiring M0c, which is a GND wiring, is electrically connected to the interconnect wiring MDa through the via VDb. The interconnect wiring MDa is also electrically connected to the first wiring M0b through the via VDa. Furthermore, the first wiring M0b is electrically connected to the output wiring M1a through the via V0a. In this way, the output wiring M1a is electrically connected to the GND wiring.

[0021] Therefore, the output wiring M1a of the potential fixed cell VFC1 according to the first embodiment is formed in the metal 1 layer via the wiring M0b. At this time, it is possible to draw out wiring in a layer higher than the output wiring M1a, for example, in the metal 2 layer or the metal 3 layer. That is, the output wiring M1a can be electrically connected to the input wiring connected to the gate of the transistor of the spare cell (not shown) in the metal 2 layer or higher.

[0022] In the above embodiment 1, the interconnection wiring MDa is electrically connected to the GND wiring. However, the interconnection wiring MDa can also be electrically connected to the third wiring M0a through another via (not shown) instead of the second wiring M0c. The third wiring M0a is a VDD wiring having a VDD potential. When the interconnection wiring MDa is electrically connected to the third wiring M0a, the output wiring M1a is electrically connected to the VDD wiring and outputs a reference potential corresponding to the VDD potential.

[0023] Furthermore, the via VDa, the first wiring M0b, the via V0a, and the output wiring M1a can be moved in the Y-axis direction on the interconnection wiring MDa within a range of lc while maintaining the electrical connection relationship.

[0024] <Configuration of potential fixing cells and logic cells (in the case of inverters) in semiconductor devices> 3A and 3B are plan views showing an example of a layout in which the potential fixed cell and the logic cell according to the first embodiment are arranged adjacent to each other in the Y-axis direction. FIG. 3A shows an upper layer part of the wiring in which the potential fixed cell and the logic cell are formed adjacent to each other, and FIG. 3B shows a lower layer part. The length of the potential fixed cell VFC1 and the logic cell LC1 in the X-axis direction is le. The total length of the potential fixed cell VFC1 and the logic cell LC1 in the Y-axis direction is ld. In the XY plane, the dashed line CC in FIG. 3A overlaps with the dashed line GG in FIG. 3B. The logic cell can have various functions, and the logic cell LC1 according to the first embodiment has a function as an inverter. The circuit configuration of the logic cell LC1 according to the first embodiment as an inverter will be described later.

[0025] Incidentally, since the plan views of the potential fixed cell VFC1 in FIG. 3(A) and FIG. 3(B) have been explained in FIG. 1(A) and FIG. 1(B), detailed explanation thereof will be omitted.

[0026] Logic cell LC1(UPPER) in FIG. 3(A) includes wiring M0c', wiring M0d, wiring M0e, wiring M0f, wiring M0g, input wiring M1g, output wiring M1b, via V0b, via V0c, and via V0f. Wiring M0c', wiring M0d, wiring M0e, wiring M0f, and wiring M0g are formed in the metal 0 layer. Input wiring M1g and output wiring M1b are formed in the metal 1 layer, which is the layer above the metal 0 layer. Vias V0b, via V0c, and via V0f are formed between the metal 0 layer and the metal 1 layer.

[0027] The wiring M0d in the metal 0 layer of the logic cell LC1 in FIG. 3A is electrically connected to the output wiring M1b of the logic cell LC1 through a via V0b. The wiring M0f in the metal 0 layer of the logic cell LC1 is also electrically connected to the output wiring M1b of the logic cell LC1 through a via V0c. The wiring M0e in the metal 0 layer of the logic cell LC1 is electrically connected to the input wiring M1g, which is the input wiring of the logic cell LC1, through a via V0f. The second wiring M0c and wiring M0c' in the metal 0 layer are GND wiring. The dashed line between the second wiring M0c and wiring M0c' indicates the cell boundary. The wiring M0g in the metal 0 layer is a VDD wiring.

[0028] The input wiring M1g of the logic cell LC1 is an input terminal of the logic cell LC1 that functions as an inverter, and the output wiring M1b of the logic cell LC1 is an output terminal of the logic cell LC1 that functions as an inverter.

[0029] In the region UR1 of the logic cell LC1 (LOWER) in FIG. 3B, two NMOS transistors connected in parallel are formed. In the region LR1 of the logic cell LC1 (LOWER) in FIG. 3B, two PMOS transistors connected in parallel are formed. The potential fixed cell VFC1 and the logic cell LC1 are formed on a semiconductor substrate (not shown). The semiconductor substrate includes a P-type well (P-type semiconductor layer) formed by doping with P-type impurities and an N-type well (N-type semiconductor layer) formed by doping with N-type impurities. The region UR1 of the logic cell LC1 is included in the region of the P-type well (not shown), and the region LR1 of the logic cell LC1 is included in the region of the N-type well (not shown). Therefore, the two NMOS transistors of the logic cell LC1 are formed in the region of the P-type well, and the two PMOS transistors of the logic cell LC2 are formed in the region of the N-type well.

[0030] The region UR1 of the logic cell LC1 in FIG. 3B includes gate electrodes g1 and g2, an N-type diffusion region ODa, an interconnection wiring MDb, and a via VDc. In the region UR1, the gate electrodes g1 and g2 are formed on an upper layer of a P-type well (not shown) via an insulating layer. The N-type diffusion region ODa is formed on the surface layer of the P-type well (not shown) by doping with an N-type impurity, and is formed on both sides of the gate electrodes g1 and g2 in the XY plane. That is, the N-type diffusion region ODa is disposed on both sides of the region of the P-type well covered by the gate electrodes g1 and g2. The N-type diffusion region ODa functions as the drain (D) or source (S) of the NMOS transistor. The N-type diffusion region ODa located at a position sandwiched between the gate electrodes g1 and g2 is electrically connected to the interconnection wiring MDb of the interconnection layer located on the upper layer of the N-type diffusion region ODa. The via VDc electrically connects the interconnection wiring MDb and the wiring M0d in FIG. 3A. Therefore, the N-type diffusion region ODa located between the gate electrodes g1 and g2 functions as the drain (D) of the NMOS transistor and is connected to the output of the inverter (logic cell). On the other hand, the N-type diffusion region ODa located not between the gate electrodes g1 and g2 is electrically connected to the wiring M0c' through the via. Therefore, the N-type diffusion region ODa located not between the gate electrodes g1 and g2 functions as the source (S) of the NMOS transistor and receives the GND potential.

[0031] The region LR1 of the logic cell LC1 in FIG. 3B includes gate electrodes g1 and g2, a P-type diffusion region ODb, an interconnection wiring MDc, and a via VDd. In the region LR1, the gate electrodes g1 and g2 are formed on an upper layer of an N-type well (not shown) via an insulating layer. The P-type diffusion region ODb is formed on the surface layer of the N-type well (not shown) by doping with P-type impurities, and is formed on both sides of the gate electrodes g1 and g2 in the XY plane. That is, the P-type diffusion region ODb is disposed on either side of the region of the N-type well covered by the gate electrodes g1 and g2. The P-type diffusion region ODb functions as the drain (D) or source (S) of a PMOS transistor. The P-type diffusion region ODb located at a position sandwiched between the gate electrodes g1 and g2 is electrically connected to the interconnection wiring MDc of the interconnection layer located on the upper layer of the P-type diffusion region ODb. The via VDd electrically connects the interconnection wiring MDc and the wiring M0f in FIG. 3A. Therefore, the P-type diffusion region ODb located between the gate electrodes g1 and g2 functions as the drain (D) of the PMOS transistor and is connected to the output of the inverter (logic cell). On the other hand, the P-type diffusion region ODb located not between the gate electrodes g1 and g2 is electrically connected to the wiring M0g through a via. Therefore, the P-type diffusion region ODb located not between the gate electrodes g1 and g2 functions as the source (S) of the PMOS transistor and receives the VDD potential.

[0032] 3, the gate electrode g1 and the gate electrode g2 are a common gate electrode for the N-type transistor and the P-type transistor. The gate electrode g1 and the gate electrode g2 are connected to the input wiring M1g through a via and a wiring M0e.

[0033] 4 is a cross-sectional view showing an example of a layout in which the potential clamped cell and logic cell of FIG. 3(A) and FIG. 3(B) according to the first embodiment are arranged adjacent to each other in the Y-axis direction. FIG. 4 shows a cross section taken along dashed line CC in FIG. 3(A) and dashed line GG in FIG. 3(B). Therefore, FIG. 4 includes the dashed line CC cross section of FIG. 3 on the upper layer side and the dashed line GG cross section on the lower layer side. In addition, the cross section of the potential clamped cell VFC1 of FIG. 4 is equivalent to the cross section of the potential clamped cell VFC1 of FIG. 2, and therefore a detailed description thereof will be omitted. The cross section of the logic cell LC1 of FIG. 4 is a cross section of an output portion of an inverter composed of an NMOS transistor and a PMOS transistor.

[0034] The N-type diffusion region ODa functioning as the drain (D) of the NMOS transistor in FIG. 4 is electrically connected to an interconnection wiring MDb. The interconnection wiring MDb is electrically connected to a wiring M0d through a via VDc. The wiring M0d is electrically connected to an output wiring M1b through a via V0b. Furthermore, the P-type diffusion region ODb functioning as the drain (D) of the PMOS transistor is electrically connected to an interconnection wiring MDc. The interconnection wiring MDc is electrically connected to a wiring M0f through a via VDd. The wiring M0f is electrically connected to an output wiring M1b through a via V0c. The wiring M0d and the wiring M0f are wired in the metal 0 layer. The output wiring M1b is wired in the metal 1 layer.

[0035] Here, as shown in Fig. 4, the distance between the output wiring M1a of the potential fixed cell VFC1 and the output wiring M1b of the logic cell LC1 in the Y-axis direction is set to distance l2. If the distance l2 is short, there is a risk of a design rule violation (spacing error). In other words, it is important to ensure a sufficient distance between the output wiring of the potential fixed cell and the wiring of the adjacent logic cell. In Fig. 3(A), the location corresponding to the distance l2 in Fig. 4 is indicated by region SR1.

[0036] Fig. 5 shows an example (comparative example) of a layout in which the probability of occurrence of a design rule violation (spacing error) is high. The potential fixed cell in Fig. 5 (left side of Fig. 5) has an output wiring M1j that outputs a reference potential to the input wiring of a spare cell (not shown). As shown in Fig. 5, the output wiring Mij is formed above the second wiring (GND wiring) M0c of the metal 0 layer. Specifically, the output wiring M1j is formed above the GND wiring M0c from the GND wiring M0c through a via V0j.

[0037] Here, as shown in Fig. 5, the distance between the output wiring Mj1 of the potential clamp cell and the output wiring M1b of the logic cell LC1 is set as a distance l1. The potential clamp cell shown in Fig. 5 can easily form the output wiring M1j that outputs a reference potential to a spare cell (not shown) with a simple structure. However, the distance l1 in Fig. 5 is shorter than the distance l2 in Fig. 4, and the probability of occurrence of a design rule violation (spacing error) increases.

[0038] In this way, the potential fixed cell of the semiconductor device according to the first embodiment has an output wiring for outputting a reference potential to the input wiring of the spare cell at a position raised in a direction away from the semiconductor substrate. Therefore, even if a design change using the spare cell is required for logic change or logic correction during the design process of the semiconductor device, the design change can be accommodated by only changing the wiring pattern of the upper wiring layer located away from the semiconductor substrate. Furthermore, the potential fixed cell of the semiconductor device according to the first embodiment has an output wiring for outputting a reference potential at a position away from the cell boundary, that is, at a position moved to the inside of the potential fixed cell, rather than directly above the power supply wiring located at the cell boundary. As a result, the potential fixed cell of the semiconductor device according to the first embodiment can suppress the occurrence of a spacing error between the potential fixed cell and another cell (logic cell) adjacent thereto, compared to the potential fixed cell according to the comparative example in which the output wiring is located directly above the power supply wiring located at the cell boundary.

[0039] <Equivalent circuit of logic cell LC1 in Figure 3> Fig. 6 is an example of an equivalent circuit diagram of the logic cell LC1 according to embodiment 1. As described above, the logic cell LC1 shown in Fig. 3(A) and Fig. 3(B) is a logic cell in which two inverters each formed by a combination of an NMOS transistor and a PMOS transistor are arranged in parallel.

[0040] The gate electrode g1 functions as a common gate electrode for the gate of the NMOS transistor and the gate of the PMOS transistor. The gate electrode g2 also functions as a common gate electrode for the gate of another NMOS transistor and the gate of another PMOS transistor. The input wiring M1g, which is the input wiring of the logic cell, is electrically connected to the gate electrodes g1 and g2. The drain (D) of the NMOS transistor and the drain (D) of the PMOS transistor are electrically connected to each other. The output wiring M1b is electrically connected to the drain (D) of the NMOS transistor and the drain (D) of the PMOS transistor. The source (S) of the NMOS transistor is connected to the wiring M0c', which is a GND wiring. The source (S) of the PMOS transistor is connected to the wiring M0g, which is a VDD wiring.

[0041] <Example of overall planar layout of cells> FIG. 7 is a plan view showing an example of the overall arrangement of cells according to the first embodiment. That is, FIG. 7 is a view showing an example of the planar arrangement of various cells included in the semiconductor device 200a according to the first embodiment. The spare cells SPC1, SPC2, SPC3, SPC4, SPC5, and the logic cell LC1 shown in FIG. 3 and FIG. 4 surround the potential fixed cell VFC1 shown in FIG. 1. The logic cell LC1 is a logic cell having an inverter function. In addition, the spare cell can be various types of logic cells, but in the first embodiment, it is assumed that the spare cell is a logic cell having an inverter function like the logic cell LC1. The potential fixed cell VFC1 in FIG. 7 and the upper layer wiring of the cells around the potential fixed cell VFC1 are enlarged and shown in FIG. 8.

[0042] Fig. 8 is a plan view showing an example of the layout of wiring for fixing the potential of the input wiring of the spare cell according to embodiment 1. Specifically, Fig. 8 shows wiring in the metal 1 layer to the metal 3 layer and power supply wiring in the metal 0 layer of each of the potential fixed cell VFC1, logic cell LC1, and spare cells SPC1, SPC2, SPC3, SPC4, and SPC5 in Fig. 7.

[0043] The spare cell SPC1 includes an input wiring M1s1i, potential fixing wiring M2c, M3a, and power supply wiring M0a, M0e. The input wiring M1s1i is wired in the metal 1 layer. The potential fixing wiring M2c is wired in the metal 2 layer. The potential fixing wiring M3a is wired in the metal 3 layer. The power supply wiring M0a, M0e are wired in the metal 0 layer. The input wiring M1s1i is electrically connected to the potential fixing wiring M2c through a via. The potential fixing wiring M2c is electrically connected to the potential fixing wiring M3a through a via. The potential fixing wiring M3a is a wiring electrically connected to the output wiring M1a of the potential fixing cell VFC1.

[0044] The spare cell SPC2 includes an input wiring M1s2i, potential fixing wiring M2a, M3a, and power supply wiring M0a, M0c. The input wiring M1s2i is wired in the metal 1 layer. The potential fixing wiring M2a is wired in the metal 2 layer. The potential fixing wiring M3a is wired in the metal 3 layer. The power supply wiring M0a, M0c are wired in the metal 0 layer. The input wiring M1s2i is electrically connected to the potential fixing wiring M2a through a via. The potential fixing wiring M2a is electrically connected to the potential fixing wiring M3a through a via.

[0045] Descriptions of spare cells SPC3 to SPC5, potential fixed cell VFC1, and logic cell LC1 that overlap with other cells will be omitted.

[0046] The spare cell SPC3 includes an input wiring M1s3i, potential fixing wiring M2b, M3a, and power supply wiring M0c, M0d. The input wiring M1s3i is wired in the metal 1 layer. The potential fixing wiring M2b is wired in the metal 2 layer. The power supply wiring M0d is wired in the metal 0 layer. The input wiring M1s3i is electrically connected to the potential fixing wiring M2b through a via. The potential fixing wiring M2b is electrically connected to the potential fixing wiring M3a through a via.

[0047] The spare cell SPC4 includes an input wiring M1s4i, potential fixing wiring M2b, M3a, and power supply wiring M0c, M0d. The input wiring M1s4i is wired in the metal 1 layer. The input wiring M1s4i is electrically connected to the potential fixing wiring M2b through a via. The potential fixing wiring M2b is electrically connected to the potential fixing wiring M3a through a via.

[0048] The spare cell SPC5 includes an input line M1s5i, a potential fixing line M2a, and power supply lines M0a and M0c. The input line M1s5i is laid on the metal 1 layer. The input line M1s5i is electrically connected to the potential fixing line M2a through a via.

[0049] The logic cell LC1 includes an output line M1l1o, an input line M1g, and power supply lines M0a and M0e. The output line M1l1o and the input line M1g are laid out on the metal 1 layer.

[0050] The potential fixed cell VFC1 includes an output wiring M1a, a potential fixed wiring M2a, and power supply wirings M0a and M0c. The output wiring M1a is electrically connected to the potential fixed wiring M2a through a via. The output wiring M1a is electrically connected to the power supply wiring M0c that supplies a power supply potential through an interconnection wiring (not shown).

[0051] As described above, the input wiring of each of the spare cells SPC1, SPC2, SPC3, SPC4, and SPC5 is electrically connected to the output wiring M1a of the potential fixed cell VFC1 via the potential fixed wiring. Therefore, the input wiring of each of the spare cells SPC1, SPC2, SPC3, SPC4, and SPC5 is electrically connected to the power supply wiring that supplies the power supply potential. In addition, the power supply wirings M0a, M0c, M0d, and M0e are arranged on the cell boundary and extend in the X-axis direction.

[0052] 8, the distance between the output wiring M1a of the potential fixed cell VFC1 and the input wiring M1s4i of the spare cell SPC4 adjacent to the potential fixed cell VFC1 is a distance l3, which is a distance that can suppress the occurrence of a spacing error.

[0053] In the layout of FIG. 8, a state of modification of the mask pattern when a metal change occurs for connecting the spare cell SPC1 to the logic cell LC1 will be described with reference to FIGS.

[0054] <An example of mask pattern change when metal is revised> Fig. 9 is a plan view showing an example of a layout change of wiring using a spare cell at the time of metal revision according to the first embodiment. Specifically, Fig. 9 shows a wiring change in which the input wiring M1s1i of the spare cell SPC1 is connected to the output wiring M1l1o of the logic cell LC1. That is, the connection destination of the input wiring M1s1i of the spare cell SPC1 in Fig. 8 is changed from the output wiring M1a of the potential fixed cell VFC1 to the output wiring M1l1o of the logic cell LC1.

[0055] Therefore, it is necessary to cut off the electrical connection between the input wiring M1s1i of the spare cell SPC1 and the output wiring M1a of the potential fixed cell VFC1. The wiring layer in which the electrical connection is cut off is preferably an upper metal layer in which the change cost is lower. In this embodiment, the electrical connection between the input wiring M1s1i of the spare cell SPC1 and the output wiring M1a of the potential fixed cell VFC1 is electrically cut off by not using part of the wiring in the metal 3 layer.

[0056] Specifically, the potential fixing wiring M3a in the metal 3 layer in the region GR1 in Fig. 9 is left, and the potential fixing wiring M3a in the metal 3 layer in the other regions is removed. Then, in the region GR2, the input wiring M1s1i of the spare cell SPC1 is electrically connected to the output wiring M1l1o of the logic cell LC1 via the potential fixing wiring M2c' in the metal 2 layer.

[0057] <Another example of mask change when metal is revised> Fig. 10 is a plan view showing another example of a change in layout of wiring using spare cells at the time of metal revision according to the first embodiment. Specifically, Fig. 10 is a diagram in which the connection destination of the input wiring M1s1i connected to the gate of the transistor of the spare cell SPC1 is changed from the output wiring M1a of the potential fixed cell VFC1 to the output wiring M1l1o of the logic cell LC1, similar to Fig. 9. Fig. 10 differs from Fig. 9 in that the potential fixed wiring M3a of the metal 3 layer is not deleted, the potential fixed wiring M2c of the metal 2 layer in the region GR3 is removed, and the input wiring M1s1i is electrically connected to the output wiring M1l1o via the potential fixed wiring M2d of the metal 2 layer.

[0058] <An example of semiconductor device design> Fig. 11(A) is a flowchart showing an example of the design of the semiconductor device according to embodiment 1. Note that the flowchart of Fig. 11(A) can also be applied to the design of the semiconductor device according to embodiment 2 and embodiment 3 described below.

[0059] In step S1001, RTL (Register Transfer Level) design is performed. The RTL is created based on the design specifications of the semiconductor device. The RTL is written using a hardware description language.

[0060] In step S1002, logic synthesis is performed using an RTL source file written in a hardware description language.

[0061] In step S1003, a netlist of logic gates and transistors is generated using the results of logic synthesis and a cell library.

[0062] In step S1004, the netlist is input to a physical placement and wiring tool to perform physical placement and wiring. Here, the placement and wiring of the voltage-fixed cells described above is also performed. That is, the output wiring of the voltage-fixed cells is formed on the metal 1 layer or higher from the GND wiring on the metal 0 layer via the interconnection wiring on a layer lower than the metal 0 layer.

[0063] In step S1005, netlist and placement information is generated based on the results of the physical placement and routing process.

[0064] In step S1006, mask pattern information is generated using the netlist and placement information.

[0065] <An example of processing procedures for metal revision of semiconductor device> Fig. 11(B) is a flowchart showing an example of a processing procedure at the time of metal revision of the semiconductor device according to embodiment 1. Note that the flowchart in Fig. 11(B) can also be applied to the design of the semiconductor device according to embodiment 2 and embodiment 3 described later.

[0066] In step S1011, logic change / modification occurs. In this case, circuit change points are extracted, and required functional cells are extracted.

[0067] In step S1012, connections and rewiring between the cells are performed using a physical placement and wiring tool.

[0068] In step S1013, a netlist and placement information is generated based on the results of the connection and rewiring processes between the cells.

[0069] In step S1014, mask pattern information is generated using the netlist and placement information.

[0070] Thus, according to the first embodiment, the output wiring of the potential-fixed cell, which outputs a reference potential for fixing the potential of the input wiring of the spare cell so that no through current flows through the spare cell, is formed at a position away from the cell boundary, that is, at a position moved inside the potential-fixed cell. As a result, compared with the case where the output wiring is formed directly above the power supply wiring located at the cell boundary, the output wiring of the potential-fixed cell according to the first embodiment can secure a sufficient space with the wiring of other cells adjacent to the potential-fixed cell and can maintain a distance equal to or greater than the minimum wiring interval distance specified by the design rule. That is, the output wiring of the potential-fixed cell according to the first embodiment can suppress the cost associated with mask changes of the wiring pattern when metal is revised, and can suppress the occurrence of spacing errors before and after the metal revision.

[0071] (Embodiment 2) <Configuration of a Semiconductor Device with a Tap Cell Added with a Function of a Potential Fixing Cell> The area of ​​the semiconductor device increases due to the potential clamping cell according to the first embodiment. On the other hand, the tap cell is arranged in the semiconductor device as a cell for outputting a power supply potential to a well (semiconductor layer) in which the logic cell is arranged. Therefore, by adding the function of the potential clamping cell to the tap cell according to the first embodiment, in other words, by adding the function of the tap cell to the potential clamping cell according to the first embodiment, it is possible to suppress an increase in the area of ​​the semiconductor device. Therefore, in the second embodiment, a semiconductor device in which the function of the potential clamping cell is added to the tap cell so as to suppress an increase in the area of ​​the semiconductor device, in other words, a semiconductor device in which the function of the tap cell is added to the potential clamping cell, will be described below. A tap cell VFTAP1 with a potential clamping function, which is an example in which the function of the potential clamping cell is added to the tap cell, will be described below.

[0072] Fig. 12 is a plan view showing an example of the overall arrangement of cells according to the second embodiment. Specifically, Fig. 12 is a plan view showing an example of the formation position of the potential clamping tap cell VFTAP1 in the semiconductor device 200b. In Fig. 12, the tap cells are arranged adjacent to each other in the Y-axis direction, and the adjacent tap cells are arranged at regular intervals in the X-axis direction. This arrangement of the tap cells makes it possible to reduce the variation in the power supply potential to the logic cells.

[0073] The arrangement of the tap cells is not limited to that shown in Fig. 12, and one or more tap cells may be arranged in an island-like arrangement. The arrangement density of the tap cells may be increased around logic cells that consume a relatively large amount of power. In other words, the tap cells are arranged at a predetermined constant or variable density.

[0074] In addition, the spare cells whose potentials should be fixed are also arranged at a predetermined constant or variable density. Therefore, there is a possibility that the arrangement density of the tap cells and the arrangement density of the spare cells will be the same or close to each other. In such a case, if the tap cell is changed to the tap cell VFTAP1 with potential fixing function, the tap cell VFTAP1 with potential fixing function is arranged efficiently. As described above, the tap cell VFTAP1 with potential fixing function can suppress an increase in the area of ​​the semiconductor device 200b.

[0075] 12, tap cell row interval b1 indicates the distance between tap cell row TC1 and tap cell row TC2 in the X-axis direction, and tap cell row interval b2 indicates the distance between tap cell row TC2 and tap cell row TC23 in the X-axis direction.

[0076] 13(A) and 13(B) are plan views showing an example of the layout of a tap cell with potential clamping function according to embodiment 2. Fig. 13(A) shows the layout of the upper layer side of the tap cell with potential clamping function, and Fig. 13(B) shows the layout of the lower layer side of the tap cell with potential clamping function. Therefore, in the XY plane, the dashed dotted line FF in Fig. 13(A) overlaps with the dashed dotted line EE in Fig. 13(B). The length of the tap cell with potential clamping function VFTAP1 in the X-axis direction is lg, and the length in the Y-axis direction is lf.

[0077] The tap cell VFTAP1(UPPER) with potential fixing function in FIG. 13(A) includes a first wiring M0i, a second wiring M0j, a third wiring M0h, an output wiring M1c, and a via V0d. The first wiring M0i, the second wiring M0j, and the third wiring M0h are formed in the metal 0 layer. The output wiring M1c is formed in the metal 1 layer, which is the layer above the metal 0 layer. The via V0d is formed between the metal 0 layer and the metal 1 layer. The via V0d electrically connects the first wiring M0i and the output wiring M1c. The second wiring M0j is a GND wiring having a GND potential. The third wiring M0h is a VDD wiring having a VDD potential.

[0078] The tap cell VFTAP1 (LOWER) with potential fixing function in FIG. 13(B) has an NWELL (N-type well, N-type semiconductor layer) and a PWELL (P-type well, P-type semiconductor layer). The region of the NWELL includes an N-type diffusion region ODc, an interconnection wiring MDd, and a via VDe. The N-type diffusion region ODc is formed on the surface layer of the NWELL by doping with an N-type impurity. The N-type impurity concentration of the N-type diffusion region ODc is set to be higher than the N-type impurity concentration of the NWELL. A part of the interconnection wiring MDd of the interconnection layer is formed on the N-type diffusion region ODc, and the interconnection wiring MDd is electrically connected to the NWELL through the N-type diffusion region ODc. The via VDe is located between the interconnection layer and the metal 0 layer. The via VDe electrically connects the interconnection wiring MDd to the third wiring M0h in FIG. 13(A).

[0079] The PWELL includes a P-type diffusion region ODd, an interconnection wiring MDe, a via VDf, and a via VDg. The P-type diffusion region ODd is formed on the surface layer of the PWELL by doping with a P-type impurity. The P-type impurity concentration of the P-type diffusion region ODd is set to be greater than the P-type impurity concentration of the PWELL. A part of the interconnection wiring MDe of the interconnection layer is formed on the P-type diffusion region Odd, and the interconnection wiring MDe is electrically connected to the PWELL through the P-type diffusion region ODd. The via VDg and the via VDf are located between the interconnection layer and the metal 0 layer. The via VDg electrically connects the interconnection wiring MDe to the second wiring M0j of FIG. 13(A). The via VDf electrically connects the interconnection wiring MDe to the first wiring M0i of FIG. 13(A).

[0080] Fig. 14 is a cross-sectional view showing an example of the layout of a tap cell with a potential clamping function according to embodiment 2. Fig. 14 shows cross sections taken along dashed line FF in Fig. 13(A) and dashed line EE in Fig. 13(B). Therefore, Fig. 14 includes the FF cross section in Fig. 13(A) on the upper layer side and the EE cross section in Fig. 13(B) on the lower layer side.

[0081] Region R1 in FIG. 14 includes the function of a potential fixing cell and the function of a tap cell. Region R1 includes a P-type diffusion region ODd, an interconnection wiring MDe, a first wiring M0i, a second wiring M0j, an output wiring M1c, a via VDf, a via VDg, and a via V0d. The interconnection wiring MDe is electrically connected to the P-type diffusion region ODd. The first wiring M0i and the second wiring M0j are formed in the metal 0 layer, which is the upper layer of the interconnection layer. The output wiring M1c is formed in the metal 1 layer, which is the upper layer of the metal 0 layer. The via V0d is formed between the metal 0 layer and the metal 1 layer.

[0082] The via VDg electrically connects the second wiring M0j and the interconnection wiring MDe. The second wiring M0j is a GND wiring. The P-type diffusion region ODd is electrically connected to the PWELL. Therefore, the GND potential is supplied from the second wiring M0j to the PWELL through the P-type diffusion region ODd and the interconnection wiring MDe. That is, in the region R1 of FIG. 14, a function as a tap cell, that is, a function of supplying a power supply potential to the PWELL, is realized. The via VDf electrically connects the first wiring M0i and the interconnection wiring MDe. The via V0d electrically connects the first wiring M0i and the output wiring M1c. Therefore, the output wiring M1c is electrically connected to the second wiring M0j, which is a GND wiring, through the first wiring M0i and the interconnection wiring MDe. That is, in the region R1 of FIG. 14, a function as a potential fixed cell is realized.

[0083] 14, only the function as a tap cell, that is, the function of supplying a power supply potential to the NWELL, is realized. Specifically, the third wiring M0h is connected to the NWELL through the via VDe, the interconnection wiring MDd, and the N-type diffusion region ODc. Therefore, the VDD potential is supplied to the NWELL from the third wiring M0h.

[0084] The output wiring M1c in the metal 1 layer of the region R1 is a wiring to be connected to the input wiring of a spare cell (not shown) in the layer above the output wiring M1c. As shown in Fig. 14, the distance between the output wiring M1c in the metal 1 layer and the wiring in the metal 1 layer of an adjacent cell is indicated by a distance l4. As with the potential clamping cell according to the first embodiment, the tap cell with potential clamping function according to the second embodiment can also ensure the distance l4 that makes it possible to suppress the occurrence of spacing errors.

[0085] As described above, according to the tap cell with potential fixing function of the second embodiment, the region R1 of the tap cell is a region where the function of fixing the potential is realized, and therefore the same effect as that of the first embodiment can be achieved. In addition, the function of fixing the potential can be realized within the region of the tap cell. Therefore, the semiconductor device of the second embodiment can also achieve space saving compared to the semiconductor device of the first embodiment.

[0086] In the above-mentioned second embodiment, the configuration in which the function of the potential fixing cell is added to the part that supplies the GND potential to the PWELL has been described. However, the function of the potential fixing cell may be added to the part that supplies the VDD potential to the NWELL. In that case, the via VDf is connected to the interconnection wiring MDd, not the interconnection wiring MDe. With this configuration, the third wiring M0h is connected not only to the NWELL but also to the output wiring M1c through the interconnection wiring MDd. As a result, the output wiring M1c outputs a reference potential corresponding to the VDD potential.

[0087] In the above-mentioned second embodiment, the tap cell VFTAP1 with the potential clamping function is described, in which the function of the potential clamping cell according to the first embodiment is added to the tap cell. However, the function of the tap cell may be added to the potential clamping cell according to the first embodiment. In that case, for example, it is possible to reduce the number of tap cells that should be originally arranged in the semiconductor device. In addition, when the number of tap cells that should be originally arranged in the semiconductor device is not reduced, the well potential of the logic cell can be further stabilized by arranging the potential clamping cell with the tap cell function.

[0088] (Embodiment 3) <Configuration when a function for fixing potential is added to a logic cell of a semiconductor device> The logic cell according to the third embodiment is a logic cell with a potential fixing function, which is obtained by adding a function of fixing a potential to a logic cell. The semiconductor device including the logic cell with the potential fixing function of the third embodiment can reduce the area of ​​the semiconductor device compared to the semiconductor device according to the first embodiment, that is, the case where a fixed potential cell is arranged in the semiconductor device separately from the logic cell.

[0089] 15(A) and 15(B) are plan views showing an example of the layout of the logic cell with potential clamping function according to the third embodiment. Fig. 15(A) shows the layout of the upper layer side of the logic cell with potential clamping function, and Fig. 15(B) shows the layout of the lower layer side of the logic cell with potential clamping function. Therefore, in the XY plane, the dashed dotted line HH in Fig. 15(A) overlaps with the dashed dotted line II in Fig. 15(B). The length of the logic cell with potential clamping function VFLC1 in the X-axis direction is lj, and the length in the Y-axis direction is li.

[0090] As shown in FIG. 15B, the logic cell VFLC1 with potential clamping function is a logic cell in which six inverters are connected in parallel. Gate electrodes g4 to g9 indicate six gate electrodes. Note that the region R4 of the logic cell VFLC1 (LOWER) with potential clamping function in FIG. 15B is included in the region of an N-type well (not shown), and is a region in which six PMOS transistors are formed. Note that the region R5 of the logic cell VFLC1 with potential clamping function in FIG. 15B is included in the region of a P-type well (not shown), and is a region in which six NMOS transistors are formed. Note that the function of clamping the potential is realized by the region R2 of the logic cell VFLC1 (UPPER) with potential clamping function in FIG. 15A and the region R3 of the logic cell VFLC1 with potential clamping function in FIG. 15B. Note that the inverters composed of PMOS transistors and NMOS transistors shown in FIG. 15 are the same as the inverters shown in FIG. 3 except for the number of inverters connected in parallel, so detailed description here will be omitted.

[0091] Region R2 in FIG. 15A includes a first wiring M0o, a second wiring M0q, an output wiring M1d, and a via V0e. The first wiring M0o and the second wiring M0q are formed in the metal 0 layer. The output wiring M1d is formed in the metal 1 layer, which is an upper layer of the metal 0 layer. The via V0e is formed between the metal 0 layer and the metal 1 layer. The via V0e electrically connects the first wiring M0o and the output wiring M1d. Note that the metal 1 layer is located in the +Z-axis direction from the metal 0 layer in FIG. 15A. The second wiring M0q is a GND wiring having a GND potential. The third wiring M0k is a VDD wiring having a VDD potential.

[0092] The region R3 in FIG. 15B includes an N-type diffusion region ODf, an interconnection line MDg, a via VDi, and a via VDj. The interconnection line MDg is formed in an interconnect layer. The interconnection line MDg is electrically connected to the N-type diffusion region ODf. The interconnection line MDg is electrically connected to the vias VDi and VDj formed in the +Z-axis direction from the interconnection line MDg.

[0093] Fig. 16 is a cross-sectional view showing an example of the layout of a logic cell with a potential fixing function according to the third embodiment. Fig. 16 shows a cross-sectional view taken along dashed line HH in Fig. 15(A) and dashed line II in Fig. 15(B). Therefore, Fig. 16 includes the HH cross section in Fig. 15(A) on the upper layer side and the II cross section in Fig. 15(B) on the lower layer side. In region R6 in Fig. 16, a function of outputting a reference potential to a spare cell (not shown) is realized.

[0094] The region R6 includes the output wiring M1d, the first wiring M0o, the second wiring M0q, the interconnection wiring MDg, the N-type diffusion region ODf, and the vias V0e, VDi, and VDj. The output wiring M1d is connected to the second wiring M0q through the via V0e, the first wiring M0o, the via VDi, the interconnection wiring MDg, and the via VDj, and receives the GND potential from the second wiring M0q. As a result, the output wiring M1d can output a reference potential corresponding to the GND potential. In addition, the GND potential is supplied to the N-type diffusion region ODf from the second wiring M0q through the via VDj and the interconnection wiring MDg. The N-type diffusion region ODf functions as the source (S) of the NMOS transistor.

[0095] 16, the distance between the output wiring M1d in the metal 1 layer and the wiring in the metal 1 layer of the adjacent cell in the +Y-axis direction is indicated by a distance 15. As in the potential clamping cell according to the first embodiment, the logic cell with potential clamping function according to the third embodiment can also ensure the distance 15 that makes it possible to suppress the occurrence of spacing errors.

[0096] FIG. 17 is a plan view showing an example of the overall arrangement and wiring of the cell according to the third embodiment. That is, FIG. 17 is a plan view showing an example of the layout of the potential clamping function-equipped logic cell VFLC1 and the spare cell included in the semiconductor device 200c according to the third embodiment. The input wiring M1s6i of the spare cell SPC6 is formed in the metal 1 layer. The input wiring M1s6i formed in the metal 1 layer is electrically connected to the output wiring M1d of the potential clamping function-equipped logic cell VFLC1 via the wiring M2f of the metal 2 layer, the wiring M3b of the metal 3 layer, and the wiring M2e of the metal 2 layer. The output wiring M1d of the potential clamping function-equipped logic cell VFLC1 is electrically connected to the second wiring M0q, which is also a GND wiring. Therefore, the input wiring M1s6i of the spare cell is electrically connected to the GND wiring.

[0097] As described above, according to the logic cell with potential fixing function of the third embodiment, the region R6 of the logic cell is a region where the function of fixing the potential is realized, and therefore the same effect as that of the first embodiment can be achieved. In addition, the function of fixing the potential can be realized within the region of the logic cell. Therefore, the semiconductor device of the third embodiment can also realize space saving compared to the semiconductor device of the first embodiment.

[0098] In the above-described third embodiment, the configuration has been described in which the function of the potential fixed cell is added to the region in which the N-type diffusion region ODf functioning as the source (S) of the NMOS transistor is formed. However, the function of the potential fixed cell may be added to the region in which the P-type diffusion region ODe functioning as the source (S) of the PMOS transistor is formed. In that case, the via VDi is connected to the interconnection wiring MDf instead of the interconnection wiring MDg. With this configuration, the third wiring M0k is connected not only to the P-type diffusion region ODe but also to the output wiring M1d via the interconnection wiring MDf. As a result, the output wiring M1c outputs a reference potential corresponding to the VDD potential.

[0099] In the above-described third embodiment, the logic cell VFLC1 with potential clamping function is described, in which the function of the potential clamping cell according to the first embodiment is added to the logic cell. However, the function of the logic cell may be added to the potential clamping cell according to the first embodiment. In this case, too, the area of ​​the semiconductor device can be reduced compared to the semiconductor device according to the first embodiment.

[0100] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention. [Explanation of symbols]

[0101] LC1 logic cell SPC1, SPC2, SPC3, SPC4, SPC5 spare cells VFC1 voltage clamp cell VFLC1 Logic cell with voltage fixing function VFTAP1 Tap cell with potential fixing function M0b, M0i, M0o 1st wiring M0c, M0j, M0q 2nd wiring MDa, MDe, MDg Interconnect Wiring M1a, M1c, M1d output wiring ODd, ODf diffusion area 200a, 200b, 200c Semiconductor device

Claims

1. A logic cell; a spare cell which is combined with the logic cell to configure a new logic function when a design change occurs; a potential fixing cell that outputs a reference potential for fixing a potential of an input wiring of the spare cell, The voltage clamp cell comprises: [0023] An interconnect wiring; a first wiring formed in an upper layer of the interconnection wiring and connected to the interconnection wiring; a second wiring formed in an upper layer of the interconnection wiring and connected to the interconnection wiring; an output wiring formed in an upper layer of the first wiring and connected to the first wiring; Equipped with the second wiring has a power supply potential, is disposed in a lower layer of the output wiring, and is disposed on a cell boundary between the potential fixed cell and another cell adjacent thereto; the first wiring is routed on the inner side of the potential fixing cell relative to the second wiring, The output wiring receives the power supply potential via the second wiring, the interconnection wiring, and the first wiring, thereby outputting the reference potential.

2. 2. The semiconductor device according to claim 1, the second wiring is a power supply wiring of the semiconductor device; Semiconductor device.

3. 2. The semiconductor device according to claim 1, a tap cell for supplying a power supply potential from a power supply wiring of the semiconductor device to a well of the semiconductor device; The tap cell is the interconnection wiring, the first wiring, and the output wiring; a power supply wiring of the tap cell used as the second wiring; the well to which the power supply wiring is connected via the interconnect wiring; the power supply wiring has the power supply potential, is in a lower layer of the output wiring, and is wired on a cell boundary between the tap cell and another cell adjacent thereto; the first wiring is routed inside the tap cell with respect to the power supply wiring, the output wiring receives the power supply potential via the power supply wiring, the interconnection wiring, and the first wiring, thereby outputting the reference potential and realizing a function of the potential fixed cell in place of the potential fixed cell; Semiconductor device.

4. 2. The semiconductor device according to claim 1, The logic cell comprises: the interconnection wiring, the first wiring, and the output wiring; a power supply wiring of the logic cell used as the second wiring; a diffusion layer to which the power supply wiring is connected via the interconnection wiring; the power supply wiring has the power supply potential, is in a lower layer of the output wiring, and is wired at a cell boundary between the logic cell and another cell adjacent thereto; the first wiring is routed inside the logic cell with respect to the power supply wiring, the output wiring receives the power supply potential via the power supply wiring, the interconnection wiring, and the first wiring, thereby outputting the reference potential and realizing a function of the potential fixed cell in place of the potential fixed cell; Semiconductor device.

5. 2. The semiconductor device according to claim 1, a connection wiring for connecting the input wiring of the spare cell and the output wiring of the potential fixed cell; the connection wiring is wired in a wiring layer above a wiring layer in which the input wiring of the spare cell and the output wiring of the potential fixed cell are wired; Semiconductor device.

6. a logic cell including a first transistor; a spare cell including a second transistor connectable to the first transistor when a design change is made; a voltage clamp cell arranged adjacent to the logic cell along a first direction and supplying a reference voltage to an input of the second transistor; a first power supply wiring extending along a second direction different from the first direction at a first cell boundary of the logic cell and supplying a first power supply potential to the first transistor; a second power supply wiring extending along the second direction at a second cell boundary of the logic cell and supplying a second power supply potential to the first transistor; A semiconductor device comprising: the first cell boundary is a cell boundary between the logic cell and the voltage-fixed cell; The voltage clamp cell comprises: An interconnection line extending along the first direction; a first wiring formed in an upper layer of the interconnection wiring and connected to the interconnection wiring; an output wiring formed in an upper layer of the first wiring and connected to the first wiring; having the first power supply wiring is formed in an upper layer of the interconnect wiring and is disposed between the logic cell and the first wiring in the first direction; the output wiring receives the first power supply potential from the first power supply wiring via the interconnection wiring and the first wiring, and outputs the reference potential. Semiconductor device.

7. 7. The semiconductor device according to claim 6, The voltage clamp cell comprises: A first semiconductor layer of a first conductivity type; a first diffusion layer of the first conductivity type formed on a surface of the first semiconductor layer and connected to the interconnection wiring; Further equipped with the first power supply potential is supplied from the first power supply wiring to the first semiconductor layer via the interconnection wiring and the first diffusion layer; Semiconductor device.

8. 8. The semiconductor device according to claim 7, the semiconductor device further includes a third power supply wiring extending along the second direction at a third cell boundary of the potential fixed cell and supplying the second power supply potential; The voltage clamp cell comprises: a second semiconductor layer of a second conductivity type different from the first conductivity type, the second semiconductor layer being disposed adjacent to the first semiconductor layer in the first direction; a second diffusion layer of the second conductivity type formed on a surface layer of the second semiconductor layer and connected to the third power supply wiring; Further equipped with the second power supply potential is supplied from the third power supply wiring to the second semiconductor layer via the second diffusion layer; Semiconductor device.

9. 7. The semiconductor device according to claim 6, The voltage clamp cell comprises: a third semiconductor layer of the first conductivity type; a gate electrode formed on the third semiconductor layer and extending in the first direction; a third diffusion layer of the first conductivity type formed on a surface of the third semiconductor layer and connected to the interconnection wiring; a fourth diffusion layer formed on a surface of the third semiconductor layer; Further equipped with the third diffusion layer and the fourth diffusion layer are disposed on either side of a region of the third semiconductor layer that is covered by the gate electrode; the first power supply potential is supplied from the first power supply wiring to the third diffusion layer via the interconnection wiring; Semiconductor device.

10. 10. The semiconductor device according to claim 9, the semiconductor device further includes a third power supply wiring extending along the second direction at a third cell boundary of the potential fixed cell and supplying the second power supply potential; The voltage clamp cell comprises: a fourth semiconductor layer of a second conductivity type different from the first conductivity type, the fourth semiconductor layer being disposed adjacent to the third semiconductor layer in the first direction; a fifth diffusion layer of the second conductivity type formed on a surface layer of the fourth semiconductor layer and connected to the third power supply wiring; a sixth diffusion layer formed on a surface layer of the fourth semiconductor layer; Further equipped with the gate electrode is formed on the third semiconductor layer and the fourth semiconductor layer, the fifth diffusion layer and the sixth diffusion layer are disposed on either side of a region of the fourth semiconductor layer that is covered by the gate electrode; the second power supply potential is supplied from the third power supply wiring to the fifth diffusion layer; Semiconductor device.

11. 7. The semiconductor device according to claim 6, The second direction is a direction perpendicular to the first direction. Semiconductor device.

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