Display device

Abstract

The purpose of the present invention is to provide a display device capable of satisfactorily performing gradation control.　A display device (1) comprises: a plurality of light-emitting elements (100) that are arranged in a display region; a first pixel circuit (50a) and a second pixel circuit (50b) that are respectively connected to each of the plurality of light-emitting elements; a first driving transistor (DRT1) that is provided in the first pixel circuit and supplies a first driving current to the light-emitting element; a second driving transistor (DRT2) that is provided in the second pixel circuit and supplies a second driving current to the light-emitting element; a driving circuit (13) that supplies a video signal to each of the first driving transistor and the second driving transistor; a first connection switching transistor (CNT1) that is provided between the first driving transistor and the light-emitting element; and a second connection switching transistor (CNT2) that is provided between the second driving transistor and the light-emitting element. The first connection switching transistor and the second connection switching transistor are turned off during a non-light-emission period of the light-emitting element.

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] There are known display devices using light-emitting elements such as inorganic light-emitting diodes (micro LEDs) and organic light-emitting diodes (OLEDs). The following Patent Document 1 describes a gradation control method for performing display by combining, as a driving method for performing gradation expression of light-emitting elements, a current driving method for expressing gradation by adjusting a current value and a pulse width modulation method for expressing gradation by controlling a lighting time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-64159 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the current driving method, the light emission intensity depends on the performance of the transistor that adjusts the current value, and may vary from the desired light emission intensity depending on the characteristics of the transistor that adjusts the current value. On the other hand, in the pulse width modulation method, it is necessary to switch the switching element of the pixel circuit on and off depending on the lighting time, and it takes a driving time to rise to the desired current value, making it difficult to perform a high-speed pixel writing operation. For this reason, it may be difficult to control fine gradation expression. Patent Document 1 does not describe a specific circuit configuration for realizing the current driving method and the pulse width modulation method.

[0005] An object of the present invention is to provide a display device capable of performing favorable gradation control. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention comprises a plurality of light-emitting elements arranged in a display area, a first pixel circuit and a second pixel circuit connected to each of the plurality of light-emitting elements, a first drive transistor provided in the first pixel circuit for supplying a first drive current to the light-emitting element, a second drive transistor provided in the second pixel circuit for supplying a second drive current to the light-emitting element, a drive circuit for supplying video signals to the first drive transistor and the second drive transistor, a first connection switching transistor provided between the first drive transistor and the light-emitting element, and a second connection switching transistor provided between the second drive transistor and the light-emitting element, wherein the first connection switching transistor and the second connection switching transistor are turned off during a non-light-emitting period of the light-emitting element. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing a display device according to an embodiment. [Diagram 2] FIG. 2 is a plan view showing an example of a pixel of the display device according to the embodiment. [Diagram 3] FIG. 3 is a block diagram illustrating an example of the configuration of the display device according to the embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a configuration example of a pixel circuit. [Diagram 5] FIG. 5 is a timing chart for explaining an example of the operation of the display device according to the embodiment. [Figure 6] FIG. 6 is a timing chart for explaining an example of operation during the writing period shown in FIG. [Figure 7] FIG. 7 is an explanatory diagram for explaining an example of a combination of a current driving method and a PWM driving method for each display luminance level. [Figure 8] FIG. 8 is an explanatory diagram for explaining the arrangement relationship between the first pixel circuits and the second pixel circuits of the plurality of sub-pixels according to the embodiment. [Figure 9]FIG. 9 is a plan view illustrating a schematic configuration example of a plurality of sub-pixels according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The form (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present disclosure is not limited by the contents described in the following embodiments. The components described below include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the components described below can be appropriately combined. Note that the disclosure is merely an example, and those that a person skilled in the art can easily imagine appropriate modifications while maintaining the gist of the present disclosure are naturally included in the scope of the present disclosure. In addition, in order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment, but they are merely examples and do not limit the interpretation of the present disclosure. In addition, in this disclosure and each figure, elements similar to those described above with respect to the previously mentioned figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In this specification and the claims, when expressing an aspect of arranging another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is arranged directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is arranged above a certain structure via yet another structure.

[0010] (Embodiment) 1 is a plan view showing a display device according to an embodiment. The display device 1 of this embodiment is a micro LED display device equipped with a micro LED. As shown in FIG. 1, the display device 1 includes an array substrate 2, a plurality of pixels PX, a scanning line driving circuit 12, a signal line driving circuit 13, a light emission control circuit 14, and a driving IC (Integrated Circuit) 210.

[0011] The array substrate 2 is a drive circuit substrate for driving each pixel PX, and is also called a backplane or active matrix substrate. The array substrate 2 is formed using a substrate 21 as a base, and has a plurality of thin film transistors, a plurality of capacitors, various wirings, etc. on the substrate 21. Although not shown in particular, a wiring substrate (e.g., a flexible printed circuit board (FPC)) for inputting various control signals and power from an external control substrate may be connected to the array substrate 2.

[0012] In the following description, the first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the substrate 21. In addition, "planar view" refers to the positional relationship when viewed from the third direction Dz.

[0013] The scanning line driving circuit 12 is a circuit that drives multiple scanning lines (e.g., a reset control signal line L5, a write control scanning line L7, and an initialization control signal line L8 (see FIG. 4)) based on various control signals from the driving IC 210. The scanning line driving circuit 12 selects multiple gate lines sequentially or simultaneously, and supplies a gate driving signal to the selected scanning lines. In this way, the scanning line driving circuit 12 selects multiple pixels PX connected to the gate lines.

[0014] The signal line driving circuit 13 is a driving circuit that drives a plurality of pixels PX by supplying potentials (video signal VSG, reset power supply potential Vrst, and initialization potential Vini) to the signal lines (video signal line L2, reset power supply line L3, and initialization power supply line L4 (see FIG. 4)) in the display area AA. The light emission control circuit 14 is a driving circuit that drives a plurality of pixels PX by supplying signals to the scanning lines (light emission control scanning line L6 and connection control scanning line L9 (see FIG. 4)) in the display area AA.

[0015] The driving IC 210 is a circuit that supplies control signals to the scanning line driving circuit 12, the signal line driving circuit 13, and the light emission control circuit 14 to control the display of the multiple pixels PX. At least a part of the scanning line driving circuit 12, the signal line driving circuit 13, and the light emission control circuit 14 may be formed integrally with the driving IC 210. The driving IC 210 is provided on the array substrate 2. However, the present invention is not limited to this, and the driving IC 210 may be provided on a wiring substrate connected to the array substrate 2.

[0016] The array substrate 2 has a display area AA and a peripheral area GA. A plurality of pixels PX are provided in the display area AA. The plurality of pixels PX are arranged in a matrix in the display area AA. The peripheral area GA is an area outside the display area AA, where the plurality of pixels PX are not provided. The peripheral area GA is provided with a scanning line driving circuit 12, a signal line driving circuit 13, a light emission control circuit 14, and a driving IC 210. The scanning line driving circuit 12 and the light emission control circuit 14 are provided in an area of ​​the peripheral area GA extending along the second direction Dy. The signal line driving circuit 13 and the driving IC 210 are provided in an area of ​​the peripheral area GA extending along the first direction Dx. The scanning line driving circuit 12 and the light emission control circuit 14 may be provided in an area along the same side of the peripheral area GA.

[0017] In the following explanation, an example will be described in which the display area AA is divided into four parts, and the display operation of the display device 1 is performed for each of the first partial display area AAs1, the second partial display area AAs2, the third partial display area AAs3, and the fourth partial display area AAs4 (see Figure 5).

[0018] In this embodiment, for ease of explanation, the display area AA is rectangular, and the surrounding area GA is a rectangular frame surrounding the periphery of the display area AA. However, the display area AA is not limited to this, and may be polygonal or may have an irregular shape with a notch or curved portion on the periphery. The surrounding area GA may also be of various different shapes corresponding to the shape of the display area AA.

[0019] FIG. 2 is a plan view showing an example of a pixel of the display device according to the embodiment. As shown in FIG. 2, the pixel PX has a first subpixel SPX1, a second subpixel SPX2, and a third subpixel SPX3. The first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 each include a light-emitting element 100. The light-emitting element 100 is an inorganic light-emitting diode (LED: Light Emitting Diode) chip having a size of about 3 μm or more and 300 μm or less in a plan view, and is called a micro LED. Note that the "micro" in micro LED does not limit the size of the light-emitting element 100. Note that in the following description, when it is not necessary to distinguish between the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3, they are simply referred to as subpixels SPX. Also, although the light-emitting element 100 is arranged in the center of each subpixel SPX, FIG. 2 is merely a schematic illustration, and the position of the light-emitting element 100 in each subpixel SPX can be changed as appropriate.

[0020] The first subpixel SPX1 displays, for example, red (R). The second subpixel SPX2 displays, for example, green (G). The third subpixel SPX3 displays, for example, blue (B). The first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 are arranged side by side in the first direction Dx. However, the arrangement is not limited to this, and the pixel PX may have another arrangement. For example, the first subpixel SPX1 and the second subpixel SPX2 may be arranged adjacent to each other in the second direction Dy, and one third subpixel SPX3 may be arranged adjacent to the first subpixel SPX1 and the second subpixel SPX2 adjacent to each other in the second direction Dy in the first direction Dx. The pixel PX may be configured in a so-called Pentile arrangement. The pixel PX is not limited to three subpixels SPX, and may be configured with four or more subpixels SPX.

[0021] Next, the gradation control of the display device 1 will be described. Fig. 3 is a block diagram showing an example of the configuration of a display device according to an embodiment. As shown in Fig. 3, the display device 1 has a pixel circuit 50 and a drive signal control unit 200 that controls driving of the pixel circuit 50. The pixel circuit 50 is a circuit that supplies a drive signal (current) to the light-emitting element 100 to drive the light-emitting element 100. Note that, although Fig. 3 shows a schematic of one pixel circuit 50 (light-emitting element 100), a plurality of pixel circuits 50 and a plurality of light-emitting elements 100 are provided for each sub-pixel SPX (see Fig. 2) and are arranged in a matrix in the display area AA.

[0022] The drive signal control unit 200 includes a gradation value analysis unit 201, a drive gradation generation unit 202, and a timing signal generation unit 203. The gradation value analysis unit 201 is a circuit that calculates a gradation value (hereinafter, sometimes referred to as a target luminance level) for each pixel PX (sub-pixel SPX) based on an image signal input from an external control circuit.

[0023] The drive gradation generation unit 202 is a circuit that generates a first video signal VSG1 and a second video signal VSG2 based on the target luminance level received from the gradation value analysis unit 201. The signal line drive circuit 13 of the array substrate 2 outputs the first video signal VSG1 and the second video signal VSG2 supplied from the drive gradation generation unit 202 to the pixel circuit 50, and drives a plurality of pixels PX at the target luminance level. In the following description, when there is no need to distinguish between the first video signal VSG1 and the second video signal VSG2, they may be simply referred to as a video signal VSG.

[0024] The timing signal generation unit 203 generates a timing signal based on a synchronization signal input from an external control circuit and a target luminance level received from the gradation value analysis unit 201. The scanning line driving circuit 12 and the light emission control circuit 14 output control signals (write control signal SG, light emission control signal BG, etc.) to the pixel circuit 50 based on the timing signal (control signal) supplied from the timing signal generation unit 203.

[0025] The first video signal VSG1 and the second video signal VSG2 have a predetermined signal potential for lighting the light emitting element 100. The timing signal (control signal) supplied from the timing signal generating unit 203 includes information related to the lighting period of the light emitting element 100 by the light emission control circuit 14. The display device 1 can perform multi-tone display by combining a method of expressing gradation by controlling the current value supplied to the light emitting element 100 of each subpixel SPX (hereinafter referred to as a current driving method or an analog driving method) and a method of expressing gradation by controlling the lighting time while keeping the current value supplied to the light emitting element 100 constant (hereinafter referred to as a PWM driving method or a pulse width modulation method). The drive signal control unit 200 may be formed integrally with the drive IC 210, or may be provided in an external control circuit.

[0026] FIG. 4 is a circuit diagram showing a configuration example of a pixel circuit. As shown in FIG. 4, the pixel circuit 50 includes a first pixel circuit 50a and a second pixel circuit 50b. The first pixel circuit 50a and the second pixel circuit 50b are connected to one light-emitting element 100. That is, the first pixel circuit 50a and the second pixel circuit 50b are provided in each sub-pixel SPX. The first pixel circuit 50a is a circuit that drives the light-emitting element 100 by a current driving method. The first pixel circuit 50a can be used as a circuit that drives the light-emitting element 100 by a PWM driving method during a part of a frame period in which one screen is displayed. The second pixel circuit 50b is a circuit that drives the light-emitting element 100 by a PWM driving method.

[0027] The first pixel circuit 50a includes a first emission control transistor BCT1, a first write transistor SST1, a first drive transistor DRT1, a first initialization transistor IST1, a first reset transistor RST1, and a first connection switching transistor CNT1. Each of the thin film transistors included in the first pixel circuit 50a is an n-type TFT (Thin Film Transistor). The first pixel circuit 50a also includes a first storage capacitance Cs1 and a first additional capacitance Cad1.

[0028] The gate of the first light emission control transistor BCT1 is connected to the first light emission control scanning line L6a. The first light emission control signal BG1 is supplied to the first light emission control scanning line L6a. One of the source and drain of the first light emission control transistor BCT1 is connected to the first anode power line L1a, and a power supply voltage PVDD is supplied from the first anode power line L1a. The other of the source and drain of the first light emission control transistor BCT1 is connected to the first drive transistor DRT1. When the first light emission control transistor BCT1 is turned on (conductive state), the power supply voltage PVDD is supplied to the first drive transistor DRT1.

[0029] The gate of the first write transistor SST1 is connected to a first write control scanning line L7a. A first write control signal SG1 is supplied to the first write control scanning line L7a. One of the source and drain of the first write transistor SST1 is connected to a first video signal line L2a. The other of the source and drain of the first write transistor SST1 is connected to the gate of the first drive transistor DRT1. When the first write transistor SST1 is turned on (conductive state), a first video signal VSG1 is supplied from the signal line drive circuit 13 to the gate of the first drive transistor DRT1.

[0030] Here, the ON state of the drive transistor DRT changes according to the magnitude of the first video signal VSG1. For example, if the first video signal VSG1 corresponds to a signal potential that results in the maximum luminance of the light-emitting element 100, the drive transistor DRT is almost completely turned on according to the potential of the first video signal VSG1, and a current (predetermined fixed potential) from the power supply voltage PVDD passes through the drive transistor DRT almost as it is and is supplied to the light-emitting element 100. On the other hand, if the first video signal VSG1 corresponds to a signal potential that results in the minimum luminance of the light-emitting element 100, that is, black, the drive transistor DRT is turned off, and no current from the power supply voltage PVDD is supplied to the light-emitting element 100.

[0031] In this way, the on state of the drive transistor DRT changes with a magnitude corresponding to the signal potential of the first video signal VSG1, and as a result, only the current from the power supply voltage PVDD corresponding to the on state of the drive transistor DRT is supplied to the light-emitting element 100.

[0032] The gate of the first initialization transistor IST1 is connected to a first initialization control signal line L8a. A first initialization control signal IG1 is supplied to the first initialization control signal line L8a. One of the source and drain of the first initialization transistor IST1 is connected to a first initialization power line L4a. The other of the source and drain of the first initialization transistor IST1 is connected to the gate of the first drive transistor DRT1 and the other of the source and drain of the first write transistor SST1. An initialization potential Vini is supplied to the first initialization power line L4a. That is, when the first initialization transistor IST1 is turned on (conductive state), the initialization potential Vini is supplied to the gate of the drive transistor DRT via the first initialization transistor IST1.

[0033] The gate of the first reset transistor RST1 is connected to the first reset control signal line L5a. The first reset control signal RG1 is supplied to the first reset control signal line L5a. One of the source and drain of the first reset transistor RST1 is connected to the first reset power line L3a. The other of the source and drain of the first reset transistor RST1 is connected to the source (node ​​N1 on the output side) of the first drive transistor DRT1. The reset power potential Vrst is supplied to the first reset power line L3a. That is, when the first reset transistor RST1 is turned on (conductive state), the source (node ​​N1 on the output side) of the drive transistor DRT is supplied with the reset power potential Vrst via the first reset transistor RST1.

[0034] The gate of the first connection switching transistor CNT1 is connected to the first connection control scanning line L9a. A first connection control signal PWM1 is supplied to the first connection control scanning line L9a. One of the source and drain of the first connection switching transistor CNT1 is connected to the source of the first drive transistor DRT1 (the output side node N1) via the output side node N1. The other of the source and drain of the first connection switching transistor CNT1 is connected to the anode 23 of the light emitting element 100. In other words, the first connection switching transistor CNT1 is connected between the first drive transistor DRT1 and the light emitting element 100.

[0035] A power supply voltage PVSS is supplied to the cathode of the light emitting element 100 via a cathode power line L10. Ideally, the light emitting element 100 emits light when a forward current (drive current) is supplied due to the potential difference (PVDD-PVSS) between the power supply voltage PVDD supplied to the anode and the power supply voltage PVSS supplied to the cathode.

[0036] The first write control scanning line L7a, the first initialization control signal line L8a, and the first reset control signal line L5a are connected to a scanning line driving circuit 12 shown in FIG. 3. The scanning line driving circuit 12 supplies various control signals to the first write control scanning line L7a, the first initialization control signal line L8a, and the first reset control signal line L5a. The first light emission control scanning line L6a and the first connection control scanning line L9a are connected to a light emission control circuit 14. The light emission control circuit 14 supplies control signals to the first light emission control scanning line L6a and the first connection control scanning line L9a, respectively.

[0037] The first pixel circuit 50a has a first storage capacitance Cs1 which is formed between the gate and source (node ​​N1 on the output side) of the first drive transistor DRT1. The first additional capacitance Cad1 is formed between the node N1 on the output side and the first cathode power line L10a.

[0038] The second pixel circuit 50b includes a second emission control transistor BCT2, a second write transistor SST2, a second drive transistor DRT2, a second initialization transistor IST2, a second reset transistor RST2, and a second connection switching transistor CNT2. The second pixel circuit 50b includes a second anode power line L1b, a second video signal line L2b, a second reset power line L3b, a second initialization power line L4b, a second reset control signal line L5b, a second emission control scanning line L6b, a second write control scanning line L7b, a second initialization control signal line L8b, a second connection control scanning line L9b, and a second cathode power line L10b. The second pixel circuit 50b has a similar configuration to the first pixel circuit 50a, and a repeated description will be omitted. In the second pixel circuit 50b, when the second emission control transistor BCT2 is turned on (conductive state), a power supply voltage PVDD is supplied to the second drive transistor DRT2.

[0039] The gate of the second connection switching transistor CNT2 is connected to a second connection control scanning line L9b. A second connection control signal PWM2 is supplied to the second connection control scanning line L9b. One of the source and drain of the second connection switching transistor CNT2 is connected to the second drive transistor DRT2. The other of the source and drain of the second connection switching transistor CNT2 is connected to the anode 23 of the light-emitting element 100. In other words, the second connection switching transistor CNT2 is connected between the second drive transistor DRT2 and the light-emitting element 100.

[0040] The second pixel circuit 50b also includes a second storage capacitor Cs2 and a second additional capacitor Cad2. The second storage capacitor Cs2 is a capacitor formed between the gate and source (output node N2) of the second drive transistor DRT2. The second additional capacitor Cad2 is a capacitor formed between the output node N2 and the second cathode power line L10b.

[0041] For ease of understanding, in Fig. 4, the wirings (from the first anode power line L1a to the first cathode power line L10a) of the first pixel circuit 50a and the wirings (from the second anode power line L1b to the second cathode power line L10b) of the second pixel circuit 50b are shown separately for each circuit. However, as will be described later with reference to Fig. 9, the first pixel circuit 50a and the second pixel circuit 50b may share some of the wirings.

[0042] In addition, in the following description, when there is no need to distinguish between the thin-film transistors of the first pixel circuit 50a and the thin-film transistors of the second pixel circuit 50b, they may simply be referred to as the light-emitting control transistor BCT, the write transistor SST, the drive transistor DRT, the initialization transistor IST, the reset transistor RST, and the connection switching transistor CNT.

[0043] Furthermore, when there is no need to distinguish between the wirings of the first pixel circuit 50a and the wirings of the second pixel circuit 50b, they may simply be referred to as the anode power line L1, the video signal line L2, the reset power line L3, the initialization power line L4, the reset control signal line L5, the light emission control scanning line L6, the write control scanning line L7, the initialization control signal line L8, the connection control scanning line L9, and the cathode power line L10.

[0044] Furthermore, when there is no need to distinguish between the control signals supplied to the first pixel circuit 50a and the control signals supplied to the second pixel circuit 50b, they may simply be referred to as the light emission control signal BG, the write control signal SG, the initialization control signal IG, the reset control signal RG, and the connection control signal PWM.

[0045] Fig. 5 is a timing chart for explaining an example of the operation of the display device according to the embodiment. Fig. 5 shows the operation of driving the subpixels SPX in the first partial display area AAs1 and the second partial display area AAs2, but driving continues from the third partial display area AAs3 onwards up to the subpixels SPX in the last row. In the following explanation, the period during which the subpixels SPX in the first row to the subpixels SPX in the last row are driven is referred to as a frame period.

[0046] 5, the period t1 is a video signal write operation period for the first partial display area AAs1. Specifically, in the period t1, the potentials of the first light-emission control scanning line L6a and the second light-emission control scanning line L6b (the first light-emission control signal BG1 and the second light-emission control signal BG2) become L level and the potentials of the write control scanning lines L7-1, L7-2, ..., L7-270 (the first write control signal SG1 and the second write control signal SG2) become H level due to the control signals supplied from the scanning line driving circuit 12 and the light-emission control circuit 14.

[0047] In the period t1, the first emission control transistor BCT1 of the first pixel circuit 50a and the second emission control transistor BCT2 of the second pixel circuit 50b are turned off. In addition, the first write transistor SST1 of the first pixel circuit 50a and the second write transistor SST2 of the second pixel circuit 50b are turned on. In the period t1, the write control scanning lines L7 belonging to the first partial display area AAs1 are sequentially scanned. The write control scanning line L7-1 is the write control scanning line L7 connected to the subpixel SPX of the first row, and the write control scanning line L7-2 is the write control scanning line L7 connected to the subpixel SPX of the second row. The first partial display area AAs1 is, for example, an area including the write control scanning lines L7-1 to L7-270.

[0048] The video signal write operation period will be described in detail below with reference to Fig. 6. Fig. 6 is a timing chart for explaining an example of operation of the write period shown in Fig. 5. Note that Fig. 6 shows an enlarged view of the video signal write operation period SW shown in period t4 in Fig. 5, but the explanation of the video signal write operation period SW in period t4 can also be applied to the video signal write operation period in period t1. Note that in the period before period t1, the subpixel SPX continues the light-emitting state of the previous frame.

[0049] 6, the period t11 is a source initialization period of the drive transistor DRT. Specifically, in the period t1, the potential of the light emission control scan line L6 (first light emission control signal BG1 and second light emission control signal BG2) becomes L level and the potential of the reset control signal line L5 (first reset control signal RG1 and second reset control signal RG2) becomes H level by each control signal supplied from the scanning line drive circuit 12 and the light emission control circuit 14. As a result, the light emission control transistor BCT becomes OFF (non-conductive state) and the reset transistor RST becomes ON (conductive state).

[0050] During the video signal write operation period, the first connection control signal PWM1 and the second connection control signal PWM2 are at the L level from the period t11 to the period t17, and the connection switching transistor CNT is turned off. That is, during the video signal write operation period, which is the non-light-emitting period of the light-emitting element 100, the light-emitting element 100 is disconnected from the first pixel circuit 50a and the second pixel circuit 50b. This makes it possible to prevent the potential generated at the node N1 of the first pixel circuit 50a and the node N2 of the second pixel circuit 50b during the video signal write operation period from being applied to the light-emitting element 100. This makes it possible to prevent the light-emitting element 100 from being damaged by preventing an unintended reverse bias potential from being applied to the light-emitting element 100.

[0051] In period t11, the current from the anode power line L1 is cut off by the light-emitting control transistor BCT, and the connection switching transistor CNT is turned off as described above. The light-emitting element 100 stops emitting light, and the charge remaining in the subpixel SPX flows to the outside through the reset transistor RST. As a result, the source of the drive transistor DRT is fixed to the reset power supply potential Vrst.

[0052] Next, the period t12 is a gate initialization period of the drive transistor DRT. Specifically, in the period t12, the potentials of the initialization control signal line L8 (first initialization control signal IG1 and second initialization control signal IG2) become H level by the control signals supplied from the scanning line drive circuit 12 and the light emission control circuit 14. The initialization transistor IST is turned on. In the subpixel SPX belonging to the first partial display region AAs1, the gate of the drive transistor DRT is fixed to the initialization potential Vini via the initialization transistor IST. The initialization potential Vini has a potential higher than the threshold value of the drive transistor DRT with respect to the reset power supply potential Vrst. Therefore, the drive transistor DRT is turned on. However, in the period t12, since the light emission control transistor BCT maintains the off state, no current flows through the drive transistor DRT.

[0053] Next, the period t13 is an offset cancel operation period. Specifically, in the period t13, the potential of the light emission control scanning line L6 (the first light emission control signal BG1 and the second light emission control signal BG2) becomes H level and the potential of the reset control signal line L5 (the first reset control signal RG1 and the second reset control signal RG2) becomes L level by each control signal supplied from the scanning line driving circuit 12 and the light emission control circuit 14. As a result, the light emission control transistor BCT is turned on and the reset transistor RST is turned off.

[0054] The driving transistor DRT is in an on state due to the operation in the period t12. Therefore, a current is supplied to the driving transistor DRT from the anode power line L1 (power supply voltage PVDD) via the light-emission control transistor BCT.

[0055] At this stage, the connection switching transistor CNT is off, and no current flows to the light emitting element 100. Therefore, the source of the drive transistor DRT is charged by the power supply voltage PVDD, and the potential of the source rises. The gate potential of the drive transistor DRT is the initialization potential Vini. Therefore, when the source potential of the drive transistor DRT becomes (Vini-Vth), the drive transistor DRT turns off, and the rise in potential stops. Here, Vth is the threshold voltage Vth of the drive transistor DRT.

[0056] The threshold voltage Vth varies for each subpixel SPX (and for each pixel circuit 50). Therefore, the potential of the source of the drive transistor DRT when the potential stops rising differs for each subpixel SPX (and for each pixel circuit 50). In other words, a voltage equivalent to the threshold voltage Vth of the drive transistor DRT is acquired in each subpixel SPX by the operation in period t13.

[0057] Next, in periods t14 and t15, the initialization transistor IST and the light emission control transistor BCT are sequentially turned off. In the next period t16, the potentials of the write control scanning line L7 (the first write control signal SG1 and the second write control signal SG2) become H level due to the control signals supplied from the scanning line driving circuit 12 and the light emission control circuit 14.

[0058] As a result, the light-emission control transistor BCT is turned off, the initialization transistor IST is turned off, and the writing transistor SST is turned on. During period t16, in the subpixel SPX belonging to the first partial display region AAs1, the video signal VSG is input to the gate of the drive transistor DRT. The gate potential of the drive transistor DRT changes from the initialization potential Vini to the potential of the video signal VSG. Meanwhile, the potential of the source of the drive transistor DRT is maintained at (Vini-Vth). As a result, the voltage between the gate and source of the drive transistor DRT becomes (VSG-(Vini-Vth)), which reflects the variation in threshold voltage Vth between the subpixels SPX.

[0059] Returning to FIG. 5, in the subpixel SPX belonging to the write control scanning line L7 that is at the H level during the video signal write operation period described above, the first video signal VSG1-1 is input to the gate of the first drive transistor DRT1 of the first pixel circuit 50a during the period t1. The video signal write operation during the period t1 changes the gate potential of the first drive transistor DRT1 to the potential of the first video signal VSG1-1. During the same period, the second video signal VSG2-1 is input to the gate of the second drive transistor DRT2 of the second pixel circuit 50b. The gate potential of the second drive transistor DRT2 changes to the potential of the second video signal VSG2-1.

[0060] As shown in FIG. 5, in periods t1a and t1b following the period t1, displays based on the first video signal VSG1-1 and the second video signal VSG2-1 are both displayed by the so-called PWM drive method.

[0061] Next, periods t1a and t1b after the period t1 are light emission operation periods. During periods t1a and t1b, display is performed by a so-called PWM driving method based on the first video signal VSG1-1 and the second video signal VSG2-1. The PWM driving method expresses the gradation of the light emitting element 100 according to the length of the pulse width of the light emission control signal BG output from the light emission control circuit 14 to each light emission control scanning line L6. When the light emitting element 100 is turned on in the PWM driving method, it is preferable that the brightness is the maximum luminance of the light emitting element 100. Therefore, in this embodiment, the video signals input during period t1 are all video signals VSG (signal potential) corresponding to the so-called maximum luminance of the light emitting element 100. In this way, during the period of the PWM driving method, the gradation of the light emitting element 100 is controlled to the maximum luminance or luminance 0. Hereinafter, the video signal VSG supplied during the display period by the PWM driving method may be referred to as a digital signal.

[0062] Specifically, in the period t1a, the first light-emission control signal BG1 supplied to the first light-emission control scanning line L6a goes to H level, and the second light-emission control signal BG2 supplied to the second light-emission control scanning line L6b goes to L level, due to the control signals supplied from the scanning line driving circuit 12 and the light-emission control circuit 14. In addition, the write control scanning lines L7-1, L7-2, ..., L7-270 of the first partial display area AAs1 go to L level.

[0063] As a result, the first emission control transistor BCT1 of the first pixel circuit 50a is turned on, and the first write transistor SST1 is turned off. Furthermore, during the emission operation period, the first connection switching transistor CNT1 is turned on. A power supply voltage PVDD is supplied to the first drive transistor DRT1 via the first emission control transistor BCT1. The first drive transistor DRT1 supplies a current to the light emitting element 100 according to the gate-source voltage set in period t1. That is, the first drive transistor DRT1 is almost completely turned on by the video signal, and the light emitting element 100 emits light at the maximum brightness according to the potential difference PVDD-PVSS.

[0064] During the period t1a, the period (pulse width) during which the first emission control transistor BCT1 is on is set to a period that provides a target luminance level of 12.5% ​​of the maximum lighting luminance. During the period t1a, the second emission control transistor BCT2 of the second pixel circuit 50b is off, so no current flows from the second drive transistor DRT2 to the light emitting element 100. However, the voltage between the gate and source of the second drive transistor DRT2 is held by the second storage capacitor Cs2. During the period t1a, the second connection switching transistor CNT2 of the second pixel circuit 50b is off, so fluctuations in the voltage between the gate and source of the second drive transistor DRT2 due to the current from the first drive transistor DRT1 are suppressed.

[0065] Next, in a period t1b, the first light-emission control signal BG1 supplied to the first light-emission control scanning line L6a goes to L level, and the second light-emission control signal BG2 supplied to the second light-emission control scanning line L6b goes to H level, due to the control signals supplied from the scanning line driving circuit 12 and the light-emission control circuit 14. In addition, the write control scanning lines L7-1, L7-2, ..., L7-270 of the first partial display area AAs1 are maintained at L level.

[0066] As a result, the second emission control transistor BCT2 of the second pixel circuit 50b is turned on, and the second write transistor SST2 is turned off. Furthermore, the second connection switching transistor CNT2 is turned on. A power supply voltage PVDD is supplied to the second drive transistor DRT2 via the second emission control transistor BCT2. The second drive transistor DRT2 supplies a current according to the gate-source voltage set in period t1 to the light-emitting element 100. That is, the second drive transistor DRT2 is almost completely turned on by the digital signal, and the light-emitting element 100 emits light with the maximum brightness based on the potential difference PVDD-PVSS.

[0067] In the period t1b, the period (pulse width) during which the second emission control transistor BCT2 is on is set to a period that is a target luminance level of 50% of the maximum lighting luminance. That is, the period t1b is longer than the period t1a, and in this embodiment, the period t1b is four times the period t1a. Note that, in the period t1b, the first emission control transistor BCT1 of the first pixel circuit 50a is off, so that no current flows from the first drive transistor DRT1 to the light emitting element 100. In addition, in the period t1b, the first connection switching transistor CNT1 of the first pixel circuit 50a is off, so that fluctuations in the gate-source voltage of the first drive transistor DRT1 due to the current from the second drive transistor DRT2 are suppressed.

[0068] In both periods t1a and t1b, which are light-emitting periods, the light-emitting element 100 is lit at the maximum luminance. On the other hand, the light-emitting period in period t1a is shorter than that in period 1b. Therefore, the luminance of the light-emitting element 100 can be changed by switching the light-emitting element 100 on / off in periods t1a and t1b. More specifically, if the light-emitting element 100 is lit at the maximum luminance in both periods t1a and t1b, the user of the display device 1 visually recognizes that the light-emitting element 100 is lit at the brightest luminance during the period spanning periods t1a and t1b due to the integral effect of the human eye (the luminance at this time is referred to as luminance A).

[0069] On the other hand, if the light-emitting element 100 is lit only during period t1b, even if the light-emitting element 100 is lit at maximum brightness during period t1b, due to the integration effect in the time axis direction, when viewed over the entire period spanning periods t1a and t1b, the light-emitting element 100 will appear darker than brightness A, and the user will visually perceive the light-emitting element 100 as being lit at brightness B, which is darker than brightness A.

[0070] Also, if the light-emitting element 100 is lit only during period t1a and period t1b, even if the light-emitting element 100 is lit at maximum luminance during period t1a, due to an integration effect in the time axis direction, when viewed over the entire period spanning periods t1a and t1b, the luminance becomes darker than luminance B, and the user visually recognizes the light-emitting element 100 as being lit at luminance C darker than luminance B. In this way, in the PWM driving method, the luminance is changed according to the length of the lighting period of the light-emitting element 100.

[0071] During periods t2 to t3 overlapping with periods t1a and t1b, video signal writing operations are sequentially performed in the second to fourth partial display areas AAs2 to AAs4. During periods t2a, t2b, t5a, and t5b, a light emission operation in the second partial display area AAs2 is performed in the same manner as in the first partial display area AAs1.

[0072] In period t4, similarly to period t1, the video signal writing operation for the first partial display area AAs1 is executed. By the video signal writing operation in period t4, the gate potential of the first drive transistor DRT1 changes to the potential of the first video signal VSG1-2. The gate potential of the second drive transistor DRT2 changes to the potential of the second video signal VSG2-2.

[0073] Next, in a period t4a, the first light-emission control signal BG1 supplied to the first light-emission control scanning line L6a becomes L level, and the second light-emission control signal BG2 supplied to the second light-emission control scanning line L6b becomes H level, due to the control signals supplied from the scanning line driving circuit 12 and the light-emission control circuit 14. In addition, the write control scanning lines L7-1, L7-2, ..., L7-270 of the first partial display area AAs1 become L level. Note that the operation of each transistor of the second pixel circuit 50b in the period t4a is the same as that in the above-mentioned period t1b, and a repeated description will be omitted.

[0074] Here, as shown in FIG. 5, the period t4a following the period t4 is one period of display by the PWM driving method. Meanwhile, the period t4b is a display period by analog gradation. Display by analog gradation means that the lighting period is fixed to a predetermined period, while the pixel signal (video signal VSG) is an analog potential, the ON state of the gate of the driving transistor DRT is adjusted according to the analog potential, and the current from the power supply voltage PVDD to the light emitting element 100 has a magnitude according to the ON state of the gate. As a result, the luminance of the light emitting element 100 becomes a brightness according to the analog potential of the pixel signal (video signal VSG). More specifically, the brightness of the light emitting element 100 based on the pixel signal (video signal VSG) of the analog potential has any brightness between luminance 0 and a predetermined luminance. In other words, if the period is a PWM driving method period, the light emitting element 100 will only emit light at the maximum luminance or luminance 0 throughout the period, whereas in the display period by analog gradation, the light emitting element 100 emits light at any luminance between luminance 0 and maximum luminance according to the gradation expression by the analog potential. Hereinafter, the display using analog gradations may be referred to as an analog driving method.

[0075] The pixel signal supplied to the pixel circuit 50 during the display period using the analog drive method can be set to correspond to a gradation of 0 to 255. In this embodiment, however, taking into consideration that the period during which the gradation expression based on the analog potential is performed is 12.5% ​​of the entire lighting period, the luminance expression by the pixel signal is approximately 0 to 32 gradations.

[0076] In the period t4a, the period (pulse width) during which the second emission control transistor BCT2 is on is set to a period for which the target luminance level is 25% of the maximum lighting luminance. Note that, in the period t4a, the first emission control transistor BCT1 of the first pixel circuit 50a is off, so that no current flows from the first drive transistor DRT1 to the light emitting element 100.

[0077] Next, in period t4b, the first light emission control signal BG1 supplied to the first light emission control scanning line L6a becomes H level, and the second light emission control signal BG2 supplied to the second light emission control scanning line L6b becomes L level, due to the control signals supplied from the scanning line driving circuit 12 and the light emission control circuit 14. In addition, the write control scanning lines L7-1, L7-2, ..., L7-270 of the first partial display area AAs1 maintain the L level. Note that the operation of each transistor of the first pixel circuit 50a in period t4b is the same as that in the above-mentioned period t1a, and a repeated description will be omitted.

[0078] During period t4b, a current (first drive current) according to the first video signal VSG1-2, which is an analog signal, is supplied from the first drive transistor DRT1 to the light emitting element 100. The period (pulse width) during which the first emission control transistor BCT1 is on is fixed to a period during which the target luminance level is 12.5% ​​of the maximum lighting luminance. The potential of the first video signal VSG1-2 during period t4b is set for each sub-pixel SPX by the drive signal controller 200. During period t4b, the second emission control transistor BCT2 of the second pixel circuit 50b is off, so that no current flows from the second drive transistor DRT2 to the light emitting element 100.

[0079] When the above operations are completed for the second partial display area AAs2 to the fourth partial display area AAs4, one frame of image is displayed.

[0080] The drive signal control unit 200 (see FIG. 3) can control the luminance (grayscale) of the light emitting element 100 by the sum of the light emitting operation periods of the periods t1a, t1b and the periods t4a, t4b. More specifically, 87.5% of the luminance of the optical element is constituted by the display period by the PWM drive method based on the video signal of the digital potential (first video signal VSG1-1, second video signal VSG2-1, VSG2-2), and the remaining luminance of 12.5% ​​is constituted by the video signal of the analog potential (first video signal VSG1-2). Moreover, the brightness of the luminance of the 12.5% ​​can be set more finely according to the analog potential. Therefore, by combining these PWM drive method periods and analog drive method periods, extremely fine gradation expression can be realized.

[0081] 5 shows a case where a current flows through the light emitting element 100 during all of the periods t1a, t1b and t4a and t4b, and the light emitting element 100 displays 100% brightness. However, the drive signal control unit 200 (see FIG. 3) supplies a fixed current to the light emitting element 100 for a period whose length corresponds to the video signal VSG by controlling the on / off of the lighting during the periods t1a, t1b and t4a and t4b. In addition, the current during the period t4b (first video signal VSG1-2) is adjusted, so that the brightness (grayscale) can be appropriately controlled.

[0082] During the light emission period, the first connection switching transistor CNT1 is on / off controlled in synchronization with the first light emission control transistor BCT1. The second connection switching transistor CNT2 is on / off controlled in synchronization with the second light emission control transistor BCT2. As a result, during periods t1a, t1b and periods t4a, t4b, the light emitting element 100 is connected to one of the first pixel circuit 50a and the second pixel circuit 50b and is not connected to the other of the first pixel circuit 50a and the second pixel circuit 50b.

[0083] 7 is an explanatory diagram for explaining an example of a combination of a current driving method and a PWM driving method for each display luminance level. As shown in FIG. 7, when the target luminance level is in the range of more than 0% and less than or equal to 12.5%, the drive signal control unit 200 turns on the first emission control transistor BCT1 in the period t4b, supplies a current (first video signal VSG1-2) to the light emitting element 100, and adjusts it to the lighting luminance level. That is, the drive signal control unit 200 turns off the first emission control transistor BCT1 and the second emission control transistor BCT2 in the periods t1a, t1b, and t4a. That is, in the above, the light emitting element 100 is off (non-emitting) in the periods t1a, t1b, and t4a.

[0084] When the target luminance level is in the range of more than 12.5% ​​and 25% or less, the driving signal control unit 200 turns on the first emission control transistor BCT1 in the period t1a and supplies a current (first video signal VSG1-1) to the light emitting element 100 in a period corresponding to the target luminance level of 12.5%. The driving signal control unit 200 also turns on the first emission control transistor BCT1 in the period t4b and supplies a current (first video signal VSG1-2) to the light emitting element 100 to adjust the lighting luminance level in the range of 12.5% ​​to 25% or less. That is, the driving signal control unit 200 turns off the first emission control transistor BCT1 and the second emission control transistor BCT2 in the periods t1b and t4a. That is, in the above, the light emitting element 100 is off (non-emitting) in the periods t1b and t4a.

[0085] When the target luminance level is in the range of more than 25% and 37.5% or less, the driving signal control unit 200 turns on the second emission control transistor BCT2 in the period t4a and supplies a current (second video signal VSG2-2) to the light emitting element 100 for a period corresponding to the target luminance level of 25%. In addition, the driving signal control unit 200 turns on the first emission control transistor BCT1 in the period t4b and supplies a current (first video signal VSG1-2) to the light emitting element 100 to adjust the lighting luminance level in the range of 25% to 37.5% or less. That is, the driving signal control unit 200 turns off the first emission control transistor BCT1 and the second emission control transistor BCT2 in the periods t1a and t1b. That is, in the above, the light emitting element 100 is off (non-emitting) in the periods t1a and t1b.

[0086] When the target luminance level is in the range of more than 37.5% and 50% or less, the driving signal control unit 200 turns on the first light emission control transistor BCT1 and the second light emission control transistor BCT2 in the period t1a and the period t4a, respectively, and supplies a current (first video signal VSG1-1, second video signal VSG2-2) to the light emitting element 100 in the period corresponding to the target luminance level of 12.5% ​​and the period corresponding to the target luminance level of 25%. In addition, the driving signal control unit 200 turns on the first light emission control transistor BCT1 in the period t4b, and supplies a current (first video signal VSG1-2) to the light emitting element 100, thereby adjusting the lighting luminance level in the range of 37.5% to 50% or less. That is, the driving signal control unit 200 turns off the first light emission control transistor BCT1 and the second light emission control transistor BCT2 in the period t1b. That is, in the above, the light emitting element 100 is off (non-emitting) in the period t1b.

[0087] Similarly, the drive signal control unit 200 can realize a display of a lighting luminance level by combining a current (first video signal VSG1-1, second video signal VSG2-1, VSG2-2) and a current (first video signal VSG1-2).

[0088] Next, a configuration example of the first pixel circuit 50a and the second pixel circuit 50b in the multiple subpixels SPX will be described. Fig. 8 is an explanatory diagram for explaining the arrangement relationship of the first pixel circuit and the second pixel circuit in the multiple subpixels according to the embodiment. In Fig. 8, the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 are shown with hatching. Also, the L-shaped pattern shown in each subpixel SPX is for illustrative purposes only to explain the arrangement relationship (symmetry of arrangement) of the transistors and wirings in the multiple subpixels SPX, and does not represent the actual arrangement pattern or shape of the transistors and wirings.

[0089] 8, a plurality of pixels PX are arranged in a first direction Dx. In the first direction Dx, the first subpixel SPX1, the second subpixel SPX2, the third subpixel SPX3, the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 are repeatedly arranged in this order. In each subpixel SPX, the first pixel circuit 50a and the second pixel circuit 50b are arranged adjacent to each other in the second direction Dy.

[0090] As shown typically in an L-shaped pattern, in one subpixel SPX, the arrangement pattern of the transistors and wiring of the first pixel circuit 50a is arranged line-symmetrically with the arrangement pattern of the transistors and wiring of the second pixel circuit 50b about an axis of symmetry parallel to the first direction Dx. In the example shown in Fig. 8, in one subpixel SPX, the arrangement pattern of the transistors and wiring of the first pixel circuit 50a is an arrangement pattern that is upside down with respect to the arrangement pattern of the transistors and wiring of the second pixel circuit 50b.

[0091] In two subpixels SPX adjacent in the first direction Dx (for example, the first subpixel SPX1 on the far left in FIG. 8 and the second subpixel SPX2 adjacent thereto), the first pixel circuit 50a and the second pixel circuit 50b of one subpixel SPX (first subpixel SPX1) and the first pixel circuit 50a and the second pixel circuit 50b of the other subpixel SPX (second subpixel SPX2) are arranged symmetrically with respect to an axis of symmetry parallel to the second direction Dy. In the example shown in FIG. 8, in the two adjacent subpixels SPX, the arrangement patterns of the transistors and wirings of the first pixel circuit 50a and the second pixel circuit 50b are left-right inverted.

[0092] Moreover, when focusing on two pixels PX adjacent to each other in the first direction Dx, the first subpixel SPX1 of one pixel PX (pixel PX on the left side in FIG. 8) and the first subpixel SPX1 of the other pixel PX (pixel PX on the right side in FIG. 8) are arranged in a left-right inverted arrangement pattern. That is, the first subpixel SPX1, the second subpixel SPX2, the third subpixel SPX3, the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 are repeatedly arranged in this order in the first direction Dx, and in two first subpixels SPX1 adjacent to each other with the second subpixel SPX2 and the third subpixel SPX3 in between, the first pixel circuit 50a and the second pixel circuit 50b of one first subpixel SPX1 and the first pixel circuit 50a and the second pixel circuit 50b of the other first subpixel SPX1 are arranged line-symmetrically with respect to an axis of symmetry parallel to the second direction Dy.

[0093] In this way, by forming the arrangement patterns of the transistors and wirings in an inverted manner in adjacent subpixels SPX, the adjacent subpixels SPX can share the wirings, and the arrangement pitch of the multiple subpixels SPX can be reduced. Also, by forming the arrangement patterns of the transistors and wirings in an inverted manner in the first pixel circuit 50a and the second pixel circuit 50b adjacent in the second direction Dy, the adjacent first pixel circuit 50a and the second pixel circuit 50b can share the wirings, and the first pixel circuit 50a and the second pixel circuit 50b can be efficiently arranged in one subpixel SPX.

[0094] Fig. 9 is a plan view showing a schematic configuration example of a plurality of subpixels according to an embodiment. Fig. 9 shows a configuration example of a first subpixel SPX1, a second subpixel SPX2, and a third subpixel SPX3 arranged in a first direction Dx. Note that the electrical connection relationship of each transistor and each wiring of the first pixel circuit 50a and the second pixel circuit 50b shown in Fig. 9 is the same as that described above in Fig. 4, and therefore repeated explanation will be omitted.

[0095] 9, when focusing on one subpixel SPX (for example, the first subpixel SPX1), the transistors of the first pixel circuit 50a and the transistors of the second pixel circuit 50b are arranged line-symmetrically with respect to an axis of symmetry Q1 parallel to the first direction Dx. More specifically, in the first pixel circuit 50a, the first reset transistor RST1, the first connection switching transistor CNT1, the first drive transistor DRT1, the first emission control transistor BCT1, the first write transistor SST1, and the first initialization transistor IST1 are arranged in this order from the axis of symmetry Q1 toward one side of the second direction Dy (the upper side in FIG. 9).

[0096] In the second pixel circuit 50b, a second reset transistor RST2, a second connection switching transistor CNT2, a second drive transistor DRT2, a second emission control transistor BCT2, a second write transistor SST2, and a second initialization transistor IST2 are arranged in this order from the symmetry axis Q1 toward the other side of the second direction Dy (the lower side of Figure 9).

[0097] The light emitting element 100 (not shown in FIG. 9) is connected to the first connection switching transistor CNT1 via a contact portion CH1, and is connected to the second connection switching transistor CNT2 via a contact portion CH2.

[0098] Moreover, the wirings of the first pixel circuit 50a and the wirings of the second pixel circuit 50b are arranged symmetrically with respect to an axis of symmetry Q1 parallel to the first direction Dx. More specifically, in the first pixel circuit 50a, the reset control signal line L5, the first connection control scanning line L9a, the first light emission control scanning line L6a, the first write control scanning line L7a, and the first initialization control signal line L8a are arranged in this order from the axis of symmetry Q1 toward one side of the second direction Dy (the upper side in FIG. 9).

[0099] In the second pixel circuit 50b, the reset control signal line L5, the second connection control scanning line L9b, the second light emission control scanning line L6b, the second write control scanning line L7b, and the second initialization control signal line L8b are arranged in this order from the axis of symmetry Q1 toward the other side of the second direction Dy (the lower side of Figure 9).

[0100] 9, one reset control signal line L5 is shared by the first pixel circuit 50a and the second pixel circuit 50b. That is, the first reset transistor RST1 of the first pixel circuit 50a and the second reset transistor RST2 of the second pixel circuit 50b are arranged adjacent to each other in the second direction Dy with the reset control signal line L5 in between. The gate of the first reset transistor RST1 of the first pixel circuit 50a and the gate of the second reset transistor RST2 of the second pixel circuit 50b are connected to the common reset control signal line L5.

[0101] Next, when focusing on two subpixels SPX (for example, the first subpixel SPX1 and the second subpixel SPX2) adjacent to each other in the first direction Dx, the first pixel circuit 50a and the second pixel circuit 50b of one subpixel SPX (the first subpixel SPX1) and the first pixel circuit 50a and the second pixel circuit 50b of the other subpixel SPX (the second subpixel SPX2) are arranged line-symmetrically with respect to an axis of symmetry Q2 parallel to the second direction Dy. That is, the transistors of the first subpixel SPX1 and the transistors of the second subpixel SPX2 are arranged line-symmetrically with respect to the axis of symmetry Q2. The axis of symmetry Q2 is located between the first video signal line L2a connected to the first subpixel SPX1 and the first video signal line L2a connected to the second subpixel SPX2.

[0102] That is, the reset transistor RST, connection switching transistor CNT, drive transistor DRT, emission control transistor BCT, initialization transistor IST, and write transistor SST of the second subpixel SPX2 and the reset transistor RST, connection switching transistor CNT, drive transistor DRT, emission control transistor BCT, initialization transistor IST, and write transistor SST of the first subpixel SPX1 have an inverted arrangement relative to the axis of symmetry Q2.

[0103] The first subpixel SPX1 has a reset power line L3, a second video signal line L2b, an anode power line L1, and a first video signal line L2a. The reset power line L3, the second video signal line L2b, the anode power line L1, and the first video signal line L2a are arranged in this order in the first direction Dx. The connection switching transistor CNT, the drive transistor DRT, the light emission control transistor BCT, the initialization transistor IST, and the write transistor SST are arranged between the second video signal line L2b and the anode power line L1, which are adjacent to each other in the first direction Dx. The reset transistor RST is arranged between the reset power line L3 and the second video signal line L2b.

[0104] The reset power line L3 is shared by the first pixel circuit 50a and the second pixel circuit 50b of the first subpixel SPX1. That is, in one first subpixel SPX1, the first reset transistor RST1 of the first pixel circuit 50a and the second reset transistor RST2 of the second pixel circuit 50b are connected to a common reset power line L3. In addition, the anode power line L1 is shared by the first pixel circuit 50a and the second pixel circuit 50b of the first subpixel SPX1. That is, in one first subpixel SPX1, the first emission control transistor BCT1 of the first pixel circuit 50a and the second emission control transistor BCT2 of the second pixel circuit 50b are connected to a common anode power line L1. In addition, the first video signal line L2a is provided corresponding to the first pixel circuit 50a of the first subpixel SPX1. The second video signal line L2b is provided corresponding to the second pixel circuit 50b of the first subpixel SPX1.

[0105] Focusing on the second subpixel SPX2 adjacent to the first subpixel SPX1 in the first direction Dx, the second subpixel SPX2 has a first video signal line L2a, an anode power line L1, a second video signal line L2b, and an initialization power line L4. The first video signal line L2a, the anode power line L1, the second video signal line L2b, and the initialization power line L4 are arranged in this order in the first direction Dx. The initialization power line L4 is shared by the first pixel circuit 50a and the second pixel circuit 50b of the first subpixel SPX1. The anode power line L1 is shared by the first pixel circuit 50a and the second pixel circuit 50b of the second subpixel SPX2. The first video signal line L2a is provided corresponding to the first pixel circuit 50a of the second subpixel SPX2. The second video signal line L2b is provided corresponding to the second pixel circuit 50b of the second subpixel SPX2.

[0106] In the first subpixel SPX1 and the second subpixel SPX2, the first video signal line L2a, the anode power line L1, and the second video signal line L2b are arranged symmetrically with respect to the axis of symmetry Q2. On the other hand, the reset power line L3 of the first subpixel SPX1 and the initialization power line L4 of the second subpixel SPX2 are arranged asymmetrically with respect to the axis of symmetry Q2.

[0107] Of the first subpixel SPX1 and the second subpixel SPX2, the first subpixel SPX1 has a reset power line L3 but does not have an initialization power line L4. The other subpixel SPX2 does not have the reset power line L3 but has an initialization power line L4. In this embodiment, the reset power line L3 and the initialization power line L4 are shared by two subpixels SPX adjacent in the first direction Dx. This makes it possible to reduce the arrangement pitch of the multiple subpixels SPX in the first direction Dx compared to the case where the reset power line L3 and the initialization power line L4 are provided for each subpixel SPX.

[0108] In the second subpixel SPX2 and the third subpixel SPX3, the first pixel circuit 50a and the second pixel circuit 50b of one subpixel SPX (the second subpixel SPX2) and the first pixel circuit 50a and the second pixel circuit 50b of the other subpixel SPX (the third subpixel SPX3) are also arranged symmetrically with respect to the axis of symmetry Q3 parallel to the second direction Dy. That is, the transistors and wiring of the third subpixel SPX3 have a similar arrangement relationship to those of the first subpixel SPX1. The axis of symmetry Q3 is located between the initialization power line L4 provided on the second subpixel SPX2 side and the reset power line L3 provided on the third subpixel SPX3 side.

[0109] Focusing on the second subpixel SPX2 and the third subpixel SPX3, one initialization power line L4 is shared by the first pixel circuit 50a and the second pixel circuit 50b of the second subpixel SPX2 and the first pixel circuit 50a and the second pixel circuit 50b of the third subpixel SPX3. In other words, one initialization power line L4 is connected to four initialization transistors IST.

[0110] Furthermore, one reset power line L3 is shared by the first pixel circuit 50a and the second pixel circuit 50b of the second subpixel SPX2 and the first pixel circuit 50a and the second pixel circuit 50b of the third subpixel SPX3. That is, one reset power line L3 is connected to four reset transistors RST.

[0111] With the above-described configuration, even if each of the sub-pixels SPX has two pixel circuits (the first pixel circuit 50a and the second pixel circuit 50b), the transistors and wirings can be arranged efficiently.

[0112] 9 is merely an example, and the arrangement of the transistors and wirings may be changed as appropriate. For example, some of the transistors in each subpixel SPX may be arranged asymmetrically.

[0113] As described above, the display device 1 includes a plurality of light-emitting elements 100 arranged in a display area AA, a first pixel circuit 50a and a second pixel circuit 50b connected to each of the plurality of light-emitting elements 100, a first drive transistor DRT1 provided in the first pixel circuit 50a for supplying a first drive current (a current corresponding to a first video signal VSG1-2) to the light-emitting element 100, a second drive transistor DRT2 provided in the second pixel circuit 50b for supplying a second drive current (e.g., a current corresponding to a second video signal VSG2-2) to the light-emitting element 100, a drive circuit (signal line drive circuit 13) for supplying a video signal VSG to each of the first drive transistor DRT1 and the second drive transistor DRT2, a first connection switching transistor CNT1 provided between the first drive transistor DRT1 and the light-emitting element 100, and a second connection switching transistor CNT2 provided between the second drive transistor DRT2 and the light-emitting element 100. The first connection switching transistor CNT1 and the second connection switching transistor CNT2 are turned off during a period in which the light emitting element 100 is not emitting light.

[0114] According to this, since the first connection switching transistor CNT1 and the second connection switching transistor CNT2 are provided, the light emitting element 100 is disconnected from the first pixel circuit 50a and the second pixel circuit 50b during the non-light emitting period (video signal writing operation period) of the light emitting element 100. This makes it possible to prevent the potential generated at the node N1 of the first pixel circuit 50a and the node N2 of the second pixel circuit 50b during the non-light emitting period from being applied to the light emitting element 100. By preventing an unintended reverse bias potential from being applied to the light emitting element 100, it is possible to prevent damage to the light emitting element 100.

[0115] In the display device 1, the first drive transistor DRT1 provided in the first pixel circuit 50a supplies the light-emitting element 100 with a first drive current (current corresponding to the first video signals VSG1-2) set according to the video signal VSG, and the second drive transistor DRT2 provided in the second pixel circuit 50b supplies the light-emitting element 100 with a fixed second drive current (for example, a fixed current corresponding to the second video signals VSG2-1, VSG2-2) for a period (periods t1b, t4a) having a length corresponding to the video signal VSG. The control circuit (drive signal control unit 200) sets the light-emitting period by the first pixel circuit 50a to a predetermined period, and changes the light-emitting period by the second pixel circuit 50b.

[0116] According to this, the display device 1 can achieve good gradation control by combining a PWM driving method that expresses gradation by combining periods t1a, t1b, and t4a with different light emission periods, and an analog driving method that expresses gradation by controlling the amount of current (first video signal VSG1-2) to the light-emitting element 100 in period t4a.

[0117] In the display device 1, in a range below the maximum low gradation value defined by the maximum value of the first drive current (current corresponding to the first video signal VSG1-2) (for example, a range below the target luminance level of 12.5% ​​in FIG. 7), the light emitting element 100 is driven by the first drive current. In a range on the high gradation side higher than the maximum gradation value defined by the maximum value of the first drive current (for example, a range higher than the target luminance level of 12.5% ​​in FIG. 7), the light emitting element 100 is driven by at least the second drive current (for example, at least one of the currents corresponding to the first video signal VSG1-1, the second video signal VSG2-1, and VSG2-2).

[0118] This allows the gradation control range to be narrowed compared to when all gradations are controlled by the current driving method. Also, in this embodiment, the current value of the PWM driving method is larger than the current value of the current driving method on the high gradation side. Therefore, it is possible to suppress the change in luminescence chromaticity caused by the variation in the current value.

[0119] Furthermore, in the display device 1, the first drive transistor DRT1 and the second drive transistor DRT2 are each supplied with a video signal VSG during a common writing period (e.g., periods t1 and t4), and supply a first drive current (a current corresponding to the first video signal VSG1-2) and a second drive current (e.g., a current corresponding to the second video signals VSG2-1 and VSG2-2) to the light-emitting element 100 in a time-division manner.

[0120] In the display device 1, two pixel circuits, a first pixel circuit 50a and a second pixel circuit 50b, are provided in one light emitting element 100, and therefore the video signal writing operation of the first pixel circuit 50a and the second pixel circuit 50b can be performed in the same writing period (e.g., period t1). Therefore, the time required for the video signal writing operation can be shortened compared to the case where multi-tone display is performed with one pixel circuit.

[0121] 4 to 7 are merely examples and may be modified as appropriate. For example, the display device 1 realizes the PWM driving method by combining three periods t1a, t1b, and t2a (pulse widths) of different lengths, but is not limited to this. The display device 1 may realize the PWM driving method by combining, for example, two different periods (pulse widths) or four or more different periods (pulse widths).

[0122] 5, when comparing the display periods in the PWM driving method, the period on the first pixel circuit 50a side is longer than the period on the second pixel circuit 50b side. Therefore, it is also possible to adopt a configuration in which the first storage capacitor Cs1 is larger than the second storage capacitor Cs2.

[0123] Although the preferred embodiment of the present invention has been described above, the present invention is not limited to such an embodiment. The contents disclosed in the embodiment are merely examples, and various modifications are possible within the scope of the present invention. Appropriate modifications made within the scope of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made within the scope of the gist of each of the above-mentioned embodiments and each modified example. [Explanation of symbols]

[0124] 1 Display device 2 Array Board 12 Scanning line driving circuit 13 Signal line driver circuit 14 Light Emitting Control Circuit 50 Pixel circuit 50a First pixel circuit 50b Second pixel circuit 100 Light emitting element 200 Drive signal control section DRT Drive transistor BCT Light Emitting Control Transistor CNT connection switching transistor IST Initialization Transistor RST Reset transistor SST Write Transistor SG Write control signal BG light emission control signal VSG1 1st video signal VSG2 Second video signal IG Initialization control signal RG Reset control signal PWM connection control signal L1 Anode power line L2 video signal line L3 Reset power line L5 Reset control signal line SPX subpixel

Claims

1. A plurality of light emitting elements arranged in a display area; a first pixel circuit and a second pixel circuit connected to each of the plurality of light-emitting elements; a first driving transistor provided in the first pixel circuit and configured to supply a first driving current to the light emitting element; a second driving transistor provided in the second pixel circuit and configured to supply a second driving current to the light emitting element; a drive circuit for supplying a video signal to each of the first drive transistor and the second drive transistor; a first connection switching transistor provided between the first driving transistor and the light emitting element; a second connection switching transistor provided between the second driving transistor and the light emitting element; the first connection switching transistor and the second connection switching transistor are turned off during a non-light emitting period of the light emitting element, a non-light-emitting period of the light-emitting element is a period during which the light-emitting element is not connected to the first pixel circuit and the second pixel circuit, and the first driving current and the second driving current are not supplied to the light-emitting element; the first driving transistor provided in the first pixel circuit supplies the first driving current set in response to the video signal to the light emitting element; the second driving transistor provided in the second pixel circuit supplies the fixed second driving current to the light emitting element; The control circuit sets the light emission period of the first pixel circuit to a predetermined period, and changes the light emission period of the second pixel circuit. Display device.

2. In a low gradation range equal to or lower than a maximum gradation value defined by a maximum value of the first driving current, the light emitting element is driven by the first driving current, In a range on the high gradation side that is greater than the maximum gradation value defined by the maximum value of the first driving current, the light emitting element is driven at least by the second driving current. The display device according to claim 1 .

3. The first driving transistor and the second driving transistor are The video signals are supplied in a common writing period, The first driving current and the second driving current are supplied to the light emitting element in a time division manner. The display device according to claim 1 .

4. a first reset transistor connected to the first drive transistor and supplying a reset power supply potential to the first drive transistor; a second reset transistor connected to the second drive transistor and supplying the reset power supply potential to the second drive transistor; The gate of the first reset transistor and the gate of the second reset transistor are connected to a common reset control signal line. The display device according to claim 1 .

5. a reset power supply line for supplying the reset power supply potential; The first reset transistor of the first pixel circuit and the second reset transistor of the second pixel circuit are connected to a common reset power line. The display device according to claim 4.

6. A plurality of sub-pixels are arranged in a first direction, Each of the plurality of sub-pixels includes the light-emitting element, the first pixel circuit, and the second pixel circuit, In two of the subpixels adjacent to each other in the first direction, the first pixel circuit and the second pixel circuit of one of the subpixels and the first pixel circuit and the second pixel circuit of the other subpixel are arranged symmetrically with respect to an axis of symmetry that is parallel to a second direction intersecting the first direction. The display device according to claim 1 .

7. In one of the subpixels, the first pixel circuit and the second pixel circuit are arranged symmetrically with respect to an axis of symmetry parallel to the first direction. The display device according to claim 6.

8. The plurality of subpixels include a first subpixel, a second subpixel, and a third subpixel, the first subpixel, the second subpixel, the third subpixel, the first subpixel, the second subpixel, and the third subpixel are repeatedly arranged in this order in the first direction; In the two first subpixels sandwiching the second subpixel and the third subpixel, the first pixel circuit and the second pixel circuit of one of the first subpixels and the first pixel circuit and the second pixel circuit of the other first subpixel are arranged symmetrically with respect to an axis of symmetry that is parallel to a second direction intersecting the first direction. The display device according to claim 6.

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